Semiconductor device
By integrating a self-power management circuit inside the SoC to generate control signals for the power channel, the complexity of external circuits is solved, and power management is simplified and power consumption is reduced.
Patent Information
- Application Number
- CN202510260077.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-04-17
- Filing Date
- 2025-03-06
- Publication Date
- 2025-10-24
AI Technical Summary
Existing SoC power management circuits require external circuits to generate control signals for multiple power channels, resulting in complex circuits that are difficult to meet various power function specifications, which can easily lead to SoC malfunctions or damage.
The SoC integrates a self-power management circuit to generate control signals for multiple power channels, including enable signals and reference voltage signals, to control the power-on timing, power-off timing, and ramp time of the power channels.
It simplifies the design of external power supply circuitry, ensures that the SoC's power management meets functional specifications, avoids malfunctions or damage, and reduces the complexity and power consumption of external circuitry.
Smart Images
Figure CN120832001A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present disclosure relate to a semiconductor device. BACKGROUND
[0002] In recent years, SoC (System on Chip) is being made lower in voltage and larger in current due to miniaturization and high performance of processes. In addition, as the internal structure of the SoC is becoming more complex, various power supply specifications are required (for example, refer to Non-Patent Literature 1).
[0003] Non-Patent Literature 1: Renesas Electronics RAA271000 (General-Purpose Power Management IC for the Renesas R-Car SoC series) Data Sheet https: / / www.renesas.com / jp / ja / document / dst / raa271000-datasheet?r=1497496
[0004] In recent years, SoC for calculation such as AI processing is being made lower in voltage and larger in current due to miniaturization and high performance of processes. In addition, as the internal structure of the SoC is becoming more complex, as a power supply, it is required to have the following (1) to (4) shown as a functional specification.
[0005] (1) There are multiple power supply channels (power supply channels of different voltages, even if the same voltage, different power supply channels).
[0006] (2) At the time of power-on of the SoC, there is a provision of a power-on sequence (timing) of multiple power supply channels.
[0007] (3) At the time of power-off of the SoC, there is a provision of a power-off sequence (timing) of multiple power supply channels.
[0008] (4) There is a power supply channel with a specified rise time (sloping time) in the power supply channel.
[0009] As shown in Figure 5 , all of these power supply specifications are implemented by an external power supply circuit. Therefore, it is necessary to perform control as shown in Figure 6 in the external circuit for each SoC so as to conform to the functional specifications of the power supply. In the example of Figure 5 , as a power supply channel of the SoC, there are VDD, VCORE, VCC, and if the respective voltages are set to V1, V2,..., Vn, the SoC side requires the following specifications.
[0010] • Power supply turn-on timing: turned on in the order of V2→Vn→V1, the time interval being defined by tON2n and tONn1
[0011] • Power supply turn-off timing: turned off in the order of V1→Vn→V2, the time interval being defined by tOF1n and tOFn2
[0012] • Rise time (sloping time) of V1 is defined by tR1
[0013] • Rise time (sloping time) of V2 is defined by tR2
[0014] If the above-mentioned regulations are not observed, the SoC sometimes performs an erroneous operation, or is damaged depending on the situation. Therefore, in the power management circuit, as shown in FIG. 1, it is necessary to generate the enable signals (EN1, EN2,..., ENn) of each power supply circuit and the reference voltage signals (VREF1, VREF2) for controlling the rise time (sloping time) in accordance with the specifications of the SoC. Figure 6 SUMMARY
[0015] The present disclosure is to provide a semiconductor device capable of simplifying external power supply circuits.
[0016] The semiconductor device of the present disclosure has a plurality of power supply channels that respectively receive supply of power from a plurality of external power supply circuits, and has a self power management circuit that outputs a plurality of control signals for respectively controlling the plurality of power supply circuits.
[0017] The semiconductor device of the present disclosure is capable of controlling a plurality of external power supply circuits, and is capable of simplifying the external power supply circuits. BRIEF DESCRIPTION OF DRAWINGS
[0018] Figure 1 is a view showing the structure of an embodiment of a semiconductor device.
[0019] Figure 2 is a waveform chart showing a functional specification example of a power supply channel of the semiconductor device shown in FIG. 1. Figure 1
[0020] Figure 3 is a view showing a structure example of a self power management circuit.
[0021] Figure 4 is a waveform chart of an enable signal and a reference voltage signal.
[0022] Figure 5 is an example of a conventional SoC power management circuit.
[0023] Figure 6 is an example of a control waveform of a related-art SoC power management circuit.
[0024] Explanation of reference numerals
[0025] 1: SoC; 2: auxiliary power supply circuit; 3: self power management circuit; 201, 202, 20 n : power IC; 31: built-in oscillator; 32: VIN voltage detection circuit; 331, 332: delay circuit; 34 EN1 EN2 ENn RESET : flip-flop; 35 ON2n ONn1 OF1n OFn2 R1 R2 : delay counter; 36 REF1 REF2 : D / A converter; 37 REF1 REF2 : data selector; EN1, EN2, ENn: enable signal; VREF1, VREF2: reference voltage signal. DETAILED DESCRIPTION
[0026] Hereinafter, a preferred embodiment of the present application will be described with reference to the drawings.
[0027] The semiconductor device of the present embodiment is an SoC 1 constituted by devices of various functions. Referring to Figure 1 , as devices of various functions, the SoC 1 has a CPU 11, a GPU 12, a CACHE 13, and other peripheral devices 14. The SoC 1 has a plurality of power supply channels VDD, VCORE, VCC, and operates by accepting supply of power voltages (V1, V2, Vn) from an external power block for each power supply channel. Note that the power supply channels of the SoC are not limited to VDD, VCORE, VCC shown here. In addition to these, there are generally a plurality of power supply channels.
[0028] The SoC 1 has an auxiliary power supply circuit 2 constituted by an LDO (Low Drop Out) regulator and a self power management circuit 3. The auxiliary power supply circuit 2 is a circuit that generates a power source for the self power management circuit 3 to operate from a basic input voltage VIN.
[0029] The power supply management circuit 3 receives the power supply from the auxiliary power supply circuit 2, and outputs an enable signal ENx and a reference voltage signal VREFx to the outside of the power supply block. The enable signal ENx is a control signal that controls the power-up timing (order and time interval of power-up) and the power-down timing (order and time interval of power-down) of the plurality of power supply channels. The reference voltage signal VREFx is a control signal for slope control that controls the rise time (slope time). Further, the power supply management circuit 3 generates a reset signal RESETn to the inside of the SoC 1.
[0030] The power supply block has the power ICs 201, 202, 20 n The power ICs 201, 202, 20 n generate the power supply voltages (V1, V2, Vn) of each of the plurality of power supply channels possessed by the SoC 1. The power ICs 201, 202, 20 n are not limited, and are constituted by, for example, a switching power supply. The enable signal ENx is output to the power ICs 201, 202, 20 n that have prescribed power supply channels with timing (power-up, power-down). The reference voltage signal VREFx is output to the power ICs 201, 202 that have prescribed power supply channels with a rise time (slope time).
[0031] Figure 2 are the functional specifications of the power supply voltages V1, V2, Vn of the power supply channels VDD, VCORE, VCC possessed by the SoC 1, and prescribe the power-up timing, the power-down timing, and the slope time.
[0032] The power-up timing is the order of the power supply voltage V2, the power supply voltage Vn, and the power supply voltage V1, and prescribes the time tON2n from the completion of power-up of the power supply voltage V2 to the start of power-up of the power supply voltage Vn and the time tONn1 from the start of power-up of the power supply voltage Vn to the start of power-up of the power supply voltage V1.
[0033] The power-down timing is the order of the power supply voltage V1, the power supply voltage Vn, and the power supply voltage V2, and prescribes the time tOF1n from the start of power-down of the power supply voltage V1 to the start of power-down of the power supply voltage Vn and the time tOFn2 from the start of power-down of the power supply voltage Vn to the start of power-down of the power supply voltage V2.
[0034] With respect to the slope time, the time tR1 from the start of rise of the power supply voltage V1 to the reaching of a predetermined level and the time tR2 from the start of rise of the power supply voltage V2 to the reaching of a predetermined level are prescribed.
[0035] The power supply management circuit 3 controls the power supply voltages (V1, V2, Vn) of each of the plurality of power supply channels possessed by the SoC 1 by outputting the enable signal ENx and the reference voltage signal VREFx to the power ICs 201, 202, 20 nThe enable signals EN1, EN2 and ENn are outputted respectively to control the power-on sequence and the power-off sequence. n The power supply ICs with specified ramp times in the SoC 1 output reference voltage signals VREF1 and VREF2 to control the ramp times. Specifically, the SoC 1, which receives power from the outside to multiple power supply channels, includes a built-in power management circuit 3 that outputs signals that control the timing or rise time (ramp time) of the power supply ICs supplying power to each power channel.
[0036] Reference Figure 3 The self-power management circuit 3 includes an internal oscillator 31 for internal logic operation, a VIN voltage detection circuit 32, and delay circuits 331 and 332. The VIN voltage detection circuit 32 is composed of a voltage comparator and the like, and monitors the input voltage VIN to perform startup detection and shutdown detection.
[0037] The self-power management circuit 3 has a trigger 34 EN1 , 34 EN2 , 34 ENn , 34 RESET Trigger 34 EN1 , 34 EN2 , 34 ENn They are respectively set at the output stage of the enable signals EN1, EN2, and ENn, so that the enable signals EN1, EN2, and ENn are enabled by setting and disabled by resetting. RESET Provided at the output stage of the reset signal RESETn, the reset signal RESETn is set to a high level (negative logic invalid) by a set, and is set to a low level (negative logic valid) by a reset.
[0038] The self-power management circuit 3 has a delay counter 35 ON2n , 35 ONn1 , 35 OF1n , 35 OFn2 , 35 R1 , 35 R2 Delay counter 35 ON2n , 35 ONn1 Count the time tON2n and tONn1 specified by the power-on sequence. Delay counter 35 OF1n , 35 OFn2 The time tOF1n and tOFn2 specified by the power-off sequence are counted. Delay counter 35 R1 , 35 R2 The ramp times tR1 and tR2 are counted.
[0039] The self-power management circuit 3 has a D / A converter 36 REF1 , 36REF2 and data selector 37 REF1 , 37 REF2 D / A converter 36 REF1 , 36 REF2 converts the count value (digital input) of delay counter 35 R1 , 35 R2 into an analog voltage and outputs it as reference voltage signal VREF1, VREF2, respectively. Data selector 37 REF1 , 37 REF2 is a circuit that switches the digital input to D / A converter 36 REF1 , 36 REF2 to any of delay counter 35 R1 , 35 R2 and zero.
[0040] With reference to Figure 4 , the operation of self-power management circuit 3 will be described.
[0041] When the VIN voltage that has been turned on reaches a predetermined start voltage, which is detected by VIN voltage detection circuit 32 at time tO, a start detection signal is output from delay circuit 331 at time tl. The start detection signal sets flip-flop 34 EN2 , making enable signal EN2 valid, and starts the counting of delay counter 35 R2 . Delay counter 35 R2 is a counter that counts the ramp time tR2 of reference voltage signal VREF2. The count value of delay counter 35 R2 is set to the reference voltage signal VREF2 that is analog-converted by D / A converter 36 REF2 reaches a predetermined voltage at time t2 after the ramp time tR2 has elapsed.
[0042] When delay counter 35 R2 overflows at time t2, the counting of delay counter 35 ON2n is started. Delay counter 35 ON2n is a counter that counts the time tON2n specified by the power-on sequence. When delay counter 35 ON2n overflows at time t3, flip-flop 34 ENn is set, making enable signal ENn valid, and the counting of delay counter 35 ONn1 is started. Delay counter 35 ONn1 is a counter that counts the time tONn1 specified by the power-on sequence. When delay counter 35 ONn1 overflows at time t4, the counting of delay counter 35 R1 is started. Delay counter 35 R1This is a counter that counts the ramp time tR1. Delay counter 35 R1 The count value is set to the value obtained by the D / A converter 36 REF1 The analog-converted reference voltage signal VREF1 reaches a predetermined voltage at time t5 after a ramp time tR2 has elapsed.
[0043] Delay counter 35 R1 When the time t5 overflows, at the time t6 delayed by the delay circuit 332, the flip-flop 34 RESET When set, the reset signal RESETn becomes high level (negative logic is invalid).
[0044] Thus, the plurality of external power supply ICs 201, 202, 20 n The enable signals EN1, EN2, and ENn are set to be valid in a specified order and time interval. In addition, the reference voltage signals VREF1 and VREF2 for controlling the rise time (ramp time) of the power supply voltages V1 and V2 to the external power supply ICs 201 and 202 are controlled by the delay counter 35. R1 , 35 R2 , D / A converter 36 REF1 , 36 REF2 generate.
[0045] Next, when the VIN voltage detection circuit 32 detects that the VIN voltage is lower than the preset cutoff voltage at time t10, the delay circuit 331 outputs a cutoff detection signal at time t11. The cutoff detection signal turns on the flip-flop 34. EN1 Reset, make the enable signal EN1 invalid, and input to the data selector 37 REF1 Data Selector 37 REF1 D / A converter 36 REF1 The digital input of is switched to 0. As a result, the reference voltage signal VREF1 to the power supply IC 201 drops to zero potential at the timing when the enable signal EN1 connected to the same power supply IC 201 is deactivated.
[0046] In addition, the cut-off detection signal causes the trigger 34 to RESETn Reset, set the reset signal RESETn to low level (negative logic valid), and start delay counter 35 OF1n Delay counter 35 OF1n This is a counter that counts the time tOF1n specified by the power-off sequence. Delay counter 35 OF1n When the time t12 overflows, the flip-flop 34 ENn Reset, disable the enable signal ENn, and start the delay counter 35 OFn2 Count.
[0047] Delay counter 35 OFn2 is a counter that counts the time tOFn2 defined by the power-off sequence. The delay counter 35 OFn2 is reset at the time t13 overflow, the flip-flop 34 EN2 is reset, the enable signal EN2 is invalidated, and the digital input to the data selector 37 REF2 is switched to zero. The data selector 37 REF2 switches the digital input of the D / A converter 36 REF2 to zero. Thereby, the reference voltage signal VREF2 to the power IC 202 drops to zero potential at the timing at which the enable signal EN2 connected to the same power IC 202 is invalidated.
[0048] Thereby, the enable signals EN1, EN2, ENn of the plurality of external power ICs 201, 202, 20 n are invalidated in a prescribed order and time interval. Also, the reference voltage signals VREF1, VREF2 drop to zero potential at the timing at which the enable signals EN1, EN2 connected to the same power IC 201, 202 are invalidated.
[0049] The self-power management circuit 3 is built in the SoC 1, and therefore, according to the operation state of the SoC 1, a state notification signal is output to the external power ICs 201, 202, 20 n , whereby the characteristics of the power supply can be changed. Although not particularly illustrated, the self-power management circuit 3 outputs the state notification signal, for example, during a period in which the processing load of the SoC 1 is lightened and the power consumption is reduced. Thereby, the power ICs 201, 202, 20 n reduce the switching frequency or change the transfer function of the feedback control, whereby the power supply capability can be reduced, and the power consumption of the power ICs 201, 202, 20 n themselves can be reduced.
[0050] As explained above, the present embodiment is a SoC 1 (semiconductor device) that has a plurality of power supply channels VDD, VCORE, VCC that respectively accept the supply of power supply voltages V1, V2, Vn from a plurality of external power ICs 201, 202, 20 n (power supply circuits), wherein the SoC 1 has a self-power management circuit 3 that outputs a plurality of control signals that respectively control the plurality of power ICs 201, 202, 20 n .
[0051] According to this structure, the SoC 1 (self power management circuit 3) that receives supply of the power supply voltages V1, V2, Vn to the plurality of power supply channels VDD, VCORE, VCC is able to control the plurality of external power supply circuits, and the external power supply circuits can be simplified.
[0052] Also, according to the present embodiment, the plurality of control signals are a plurality of enable signals EN1, EN2, ENn that control the sequence and time interval of power up and power down of the power supply voltages V1, V2, Vn from the plurality of power ICs 201, 202, 20 n
[0053] According to this structure, since the SoC 1 (self power management circuit 3) is able to control the timing of the power supply voltages V1, V2, Vn, the external power supply circuits do not need to prepare a circuit for timing control for each different product, and simplification is possible.
[0054] Further, according to the present embodiment, the control signals are reference voltage signals VREF1, VREF2 that control the ramp time at power up of the power supply, and the reference voltage signals VREF1, VREF2 drop to zero potential at the timing of invalidating the enable signals EN1, EN2 input to the same power IC 201, 202.
[0055] According to this structure, the SoC 1 (self power management circuit 3) is able to control the ramp time of the power supply voltages V1, V2, Vn, and therefore the external power supply circuits do not need to prepare a circuit for ramp time control for each different product, and simplification is possible.
[0056] The reference voltage signals VREF1, VREF2 are not limited to control of the rise (ramp) time of the power supply voltage. For an SoC 1 that needs to perform slope control at power down of the power supply voltage, it is also possible to make the reference voltage signals VREF1, VREF2 slowly drop in potential without sharply dropping to zero potential to obtain a desired specification.
[0057] In addition, the present application is not limited to the above-described embodiments, and it is understood that each of the embodiments can be appropriately changed within the scope of the technical idea of the present application. Further, the number, position, shape, and the like of the above-described structural components are not limited to those of the above-described embodiments, and can be a number, position, shape, and the like that are suitable for implementing the present application. In addition, the same reference numerals are assigned to the same structural elements in each drawing.
Claims
1. A semiconductor device having a plurality of power supply channels that respectively receive supply of power from a plurality of external power supply circuits, the semiconductor device characterized by, the semiconductor device having a self power management circuit that outputs a plurality of control signals that respectively control the plurality of power supply circuits.
2. The semiconductor device according to claim 1, characterized by, the plurality of control signals being a plurality of enable signals that control the order and time interval of power up and power down of the power supply from the plurality of power supply circuits.
3. The semiconductor device according to claim 1, characterized by, the plurality of control signals being a plurality of reference voltage signals that control the slope at the time of power up or power down of the power supply.