Memory system, operating method thereof, electronic device, and computer-readable

Abstract

The embodiment of the invention discloses a memory system, an operation method of the memory system, electronic equipment and a computer readable medium. The memory system includes a memory and a memory controller coupled to the memory, the memory including a memory cell array and a peripheral circuit coupled to the memory cell array, the peripheral circuit including a page buffer; the memory controller is configured to: in response to a first read request including a first logical address, read data from the memory cell array, and store the read data through the page buffer, the data including all data stored in a physical page to which a first physical address corresponding to the first logical address points; in response to a second read request including a second logical address, reading data corresponding to the second logical address from the page buffer; wherein the second logical address is related to the first logical address.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of memory, and relate to but are not limited to a memory and an operating method thereof, a memory system, and an electronic device. BACKGROUND

[0002] Memory is classified into volatile memory and non-volatile memory according to whether data is retained when power is off, wherein the non-volatile memory that retains data when power is off can include Read-Only Memory (ROM), Electrically Erasable and Programmable ROM (EEPROM), flash memory, etc.

[0003] With the increasing demand for storage density, the industry has developed three-dimensional memory (for example, 3D NAND) with a three-dimensional structure to improve storage density by arranging storage cells in three dimensions. However, the improvement of storage density has led to more data read problems. SUMMARY

[0004] According to a first aspect of embodiments of the present disclosure, a memory system is provided, the memory system comprising: a memory comprising a storage cell array and a peripheral circuit, the peripheral circuit being coupled with the storage cell array, the peripheral circuit comprising a page buffer; and a memory controller coupled with the memory, the memory controller being configured to: in response to a first read request comprising a first logical address, read data from the storage cell array, the data comprising all data stored in a physical page pointed to by a first physical address corresponding to the first logical address, and store the read data through the page buffer; in response to a second read request comprising a second logical address, read data corresponding to the second logical address from the page buffer; wherein the second logical address and the first logical address are related.

[0005] According to a second aspect of an embodiment of the present disclosure, a method for operating a memory system is provided, wherein the memory system includes a memory and a memory controller coupled to the memory; the memory includes a memory cell array and a peripheral circuit coupled to the memory cell array, and the peripheral circuit includes a page buffer; the operating method includes: in response to a first read request including a first logical address, controlling the peripheral circuit to read data stored in the memory cell array, and storing the read data through the page buffer; wherein the data includes all data stored in a physical page pointed to by a first physical address corresponding to the first logical address; and in response to a second read request including a second logical address, controlling the peripheral circuit to read data corresponding to the second logical address in the page buffer; wherein the second logical address is related to the first logical address.

[0006] According to a third aspect of an embodiment of the present disclosure, there is provided an electronic device, including:

[0007] The memory system as described in any one of the embodiments of the first aspect of the present disclosure;

[0008] A host is coupled to the memory system.

[0009] According to a fourth aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, on which instructions are stored. When the instructions are executed by a processor, the operating method as described in any embodiment of the second aspect of the embodiment of the present disclosure is implemented.

[0010] In an embodiment of the present disclosure, a memory controller is configured to respond to a first read request including a first logical address, read data from a memory cell array, and store the read data in a page buffer. The data includes all data stored in a physical page pointed to by a first physical address corresponding to the first logical address; and respond to a second read request including a second logical address, read data corresponding to the second logical address from the page buffer. The second logical address is related to the first logical address. In this way, firstly, in the process of responding to the second read request, the number of read operations performed on the memory cell array is reduced, that is, the number of times the corresponding read operation voltage is applied to the word line is reduced, thereby reducing read interference between adjacent word lines and the probability of read errors, which is beneficial to improving the reliability of the memory. Secondly, reading the relevant data directly from the page buffer can save read time and reduce power consumption. Thirdly, this can be achieved by utilizing the existing page buffer in the memory without adding additional hardware costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the drawings, like reference numerals refer to like elements throughout the various figures. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating the principles of the application. It should be understood that the drawings are merely schematic and that the application can be embodied in many different forms.

[0012] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0013] Figure 2a is a schematic diagram of a memory card according to an embodiment of the present disclosure.

[0014] Figure 2b is a schematic diagram of a solid state drive according to an embodiment of the present disclosure.

[0015] Figure 3 is a schematic block diagram of a three-dimensional NAND memory according to an embodiment of the present disclosure.

[0016] Figure 4 is a schematic diagram of a memory according to an embodiment of the present disclosure.

[0017] Figure 5 is a schematic diagram of a memory including an array of memory cells and a peripheral circuit according to an embodiment of the present disclosure.

[0018] Figure 6 is a schematic diagram of a memory system according to an embodiment of the present disclosure.

[0019] Figure 7 is a schematic diagram of reading stored data from a page buffer according to an embodiment of the present disclosure.

[0020] Figure 8 is a flowchart of an operating method of a memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] In order to facilitate the understanding of the present disclosure, exemplary embodiments thereof will be described in detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be more thoroughly understood and so that the scope of the present disclosure can be completely conveyed to those skilled in the art.

[0022] In the following description, numerous specific details are given to provide a thorough understanding of the disclosure. However, it will be apparent that the disclosure can be practiced without one or more of the specific details. In some embodiments, well-known structures and techniques are not described in order to avoid obscuring the disclosure. In some embodiments, in order to avoid obscuring the disclosure, some technical features that are well known in the art are not described.

[0023] Generally, the terminology can be understood at least in part from usage of the singular throughout the present disclosure. For example, as used herein, the terms "one or more of", "any of" or "one or more of a set of" can be taken to describe any feature, structure, or property, either in the singular or in combination. Similarly, the terms such as "a" or "said" can also be understood, depending at least in part upon context, either to convey a singular usage or to convey a plural usage. Additionally, terms such as "based on" can be understood as not necessarily requiring explicitly stated factors to constitute an exclusive list of factors for determining an outcome, and can instead allow additional factors, not necessarily explicitly described, to be present as well, depending at least in part on context.

[0024] Unless otherwise defined, the terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0025] For a thorough understanding of the present disclosure, reference is made to the following description taken in conjunction with the accompanying drawings. The preferred embodiments of the present disclosure are described in detail below with reference made to the figures. However, the present disclosure can have other embodiments in addition to those described in detail below.

[0026] The memory in the embodiments of the present disclosure includes, but is not limited to, a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is taken as an example for description.

[0027] Figure 1is a schematic diagram of an electronic device 100 according to embodiments of the present disclosure. The electronic device 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a memory. Referring to Figure 1 As shown, the electronic device 100 can include a host 108 and a memory system 102 having one or more memories 104 and a memory controller 106. The host 108 can be a processor (e.g., a Central Processing Unit (CPU)) or a System on Chip (SoC) (e.g., an Application Process (AP)) of the electronic device. The host 108 can be configured to send data to or receive data from the memory 104.

[0028] According to some embodiments, the memory controller 106 is coupled to the memory 104 and the host 108, and is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104, and communicate with the host 108. In some embodiments, the memory controller 106 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed for operation in a high duty cycle environment, such as a Solid State Disk (SSD) or an embedded Multi-Media Card (eMMC), and the SSD or eMMC is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0029] The memory controller 106 can be configured to control operations of the memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions with respect to data stored in or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to handle error correction codes (ECC) with respect to data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., the host 108 in Figure 1 FIG. 1) in accordance with a particular communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a Peripheral Component Interconnect Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Development Equipment (IDE) protocol, a Firewire protocol, etc.

[0030] The memory controller 106 and the one or more memories 104 can be integrated into various types of memory devices, such as included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. In as Figure 2aIn one example shown in FIG, the memory controller 106 and the single memory 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (Personal Computer Memory Card), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC (Multi-Media Card), RS-MMC (Reduced-Size MMC), MMCmicro), an SD card (SD, miniSD, microSD, SDHC (Reduced-Size MMC)), UFS, etc. The memory card 202 can also include a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in FIG. Figure 2b In another example shown in , the memory controller 106 and the plurality of memories 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0031] Figure 3 3 is a schematic block diagram of a three-dimensional NAND memory 300 according to an embodiment of the present disclosure. The memory 300 may be Figure 1 3. An example of a memory 104 in FIG. Memory 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is described as a three-dimensional NAND memory cell array, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the area of ​​the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0032] In some embodiments, each storage cell 306 is a Single Level Cell (SLC) that has two possible storage states and thus can store one bit of data. For example, a first storage state "0" can correspond to a first voltage range, and a second storage state "1" can correspond to a second voltage range. In some embodiments, each storage cell 306 is a Multi Level Cell (MLC) that can store more than a single bit of data in more than four storage states. For example, an MLC can store two bits per cell, three bits per cell (also referred to as a Triple Level Cell (TLC)), or four bits per cell (also referred to as a Quad Level Cell (QLC)). Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed by writing one of three possible nominal storage values to the cell, and a fourth nominal storage value outside of the three can be used to represent an erased state.

[0033] As Figure 3As shown in FIG. 3, each NAND memory string 308 can include a bottom select gate (BSG) 310 at its source end and a top selective gate (TSG) 312 at its drain end. The BSG 310 and the TSG 312 can be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a respective bit line (BL) 316 from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor with the TSG 312) or a deselect voltage (e.g., 0V) to the respective TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor with the BSG 310) or a deselect voltage (e.g., 0V) to the respective BSG 310 via one or more BSG lines 315.

[0034] As Figure 3As shown in FIG. 3, the NAND memory strings 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic unit of data for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased at the same time. To erase the memory cells 306 in a selected memory block, the source lines coupled to the selected memory block and unselected memory blocks in the same face as the selected memory block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be appreciated that in some examples, erase operations can be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, the memory cells 306 in a memory block 304 coupled to the same word line 318 can constitute at least one physical page. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 of the respective physical page and a gate line coupling the control gates.

[0035] Figure 4 is a cross-sectional view of a memory according to embodiments of the present disclosure. Referring to FIG. 4, a memory array 301 can include a plurality of memory cells 306 arranged in rows and columns. The memory cells 306 can be arranged in a plurality of memory blocks 304. Each memory block 304 can include a plurality of memory cells 306 arranged in rows and columns. The memory cells 306 in each memory block 304 can be coupled to a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic unit of data for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased at the same time. To erase the memory cells 306 in a selected memory block, the source lines coupled to the selected memory block and unselected memory blocks in the same face as the selected memory block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be appreciated that in some examples, erase operations can be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 306 of adjacent memory blocks 304 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, the memory cells 306 in a memory block 304 coupled to the same word line 318 can constitute at least one physical page. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 of the respective physical page and a gate line coupling the control gates. Figure 4 As shown in FIG. 3, the NAND memory strings 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic unit of data for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased at the same time. To erase the memory cells 306 in a selected memory block, the source lines coupled to the selected memory block and unselected memory blocks in the same face as the selected memory block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be appreciated that in some examples, erase operations can be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, the memory cells 306 in a memory block 304 coupled to the same word line 318 can constitute at least one physical page. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 of the respective physical page and a gate line coupling the control gates.

[0036] The constituent material of the gate layers 411 can include a conductive material. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, e.g., a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 can include a control gate that surrounds a memory cell. The gate layers 411 at the top of the stack structure 410 can extend laterally as upper select gate lines, the gate layers 411 at the bottom of the stack structure 410 can extend laterally as lower select gate lines, and the gate layers 411 extending laterally between the upper select gate lines and the lower select gate lines can serve as word line layers.

[0037] In some embodiments, the stack structure 410 can be disposed on a substrate 401. The substrate 401 can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0038] In some embodiments, the NAND memory string 308 includes a channel structure that extends vertically through the stack structure 410. In some implementations, the channel structure includes a channel hole that is filled with a semiconductor material(s) (e.g., as a semiconductor channel) and a dielectric material(s) (e.g., as a memory film). In some implementations, the semiconductor channel includes silicon, e.g., polysilicon. In some implementations, the memory film is a composite dielectric layer that includes a tunneling layer, a storage layer (also referred to as a “charge trapping / storage layer”), and a blocking layer. The channel structure can have a cylindrical shape (e.g., a column shape). According to some implementations, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0039] Referring back to Figure 3 , the peripheral circuitry 302 can be coupled to the memory cell array 301 through the bit lines 316, the word lines 318, the source lines 314, the BSG lines 315, and the TSG lines 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory cell array 301 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target memory cell 306 via the bit lines 316, the word lines 318, the source lines 314, the BSG lines 315, and the TSG lines 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some example peripheral circuitry is shown, the peripheral circuitry 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, registers 514, an interface 516, and a data bus 518. It should be understood that additional peripheral circuitry not shown in FIG. 6 can also be included in some examples. Figure 5

[0040] ​The page buffer / sense amplifier 504 can be configured to read data from and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store a page of program data (write data) to be programmed into one physical page of the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells 306 coupled to a selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense low power signals from the bit lines 316 representing data bits stored in the memory cells 306 and amplify small voltage swings to identifiable logic levels in read operations. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more NAND memory strings 308 by applying bit line voltages generated from the voltage generator 510.

[0041] The row decoder / word line driver 508 can be configured to be controlled by the control logic 512 and select / deselect memory blocks 304 of the memory cell array 301 and select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and the TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform program operations on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by the control logic 512 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, channel boost voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0042] The control logic 512 can be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The registers 514 can be coupled to the control logic 512 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses used to control the operation of each of the peripheral circuits. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, and to buffer status information received from the control logic 512 and relay them to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay them to or from the memory cell array 301.

[0043] As mentioned above, the increase of storage density leads to more data read problems, such as Read Disturb (RD). Specifically, when performing a read operation, a read voltage Vread is applied to the selected word line, and a pass voltage Vpass is applied to the unselected word line. Since Vpass is greater than Vread, the storage cells coupled to the unselected word line can be slightly programmed. If the number of read operations is too large, the accumulation of slight programming will cause the threshold voltage distribution of the storage cells coupled to the unselected word line to shift to the right, resulting in read errors. Among them, Single Page Read Disturb (SPRD) will significantly affect the adjacent word line, causing the error bit count to increase during reading, and reducing the reliability of NAND. It should be noted that read disturb is caused by the physical structure of NAND itself, and although it can be alleviated by some methods (such as appropriately reducing Vpass), it cannot be solved from the root cause.

[0044] Based on one or more of the above technical problems, the embodiments of the present disclosure provide a memory system. Figure 6 is a schematic diagram of a memory system according to an embodiment of the present disclosure, Figure 7 is a schematic diagram of reading stored data from a page buffer according to an embodiment of the present disclosure. The following will be described in conjunction with Figure 6 and Figure 7 The memory system provided by the embodiments of the present disclosure is exemplarily described.

[0045] Referring to Figure 6As shown, the memory system 600 includes a memory controller 610 and a memory 620 coupled to the memory controller 610, which can be coupled in any suitable manner. The memory controller 610 includes a processor 611, a buffer 612, a host interface 613, a memory interface 614, and the like. Of course, the memory controller 610 can also include other circuitry or modules not shown.

[0046] In some embodiments, the host interface 613 outputs requests, data, and the like received from a host (e.g., the host 108 in FIG. 1) to the internal bus 615, and sends data read from the memory 620, responses from the processor 611, and the like to the host. The memory interface 614 controls the process of writing data and the like to the memory 620 and the process of reading from the memory 620 based on an instruction of the processor 611. The processor 611 controls the memory system 600 as a whole, and is, for example, a central processing unit, a micro processing unit (MPU), and the like. The processor 611 performs control according to a request received from the host via the host interface 613, for example, the processor 611 instructs the memory interface 614 to write data to the memory 620 according to a write request from the host. In addition, the processor 611 instructs the memory interface 614 to read data from the memory 620 according to a read request from the host. Figure 1

[0047] It should be noted that the processor 611 described in the embodiments of the present disclosure can include a plurality of functional modules, each functional module of the processor 611 can be a software module running on a part of the processor 611 (e.g., a micro controller unit (MCU)), or can be a hardware module (e.g., an integrated circuit (IC), such as an application specific IC (ASIC), a field programmable gate array (FPGA), and the like) of a finite state machine (FSM), or can be a combination of a software module and a hardware module.

[0048] In some embodiments, the memory controller 610 is configured to perform mapping management on data stored in the memory 620, specifically, the memory controller 610 can update and maintain an L2P table, each mapping entry in the L2P table can represent a mapping relationship between a logical address and a physical address. When the host sends a read request including a logical address to the memory controller 610, the memory controller 610 can obtain a corresponding physical address based on the L2P table and the logical address in the read request, and read data from the memory 620 according to the physical address and send it to the host.

[0049] ​In some embodiments, the memory controller 610 includes a buffer 612, which can include but is not limited to static random-access memory (SRAM), and the memory system 600 further includes a memory, e.g., dynamic random-access memory (DRAM), for storing the L2P table. The memory controller 610 can quickly obtain the L2P table from the DRAM, thereby achieving a higher read efficiency. The DRAM can be disposed internally or externally to the memory controller 610. Of course, in other embodiments, the memory system 600 can be of the DRAM-less type, and the L2P table can be stored in a three-dimensional NAND memory. At least part of the L2P table is loaded into the buffer 612 in the memory controller 610 upon power-up of the memory system 600.

[0050] The memory 620 includes a memory cell array 621 and a peripheral circuit 622 coupled to the memory cell array 621. The peripheral circuit 622 includes a page buffer 623 coupled to the memory cell array 621 through a bit line. The number of page buffers 623 in the memory 620 can be one or more. For ease of illustration, Figure 6

[0051] In some embodiments, the memory controller 610 is configured to, in response to a first read request including a first logical address, read data from the memory cell array 621 and store the read data through the page buffer 623, the data including all data stored in a physical page pointed to by a first physical address corresponding to the first logical address; and in response to a second read request including a second logical address, read data corresponding to the second logical address from the page buffer 623; wherein the second logical address is related to the first logical address.

[0052] ​In this embodiment, the memory controller 610 can read all data in the physical page pointed by the first physical address corresponding to the first logical address in response to the first read request, and store all the read data in the page buffer 623; in the case of receiving the second read request, since the second logical address is related to the first logical address, the related data can be directly read from the page buffer 623. It can be understood that in the process of responding to the second read request, the read operation performed on the memory cell array 621 will be reduced, i.e. the number of times of applying corresponding read operation voltages to the word lines (for example, applying read voltage Vread on the selected word line and pass voltage Vpass on the unselected word line) will be reduced. In this way, in the first aspect, the number of times of applying corresponding read operation voltages to the word lines can be reduced, thereby reducing the read disturbance of adjacent word lines and the probability of read error, and facilitating to improve the reliability of the memory; in the second aspect, directly reading the related data from the page buffer can save read time and reduce power consumption; in the third aspect, the existing page buffer in the memory is utilized, and no additional hardware cost is needed to achieve the above.

[0053] It should be noted that the read request received by the memory controller 610 is not limited to the second read request, and can also include other read requests. If the logical address included in the other read request is also related to the first logical address, the above similar operation can be performed, so that the read disturbance can be reduced multiple times, and the reliability of the memory is further improved. In a specific embodiment, the first read request and the second read request are consecutive read requests.

[0054] It should be further noted that the second logical address being related to the first logical address can mean that the second logical address is completely the same as the first logical address, i.e. the first physical address and the second physical address corresponding to the second logical address point to the same physical page, then all data can be directly read from the page buffer 623, without applying corresponding read operation voltages to the word lines, thereby avoiding the read disturbance of adjacent word lines. Of course, the second logical address being related to the first logical address can also mean that the second logical address is partially the same as the first logical address, in the case of the second logical address being partially the same as the first logical address, part of the data can be directly read from the page buffer 623, the number of times of applying corresponding read operation voltages to the word lines is reduced, and the read disturbance of adjacent word lines is reduced.

[0055] In some embodiments, the memory controller 610 is specifically configured to: in response to the first read request, determine the first physical address corresponding to the first logical address, send the first read command and the first physical address to the peripheral circuit 622; in response to the second read request, determine the second physical address corresponding to the second logical address, send the second read command and the second physical address to the peripheral circuit 622; the peripheral circuit 622 is configured to: in response to the first read command and the first physical address, read N logical page data stored in the physical page pointed by the first physical address in the memory cell array 621, N being an integer greater than 1; latch the N logical page data to N first latches of the page buffer 623 respectively; in response to the second read command and the second physical address, read the corresponding logical page data in the N first latches. The process of performing the first read request and the second read request on the memory controller 610 will be described below with reference to Figure 5 and Figure 6 The process of performing the first read request and the second read request on the memory controller 610 will be described below with reference to

[0056] Referring to Figure 6 , the memory controller 610 can receive the first read request from the outside (for example, the host 108 in the Figure 1 , analyze the first read request to obtain the first logical address, determine the first physical address based on the first logical address and the L2P table, generate the first read instruction, and send the first read instruction and the first physical address to the memory. Here, the first read request can be received through the host interface 613, and the first read instruction and the first physical address can be sent through the memory interface 614.

[0057] The peripheral circuit 622 reads the data stored in the physical page pointed by the first physical address in the memory cell array 621 based on the received first read command and the first physical address. Specifically, with reference to Figure 5As shown, the control logic 512 can control the WL driver 508 to select a target word line (i.e., a selected word line) and control the BL driver 506 to select a target bit line (i.e., a selected bit line); the control logic 512 can also obtain corresponding read operation parameters from the register 514, control the voltage generator 510 to generate read operation voltages based on the obtained read operation parameters, and the WL driver 508 can use the read operation voltages (e.g., a read voltage and a pass voltage, etc.) generated from the voltage generator 510 to drive the word line, and the BL driver 506 can use the read operation voltages (e.g., a bit line read voltage and a bit line inhibit voltage, etc.) generated from the voltage generator 510 to drive the bit line, and the page buffer 623 reads the N pieces of logical page data by sensing a current on the bit line, and locks the N pieces of logical page data in the N first latches respectively, and the N pieces of logical page data can also be output through the interface 516 and returned to the host, so as to complete the first read request. It should be noted that the first latches are not reset after the N pieces of logical page data are returned to the host, but still lock the corresponding logical page data.

[0058] Still referring to Figure 6 As shown, the memory controller 610 receives a second read request from outside, parses the second read request, obtains a second logical address, determines a second physical address based on the second logical address by searching the L2P table, generates a second read instruction, and sends the second read instruction and the second physical address to the memory, and the second read instruction is used to instruct to read data from at least the page buffer 623. The peripheral circuit 622 directly reads the N pieces of logical page data locked in the N first latches based on the received second read instruction and the second physical address. It can be understood that the second logical address and the first logical address are completely same in the present example. In the case that the second logical address and the first logical address are partially same, the peripheral circuit 622 can read part of the logical page data from the N first latches and read another part of the logical page data from the memory cell array 621.

[0059] In the embodiments of the present disclosure, the N pieces of logical page data are locked by the N first latches, and when the second read request is received, the corresponding logical page data can be read from the N first latches due to the correlation between the second logical address and the first logical address, so as to reduce read interference and improve the reliability of the memory.

[0060] In some embodiments, the N first latches include (N-1) data latches and cache latches; the data latch is configured to latch one logical page of (N-1) logical pages of data in the N logical pages; the cache latch is configured to latch the remaining one logical page of data in the N logical pages; the peripheral circuit 622 is specifically configured to transmit the logical page data latched by at least one of the (N-1) data latches to the cache latch in response to a second read command and a second physical address; wherein the second read command is used to instruct to read at least one logical page of data in the (N-1) logical pages; and control the cache latch to output the logical page data transmitted by at least one data latch. For ease of understanding, the following example will be explained using a TLC memory cell and an N value of 3 as an example. In actual applications, the memory cell may also be an MLC memory cell or a QLC memory cell, and the value of N may also be 2, 4, or other values.

[0061] Reference Figure 6 As shown, the page buffer 623 includes a first latch, a second latch LLAT, and a sense latch SA; the first latch includes a data latch D1, a data latch D2, and a cache latch CLAT. The TLC memory cell is configured to store three logical pages of data, namely, a lower logical page (LP), a middle logical page (MP), and an upper logical page (UP). The LP and MP read from the selected TLC memory cell can be latched in the data latch D1 and the data latch D2, respectively, and the read UP can be latched in the cache latch CLAT, as shown in FIG. Figure 6 shown.

[0062] Figure 7 FIG. 4 shows an example in which the data latch D1 latches the relevant data. Figure 7 As shown in step ③, the LP latched by the data latch D1 is transferred to the cache latch CLAT, and the LP transferred to the cache latch CLAT is transmitted through Figure 5 The data bus 518 and the output of the interface 516 are connected. It can be understood that the output of the cache latch CLAT is coupled to the data bus 518.

[0063] If the LP latched by the data latch D1 and the MP latched by the data latch D2 are both related data, Figure 7 As shown, the MP latched by the data latch D2 is first transferred to the cache latch CLAT, and the MP transferred to the cache latch CLAT is transferred to the data bus 518, and the cache latch CLAT is reset; then the LP latched by the data latch D1 is transferred to the cache latch CLAT, and the LP transferred to the cache latch CLAT is transferred to Figure 5the data bus 518 in the data bus 518, and output through the interface 516 in the data bus 518. Figure 5

[0064] Similarly, if the UP latched by the cache latch CLAT, the MP latched by the data latch D2, and the LP latched by the data latch D1 are all the relevant data, similar operations as described above can be performed to sequentially transmit the UP, MP, and LP through the cache latch CLAT to the data bus 518 in the data bus 518, and output through the interface 516 in the data bus 518. Figure 5 Figure 5

[0065] In some embodiments, the peripheral circuit 622 is further configured to reset the at least one data latch after transmitting the logical page data latched by the at least one data latch to the cache latch, as shown in step ④ in the data bus 518. Figure 7 In some embodiments, the peripheral circuit 622 is further configured to reset the at least one data latch after transmitting the logical page data latched by the at least one data latch to the cache latch, as shown in step ④ in the data bus 518.

[0066] In some embodiments, the page buffer 623 further comprises a second latch LLAT, and the peripheral circuit 622 is further configured to, before transmitting the logical page data latched by the at least one data latch to the cache latch CLAT, control the cache latch CLAT to transmit the remaining one of the latched logical page data to the second latch LLAT, and reset the cache latch CLAT.

[0067] To avoid the occurrence of read errors and undesirable data loss, before step ③ in the data bus 518 is executed, step ① can be performed first, i.e., the UP latched by the cache latch CLAT is transmitted to the second latch LLAT, and then step ② is performed, i.e., the cache latch CLAT is reset based on the reset signal, and then the LP latched by the data latch D1 is transmitted to the cache latch CLAT. Here, the second latch LLAT does not latch information. Figure 7

[0068] In some embodiments, the peripheral circuit 622 is further configured to, after resetting the at least one data latch, transmit the remaining one of the logical page data latched by the second latch LLAT to the data latch. As shown in step ⑤ in the data bus 518, the UP latched by the second latch LLAT is transmitted to the data latch D1. Of course, in other embodiments, the UP can continue to be latched in the second latch LLAT, and the present disclosure does not have special limitations thereon. Figure 7

[0069] ​​​​​In some embodiments, the memory controller 610 is further configured to determine whether the second logical address is related to the first logical address, and in response to the second logical address being related to the first logical address, read the data corresponding to the second logical address stored in the page buffer 623.

[0070] In the present embodiment, the memory controller 610 can execute different read strategies by determining whether the second logical address is related to the first logical address when receiving a new read request (i.e., the second read request). For example, if the second logical address is related to the first logical address, the generated second read instruction is used to instruct reading data from at least the page buffer 623; otherwise, if the second logical address is not related to the first logical address, the generated second read instruction is used to instruct reading data from the memory cell array 621. In this way, by determining whether the second logical address of the second read request is related to the first logical address of the first read request, different read strategies can be selected, which is beneficial to improving the read speed.

[0071] In some embodiments, the memory controller 610 includes a first determination circuit 616 configured to determine whether the second logical address is related to the first logical address. Specifically, the first determination circuit 616 can determine whether the second logical address is related to the first logical address by comparing the second logical address with the first logical address. The first determination circuit 616 can be a software module running on the processor 611, can be implemented by a hardware module, or can be a combination of a software module and a hardware module.

[0072] In some embodiments, the memory controller 610 is further configured to determine whether the first read request is a single logical page read request, and in response to the first read request being a single logical page read request, store the read data in the page buffer 623. Here, the single logical page read (Single Page Read) request is used to instruct reading one logical page in a plurality of logical pages stored in a memory cell, for example, one logical page read in a TLC memory cell can be any one of LP, MP, and UP.

[0073] It should be noted that the known solutions for SPRD mainly include increasing a background scan of a word line adjacent to the SPRD position or reducing a threshold of a block refresh. The above solutions are based on the idea of refreshing as early as possible before the error bit count exceeds the decoding limit. Frequent refreshing will bring certain performance overhead.

[0074] In the embodiment, the memory controller 610 can avoid the severe read disturbance in the SPRD scenario by judging whether the first read request is a single logical page read request and storing the read data to the page buffer 623 when the first read request is the single logical page read request, solve the problem from the source end of the read disturbance, greatly reduce the rising rate of the failed bit count in the SPRD scenario, and thus reduce the number of read retries and the number of refreshes, which is beneficial to reducing the overhead of the firmware.

[0075] In some other embodiments, the first read request can also be a plurality of logical page read requests, the plurality of logical page read requests being used to indicate reading at least two logical pages in a plurality of logical pages stored by the storage unit, the number of the read at least two logical pages can be less than the number of bits stored by the storage unit, and the logical addresses of the read at least two logical pages are continuous and located at the same storage unit layer. For example, the read at least two logical pages in the TLC storage unit can be any two of the LP, the MP, and the UP.

[0076] In some embodiments, the memory controller 610 includes a second judgment circuit 617 configured to judge whether the first read command is a single logical page read request. The second judgment circuit 617 can be a software module running on the processor 611, can be implemented by a hardware module, or can be a combination of a software module and a hardware module.

[0077] In some embodiments, the memory controller 610 is specifically configured to, in response to the first read request being a single logical page read request, send a command of storing the read data to the page buffer 623 to the peripheral circuit 622.

[0078] In the embodiment, the data of the read one logical page can be locked in the empty latch of the page buffer 623, and then output through the cache latch CLAT, Figure 5 the data bus 518, and the interface 516. The memory controller 610 can generate a set feature, which is used to indicate storing the data of the read one logical page to the page buffer 623, that is, the empty latch locking the data of the read one logical page is not reset but continues to lock the one logical page data. Here, when the data of the read one logical page is locked in the cache latch CLAT, the one logical page data is directly output through the data bus 518 and the interface 516.

[0079] It should be noted that the set feature can be included in the first read command, for example, the first read command includes an identifier indicating storing the read data to the page buffer. The set feature can also be a specially set command, and the set feature can be called in the SPRD scenario.

[0080] Based on the above memory system, the embodiments of the present disclosure further provide an operation method of the memory system.

[0081] Figure 8 is a flowchart of an operation method of a memory system according to an embodiment of the present disclosure. The memory system can be the memory system 600 in any of the above embodiments. The operation method includes at least the following steps:

[0082] S710: in response to a first read request including a first logical address, controlling the peripheral circuit to read data stored in the memory cell array, and storing the read data in the page buffer; wherein the data includes all data stored in a physical page pointed to by a first physical address corresponding to the first logical address;

[0083] S720: in response to a second read request including a second logical address, controlling the peripheral circuit to read data corresponding to the second logical address in the page buffer; wherein the second logical address and the first logical address are related.

[0084] In some embodiments, the above-mentioned response to the first read request including the first logical address, controlling the peripheral circuit to read the data stored in the memory cell array, and storing the read data in the page buffer includes: in response to the first read request, determining the first physical address corresponding to the first logical address, sending the first read command and the first physical address to the peripheral circuit; the peripheral circuit reads N logical page data stored in the physical page pointed to by the first physical address in the memory cell array in response to the first read command and the first physical address, N is an integer greater than 1; the peripheral circuit latches the N logical page data to N first latches of the page buffer respectively; the above-mentioned response to the second read request including the second logical address, controlling the peripheral circuit to read the data corresponding to the second logical address in the page buffer includes: in response to the second read request, determining the second physical address corresponding to the second logical address, sending the second read command and the second physical address to the peripheral circuit; the peripheral circuit reads the corresponding logical page data in the N first latches in response to the second read command and the second physical address.

[0085] In some embodiments, the N first latches include (N-1) data latches and a cache latch; the operation method further includes: the data latches latch one logical page data of (N-1) logical page data in the N logical page data; the cache latch latches the remaining one logical page data in the N logical page data; and the peripheral circuit reads the corresponding logical page data in the N first latches in response to the second read command and the second physical address, including: the peripheral circuit controls at least one data latch of the (N-1) data latches to transmit the latched logical page data to the cache latch in response to the second read command and the second physical address; wherein the second read command is used to indicate reading at least one logical page data of the (N-1) logical page data; and the peripheral circuit controls the cache latch to output the logical page data transmitted by the at least one data latch.

[0086] In some embodiments, the operation method further includes: after transmitting the logical page data latched by the at least one data latch to the cache latch, the peripheral circuit resets the at least one data latch.

[0087] In some embodiments, the page buffer further includes a second latch; and the operation method further includes: before transmitting the latched remaining one logical page data to the cache latch, the peripheral circuit controls the cache latch to transmit the latched remaining one logical page data to the second latch; and the peripheral circuit resets the cache latch.

[0088] In some embodiments, the operation method further includes: after resetting the at least one data latch, the peripheral circuit transmits the remaining one logical page data latched by the second latch to the data latch.

[0089] In some embodiments, the operation method further includes: determining whether the second logical address and the first logical address are related; and in response to the second logical address and the first logical address being related, reading the data corresponding to the second logical address stored in the page buffer.

[0090] In some embodiments, the operation method further includes: determining whether the first read request is a single logical page read request; and in response to the first read request being a single logical page read request, storing the read data to the page buffer.

[0091] In some embodiments, the operation method further includes: determining whether the first read request is a single logical page read request; and in response to the first read request being a single logical page read request, storing the read data to the page buffer.

[0092] In the embodiments of the present disclosure, the operation method of the memory system can be performed by the memory controller in the memory system of any of the foregoing embodiments. The technical effects that can be achieved by the memory system of the foregoing embodiments can also be achieved by the operation method of the memory system, which will not be described here in detail. As to the operation method in the foregoing embodiments, the specific implementation of each step has been described in detail in the related device embodiments, which will not be described in detail here.

[0093] Based on the foregoing memory system, the embodiments of the present disclosure further provide an electronic device, comprising: the memory system in any of the foregoing embodiments; and a host coupled to the memory system.

[0094] Based on the foregoing memory system, the embodiments of the present disclosure further provide a computer-readable storage medium, which stores instructions. When the instructions are executed by a processor, the operation method in any of the foregoing embodiments is implemented.

[0095] Here, to implement all or part of the flow of the operation method in the foregoing embodiments, the hardware related to the instructions (for example, a computer program) can be used, and the computer program can be stored in a computer-readable storage medium. The execution of the computer program can include the flow of the operation method in any of the foregoing embodiments. The computer-readable storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD), or a solid state disk, etc. The computer-readable storage medium can also include a combination of the foregoing storage media.

[0096] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily mean the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the size of the sequence number of each process does not mean the execution order, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence number of the foregoing embodiments of the present disclosure is only for description, not representing the advantages and disadvantages of the embodiments.

[0097] It should be noted that, in the present document, the terms "comprising", "comprising" or any other variant thereof are intended to cover non-exclusive inclusions, so that a process, method, article, or apparatus that comprises a list of elements not only includes those elements, but also includes other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0098] The above description is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered by the protection scope of the present disclosure.

Claims

1. A memory system, characterized by, The memory includes a memory cell array and a peripheral circuit coupled with the memory cell array, the peripheral circuit including a page buffer; The memory controller is coupled with the memory, and is configured to: read data from the memory cell array in response to a first read request including a first logical address, and store the read data through the page buffer, the data including all data stored in a physical page pointed by a first physical address corresponding to the first logical address; read data corresponding to a second logical address from the page buffer in response to a second read request including the second logical address; wherein the second logical address and the first logical address are related. The memory controller is specifically configured to:

2. The memory system of claim 1, wherein, determine the first physical address corresponding to the first logical address in response to the first read request, send a first read command and the first physical address to the peripheral circuit; determine a second physical address corresponding to the second logical address in response to the second read request, send a second read command and the second physical address to the peripheral circuit; The peripheral circuit is configured to: read N logical page data stored in a physical page pointed by the first physical address in the memory cell array in response to the first read command and the first physical address, N being an integer greater than 1; latch the N logical page data to N first latches of the page buffer, respectively; read the logical page data in the N first latches in response to the second read command and the second physical address. The N first latches include (N-1) data latches and a cache latch; 3. The memory system of claim 2, wherein, The data latches are configured to latch one of (N-1) logical page data in the N logical page data; The cache latch is configured to latch the remaining one of the N logical page data; The peripheral circuit is specifically configured to: in response to the second read command and the second physical address, transmit the logical page data latched by at least one of the (N-1) data latches to the cache latch; wherein the second read command is used to instruct to read at least one of the (N-1) logical page data; control the cache latch to output the logical page data transmitted by the at least one data latch. The peripheral circuit is further configured to:

4. The memory system of claim 3, wherein, reset the at least one data latch after transmitting the logical page data latched by the at least one data latch to the cache latch. The page buffer further includes a second latch; and the peripheral circuit is further configured to:

5. The memory system of claim 4, wherein, control the cache latch to transmit the remaining one of the logical page data latched by the cache latch to the second latch before transmitting the logical page data latched by the at least one data latch to the cache latch; reset the cache latch. The peripheral circuit is further configured to:

6. The memory system of claim 5, wherein, ​ After resetting the at least one data latch, the remaining one logical page data latched by the second latch is transmitted to the data latch.

7. The memory system of claim 1, wherein, The memory controller is further configured to: determine whether the second logical address is related to the first logical address; read the data corresponding to the second logical address stored in the page buffer in response to the second logical address being related to the first logical address.

8. The memory system according to claim 1 or 7, wherein The memory controller is further configured to: determine whether the first read request is a single logical page read request; store the read data into the page buffer in response to the first read request being a single logical page read request.

9. The memory system of claim 8, wherein, The memory controller is specifically configured to: send a command to the peripheral circuit to store the read data into the page buffer in response to the first read request being a single logical page read request.

10. The memory system of claim 8, wherein, The memory controller comprises: a first determination circuit configured to determine whether the second logical address is related to the first logical address; a second determination circuit configured to determine whether the first read command is a single logical page read request.

11. The memory system of claim 1, wherein, The second logical address is related to the first logical address, including: the first physical address and a second physical address corresponding to the second logical address point to a same physical page.

12. An operating method of a memory system, characterized by, The memory system comprises a memory and a memory controller coupled to the memory; The memory comprises a memory cell array and a peripheral circuit coupled to the memory cell array, the peripheral circuit comprising a page buffer; the operation method comprises: in response to a first read request comprising a first logical address, controlling the peripheral circuit to read data stored in the memory cell array and store the read data through the page buffer; wherein the data comprises all data stored in a physical page pointed to by a first physical address corresponding to the first logical address; in response to a second read request comprising a second logical address, controlling the peripheral circuit to read data corresponding to the second logical address in the page buffer; wherein the second logical address is related to the first logical address.

13. The method of operation of claim 12, wherein, The response to the first read request comprising a first logical address, controlling the peripheral circuit to read data stored in the memory cell array and store the read data through the page buffer, comprises: in response to the first read request, determining a first physical address corresponding to the first logical address, sending a first read command and the first physical address to the peripheral circuit; the peripheral circuit reads N logical page data stored in a physical page pointed to by the first physical address in the memory cell array in response to the first read command and the first physical address, N being an integer greater than 1; the peripheral circuit latches the N logical page data into N first latches of the page buffer respectively; the response to the second read request comprising a second logical address, controlling the peripheral circuit to read data corresponding to the second logical address in the page buffer, comprises: In response to the second read request, determining a second physical address corresponding to the second logical address, sending a second read command and the second physical address to the peripheral circuit; The peripheral circuit reads the corresponding logical page data in the N first latches in response to the second read command and the second physical address.

14. The method of claim 13, wherein, The N first latches include (N-1) data latches and a cache latch; the operation method further comprises: The data latch latches one logical page data of (N-1) logical page data in the N logical page data; The cache latch latches the remaining one logical page data in the N logical page data; The peripheral circuit reads the corresponding logical page data in the N first latches in response to the second read command and the second physical address, comprising: The peripheral circuit controls at least one data latch of the (N-1) data latches to transmit the latched logical page data to the cache latch in response to the second read command and the second physical address; wherein the second read command is used to instruct to read at least one logical page data of the (N-1) logical page data; The peripheral circuit controls the cache latch to output the logical page data transmitted by the at least one data latch.

15. The method of operation of claim 14, wherein, The operation method further comprises: After transmitting the logical page data latched by the at least one data latch to the cache latch, the peripheral circuit resets the at least one data latch.

16. The method of operation of claim 15, wherein, The page buffer further comprises a second latch; the operation method further comprises: Before transmitting the logical page data latched by the at least one data latch to the cache latch, the peripheral circuit controls the cache latch to transmit the latched remaining one logical page data to the second latch; The peripheral circuit resets the cache latch.

17. The method of operation of claim 16, wherein, The operation method further comprises: After resetting the at least one data latch, the peripheral circuit transmits the remaining one logical page data latched by the second latch to the data latch.

18. The method of claim 12, wherein, The operation method further comprises: Determine whether the second logical address and the first logical address are related; In response to the second logical address and the first logical address being related, read the data corresponding to the second logical address stored in the page buffer.

19. The method of operating according to claim 12 or 18, characterized in that, The operation method further comprises: Determine whether the first read request is a single logical page read request; In response to the first read request being a single logical page read request, store the read data to the page buffer.

20. The method of operation of claim 19, wherein, The response to the first read request being a single logical page read request, storing the read data to the page buffer, comprises: In response to the first read request being a single logical page read request, send a command to the peripheral circuit to store the read data to the page buffer.

21. An electronic device, comprising: Comprise: The memory system of any one of claims 1 to 11; A host coupled to the memory system.

22. A computer-readable storage medium, characterized in that, The computer readable storage medium stores instructions, which, when executed by a processor, implement the operation method of any one of claims 12 to 20.

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