Memory device and memory control circuit

Abstract

The invention provides a memory device and a memory control circuit. The memory control circuit is used for controlling a memory cell array. The processing circuit of the memory control circuit is used for obtaining a mapping group through a namespace table according to a namespace and a logic address. The processing circuit is used for obtaining a block group and a mapping entry through a logic-to-virtual mapping table according to the mapping group and the offset of the logic address in the mapping group. The processing circuit is used for obtaining a super block according to the block group and the virtual block through a virtual-to-entity block mapping table. The processing circuit is configured to obtain a physical block according to the super block, the channel, the die and the plane through the virtual-to-physical block mapping table.

Description

TECHNICAL FIELD

[0001] The present application relates to an electronic device and a control circuit, and particularly relates to a memory device and a memory control circuit. BACKGROUND

[0002] For an 8TB capacity memory cell array, a 32-bit addressing technique can be used to define an address of a 4KB data block. However, for a 16TB (or higher) capacity memory cell array, the number of bits for addressing must be increased, and cannot be maintained at 32 bits.

[0003] Although the industry has developed an endurance group addressing technique to maintain the amount of data addressed at 32 bits. However, the endurance group addressing technique causes the problem of halving (or even lower) the write efficiency. For example, assuming that we have two endurance groups, because the writing between the groups does not interfere with each other, the writing on each group only uses half of the channels. Therefore, researchers are working to develop a new addressing technique, which aims to enable a 16TB (or higher) capacity memory cell array to still use 32 bits for addressing, and to maintain the write efficiency. SUMMARY

[0004] The present application relates to a memory device and a memory control circuit, which through the operation of a namespace table, a logic to virtual mapping table, and a virtual to physical block table, a 16TB (or higher) capacity memory cell array can use 32-bit virtual addresses, without increasing the number of bits for addressing, and without reducing the write efficiency.

[0005] According to one aspect of the present application, a memory control circuit is provided. The memory control circuit is used to control a memory cell array. The memory control circuit includes a storage unit and a processing circuit. The storage unit is used to store a namespace table, a logic to virtual mapping table, and a virtual to physical block mapping table. The processing circuit is connected to the storage unit. The processing circuit is used to obtain a mapping group identification according to a namespace identification and a logical address by the namespace table; obtain a block group identification and a mapping entry according to the mapping group identification and an offset of the logical address in the mapping group identification by the logic to virtual mapping table; obtain a super block identification according to the block group identification and a virtual block by the virtual to physical block mapping table; and obtain a physical block number according to the super block identification and the virtual block by the virtual to physical block mapping table.

[0006] According to another aspect of the present application, a memory control circuit is provided. The memory control circuit is used to control a memory cell array. The memory control circuit includes a storage unit and a processing circuit. The storage unit is used to store a namespace table, a logic to virtual mapping table, and a virtual to physical block mapping table. The processing circuit is connected to the storage unit. The processing circuit is used to obtain a mapping group identification according to a namespace identification and a logical address by the namespace table; obtain a block group identification and a mapping entry according to the mapping group identification and an offset of the logical address in the mapping group identification by the logic to virtual mapping table; obtain a physical block number according to the block group identification and a virtual block by the virtual to physical block mapping table.

[0007] According to yet another aspect of the present application, a memory device is provided. The memory device includes a memory cell array and a memory control circuit. The memory control circuit is configured to control the memory cell array. The memory control circuit includes a storage unit and a processing circuit. The storage unit is configured to store a namespace table, a logic to virtual mapping table, and a virtual to physical block table. The processing circuit is connected to the storage unit. The processing circuit is configured to obtain a mapping group identification according to a namespace identification and a logical address by the namespace table; obtain a block group identification and a mapping entry according to the mapping group identification and an offset of the logical address in the mapping group identification by the logic to virtual mapping table; obtain a super block identification according to the block group identification and a virtual block by the virtual to physical block table; and obtain a physical block number according to the super block identification and the virtual block by the virtual to physical block table.

[0008] For better understanding of the above objects and other aspects of the present application, a more particular description of the preferred embodiments will follow, referring to the accompanying drawings in which: BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 FIG. 1 shows a schematic diagram of a memory device 200 and a host 100 according to an embodiment of the present application.

[0010] Figure 2 FIG. 2 shows a system architecture diagram of a memory cell array 220 according to an embodiment of the present application.

[0011] Figure 3 FIG. 3 shows a schematic diagram of a virtual to physical block table V2PBT according to an embodiment of the present application.

[0012] Figure 4 FIG. 4 shows a schematic diagram of a logic to virtual mapping table L2VMT according to an embodiment of the present application.

[0013] Figure 5 The relationship between the logical-to- virtual mapping table L2VMT and the virtual-to-physical block mapping table V2PBT is illustrated.

[0014] Figure 6 A namespace table (NST) according to an embodiment of the application is illustrated.

[0015] Figure 7 The application of the namespace table NST and the logical-to- virtual mapping table L2VMT in a read operation is illustrated.

[0016] Figure 8 The application of the logical-to- virtual mapping table L2VMT and the virtual-to-physical block mapping table V2PBT in a read operation is illustrated.

[0017] Figure 9 A flowchart of a read operation according to an embodiment of the application is illustrated.

[0018] Figure 10 The application of the namespace table NST in a write operation is illustrated.

[0019] Figure 11 The application of the virtual-to-physical block mapping table V2PBT in a write operation is illustrated.

[0020] Figure 12 The application of the write buffer WB in a write operation is illustrated.

[0021] Figure 13 The application of the logical-to- virtual mapping table L2VMT and the virtual-to-physical block mapping table V2PBT in a write operation is illustrated.

[0022] Figure 14 A flowchart of a write operation according to an embodiment of the application is illustrated.

[0023] Figure 15 The application of the virtual-to-physical block mapping table V2PBT in a garbage collection operation is illustrated.

[0024] Figure 16 The application of the buffer bfgc in a garbage collection operation is illustrated.

[0025] Figure 17 The application of the namespace table NST and the logical-to- virtual mapping table L2VMT in a garbage collection operation is illustrated.

[0026] Figure 18 The application of the namespace table NST and the virtual-to-physical block mapping table V2PBT in a garbage collection operation is illustrated.

[0027] Figure 19 A flowchart illustrating a garbage collection operation according to an embodiment of the present application.

[0028] Figure 20 A virtual-to-physical block mapping table V2PBT' according to another embodiment of the present application is illustrated.

[0029] Legend:

[0030] 100: host

[0031] 200: memory device

[0032] 210: memory control circuitry

[0033] 211: host interface

[0034] 212: memory interface

[0035] 213: storage circuitry

[0036] 214: cache circuitry

[0037] 215: processing circuitry

[0038] 220: memory cell array

[0039] bf0, bf1, bfgc: buffer area

[0040] BGID: block group

[0041] BLK: data block

[0042] CH: channel

[0043] CT: count

[0044] DE: die

[0045] DT: data

[0046] EC: erase count

[0047] IX: index

[0048] L2VMT: logical-to- virtual mapping table

[0049] LA: logical address

[0050] ME: mapping entry

[0051] MGID: mapping group

[0052] NSID: namespace

[0053] NST: namespace table

[0054] PBN: physical block

[0055] PA: physical address

[0056] PG: page

[0057] PL: plane

[0058] PO: pool of unused superblocks

[0059] S110, S120, S130, S140, S150, S210, S220, S230, S240, S250, S260, S270, S280, S310, S320, S330, S340, S350, S360, S370, S380: step

[0060] SBID: superblock

[0061] SBID': superblock offset

[0062] SI: start index

[0063] ST: usage status

[0064] V2PBT, V2PBT': virtual-to-physical block mapping table

[0065] VA: virtual address

[0066] VBN: virtual block

[0067] VC: valid count

[0068] WB: cache

[0069] (1), (2), (3-a), (3-b), (4), (4-a), (5), (6-a), (6-b): mark DETAILED DESCRIPTION

[0070] The technical terms in the present specification are in reference to the conventional terms in the technical field, and the interpretation of the terms in the present specification is in reference to the description or definition in the present specification. Each of the embodiments of the present application has one or more technical features. The skilled in the art can selectively implement some or all of the technical features in any of the embodiments, or selectively combine some or all of the technical features in the embodiments, under the premise of possibility.

[0071] Please refer to Figure 1Fig. 1 illustrates a schematic diagram of a memory device 200 and a host 100 according to an embodiment. The memory device 200 is connected to the host 100. The memory device 200 includes a memory control circuit 210 and a memory cell array 220. The memory control circuit 210 includes a storage unit (including a storage circuit 213 and a cache circuit 214), a processing circuit 215, a host interface 211, and a memory interface 212.

[0072] The storage circuit 213 (or the cache circuit 214) is used to store data required for managing the memory cell array 220, such as a Dynamic Random Access Memory (DRAM). The cache circuit 214 (or the storage circuit 213) is used to cache data to be read or written, such as a Static Random Access Memory (SRAM). The host interface 211 is used to communicate with the host 100. The memory interface 212 is used to communicate with the memory cell array 220. The memory control circuit 210 is used to control Read operation, Write operation, Garbage collection, error correction, and the like of the memory cell array 220.

[0073] Please refer to Figure 2 Fig. 2 illustrates a system architecture diagram of the memory cell array 220 according to an embodiment. In this embodiment, an Endurance group, such as the one including the namespace NSIDs numbered "1", "2", but not limited to, is included. The namespace NSID numbered "1" is, for example, corresponding to the block group BGIDs numbered "0", "1", but not limited to. The namespace NSID numbered "2" is, for example, corresponding to the block group BGIDs numbered "0", "1", but not limited to.

[0074] A Super Block Identification SBID is composed of physical blocks from each plane of the memory cell array 220. Each channel CH includes a plurality of dies DE, each die DE includes a plurality of planes PL, and each plane PL includes a plurality of blocks BLK. Each block group BGID can achieve the maximum write bandwidth in each namespace NSID.

[0075] Referring to Figure 3 Fig. 1 illustrates a Virtual to Physical Block Table (V2PBT) according to an embodiment of the present application. In the Virtual to Physical Block Table (V2PBT), one number of Block Group BGID corresponds to multiple numbers of Virtual Block VBN. For example, Block Group BGID numbered "0" corresponds to Virtual Block VBN numbered "0" to "255"; Block Group BGID numbered "1" also corresponds to Virtual Block VBN numbered "0" to "255".

[0076] Virtual Block VBN corresponds to one number of Super Block SBID. For example, in Block Group BGID numbered "0", Virtual Block VBN numbered "0" corresponds to Super Block SBID numbered "2"; in Block Group BGID numbered "0", Virtual Block VBN numbered "255" corresponds to Super Block SBID numbered "511"; in Block Group BGID numbered "1", Virtual Block VBN numbered "0" corresponds to Super Block SBID numbered "1"; in Block Group BGID numbered "1", Virtual Block VBN numbered "255" corresponds to Super Block SBID numbered "234".

[0077] In Block Group BGID numbered "0" and Block Group BGID numbered "1", Super Block SBID numbered "0" to "511".

[0078] Each number of Super Block SBID corresponds to Physical Block Number PBN of different Plane PL. For example, Super Block SBID numbered "0" corresponds to Physical Block PBN numbered "0" of Channel CH numbered "0", Die DE numbered "0" and Plane PL numbered "0". Super Block SBID numbered "0" corresponds to Physical Block PBN numbered "0" of Channel CH numbered "0", Die DE numbered "0" and Plane PL numbered "1".

[0079] Each number of Super Block SBID records its Status ST as "Free" or "Used". These Status STs are used for block allocation in write operation or garbage collection operation.

[0080] Each numbered super block SBID is recorded with its valid count (Valid Count) VC and erase count (Erase Count) EC. These valid count VC and erase count EC are used for block allocation in a write operation or a garbage collection operation.

[0081] Through the design of the virtual-to-physical block mapping table V2PBT, the processing circuit 215 can obtain a super block SBID according to a block group BGID and a virtual block VBN through the virtual-to-physical block mapping table V2PBT, and obtain a physical block PBN according to the super block SBID, a channel CH, a die DE, and a plane PL.

[0082] Please refer to Figure 4 , which shows a schematic diagram of a logic-to-virtual mapping table (Logic to Virtual Mapping Table) L2VMT according to an embodiment of the present application. The logic-to-virtual mapping table L2VMT is numbered with multiple mapping group (Mapping Group Identification) MGIDs. For example, each number of the mapping group MGID corresponds to a data amount of 2 GB, and each mapping entry (mapping entry) ME is used to map 4 KB of data. In each number of the mapping group MGID, there are 524288 mapping entries ME.

[0083] In the logic-to-virtual mapping table L2VMT, multiple numbers of the mapping group MGID correspond to multiple numbers of the block group BGID in a round robin policy. For example, in the case where the block group BGID has two numbers "0" and "1", the even numbers of the mapping group MGID correspond to the number "0" of the block group BGID, and the odd numbers of the mapping group MGID correspond to the number "1" of the block group BGID. The round robin policy is only an example and does not limit the present application. For example, N consecutive numbers of the mapping group MGID can be grouped into the same block group BGID.

[0084] Each mapping entry ME corresponds to a set of 32-bit virtual address (virtual address) VA. The 32-bit virtual address VA is composed of channel CH, die DE, plane PL, virtual block VBN, page PG and block BLK. In the embodiment, the virtual address VA can be maintained at 32 bits regardless of the capacity of the storage unit array 220. For example, if the capacity of the storage unit array 220 is 16 TB, the block group BGID has 2 numbers, and in a virtual address VA, the number of channel CH occupies 4 bits, the number of die DE occupies 3 bits, the number of plane PL occupies 2 bits, the number of virtual block VBN occupies 8 bits, the number of page PG occupies 13 bits, and the number of block BLK occupies 2 bits. If the capacity of the storage unit array 220 is 32 TB, the block group BGID has 4 numbers, and in a virtual address VA, the number of channel CH occupies 4 bits, the number of die DE occupies 4 bits, the number of plane PL occupies 2 bits, the number of virtual block VBN occupies 7 bits, the number of page PG occupies 13 bits, and the number of block BLK occupies 2 bits.

[0085] Similarly, if the capacity of the storage unit array 220 is 8 TB or a multiple thereof, the number of block groups BGID is set according to the multiple of 8 TB. If the capacity of the storage unit array 220 is 8 x 2 N TB (N is a natural number), assuming that M bits are needed for block addressing in 8 TB, the virtual block VBN will occupy M-N bits.

[0086] Please refer to Figure 5 , which illustrates the relationship between the logical-to-virtual mapping table L2VMT and the virtual-to-physical block mapping table V2PBT. Through the design of the logical-to-virtual mapping table L2VMT and the virtual-to-physical block mapping table V2PBT, the processing circuit 215 can correspond the logical address (Logical address) LA to the virtual address VA through the logical-to-virtual mapping table L2VMT, and correspond the virtual address VA to the physical address (Physical address) PA through the virtual-to-physical block mapping table V2PBT.

[0087] Please refer to Figure 6The figure illustrates a Namespace Table (NST) according to an embodiment of the present application. In the Namespace Table (NST), one number of a Namespace NSID corresponds to one or more numbers of a Mapping Group MGID. Each number of a Mapping Group MGID corresponds to a data amount of 2 GB. For example, in the Namespace Table (NST), the start index SI and the count CT of the Namespace NSID numbered "1" are 0 and 4, respectively, so the index IX of the Namespace NSID numbered "1" corresponds to "0", "1", "2", "3", i.e., the Mapping Group MGID numbered "0", "1", "2", "3". The start index SI and the count CT of the Namespace NSID numbered "3" are 4 and 3, respectively, so the index IX of the Namespace NSID numbered "3" corresponds to "4", "5", "6", i.e., the Mapping Group MGID numbered "10", "11", "4". The start index SI and the count CT of the Namespace NSID numbered "6" are 7 and 2, respectively, so the index IX of the Namespace NSID numbered "6" corresponds to "7", "8", i.e., the Mapping Group MGID numbered "5", "9".

[0088] One number of a Mapping Group MGID corresponds to one number of a Block Group BGID (illustrated in Figure 5 ).

[0089] Through the design of the above-mentioned Namespace Table (NST), Logical-to-Virtual Mapping Table (L2VMT) and Virtual-to-Physical Block Mapping Table (V2PBT), a storage unit array 220 with a capacity of 16 TB (or higher) can still use 32 bits for addressing and maintain write efficiency.

[0090] In addition, one Super Block Identification (SBID) is composed of physical blocks from each plane of the storage unit array 220. The Super Block Identification (SBID) can support global wear leveling.

[0091] In order to more clearly illustrate the technology of the present application, the following will be described in detail with respect to a Read operation, a Write operation and a Garbage collection operation, respectively. Figures 7-9 to illustrate a Read operation, Figures 10-14 to illustrate a Write operation, Figures 15-19 to illustrate a Garbage collection operation.

[0092] Please refer to Figure 7, which illustrates the conversion between the namespace table NST and the logical to virtual mapping table L2VMT in a read operation. Figure 7 In the example of , each number of the mapping group MGID corresponds to 524288 mapping entries ME and corresponds to two numbers of the block group BGID.

[0093] The following example uses the data with namespace NSID "1" and logical address LA "2000000" as an example. Figure 7 As shown in the mark (1), in the namespace table NST, the starting index SI and the quantity CT of the namespace NSID numbered "1" are 0 and 4 respectively, so the indexes corresponding to the namespace NSID numbered "1" are "0", "1", "2", and "3", that is, the mapping groups MGID numbered "0", "1", "2", and "3".

[0094] Each mapping group MGID corresponds to 524,288 mapping entries ME. The logical address LA is "2000000." The division of 2000000 / 524,288 yields a quotient of "3." In other words, the logical address LA of "2000000" corresponds to the fourth mapping group MGID (i.e., mapping group MGID numbered "3").

[0095] Next, refer to Figure 7 As shown in the mark (2), the logical address LA is "2000000", and after the modulus operation (MOD) of 2000000% 524288, "427136" can be obtained. In other words, the logical address LA of "2000000" corresponds to the 427136th mapping entry ME in the mapping group MGID numbered "3".

[0096] Then, please refer to Figure 8 , which illustrates the conversion of the logical to virtual mapping table L2VMT and the virtual to physical block mapping table V2PBT in a read operation. Figure 8 As shown by the mark (3), after obtaining the mapping group MGID numbered "3", "1" can be obtained through the modulus operation of 3% 2. In other words, the mapping group MGID numbered "3" corresponds to the block group BGID numbered "1".

[0097] The 427136th mapping entry ME in the mapping group MGID numbered "3" corresponds to a virtual address VA of "(10, 3, 2, 123, 500, 2)". In the virtual address VA of "(10, 3, 2, 123, 500, 2)", the number of the channel CH is "10", the number of the die DE is "3", the number of the plane PL is "2", and the number of the virtual block VBN is "123". According to the virtual-to-physical block mapping table V2PBT, the super block SBID numbered "234" can be obtained according to the block group BGID numbered "1" and the virtual block VBN numbered "123".

[0098] Then, referring to the label (4) of Figure 8 , according to the virtual-to-physical block mapping table V2PBT, the physical block PBN numbered "262" can be obtained according to the channel CH numbered "10", the die DE numbered "3", the plane PL numbered "2", and the super block SBID numbered "234".

[0099] According to the above description, through the technology of the present application, during the read operation of the 16TB (or higher) capacity storage unit array 220, 32 bits can still be used for addressing without the need to increase the number of bits for addressing. The following is a flowchart illustrating the read operation of the present application.

[0100] Please refer to Figure 9 , which illustrates the flowchart of the read operation according to an embodiment of the present application. Figure 9 The read operation of Figure 7 includes steps S110-S150. In step S110, referring to the label (1) of , the processing circuit 215 obtains the mapping group MGID according to the namespace NSID and the logical address LA through the namespace table NST.

[0101] Figure 7 Next, in step S120, referring to the label (2) of , the processing circuit 215 obtains the block group BGID and the mapping entry ME according to the offset of the mapping group MGID in the mapping group MGID through the logical-to-virtual mapping table L2VMT. The virtual address VA corresponding to the mapping entry ME records the channel CH, the die DE, the plane PL, and the virtual block VBN.

[0102] Figure 8 Then, in step S130, referring to the label (3) of , the processing circuit 215 obtains the super block SBID according to the block group BGID and the virtual block VBN through the virtual-to-physical block mapping table V2PBT.

[0103] Next, in step S140, the processing circuit 215 refers to the mapping table V2PBT to obtain the physical block PBN according to the super block SBID, the channel CH, the die DE, and the plane PL. Figure 8

[0104] Then, in step S150, the storage unit array 220 is accessed according to the channel CH, the die DE, the plane PL, the page PG, the data block BLK, and the physical block PBN of the mapping entry ME, and the data is returned to the host 100.

[0105] The above steps S110-S150 complete the read operation, but the above steps S110-S150 are not intended to limit the application of the present technology to the read operation. The application of the present technology to the write operation is further described below.

[0106] Figure 10 Figure 10

[0107] The following describes an example of writing data into the namespace NSID "1" and the logical address LA "2000000". As shown in reference numeral (1) of FIG. 10, the start index SI and the number CT of the namespace NSID "1" in the namespace table NST are 0 and 4, respectively. Therefore, the indexes corresponding to the namespace NSID "1" are "0", "1", "2", and "3", i.e., the mapping group MGID "0", "1", "2", and "3". Figure 10

[0108] As shown in reference numeral (2) of FIG. 10, after the mapping group MGID "3" is obtained, the modulus operation 3%2 is performed to obtain "1". That is, the mapping group MGID "3" corresponds to the block group BGID "1".

[0109] Figure 10

[0110] Figure 11 ​​​​​​​​An example of the application of the virtual-to-physical block mapping table V2PBT in a write operation is illustrated in FIG. 3. Referring to Figure 11 The superblock SBID with the smallest number of erase counts EC is selected from the pool of unused superblocks PO (i.e., superblocks SBID with a status of "unused") as the opened superblock. For example, the superblock SBID numbered "123" with an erase count EC of "10" is selected as the opened superblock.

[0111] Next, referring to Figure 11 A virtual block VBN that has not been paired to a superblock SBID (i.e., corresponding to a number "-1") is selected from the block group BGID numbered "1". For example, the virtual block VBN numbered "23" is selected. In this action, the virtual block VBN numbered "23" is modified to correspond to the superblock SBID numbered "123".

[0112] Then, referring to Figure 11 The status ST of the selected superblock SBID numbered "123" is modified to "used".

[0113] Next, referring to Figure 12 which illustrates the application of the write buffer WB in a write operation. The write buffer WB includes buffer areas bfO and bfl. The buffer area bfO corresponds to the block group BGID numbered "0", and the buffer area bfl corresponds to the block group BGID numbered "1".

[0114] Referring to Figure 12 The data DT to be written is received from the host 100 (illustrated in Figure 1 ) at the logical address LA. Since the logical address LA corresponds to the block group BGID numbered "1", the data DT to be written is stored in the buffer area bfl.

[0115] Next, referring to Figure 12 When the write buffer WB is full, the data is written from the write buffer WB to the opened superblock corresponding to the block group BGID numbered "1". For example, the opened superblock corresponds to the virtual block VBN numbered "20".

[0116] Next, referring to Figure 13 which illustrates the application of the logical-to-virtual mapping table L2VMT and the virtual-to-physical block mapping table V2PBT in a write operation. Referring to Figure 13As shown by the mark (5), the logical address LA of "2000000" corresponds to the 427136th mapping entry ME in the mapping group MGID numbered "3". The 427136th mapping entry ME in the mapping group MGID numbered "3" originally corresponds to the virtual address VA of "(1, 1, 2, 45, 88, 0)". According to the address written in the foregoing, the 427136th mapping entry ME in the mapping group MGID numbered "3" is changed to correspond to the virtual address VA of "(5, 6, 2, 20, 300, 3)".

[0117] Next, referring to Figure 13 As shown by the mark (6-a), according to the virtual-to-physical block mapping table V2PBT, the super block SBID numbered "234" can be corresponded according to the block group BGID numbered "1" and the virtual block VBN numbered "20". The valid count VC of the super block SBID numbered "234" is increased by 1. As shown by the mark (6-b) of Figure 13 As shown by the mark (6-a), according to the virtual-to-physical block mapping table V2PBT, the super block SBID numbered "234" can be corresponded according to the block group BGID numbered "1" and the virtual block VBN numbered "20". The valid count VC of the super block SBID numbered "234" is increased by 1. As shown by the mark (6-b) of

[0118] According to the foregoing description, by the technology of the present application, in the process of performing the write operation on the storage unit array 220 with a capacity of 16 TB (or higher), 32 bits can still be used for addressing without the need to increase the number of bits for addressing. The write operation of the present application is further described by a flowchart as follows.

[0119] Please refer to Figure 14 which shows a flowchart of the write operation according to an embodiment of the present application. Figure 14 The write operation of the present application includes steps S210-S280. In step S210, as shown by the marks (1), (2) of Figure 10 According to the foregoing description, by the technology of the present application, in the process of performing the write operation on the storage unit array 220 with a capacity of 16 TB (or higher), 32 bits can still be used for addressing without the need to increase the number of bits for addressing. The write operation of the present application is further described by a flowchart as follows.

[0120] Next, in step S220, it is determined whether the open superblock corresponding to the block group BGID is unassigned or full. If the open superblock corresponding to the block group BGID is unassigned or full, the process proceeds to step S230. If the open superblock corresponding to the block group BGID is assigned and not full, the process proceeds to step S250.

[0121] In step S230, refer to Figure 11 As shown in the mark (3-a), the super block SBID with the smallest erase count EC is selected as the open super block.

[0122] Then, in step S240, referring to Figure 11 As shown in the mark (3-b), the virtual block VBN that has not been matched to the super block SBID is selected from the block group BGID. Figure 11 As shown in the mark (3-c), the usage status ST of the selected super block SBID will be changed to "Used".

[0123] Next, in step S250, referring to Figure 12 As shown in the mark (4), it is determined whether the buffer WB has been filled with a predetermined amount of data (for example, a page). If the buffer WB has been filled with the predetermined amount of data, the process proceeds to step S260.

[0124] In step S260, refer to Figure 12 As shown in the mark (4-a), data is written from the buffer WB to the open super block of this block group BGID.

[0125] Next, in step S270, refer to Figure 12 As shown in the mark (5), the virtual address VA of the logical to virtual mapping table L2VMT is updated according to the open super block of this block group BGID.

[0126] Then, in step S280, referring to Figure 12 As shown in the marks (6-a) and (6-b), the valid count VC of the super block SBID is updated.

[0127] The write operation can be completed through the above steps S210 to S280, but the above steps S210 to S280 are not intended to limit the application of the present invention to the write operation. The application of the present invention to the garbage collection operation is further described below.

[0128] Please refer to Figure 15 , which illustrates the application of the virtual to physical block mapping table V2PBT in garbage collection operations. Figure 15As shown in the mark (1) of FIG. 10, a virtual block VBN (or a superblock SBID) corresponding to the state ST of "used" and the valid count VC of "453" is selected as a victim superblock.

[0129] Next, please refer to Figure 16 which illustrates the application of the buffer bfgc in the garbage collection operation. Please refer to Figure 16 As shown in the mark (2) of FIG. 11, valid data is read from the victim superblock to the buffer bfgc.

[0130] Then, please refer to Figure 16 As shown in the mark (3) of FIG. 12, when the buffer bfgc is full of a predetermined data amount (for example, one page), the data is written from the buffer bfgc to an opened superblock of the block group BGID numbered "1", for example, a virtual block VBN numbered "20".

[0131] Next, please refer to Figure 17 which illustrates the application of the namespace table NST and the logical-to-virtual mapping table L2VMT in the garbage collection operation. Please refer to Figure 17 As shown in the mark (4) of FIG. 13, the virtual address VA of the logical-to-virtual mapping table L2VMT is updated according to the moved data.

[0132] Then, please refer to Figure 18 which illustrates the application of the namespace table NST and the virtual-to-physical block mapping table V2PBT in the garbage collection operation. Please refer to Figure 18 As shown in the mark (5) of FIG. 14, the state of the superblock SBID numbered "300" selected as the victim superblock is modified to "unused", and the valid count VC is modified to "0". Meanwhile, the superblock SBID numbered "300" is added to the unused superblock pool PO.

[0133] According to the above description, by the technology of the present application, in the process of the garbage collection operation of the storage unit array 220 with a capacity of 16 TB (or higher), 32 bits can still be used for addressing without the need to increase the number of bits for addressing. The garbage collection operation of the present application is described below in a flowchart.

[0134] Please refer to Figure 19 which illustrates the flowchart of the garbage collection operation according to an embodiment of the present application. Figure 19 The garbage collection operation of the present application includes steps S310-S380. In step S310, please refer toFigure 15 As shown in the mark (1), within a certain block group BGID, the block with the usage status ST as "used" and the lowest valid count VC is selected as the victim super block.

[0135] Next, in step S320, refer to Figure 16 As shown in mark (2), valid data is read from the victim super block to the cache area bfgc.

[0136] Then, in step S330, it is determined whether the open super block corresponding to the block group BGID is unassigned or full. If so, the process proceeds to step S340. If so, the process proceeds to step S360.

[0137] In step S340 , the super block SBID with the smallest erase count EC is selected as the open super block.

[0138] Next, in step S350, a virtual block VBN that has not been mapped to a super block SBID is selected from the block group BGID. At this time, the usage status ST of the selected super block SBID is modified to "Used".

[0139] Then, in step S360, referring to Figure 16 As shown in mark (3), data is written from the cache bfgc to the open super block of this block group BGID.

[0140] Next, in step S370, refer to Figure 17 As shown in the mark (4), the virtual address VA of the logic-to-virtual mapping table L2VMT is updated according to the moved data.

[0141] Then, in step S380, refer to Figure 18 As shown in the mark (5), the status of the super block SBID selected as the victim super block is changed to "unused" and the valid count VC is changed to "0".

[0142] Garbage collection can be completed through the above steps S310 to S380, but the above steps S310 to S380 are not intended to limit the application of the technology of the present invention to garbage collection.

[0143] Please refer to Figure 20Fig. 6 illustrates a virtual-to-physical block mapping table V2PBT' according to another embodiment of the present application. In another embodiment, the virtual block VBN described above can not be used. In the virtual-to-physical block mapping table V2PBT' of this embodiment, one number of the block group BGID corresponds to a plurality of numbers of the super block offset SBID'. For example, the block group BGID numbered "0" corresponds to the super block offset SBID' numbered "0" to "255"; the block group BGID numbered "1" also corresponds to the super block offset SBID' numbered "0" to "255".

[0144] With the design of the virtual-to-physical block mapping table V2PBT', the processing circuit 215 described above can obtain the physical block PBN according to the block group BGID, the super block offset SBID', the channel CH, the die DE and the plane PL through the virtual-to-physical block mapping table V2PBT'.

[0145] According to the above embodiments, through the operations of the namespace table NST, the logical-to-virtual mapping table L2VMT and the virtual-to-physical block mapping table V2PBT, the 16 TB (or higher) capacity storage unit array 220 can use 32-bit virtual addresses VA without increasing the number of bits for addressing and without reducing the write efficiency.

[0146] The above disclosure provides different features for implementing some embodiments or examples of the present application. The specific examples of components and configurations described above (e.g., the mentioned numerical values or names) are to simplify / suggest some embodiments of the present application. Of course, such components and configurations are only examples and are not intended to be limiting. In addition, some embodiments of the present application can repeatedly refer to symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0147] In summary, although the present application has been disclosed as above with embodiments, it is not intended to limit the present application. Those skilled in the art of the present application can make various modifications and decorations without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A memory control circuit for controlling a memory cell array, the memory control circuit comprising: a storage unit for storing a namespace table, a logical to virtual mapping table, and a virtual to physical block mapping table; and a processing circuit coupled to the storage unit; wherein the processing circuit is configured to: obtain a mapping group identification from a namespace identification and a logical address via the namespace table; obtain a block group identification and a mapping entry from the mapping group identification and an offset of the logical address in the mapping group via the logical to virtual mapping table; obtain a super block identification from the block group identification and a virtual block via the virtual to physical block mapping table; and obtain a physical block number via the virtual to physical block mapping table.

2. The memory control circuit of claim 1, wherein the capacity of the array of memory cells is 8x2 N TB, the block group has 2 N numberings in total, and N is a natural number.

3. The memory control circuit of claim 1, wherein the physical block number is obtained from the super block identification, a channel, a die, and a plane via the virtual to physical block mapping table.

4. The memory control circuit of claim 1, wherein in the logical to virtual mapping table, a plurality of numbers of the mapping group are corresponding to a plurality of numbers of the block group in a round robin policy.

5. The memory control circuit of claim 1, wherein in the logical to virtual mapping table, N consecutive numbers of the mapping group are corresponding to a same number of the block group.

6. The memory control circuit according to claim 1, wherein if the capacity of the memory cell array is 2 N ×8TB, the addressing bit number remains at 32 bits.

7. The memory control circuit of claim 1, wherein in the namespace table, a number of the namespace is corresponding to one or more numbers of the mapping group.

8. The memory control circuit of claim 1, wherein a number of the mapping group is corresponding to a number of the block group.

9. A memory control circuit for controlling a memory cell array, the memory control circuit comprising: a storage unit for storing a namespace table, a logical to virtual mapping table, and a virtual to physical block mapping table; and a processing circuit coupled to the storage unit; wherein the processing circuit is configured to: obtain a mapping group (Mapping Group Identification) from a namespace (Namespace Identification) and a logical address (Logical Address) via the namespace table; obtain a block group (Block Group Identification) and a mapping entry from the mapping group and an offset of the logical address in the mapping group via the logical to virtual mapping table; and obtain a physical block (Physical Block Number) from the block group and the virtual block via the virtual to physical block mapping table.

10. A memory device, comprising: a memory cell array; and a memory control circuit configured to control the memory cell array, the memory control circuit comprising: a storage unit configured to store a namespace table, a logical to virtual mapping table, and a virtual to physical block mapping table; and a processing circuit connected to the storage unit and the cache circuit; wherein the processing circuit is configured to: obtain a mapping group (Mapping Group Identification) from a namespace (Namespace Identification) and a logical address (Logical Address) via the namespace table; obtain a block group (Block Group Identification) and a mapping entry from the mapping group and an offset of the logical address in the mapping group via the logical to virtual mapping table; and obtain a physical block (Physical Block Number) from the block group and the virtual block via the virtual to physical block mapping table.

10. A memory device, comprising: a memory cell array; and a memory control circuit configured to control the memory cell array, the memory control circuit comprising: a storage unit configured to store a namespace table, a logical to virtual mapping table, and a virtual to physical block mapping table; and a processing circuit connected to the storage unit and the cache circuit; wherein the processing circuit is configured to: obtain a mapping group (Mapping Group Identification) from a namespace (Namespace Identification) and a logical address (Logical Address) via the namespace table; obtain a block group (Block Group Identification) and a mapping entry from the mapping group and an offset of the logical address in the mapping group via the logical to virtual mapping table; and obtain a physical block (Physical Block Number) from the block group and the virtual block via the virtual to physical block mapping table.

Images