Data storage device

Abstract

Various embodiments of the present disclosure relate to a memory device, and the memory device may include: a plurality of bank groups, each bank group including a plurality of banks, each bank including two sub-banks, each sub-bank including a plurality of memory cells; and a peripheral circuit configured to receive the control signal and the data chunks from an external device, and store the data chunks to be allocated in at least two or more sub-banks selected from among the sub-banks included in the plurality of bank groups.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2024-0052073, filed on April 18, 2024, which is hereby incorporated by reference in its entirety for all purposes. Technical Field

[0003] An embodiment of the present disclosure relates to a data storage device capable of allocating burst defects. Background Art

[0004] The memory device may store data based on a command from the external device and provide the stored data to the external device.

[0005] The memory device includes a plurality of memory cells that can store data. When an error occurs when storing data in the memory cell or reading data from the memory cell, the data with the error is output and transmitted to an external device.

[0006] When the external device uses data with errors, a system error of the external device may be caused. To prevent the system error, the external device may use an error correction code that can detect and correct errors in data read from the memory device.

[0007] In theory, simply adding parity bits can more accurately detect and correct more errors. However, this increase can make the structure heavier and the design more difficult, leading to numerous problems such as reduced processing speed and data transmission efficiency. Furthermore, as the area used to store parity bits in a memory device increases, the usable capacity of the memory device decreases.

[0008] When the number of errors occurring within a data chunk is small, the error correction code is sufficient to recover the original data even with fewer parity bits. Therefore, it is necessary to reduce the probability of many errors occurring simultaneously within a data chunk. Summary of the Invention

[0009] Various embodiments of the present disclosure provide a memory device capable of distributing error bits generated when a defect causing a burst error in the memory device is generated into a plurality of data chunks.

[0010] Various embodiments of the present disclosure provide a memory device capable of reducing the number of error bits generated in one data block when a burst error occurs due to a sub-word line driver failure in the memory device.

[0011] The technical problems to be solved by the embodiments of the present disclosure are not limited to the above-mentioned technical problems, and other technical problems not mentioned can be clearly understood by those skilled in the art from the following description.

[0012] According to various embodiments of the present disclosure, a memory device can include a plurality of bank groups each including a plurality of banks each including two sub-banks each including a plurality of memory cells, and a peripheral circuit configured to receive a first control signal and a data chunk from an external device and store the data chunk to be allocated in at least two or more sub-banks selected from among the sub-banks included in the plurality of bank groups.

[0013] The peripheral circuit can be configured to select one bank from among the banks of the plurality of bank groups based on the first control signal and store the data chunk to be allocated in two sub-banks in the selected bank.

[0014] The first control signal can include a first address, and the peripheral circuit can be further configured to select a first bank based on a portion of the first address and store half of the data chunk in each of two sub-banks of the selected first bank based on a remaining portion of the first address.

[0015] The peripheral circuit can be further configured to receive a second control signal from the external device and read the stored data chunk from the two sub-banks of the selected bank based on the second control signal.

[0016] The peripheral circuit can be configured to select two banks from among the banks of the plurality of bank groups based on the first control signal and store the data chunk to be allocated in four sub-banks in the selected two banks. The selected two banks can be included in the same bank group.

[0017] The first control signal can include a second address, and the peripheral circuit can be further configured to select a first bank group based on a first portion of the second address, select a first bank and a second bank among the banks of the first bank group based on a second portion of the second address, and store a quarter of the data chunk in each of two sub-banks of the first bank and two sub-banks of the second bank based on a remaining portion of the second address.

[0018] The peripheral circuit can be configured to select one bank group from among the plurality of bank groups based on the first control signal and store the data chunk to be allocated in eight sub-banks in four banks in the selected bank group.

[0019] The first control signal can include a third address, and the peripheral circuit can be configured to select a first bank group based on a first portion of the third address, and store one-eighth of the data chunk in each of two sub-banks in each of four banks in the first bank group based on a second portion of the third address.

[0020] According to various embodiments of the disclosure, a data storage device can include a plurality of first memory devices to store data chunks, a second memory device to store error correction codes generated based on the data chunks, and a peripheral circuit configured to receive a first control signal from an external device and control the plurality of first memory devices and the second memory device. Each of the plurality of first memory devices and the second memory device can include a plurality of bank groups each including a plurality of banks each including two sub-banks each including a plurality of memory cells. The peripheral circuit can be configured to store a data chunk and an error correction code to be allocated in at least two or more sub-banks selected from among the sub-banks included in the plurality of bank groups in each of the plurality of first memory devices and the second memory device.

[0021] The peripheral circuit can be further configured to select one bank from among the banks of the plurality of bank groups in each of the plurality of first memory devices and the second memory device based on the first control signal, and store a data chunk and an error correction code to be allocated in two sub-banks in the selected bank.

[0022] The first control signal can include a first address, and the peripheral circuit can be further configured to select a first bank from each of the plurality of first memory devices and the second memory device based on a portion of the first address, and store a data chunk and an error correction code in each of two sub-banks of the selected first bank based on a remaining portion of the first address.

[0023] The peripheral circuit can be further configured to receive a control signal from the external device, and read the stored data chunk and error correction code from the two sub-banks of the selected bank based on the second control signal.

[0024] The peripheral circuit can be further configured to select two banks from among the banks of the plurality of bank groups in each of the plurality of first memory devices and the second memory device based on the first control signal, and store a data chunk and an error correction code to be allocated in four sub-banks in the selected two banks.

[0025] The peripheral circuit can be further configured to select one bank from among the plurality of memory banks in each of the plurality of first memory devices and the second memory device based on the control signal, and store the data chunk and the error correction code to be allocated in eight sub-banks of four memory banks in the selected bank.

[0026] The number of the plurality of first memory devices can be four.

[0027] The size of the data chunk can be calculated by multiplying a burst length (N) by 32 bits, and the size of the error correction code can be calculated by multiplying the burst length (N) by 8 bits. Each of the plurality of first memory devices and the second memory device can be configured to receive or output 8 bits at the same time.

[0028] The peripheral circuit can sequentially receive 40-bit data signals from the external device the same number of times as the burst length (N). Also, the peripheral circuit can sequentially transfer 8 bits to each of the plurality of first memory devices and the second memory device at a time. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a block diagram illustrating a memory system according to an embodiment of the disclosure.

[0030] Figure 2 is a block diagram illustrating Figure 1 a first memory device illustrated in FIG. 1.

[0031] Figure 3 is a view illustrating a bank group and a memory bank according to an embodiment of the disclosure.

[0032] Figure 4 is a view illustrating a left sub-bank or a right sub-bank within a memory bank according to an embodiment of the disclosure.

[0033] Figure 5 is a view illustrating data read from a memory bank.

[0034] Figure 6 is a view partially illustrating a left sub-bank and a right sub-bank of a memory bank for a description purpose.

[0035] Figure 7 is a view illustrating an output result of data reading according to a method of a type proposed.

[0036] Figure 8 is a view illustrating data stored in each memory cell according to a method proposed in a first embodiment of the disclosure.

[0037] Figure 9is a view showing an output result of data reading according to the method proposed in the first embodiment of the disclosure.

[0038] Figure 10 is a view showing data stored in each memory cell according to the method proposed in the second embodiment of the disclosure.

[0039] Figure 11 is a view showing an example of an output result when reading is performed according to the method proposed in the second embodiment of the disclosure. DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily understand. However, the embodiments of the disclosure can be implemented in various forms and are not limited to the embodiments described herein. In addition, in order to clearly describe the embodiments in the drawings, parts irrelevant to the description are omitted, and similar components are given similar reference numerals throughout the specification.

[0041] Throughout the specification, when a component is referred to as "including" a certain component, unless explicitly stated otherwise, it means that it can further include other components, rather than excluding other components.

[0042] As terms used in the description of the embodiments of the disclosure, the terms are chosen to be as far as possible considering the functions of the widely used general terms. However, this can vary according to the intention of those skilled in the art, precedents, appearance of new technology, etc. In addition, the terms are randomly selected by the applicant in a specific situation, and in this case, the meanings of the terms will be described in detail in the description of the corresponding embodiment. Therefore, the terms used in the embodiments should not be defined only by the names of the terms, but should be defined based on the meanings of the terms and the overall content of the embodiments.

[0043] In the embodiments of the disclosure, although terms including ordinal numbers such as first, second, etc. can be used to describe various components, the components are not limited by the terms. The terms are used only to distinguish one component from other components. For example, without departing from the scope of the disclosure, a first component can be referred to as a second component, and similarly, a second component can also be referred to as a first component. The term "and / or" includes a combination of a plurality of related items described herein or one of a plurality of related items described herein.

[0044] In addition, in the embodiments of the disclosure, unless the context clearly dictates otherwise, a singular expression also includes a plural expression.

[0045] Figure 1 is a block diagram showing a memory system according to an embodiment of the disclosure, Figure 2 is a view showing Figure 1A block diagram of a first memory device 100a is shown in FIG.

[0046] Reference Figure 1 , the memory system may include a data storage device 10 and a controller 20 .

[0047] The data storage device 10 may include a plurality of memory devices 100a to 100e. Figure 1 The data storage device 10 shown in FIG. 1 includes five memory devices 100 a to 100 e , but the present disclosure is not limited thereto, and various numbers of memory devices may be included in the data storage device 10 as needed.

[0048] The memory devices 100a to 100e can communicate with the controller 20 through corresponding connectors. Figure 2 In the illustrated embodiment, memory devices 100 a - 100 e may communicate with controller 20 using data signals DQ, data strobe signals DQS, and control signals.

[0049] In an embodiment, the controller 20 may be included in an external host device. In this embodiment, the memory devices 100a to 100e may simultaneously receive the data signal DQ and store the received data signal DQ in response to a request from the external host device.

[0050] Each of the memory devices 100 a to 100 e may be implemented using fifth-generation double data rate (DDR5) synchronous dynamic random access memory (SDRAM). The memory devices 100 a to 100 e may communicate with the controller 20 as defined in the Joint Electron Device Engineering Council (JEDEC) standard for dual in-line memory modules (DIMMs), and more specifically, as defined in the JEDEC standard for DDR5 SDRAM DIMMs.

[0051] The memory devices 100a to 100e may sequentially receive or output data signals DQ the same number of times as the burst length BL. For example, according to the DDR5 SDRAM DIMM standard, the burst length (BL) may be 16.

[0052] exist Figure 1In the illustrated embodiment, the first to fourth memory devices 100a to 100d can be memory devices for storing data, and the fifth memory device 100e can be a memory device for storing data for error correction. The controller 20 can control the operation of the memory devices 100a to 100e in the data storage device 10 to store data in the first to fourth memory devices 100a to 100d and store error correction codes (ECCs) in the fifth memory device 100e.

[0053] In some embodiments, the control signals provided by the controller 20 to the data storage device 10 are simultaneously transmitted to the first to fifth memory devices 100a to 100e within the data storage device 10. The first to fifth memory devices 100a to 100e can be simultaneously controlled to perform the same operation based on the control signals. Further, the controller transmits data using an 8-bit data line (X8) with each of the first to fifth memory devices 100a to 100e for storage or reading.

[0054] For example, the second to fifth memory devices 100b to 100e can also have the same structure as the first memory device 100a and operate in the same manner.

[0055] Referring to Figure 1 and Figure 2 The first memory device 100a can include a plurality of bank groups BG0 110a to BGN 110b. According to the standard specification of the DDR5 SDRAM DIMM, the memory device can include up to eight bank groups. Each of the bank groups 110a and 110b (collectively, bank groups 110) can include first to fourth banks BK0, BK1, BK2, BK3. All of the bank groups 110 in the memory device can have the same structure, including the first to fourth banks BK0, BK1, BK2, and BK3, and operate in the same manner. Each bank BK0, BK1, BK2, or BK3 can include memory cells. The memory cells can be used to store data or error correction codes transmitted from the controller 20.

[0056] The memory device 100a can further include a peripheral circuit capable of receiving control signals including commands CMD and addresses ADDR, data signals DQ, and data strobe signals DQS, and transmitting the data signals DQ to a desired bank based on the control signals.

[0057] The peripheral circuit can control the selected bank to perform an operation, such as a write operation or a read operation, indicated by the command on the memory cells indicated by the address ADDR among the memory cells of the selected bank.

[0058] The peripheral circuit can communicate a data signal DQ and a data strobe signal DQS with the controller 20. The data strobe signal DQS can be used to transfer timing of latching the data signal DQ.

[0059] Figure 3 is a view illustrating a bank group and a bank according to an embodiment of the disclosure, Figure 4 is a view illustrating a left sub-bank (SBKL) or a right sub-bank (SBKR) within a bank according to an embodiment of the disclosure, Figure 5 is a view illustrating reading data from a bank.

[0060] For example, the bank group 110 is one of a plurality of bank groups 110a and 110b shown in Figure 2 In addition, referring to Figure 3 , the banks BK0, BK1, BK2, BK3 in the bank group 110 can include a left sub-bank SBKL and a right sub-bank SBKR. The left sub-bank SBKL and the right sub-bank SBKR can have the same structure as shown in Figure 4

[0061] Referring to Figures 1 to 4 Each of the left sub-bank SBKL or the right sub-bank SBKR can include a memory cell array 410, a row decoder 420, a bit line sense amplifier (BLSA) 430, a column decoder 440, and sub-word line decoders SWD 450, 451, 452, 453, and 454.

[0062] The memory cell array 410 can include memory cells arranged in a row direction and a column direction. The memory cell array 410 can be a component that actually stores data.

[0063] The row decoder 420 can be connected to rows of memory cells through word lines WL1 to WLn, where n is a positive integer greater than 1. The row decoder 420 can receive a row address RA in an address ADDR and select one of the first word line WL1 to the n-th word line WLn in response to the row address RA. For example, the row decoder 420 can apply a voltage (e.g., a positive voltage) for activating the selected word line.

[0064] The bit line sense amplifier 430 can be connected to columns of memory cells through bit lines. The bit line sense amplifier 430 can be connected to different bit lines from each other. The bit line sense amplifier 430 can apply a voltage to a bit line and / or sense a voltage of a bit line. By adjusting or sensing the voltage of the bit line, the bit line sense amplifier 430 can perform a write operation or a read operation on the memory cells of the selected row.

[0065] ​The column decoder 440 can receive a column address CA in the address ADDR. The column decoder 440 can electrically connect some bit lines to the peripheral circuit in response to the column address CA.

[0066] In Figure 5 In the illustrated embodiment, when the first word line WL1 is selected by the row decoder 420, the sub word line decoders 450, 451, 452, 453, 454 connected to the first word line WL1 can be activated and output data 510 of the memory cells. The column decoder 440 can sequentially select burst data bits DQ0 to DQ7 of BL0 to BL15 and output data read from the corresponding memory cells, so that a data chunk 520 corresponding to a burst length (e.g., 16) can be output. In Figure 5 In the illustrated embodiment, the same pattern can represent data output from the memory cells managed by the same sub word line decoder. That is, the first data bit DQ0 and the third data bit DQ2 can be data activated by the first sub word line decoder 450, the second data bit DQ1 and the fourth data bit DQ3 can be data activated by the second sub word line decoder 451, the fifth data bit DQ4 can be data activated by the third sub word line decoder 452, the sixth data bit DQ5 and the seventh data bit DQ6 can be data activated by the fourth sub word line decoder 453, and the eighth data bit DQ7 can be data activated by the fifth sub word line decoder 454.

[0067] However, when the first sub word line decoder 450 fails, all 32 data bits of the first data bit DQ0 and the third data bit DQ2 of all bursts BL0 to BL15 can be in error. In this example, even if no error occurs in other chips among the chips illustrated in FIG. 1, at least 32 bits of error can occur in a data chunk configured of 512 (= 16 x 8 x 4) data bits and 128 (= 16 x 8) error correction code bits, so that error correction of the data chunk can not be possible. Figure 1

[0068] Therefore, when one sub word line decoder fails, the number of bits in error increases, and error correction can not be possible. To solve the problem of not being able to correct errors, an embodiment of the disclosure provides a method of reducing the number of bits managed by each sub word line decoder in one data chunk by half.

[0069] Figure 6 FIG. 1 is a view partially illustrating left and right sub memory banks of a memory bank. Figure 7 FIG. 2 is a view illustrating an output result of data reading according to a method of a type proposed. Figure 8 FIG. 3 is a view illustrating data stored in each memory cell according to a method proposed in a first embodiment of the disclosure. Figure 9 ​is a diagram showing an output result of data reading according to the method proposed in the first embodiment of the present disclosure.

[0070] Although Figure 6 Only sub-word line drivers controlling the first data bit DQ0 and the third data bit DQ2 are shown, but other sub-word lines may also operate in the same manner.

[0071] Figure 6 Each of the word lines WL1 to WLn of the memory bank shown in FIG can be selected by a row address RA. The sub-word line decoders 650L and 650R can activate memory cells for read or write operations based on the row address RA. For example, the sub-word line decoder 650L connected to the first word line WL1 of the left sub-memory bank SBKL can activate the memory cells managed when the row address RA is 0x0000, as shown in FIG. Figure 7 In another example, the sub-word line decoder 650R connected to the first word line WL1 of the right sub-memory bank SBKR may activate the memory cells managed when the row address RA is 0x8000, as shown in FIG. Figure 7 As shown. That is, the left sub-memory bank SBKL can be operated by the most significant bit (MSB) of the 16-bit row address, or the right sub-memory bank SBKR can be activated by the MSB of the 16-bit row address. One type of method that has been proposed is to select the left sub-memory bank SBKL or the right sub-memory bank SBKR according to whether the value of the most significant bit RA15 is 0 or 1. When the left sub-memory bank SBKL is selected according to this method, a word line is selected by the downstream address RA14 to RA0, and the sub-word line decoder SWD connected to the selected word line activates the memory cell to read data from the memory cell. For example, when the row address RA is 0x0000, the word line WL1 connected to the first word line WL1 of the left sub-memory bank SBKL can be activated. Figure 6 The memory cell read controlled by the sub-word line decoder 650L Figure 7 When the row address RA is 0x8000, the data of the first output 710 can be obtained from the first word line WL1 connected to the right sub-memory bank SBKR. Figure 6 The memory cell read controlled by the sub-word line decoder 650R Figure 7 The second output 720 has data.

[0072] Unlike one type of method already proposed, a method is proposed as a first embodiment to reduce the number of bits controlled by a sub-wordline decoder SWD in a 16-byte data block by half. Therefore, even if errors occur in the sub-wordline decoder, the number of erroneous bits in a data block can be reduced by half compared to the previously proposed method.

[0073] To this end, the scheme can change from selecting one of the left sub-bank SBKL and the right sub-bank SBKR using the most significant bit RA15 of the row address RA to simultaneously selecting the left sub-bank SBKL and the right sub-bank SBKR in the memory bank, and each sub-word line decoder controls 16 memory cells among 32 memory cells to store or read data in or from one data chunk based on the most significant bit RA15 of the row address RA.

[0074] Referring to Figure 6 and Figure 8 The first sub-word line decoder 450 of the left sub-bank SBKL can control to store the first data bit DQ0 of all bursts BL0 to BL15 of the first data chunk or the third data bit DQ2 of all bursts BL0 to BL15 of the second data chunk in the memory cells. The first data bit DQ0 of all bursts BL0 to BL15 of the first data chunk corresponds to an address with the most significant bit RA15 of the row address RA being 0. The third data bit DQ2 of all bursts BL0 to BL15 of the second data chunk corresponds to an address with the most significant bit RA15 of the row address RA being 1.

[0075] Similarly, the second sub-word line decoder 451 of the left sub-bank SBKL can control to store the second data bit DQ1 of all bursts BL0 to BL15 of the first data chunk or the fourth data bit DQ3 of all bursts BL0 to BL15 of the second data chunk in the memory cells. The second data bit DQ1 of all bursts BL0 to BL15 of the first data chunk corresponds to an address with the most significant bit RA15 of the row address RA being 0. The fourth data bit DQ3 of all bursts BL0 to BL15 of the second data chunk corresponds to an address with the most significant bit RA15 of the row address RA being 1.

[0076] Since the number of controlled memory cells can be limited to 16, the third sub-word line decoder 452 of the left sub-bank SBKL can control to store the fifth data bit DQ4 of all bursts BL0 to BL15 of the first data chunk in the memory cells, the fifth data bit DQ4 of all bursts BL0 to BL15 of the first data chunk corresponding to an address with the most significant bit RA15 of the row address RA being 0.

[0077] The fourth sub word line decoder 453 of the left sub bank SBKL can control storing the sixth data bit DQ5 of all bursts BL0-BL15 of the first data chunk or the seventh data bit DQ6 of all bursts BL0-BL15 of the second data chunk in the memory cells. The sixth data bit DQ5 of all bursts BL0-BL15 of the first data chunk corresponds to addresses with the most significant bit RA15 of the row address RA being zero. The seventh data bit DQ6 of all bursts BL0-BL15 of the second data chunk corresponds to addresses with the most significant bit RA15 of the row address RA being one.

[0078] Since the number of memory cells controlled can be limited to 16, the fifth sub word line decoder 454 of the left sub bank SBKL can control storing the eighth data bit DQ7 of all bursts BL0-BL15 of the second data chunk in the memory cells, the eighth data bit DQ7 of all bursts BL0-BL15 of the second data chunk corresponding to addresses with the most significant bit RA15 of the row address RA being one.

[0079] The first sub word line decoder 450 of the right sub bank SBKR can control storing the third data bit DQ2 of all bursts BL0-BL15 of the first data chunk or the first data bit DQ0 of all bursts BL0-BL15 of the second data chunk in the memory cells. The third data bit DQ2 of all bursts BL0-BL15 of the first data chunk corresponds to addresses with the most significant bit RA15 of the row address RA being zero. The first data bit DQ0 of all bursts BL0-BL15 of the second data chunk corresponds to addresses with the most significant bit RA15 of the row address RA being one.

[0080] Similarly, the second sub word line decoder 451 of the right sub bank SBKR can control storing the fourth data bit DQ3 of all bursts BL0-BL15 of the first data chunk or the second data bit DQ1 of all bursts BL0-BL15 of the second data chunk in the memory cells. The fourth data bit DQ3 of all bursts BL0-BL15 of the first data chunk corresponds to addresses with the most significant bit RA15 of the row address RA being zero. The second data bit DQ1 of all bursts BL0-BL15 of the second data chunk corresponds to addresses with the most significant bit RA15 of the row address RA being one.

[0081] Since the number of memory cells controlled can be limited to 16, the third sub word line decoder 452 of the right sub bank SBKR can control storing the fifth data bit DQ4 of all bursts BL0-BL15 of the second data chunk in the memory cells, the fifth data bit DQ4 of all bursts BL0-BL15 of the second data chunk corresponding to addresses with the most significant bit RA15 of the row address RA being one.

[0082] The fourth sub word line decoder 453 of the right sub bank SBKR can control storing the seventh data bit DQ6 of all bursts BLO-BL15 of the first data chunk or the sixth data bit DQ5 of all bursts BLO-BL15 of the second data chunk in the memory cells. The seventh data bit DQ6 of all bursts BLO-BL15 of the first data chunk corresponds to the addresses with the most significant bit RA15 of the row address RA being 0. The sixth data bit DQ5 of all bursts BLO-BL15 of the second data chunk corresponds to the addresses with the most significant bit RA15 of the row address RA being 1.

[0083] Since the number of controlled memory cells can be limited to 16, the fifth sub word line decoder 454 of the right sub bank SBKR can control storing the eighth data bit DQ7 of all bursts BLO-BL15 of the first data chunk in the memory cells, the eighth data bit DQ7 of all bursts BLO-BL15 of the first data chunk corresponding to the addresses with the most significant bit RA15 of the row address RA being 0.

[0084] Thus, the first data bit DQ0, the second data bit DQ1, the fifth data bit DQ4 and the sixth data bit DQ5 of all bursts BLO-BL15 of the first data chunk corresponding to the addresses with the most significant bit RA15 of the row address RA being 0 can be stored in the left sub bank SBKL 810. The third data bit DQ2, the fourth data bit DQ3, the seventh data bit DQ6 and the eighth data bit DQ7 of all bursts BLO-BL15 of the first data chunk corresponding to the addresses with the most significant bit RA15 of the row address RA being 0 can be stored in the right sub bank SBKR 820. In addition, the first data bit DQ0, the second data bit DQ1, the fifth data bit DQ4 and the sixth data bit DQ5 of all bursts BLO-BL15 of the second data chunk corresponding to the addresses with the most significant bit RA15 of the row address RA being 1 can be stored in the right sub bank SBKR 820. The third data bit DQ2, the fourth data bit DQ3, the seventh data bit DQ6 and the eighth data bit DQ7 of all bursts BLO-BL15 of the second data chunk corresponding to the addresses with the most significant bit RA15 of the row address RA being 1 can be stored in the left sub bank SBKL 810.

[0085] From the perspective of reading data chunks, as Figure 9The first data group corresponding to the address with the most significant bit RA15 of the row address RA being 0 can be configured by the first data bit DQ0 of each of the bursts BL0-BL15, the second data bit DQ1 of each of the bursts BL0-BL15, the third data bit DQ2 of each of the bursts BL0-BL15, the fourth data bit DQ3 of each of the bursts BL0-BL15, the fifth data bit DQ4 of each of the bursts BL0-BL15, the sixth data bit DQ5 of each of the bursts BL0-BL15, the seventh data bit DQ6 of each of the bursts BL0-BL15, and the eighth data bit DQ7 of each of the bursts BL0-BL15 as shown in 910. The first data bit DQ0 of each of the bursts BL0-BL15 can be output based on the control of the first sub word line decoder 450 of the left sub bank SBKL. The second data bit DQ1 of each of the bursts BL0-BL15 can be output based on the control of the second sub word line decoder 451 of the left sub bank SBKL. The third data bit DQ2 of each of the bursts BL0-BL15 can be output based on the control of the first sub word line decoder 450 of the right sub bank SBKR. The fourth data bit DQ3 of each of the bursts BL0-BL15 can be output based on the control of the second sub word line decoder 451 of the right sub bank SBKR. The fifth data bit DQ4 of each of the bursts BL0-BL15 can be output based on the control of the third sub word line decoder 452 of the left sub bank SBKL. The sixth data bit DQ5 of each of the bursts BL0-BL15 can be output based on the control of the fourth sub word line decoder 453 of the left sub bank SBKL. The seventh data bit DQ6 of each of the bursts BL0-BL15 can be output based on the control of the fourth sub word line decoder 453 of the right sub bank SBKR. The eighth data bit DQ7 of each of the bursts BL0-BL15 can be output based on the control of the fifth sub word line decoder 454 of the right sub bank SBKR.

[0086] As Figure 9The second data chunk corresponding to an address with the most significant bit RA15 of the row address RA being 1 can be configured by the first data bit DQ0 of each of the bursts BL0 to BL15, the second data bit DQ1 of each of the bursts BL0 to BL15, the third data bit DQ2 of each of the bursts BL0 to BL15, the fourth data bit DQ3 of each of the bursts BL0 to BL15, the fifth data bit DQ4 of each of the bursts BL0 to BL15, the sixth data bit DQ5 of each of the bursts BL0 to BL15, the seventh data bit DQ6 of each of the bursts BL0 to BL15, and the eighth data bit DQ7 of each of the bursts BL0 to BL15 as shown in 920. The first data bit DQ0 of each of the bursts BL0 to BL15 can be output based on the control of the first sub word line decoder 450 of the right sub memory bank SBKR. The second data bit DQ1 of each of the bursts BL0 to BL15 can be output based on the control of the second sub word line decoder 451 of the right sub memory bank SBKR. The third data bit DQ2 of each of the bursts BL0 to BL15 can be output based on the control of the first sub word line decoder 450 of the left sub memory bank SBKL. The fourth data bit DQ3 of each of the bursts BL0 to BL15 can be output based on the control of the second sub word line decoder 451 of the left sub memory bank SBKL. The fifth data bit DQ4 of each of the bursts BL0 to BL15 can be output based on the control of the third sub word line decoder 452 of the right sub memory bank SBKR. The sixth data bit DQ5 of each of the bursts BL0 to BL15 can be output based on the control of the fourth sub word line decoder 453 of the right sub memory bank SBKR. The seventh data bit DQ6 of each of the bursts BL0 to BL15 can be output based on the control of the fourth sub word line decoder 453 of the left sub memory bank SBKL. The eighth data bit DQ7 of each of the bursts BL0 to BL15 can be output based on the control of the fifth sub word line decoder 454 of the left sub memory bank SBKL.

[0087] When the sub word line decoder 450 controlling the memory cells related to the first data bit DQ0 and the third data bit DQ2 fails as described above, the error can occur only in the data related to the first data bit DQ0 in the first data chunk, and the error can occur only in the data related to the third data bit DQ2 in the second data chunk. Accordingly, although the number of errors occurring in the entire data is the same, the number of errors occurring in each data chunk can be reduced by half.

[0088] Accordingly, the error correction code can be used to recover data in which an error occurs. For example, the error correction code can be Reed-Solomon (RS) parity data. The Reed-Solomon error correction operation is a method of correcting errors in units of data blocks. According to the Reed-Solomon error correction operation, although a plurality of error bits are included in a data block that is an error correction unit, a data block in which an error bit occurs can be corrected. In the Reed-Solomon error correction operation, the number of correctable errors can be determined by the size of the Reed-Solomon parity bit data.

[0089] Accordingly, when the number of errors occurring consecutively is reduced by half as described above, for the same size of parity bit data, the possibility of correction can be significantly increased.

[0090] In Figure 8 and Figure 9 , an embodiment of the present disclosure proposes a method of reducing the size of data controlled by each sub word line decoder within one data block by half by simultaneously operating two sub-banks SBKL and SBKR provided in one bank and using the most significant bit RA15 of the row address RA.

[0091] In a second embodiment, by simultaneously operating Figure 3 two banks provided in one bank group as shown in FIG. 10 and using the least significant bit BA0 of the bank selection address and the most significant bit RA15 of the row address RA, the size of data controlled by each sub word line decoder within one data block can be reduced to 1 / 4.

[0092] Figure 10 is a view illustrating data stored in each memory cell according to the method proposed in the second embodiment of the present disclosure. Figure 11 is a view illustrating an output result of reading according to the method proposed in the second embodiment of the present disclosure.

[0093] Referring to Figure 10 , one data block can be stored in two sub-banks SBKL and SBKR allocated in two banks, i.e., four sub-banks.

[0094] A proposed method includes selecting a bank with a bank address BA, selecting one sub-bank among a left sub-bank SBKL and a right sub-bank SBKR of the bank with the most significant bit RA15 of the row address RA, and storing all data in the data block in or reading data from the selected sub-bank.

[0095] The structure according to the second embodiment can be changed to the following structure, that is, all 4 sub-memory bodies selectable by the least significant bit BA0 of the memory body address and the most significant bit RA15 of the row address RA are activated, and each sub-word line decoder is controlled to activate only 8 memory cells among the controlled 32-bit memory cells.

[0096] According to an embodiment, when the least significant bit BA0 of the bank address is 0 and the most significant bit RA15 of the row address RA is 0, as shown in FIG. Figure 10 As shown, 1) the sub-word line decoder of the left sub-memory bank SBKL of the first memory bank activates the memory cells (1010) associated with the first data bit DQ0, the second data bit DQ1, the fifth data bit DQ4 and the sixth data bit DQ5 of the first burst BL0 to the eighth burst BL7, 2) the sub-word line decoder of the right sub-memory bank SBKR of the first memory bank activates the memory cells (1020) associated with the third data bit DQ2, the fourth data bit DQ3, the seventh data bit DQ6 and the eighth data bit DQ7 of the first burst BL0 to the eighth burst BL7, ) the sub-word line decoder of the left sub-memory bank SBKL of the second memory bank activates the memory cells (1030) associated with the third data bit DQ2, the fourth data bit DQ3, the seventh data bit DQ6 and the eighth data bit DQ7 of the ninth burst BL8 to the sixteenth burst BL15, and 4) the sub-word line decoder of the right sub-memory bank SBKR of the second memory bank activates the memory cells (1040) associated with the first data bit DQ0, the second data bit DQ1, the fifth data bit DQ4 and the sixth data bit DQ5 of the ninth burst BL8 to the sixteenth burst BL15.

[0097] When the least significant bit BA0 of the bank address is 0 and the most significant bit RA15 of the row address RA is 1, as shown in FIG. Figure 10As shown, 1) the sub word line decoders of the left sub bank SBKL of the first bank activate memory cells associated with the first data bit DQO, the second data bit DQl, the fifth data bit DQ4 and the sixth data bit DQ5 of the ninth burst BL8 to the sixteenth burst BL15 (1010), 2) the sub word line decoders of the right sub bank SBKR of the first bank activate memory cells associated with the third data bit DQ2, the fourth data bit DQ3, the seventh data bit DQ6 and the eighth data bit DQ7 of the ninth burst BL8 to the sixteenth burst BL15 (1020), 3) the sub word line decoders of the left sub bank SBKL of the second bank activate memory cells associated with the third data bit DQ2, the fourth data bit DQ3, the seventh data bit DQ6 and the eighth data bit DQ7 of the first burst BLO to the eighth burst BL7 (1030), and 4) the sub word line decoders of the right sub bank SBKR of the second bank activate memory cells associated with the first data bit DQO, the second data bit DQl, the fifth data bit DQ4 and the sixth data bit DQ5 of the first burst BLO to the eighth burst BL7 (1040).

[0098] Even when the least significant bit BAO of the bank address is one and the most significant bit RA15 of the row address RA is zero, and the least significant bit BAO of the bank address is one and the most significant bit RA15 of the row address RA is one, each sub word line decoder only controls one byte of data in each data group block, as shown. Figure 10

[0099] Thus, as shown, Figure 11 ​The first data chunk (1110) shown, corresponding to an address with the least significant bit of the bank address BA0 being 0 and the most significant bit of the row address RA being 0, can be configured from: 1) the first data bits DQ0 output from the first burst BL0 to the eighth burst BL7 based on the control of the first sub word line decoder 450 of the left sub-bank SBKL, 2) the second data bits DQ1 output from the first burst BL0 to the eighth burst BL7 based on the control of the second sub word line decoder 451 of the left sub-bank SBKL, 3) the third data bits DQ2 output from the first burst BL0 to the eighth burst BL7 based on the control of the first sub word line decoder 450 of the right sub-bank SBKR, 4) the fourth data bits DQ3 output from the first burst BL0 to the eighth burst BL7 based on the control of the second sub word line decoder 451 of the right sub-bank SBKR, 5) the fifth data bits DQ4 output from the first burst BL0 to the eighth burst BL7 based on the control of the third sub word line decoder 452 of the left sub-bank SBKL, 6) the sixth data bits DQ5 output from the first burst BL0 to the eighth burst BL7 based on the control of the fourth sub word line decoder 453 of the left sub-bank SBKL, 7) the seventh data bits DQ6 output from the first burst BL0 to the eighth burst BL7 based on the control of the fourth sub word line decoder 453 of the right sub-bank SBKR, and 8) the eighth data bits DQ7 output from the first burst BL0 to the eighth burst BL7 based on the control of the fifth sub word line decoder 454 of the right sub-bank SBKR.

[0100] The second data bank (1120) corresponding to an address in which the least significant bit BA0 of the bank address is 0 and the most significant bit RA15 of the row address RA is 1 can be configured by 1) the first data bit DQ0 output based on the control of the first sub word line decoder 450 of the right sub memory SBKR, 2) the second data bit DQ1 output based on the control of the second sub word line decoder 451 of the right sub memory SBKR, 3) the third data bit DQ2 output based on the control of the first sub word line decoder 450 of the left sub memory SBKL, 4) the fourth data bit DQ3 output based on the control of the second sub word line decoder 451 of the left sub memory SBKL, 5) the fifth data bit DQ4 output based on the control of the third sub word line decoder 452 of the right sub memory SBKR, 6) the sixth data bit DQ5 output based on the control of the fourth sub word line decoder 453 of the right sub memory SBKR, 7) the seventh data bit DQ6 output based on the control of the fourth sub word line decoder 453 of the left sub memory SBKL, and 8) the eighth data bit DQ7 output based on the control of the fifth sub word line decoder 454 of the left sub memory SBKL of the ninth to sixteenth bursts BL8 to BL15.

[0101] The third data bank (1130) corresponding to an address in which the least significant bit BA0 of the bank address is 1 and the most significant bit RA15 of the row address RA is 0 and the fourth data bank (1140) corresponding to an address in which the least significant bit BA0 of the bank address is 1 and the most significant bit RA15 of the row address RA is 1 can also be configured by 16 8-bit bursts output based on the control of all 16 sub word line decoders, as shown in Figure 11

[0102] Based on the control operation of the sub word line driver according to the second embodiment described above, when one sub word line driver fails, only an 8-bit error can occur in each of the four different data banks. Thus, although the same as one type of method in which the number of errors occurring in the entire data is 32 bits, the number of errors occurring in each data bank can be reduced to 1 / 4.

[0103] Thus, it is possible to significantly increase the possibility of recovering data in which an error has occurred by utilizing an error correction code.

[0104] In the third embodiment, by simultaneously operating Figure 3 ​The four banks provided in one bank group and using the most significant bits of the bank selection address BA1 and BA0 and the most significant bits of the row address RA15 can reduce the size of data controlled by each sub word line decoder within one data chunk to one-eighth (1 / 8). Although a detailed description thereof is omitted, it can be inferred that the data size can be reduced to one-sixteenth (1 / 16) or one-thirty-second (1 / 32) by using the most significant bits of the bank selection address BA1 and BA0 and the most significant bits of the row address RA15 in a bank group including more banks than the bank group shown in FIG. 1. Figure 10 and Figure 11 Similarly inferred.

[0105] The operation of the memory device described based on the above-described embodiments can be summarized as follows.

[0106] The memory device can include a plurality of bank groups each including a plurality of banks, and a peripheral circuit configured to receive a control signal and a data chunk from an external device and store the data chunk to be allocated in at least two or more sub-banks selected from among the plurality of bank groups.

[0107] To store the data chunk to be allocated in two sub-banks in a bank selected based on the control signal, the memory device can further include a plurality of sub word line drivers for controlling memory cells. The control signal includes a bank group address for selecting one bank group among the plurality of bank groups, a bank address for selecting one bank among the plurality of banks in the selected bank group, a row address for selecting a word line for storing the data chunk among the selected bank, and a column address for selecting a memory cell for storing the data chunk among the memory cells associated with the selected word line. The peripheral circuit is configured to select a first bank for storing the data chunk based on the bank group address and the bank address, and select a first word line for storing the data chunk in each of two sub-banks in the first bank based on the remaining bits of the row address except the most significant bit. The peripheral circuit selects a first memory cell for storing data among the memory cells associated with the first word line based on the column address in each of the two sub-banks. A first sub word line driver connected to the first word line in a first sub-bank among the two sub-banks in the first bank can be configured to control the first memory cell in the first sub-bank so that some data in the data chunk can be stored based on the most significant bit of the row address. A second sub word line driver connected to the first word line in a second sub-bank among the two sub-banks in the first bank can be configured to control the first memory cell in the first sub-bank so that the remaining data in the data chunk can be stored based on the most significant bit of the row address.

[0108] When the most significant bit of the row address is 0, the first sub word line driver can control storing four of the eight data bits of the N burst of data chunks (4N first data bits total) in the partial first memory cells of the first sub memory bank, and the second sub word line driver can control storing the remaining four of the eight data bits of the N burst of data chunks (4N second data bits total) in the partial first memory cells of the second sub memory bank.

[0109] When the most significant bit of the row address is 1, the first sub word line driver can control storing the 4N second data bits total in the remaining first memory cells of the first sub memory bank, and the second sub word line driver can control storing the 4N first data bits total in the remaining first memory cells of the second sub memory bank.

[0110] The peripheral circuit can be configured to store the data chunk to be allocated in four sub memory banks of two memory banks selected based on the control signal.

[0111] The memory device further includes a plurality of sub word line drivers for controlling the memory cells.

[0112] The control signal includes a bank group address for selecting one bank group among a plurality of bank groups, a bank address for selecting one bank among a plurality of banks in the selected bank group, a row address for selecting a word line for storing a data chunk among the selected bank, and a column address for selecting a memory cell for storing the data chunk among the memory cells associated with the selected word line.

[0113] The peripheral circuit is configured to select the first memory bank and the second memory bank for storing the data chunk based on the remaining bits of the bank group address and the bank address except the least significant bit, and select the first word line in each of two sub memory banks in the first memory bank and two sub memory banks in the second memory bank for storing the data chunk in the first memory bank based on the remaining bits of the row address except the most significant bit.

[0114] The peripheral circuit selects the first memory cell for storing the data among the memory cells associated with the first word line based on the column address in each of the four sub memory banks.

[0115] The first sub word line driver connected to the first word line in the first sub memory bank among the two sub memory banks in the first memory bank can be configured to control the first memory cells in the first sub memory bank in the first memory bank so that some data in the data chunk can be stored based on the least significant bit of the bank address and the most significant bit of the row address.

[0116] The second sub word line driver connected with the first word line of the second sub memory bank among the two sub memory banks in the first memory bank can be configured to control the first memory cells in the second sub memory bank in the first memory bank so that some data in the data chunk can be stored based on the least significant bit of the memory bank address and the most significant bit of the row address.

[0117] The third sub word line driver connected with the first word line of the first sub memory bank among the two sub memory banks in the second memory bank can be configured to control the first memory cells in the first sub memory bank in the second memory bank so that some data in the data chunk can be stored based on the least significant bit of the memory bank address and the most significant bit of the row address.

[0118] The fourth sub word line driver connected with the first word line of the second sub memory bank among the two sub memory banks in the second memory bank can be configured to control the first memory cells in the second sub memory bank in the second memory bank so that some data in the data chunk can be stored based on the least significant bit of the memory bank address and the most significant bit of the row address.

[0119] When the least significant bit of the memory bank address is 0 and the most significant bit of the row address is 0, the first sub word line driver can control two data bits among eight data bits (2N first data bits in total) of N bursts of the data chunk to be stored in the partial first memory cells of the first sub memory bank of the first memory bank, the second sub word line driver can control two data bits among eight data bits (2N second data bits in total) of N bursts of the data chunk to be stored in the partial first memory cells of the second sub memory bank of the first memory bank, the third sub word line driver can control two data bits among eight data bits (2N third data bits in total) of N bursts of the data chunk to be stored in the partial first memory cells of the first sub memory bank of the second memory bank, and the fourth sub word line driver can control the remaining two data bits among eight data bits (2N fourth data bits in total) of N bursts of the data chunk to be stored in the partial first memory cells of the second sub memory bank of the second memory bank.

[0120] As described above, since the method proposed in the disclosure reduces the number of bits in one data chunk controlled by each sub word line driver by storing data included in one data chunk to be allocated in a plurality of sub memory banks instead of storing all data in one sub memory bank, even if one sub word line driver fails, the possibility of recovering the data chunk can be increased by reducing the number of consecutive error bits occurring in one data chunk.

[0121] The memory device proposed in the disclosure can increase the possibility of recovering errors in a data chunk using an error correction code by reducing the number of error bits that can occur due to burst defects.

[0122] It will be understood by those skilled in the art that the present disclosure can be implemented in other specific forms without changing the technical spirit or essential characteristics thereof. Therefore, it should be understood that the above-described embodiments are exemplary in all aspects and are not restrictive. The scope of the present disclosure is defined by the claims described below rather than the specific embodiments, and it should be understood that the meaning and scope of the claims and all modifications or changes derived from equivalent concepts thereof are included in the scope of the present disclosure. Furthermore, the embodiments can be combined to form additional embodiments.

Claims

1. A memory device comprising: a plurality of bank groups, each bank group including a plurality of banks, each bank including two sub-banks, each sub-bank including a plurality of memory cells; and a peripheral circuit that receives a first control signal and a data chunk from an external device and stores the data chunk to be allocated in at least two or more sub-banks selected from among the sub-banks included in the plurality of bank groups.

2. The memory device of claim 1, wherein, The peripheral circuit selects one bank from among the banks of the plurality of bank groups based on the first control signal and stores the data chunk to be allocated in two sub-banks in the selected bank.

3. The memory device of claim 2, wherein, The first control signal includes a first address, and The peripheral circuit further: selects a first bank based on a portion of the first address, and stores half of the data chunk in each of two sub-banks of the selected first bank based on a remaining portion of the first address.

4. The memory device of claim 2, wherein, The peripheral circuit further receives a second control signal from the external device and reads the stored data chunk from the two sub-banks of the selected bank based on the second control signal.

5. The memory device of claim 1, wherein, The peripheral circuit selects two banks from among the banks of the plurality of bank groups based on the first control signal and stores the data chunk to be allocated in four sub-banks in the two selected banks.

6. The memory device of claim 5, wherein, The two selected banks are included in the same bank group.

7. The memory device of claim 6, wherein, The first control signal includes a second address, and The peripheral circuit further: selects a first bank group based on a first portion of the second address, selects a first bank and a second bank among the banks in the first bank group based on a second portion of the second address, and stores a quarter of the data chunk in each of two sub-banks of the first bank and two sub-banks of the second bank based on a remaining portion of the second address.

8. The memory device of claim 1, wherein, The peripheral circuit selects one bank group from among the plurality of bank groups based on the first control signal and stores the data chunk to be allocated in eight sub-banks in four banks in the selected bank group.

9. The memory device of claim 8, wherein, The first control signal includes a third address, and The peripheral circuit: selects a first bank group based on a first portion of the third address, stores an eighth of the data chunk in each of two sub-banks in each of four banks in the first bank group based on a second portion of the third address.

10. A data storage device comprising: a plurality of first memory devices for storing data chunks; a second memory device for storing an error correction code generated based on the data chunks; and a peripheral circuit that receives a first control signal from an external device and controls the plurality of first memory devices and the second memory device, wherein each of the plurality of first memory devices and the second memory device includes: a plurality of bank groups each including a plurality of banks each including two sub-banks each including a plurality of memory cells, and the peripheral circuit stores the data chunk and the error correction code to be allocated in at least two or more sub-banks selected from among the sub-banks included in the plurality of bank groups in each of the plurality of first memory devices and the second memory device.

11. The data storage device of claim 10, wherein, the peripheral circuit further selects one bank from among the banks of the plurality of bank groups in each of the plurality of first memory devices and the second memory device based on the first control signal, and stores the data chunk and the error correction code to be allocated in two sub-banks in the selected bank.

12. The data storage device of claim 11, wherein, the first control signal includes a first address, and the peripheral circuit further: selects a first bank from among each of the plurality of first memory devices and the second memory device based on a portion of the first address, and stores the data chunk and the error correction code in two sub-banks of the selected first bank based on a remaining portion of the first address.

13. The data storage device of claim 11, wherein, the peripheral circuit further: receives a second control signal from the external device, and reads the stored data chunk and error correction code from the two sub-banks in the selected bank based on the second control signal.

14. The data storage device of claim 10, wherein, the peripheral circuit further: selects two banks from among the banks of the plurality of bank groups in each of the plurality of first memory devices and the second memory device based on the first control signal, and stores the data chunk and the error correction code to be allocated in four sub-banks in the selected two banks.

15. The data storage device of claim 10, wherein, the peripheral circuit further: selects one bank group from among the plurality of bank groups in each of the plurality of first memory devices and the second memory device based on the first control signal, and stores the data chunk and the error correction code to be allocated in eight sub-banks in four banks in the selected bank group.

16. The data storage device of claim 10, wherein, the number of the plurality of first memory devices is 4.

17. The data storage device of claim 16, wherein, a size of the data chunk is calculated by multiplying a burst length, N, by 32 bits, and a size of the error correction code is calculated by multiplying the burst length, N, by 8 bits.

18. The data storage device of claim 17, wherein, each of the plurality of first memory devices and the second memory device simultaneously receives or outputs 8 bits.

19. The data storage device of claim 18, wherein, the peripheral circuit sequentially receives a 40-bit data signal from the external device a number of times corresponding to the burst length.

20. The data storage device of claim 19, wherein, the peripheral circuit sequentially transfers 8 bits to each of the plurality of first memory devices and the second memory device at a time.

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