Vector decompression system and method

Abstract

The application discloses a kind of vector decompression system and method, it relates to computer technical field, the system includes: precision conversion module, for converting mask vector into single precision mask vector;Delay chain module, for generating continuous pulse;Pulse elimination module, for eliminating part of pulse in continuous pulse according to single precision mask vector, obtain effective sampling pulse;Pulse merging and separation module, for merging effective sampling pulse into a signal, and separating the merged signal into a plurality of separated pulses which are spatially continuous and temporally separated;Data serial module, for converting a plurality of vector elements in parallel in the source vector into a single vector element that changes over time according to the separated pulses, to obtain serial data;Destination vector sampling module, for simultaneously sampling the serial data using the effective sampling pulses to obtain the destination vector.The application can perform vector decompression based on time-domain calculation, reducing the hardware overhead and power consumption required for vector decompression.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and in particular, to a vector decompression system and method. BACKGROUND

[0002] Vector decompression is an indispensable instruction in the instruction set of a processor. For example, the VPEXPANDQ instruction in the AVX512 instruction set of Intel Corporation and the VDECOMPRESS instruction in the vector extension instruction set of RISC-V. The vector decompression instruction is used to restore the compressed vector elements to their original positions. Together with vector compression, it can reduce the bandwidth demand for memory access, alleviate the bandwidth wall problem, and improve the performance of vector operations.

[0003] Reference Figure 1 , Figure 1 A vector decompression principle diagram when the precision is 8 bits is provided for an example. In the accompanying Figure 1 , the source vector and the destination vector each contain 8 8-bit elements, and the mask vector contains 8 1-bit elements. When the value of a bit element in the mask vector is 0, the corresponding data in the destination vector remains unchanged. When the value of a bit element in the mask vector is 1, the corresponding data in the destination vector comes from the source vector. The first few elements in the source vector are placed in the positions of the mask vector with a value of 1 in turn. In the accompanying Figure 1 , the value of the mask vector is "01001101". Since the lowest bit is 1, the first element a in the source vector is placed in the first element in the destination vector. Since the second bit is 0, the second element in the destination vector remains unchanged. In this way, the elements in the source vector are placed in the corresponding positions in the destination vector in turn. In the process of vector decompression, each element in the source vector may be sent to any element in the destination vector, which means that a data path needs to be established between each element in the source vector and each element in the destination vector. The size of the circuit increases in square with the bit width of the vector.

[0004] Since different applications have different requirements for computing precision, mixed precision can be used to reduce computing delay and storage overhead. For applications with high precision requirements, such as scientific computing, 32-bit or 64-bit precision can be used. For applications with low precision requirements, such as reasoning in artificial intelligence, 8-bit or 16-bit precision can be used.

[0005] Reference Figures 2-4 , Figure 2 A vector decompression principle diagram when the precision is 16 bits is provided for an example; Figure 3 A vector decompression principle diagram when the precision is 32 bits is provided for an example; Figure 4A vector decompression principle diagram with a precision of 64 bits is provided as an example. As can be seen, when the precision increases, the source vector, the mask vector and the destination vector will be combined into groups, and different data will result in different vector decompression results. However, designing multiple components with different precisions independently will bring a large amount of hardware overhead.

[0006] Compared with digital domain calculation, time domain calculation is a calculation method using signal time domain coding and delay operation. In recent years, time domain calculation has been applied in shortest path solving, multiply-accumulate operations and the like to reduce circuit overhead and improve energy efficiency. Meanwhile, since time domain calculation does not need signal strength to carry information, it can be seamlessly compatible with existing data storage methods such as registers or static random access memory.

[0007] Therefore, it is necessary to develop a vector decompression system and method based on time domain calculation to reduce the hardware overhead and power consumption required for vector decompression. SUMMARY

[0008] To solve the above-mentioned technical problems in the prior art, the present application provides a vector decompression system and method.

[0009] The technical scheme of the present application is as follows:

[0010] In a first aspect, a vector decompression system is provided, which comprises:

[0011] The precision conversion module is connected to the input end of the pulse elimination module, and is used to convert the input mask vector into a single-precision mask vector and output the single-precision mask vector to the pulse elimination module;

[0012] The delay chain module is connected to the input end of the pulse elimination module, and is used to generate a series of continuous pulses according to the input pulse and output the series of continuous pulses to the pulse elimination module;

[0013] The pulse elimination module is connected to the input end of the pulse merging and separating module and the input end of the destination vector sampling module, respectively, and is used to eliminate part of the continuous pulses received according to the input single-precision mask vector, to obtain effective sampling pulses and output the effective sampling pulses to the pulse merging and separating module and the destination vector sampling module, respectively;

[0014] The pulse merging and separating module is connected to the input end of the data serial module, and is used to merge all the effective sampling pulses received into a signal, separate the merged signal into a plurality of separated pulses which are continuous in space and separated in time, and output the plurality of separated pulses to the data serial module;

[0015] The data serial module is connected with the input end of the destination vector sampling module, and is used for converting the plurality of parallel vector elements in the input source vector into a single vector element changing with time according to the received separation pulse, obtaining serial data and outputting to the destination vector sampling module.

[0016] The destination vector sampling module is used for sampling the received serial data simultaneously by using the received effective sampling pulse to obtain the destination vector.

[0017] In some embodiments, the precision conversion module comprises a selector, which is provided with a plurality of data input ports, a control port and a data output port, the plurality of data input ports are respectively used for receiving mask vectors with different precisions, the control port is used for controlling precision, and the data output port is used for outputting a single-precision mask vector.

[0018] In some embodiments, the delay chain module comprises a plurality of buffers connected in sequence, the input of the first buffer is used for receiving an input pulse, and the outputs of the plurality of buffers jointly constitute the output of the delay chain module.

[0019] In some embodiments, the pulse rejection module comprises a plurality of first AND gates, one input end of each of the plurality of first AND gates is connected with the output end of the plurality of buffers, the other input end of each of the plurality of first AND gates is connected with the output end of the precision conversion module, the other input end of each of the plurality of first AND gates is used for receiving a plurality of elements of the single-precision mask vector, and the output ends of the plurality of first AND gates jointly constitute the output end of the pulse rejection module.

[0020] In some embodiments, the pulse merging and separating module comprises a pulse merging circuit and a pulse separating circuit, the input end of the pulse merging circuit is connected with the output end of the pulse rejection module, the output end of the pulse merging circuit is connected with the input end of the pulse separating circuit, the output end of the pulse separating circuit is connected with the input end of the data serial module, the pulse merging circuit is used for merging all the received effective sampling pulses into a signal, and outputs the merged signal to the pulse separating circuit, and the pulse separating circuit is used for separating the merged signal into a plurality of separated pulses which are continuous in space and separated in time, and outputs the plurality of separated pulses to the data serial module.

[0021] In some embodiments, the pulse merging circuit comprises a first OR gate tree, a plurality of input ends of the first OR gate tree are respectively connected with the output ends of the plurality of first AND gates, and the first OR gate tree is used for merging the effective sampling pulses output by the plurality of first AND gates into a signal, and outputs the merged signal to the pulse separating circuit.

[0022] In some embodiments, the pulse separation circuit comprises a plurality of registers, a plurality of NOT gates and a positive power supply voltage;

[0023] The data input of the first register is connected to the positive power supply voltage, the data output of the first register is connected to the data input of the second register through a NOT gate, the data input and the data output of the second register to the last register are connected in sequence, the data output of the second register to the last register is also connected to the clock input of the first register, the data output of the second register to the last register is also connected to the reset input of the previous register through a NOT gate, the data output of the second register to the last register is also connected to the data serial module, the clock input of the second register to the last register is connected to the output of the first OR gate tree, and the second register to the last register outputs a separation pulse.

[0024] In some embodiments, the data serial module comprises a plurality of second AND gates and a second OR gate tree.

[0025] One input of the plurality of second AND gates is connected to the data output of the second register to the last register in the pulse combination and separation module, the other input of the plurality of second AND gates is used to receive a plurality of elements of a source vector, the output of the plurality of second AND gates is connected to a plurality of inputs of the second OR gate tree, and the output of the second OR gate tree is connected to the destination vector sampling module.

[0026] In some embodiments, the destination vector sampling module comprises a plurality of multi-bit registers, the data input of the plurality of multi-bit registers is connected to the output of the second OR gate tree in the data serial module, and the clock input of the plurality of multi-bit registers is connected to the output of the plurality of first AND gates in the pulse elimination module.

[0027] The second aspect also provides a vector decompression method, which comprises:

[0028] Converting a mask vector into a single-precision mask vector;

[0029] Generating a series of continuous pulses;

[0030] Eliminating part of the pulses in the continuous pulses according to the single-precision mask vector to obtain effective sampling pulses;

[0031] Combining all the effective sampling pulses into a signal, and separating the combined signal into a plurality of separated pulses which are continuous in space and separated in time.

[0032] According to the separated pulse, parallel multiple vector elements in the source vector are converted into a single vector element changing over time, and serial data is obtained;

[0033] The serial data is sampled by using an effective sampling pulse, and a target vector is obtained.

[0034] The main advantages of the technical scheme of the present application are as follows:

[0035] The vector decompression system and method of the present application can perform vector decompression based on a time domain calculation mode. When performing vector decompression, data is sampled by using a pulse. By using the characteristic that the pulse has only one bit, the required selector tree and control logic circuit can be reduced, the hardware overhead can be reduced, the power consumption can be reduced, and the energy efficiency can be improved. By converting all elements in the source vector into serial data and then transmitting the serial data to the target vector, only a data path from multiple to one and then to multiple needs to be established, and the hardware overhead can be further reduced, the power consumption can be reduced, and the energy efficiency can be improved. By setting the precision conversion module to convert the mask vectors of different precisions into a single precision mask vector, vector decompression of different precisions can be realized, independent design of components corresponding to different precisions can be avoided, the hardware overhead can be reduced, the power consumption can be reduced, and the energy efficiency can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0036] The accompanying drawings, which are included to provide a further understanding of the embodiments of the present application, constitute a part of the present application and illustrate the preferred embodiments of the present application and their description serves to explain the present application and does not constitute an improper limitation of the present application. In the drawings:

[0037] Figure 1 A vector decompression principle schematic diagram when the precision is 8 bits is provided as an example;

[0038] Figure 2 A vector decompression principle schematic diagram when the precision is 16 bits is provided as an example;

[0039] Figure 3 A vector decompression principle schematic diagram when the precision is 32 bits is provided as an example;

[0040] Figure 4 A vector decompression principle schematic diagram when the precision is 64 bits is provided as an example;

[0041] Figure 5 A structure schematic diagram of a vector decompression system according to an embodiment of the present application;

[0042] Figure 6 A structure schematic diagram of another vector decompression system according to an embodiment of the present application;

[0043] Figure 7A working principle schematic diagram of a vector decompression system provided by an embodiment of the present application is provided.

[0044] Figure 8 A flow schematic diagram of a vector decompression method provided by an embodiment of the present application is provided. DETAILED DESCRIPTION

[0045] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described below in detail with specific embodiments of the present application and corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0046] The technical solutions provided by the embodiments of the present application will be described in detail below with reference to the drawings.

[0047] Reference Figure 5 In a first aspect, the embodiments of the present application provide a vector decompression system, which comprises:

[0048] The precision conversion module is connected with the input end of the pulse rejection module, and is configured to convert the input mask vector into a single-precision mask vector and output the single-precision mask vector to the pulse rejection module;

[0049] The delay chain module is connected with the input end of the pulse rejection module, and is configured to generate a series of continuous pulses according to the input pulse and output the series of continuous pulses to the pulse rejection module;

[0050] The pulse rejection module is connected with the input end of the pulse merging and separating module and the input end of the destination vector sampling module, respectively, and is configured to reject part of the continuous pulses according to the input single-precision mask vector, obtain effective sampling pulses, and output the effective sampling pulses to the pulse merging and separating module and the destination vector sampling module, respectively;

[0051] The pulse merging and separating module is connected with the input end of the data serial module, and is configured to merge all the received effective sampling pulses into a signal, separate the merged signal into a plurality of separated pulses which are continuous in space and separated in time, and output the plurality of separated pulses to the data serial module;

[0052] The data serial module is connected with the input end of the destination vector sampling module, and is configured to convert a plurality of vector elements in the input source vector which are parallel into a single vector element which changes over time according to the received separated pulses, obtain serial data, and output the serial data to the destination vector sampling module;

[0053] The destination vector sampling module is configured to sample the received serial data simultaneously by using the received effective sampling pulses, and obtain a destination vector.

[0054] The vector decompression system provided by the embodiment of the present application can realize vector decompression by time domain calculation, and can realize vector decompression of different precisions. When the vector decompression is performed, the precision conversion module is input with a mask vector used for vector decompression, the delay chain module is input with a pulse, and the data serial module is input with a source vector used for vector decompression. The precision conversion module converts the input mask vector into a single-precision mask vector and outputs the single-precision mask vector to the pulse elimination module. The delay chain module generates a series of continuous pulses according to the input pulse and outputs the series of continuous pulses to the pulse elimination module. The pulse elimination module eliminates part of the received continuous pulses according to the single-precision mask vector, that is, eliminates invalid sampling pulses, obtains valid sampling pulses, and outputs the valid sampling pulses to the pulse merging and separating module and the destination vector sampling module respectively. The pulse merging and separating module merges all the received valid sampling pulses into a signal, separates the merged signal into a plurality of separated pulses which are continuous in space and separated in time, and outputs the plurality of separated pulses to the data serial module. The data serial module converts a plurality of vector elements in parallel in the input source vector into a single vector element changing with time according to the received separated pulses, obtains serial data, and outputs the serial data to the destination vector sampling module. The destination vector sampling module simultaneously samples the received serial data by using the plurality of received valid sampling pulses, and obtains a destination vector, so as to realize vector decompression.

[0055] The vector decompression system provided by the embodiment of the present application can realize vector decompression based on a time domain calculation mode. When the vector decompression is performed, data is sampled by a pulse. By using the characteristic that the pulse has only one bit, the required selector tree and control logic circuit can be reduced, the hardware overhead can be reduced, the power consumption can be reduced, and the energy efficiency can be improved. By converting all elements in the source vector into serial data and then sending the serial data to the destination vector, only a data path from multiple to one and then to multiple needs to be established, so that the hardware overhead can be further reduced, the power consumption can be reduced, and the energy efficiency can be improved. By setting the precision conversion module to convert mask vectors of different precisions into a single-precision mask vector, vector decompression of different precisions can be realized, independent design of components corresponding to different precisions can be avoided, the hardware overhead can be reduced, the power consumption can be reduced, and the energy efficiency can be improved.

[0056] Further, with reference to Figure 6 , in order to realize the function of the precision conversion module defined above, in the embodiment of the present application, the precision conversion module comprises a selector. The selector is provided with a plurality of data input ports, a control port and a data output port. The plurality of data input ports are respectively used for receiving mask vectors of different precisions. The control port is used for controlling precision. The data output port is used for outputting a single-precision mask vector.

[0057] In the embodiment of the present application, the selector is provided with four data input ports, and the four data input ports are respectively used for receiving mask vectors with precision of 8 bits, 16 bits, 32 bits and 64 bits.

[0058] In the embodiment of the present application, the single-precision mask vector represents the mask vector with precision of 8 bits. Specifically, when the precision of the input mask vector is 8 bits, the single-precision mask vector is the input mask vector; when the precision of the input mask vector is 16 bits, compared with the mask vector with precision of 16 bits, the even bits of the single-precision mask vector remain unchanged, and the odd bits are the same as the even bits of the lower one bit; when the precision of the input mask vector is 32 bits, compared with the mask vector with precision of 32 bits, the first four bits of the single-precision mask vector are all equal to the 0th bit of the mask vector, and the last four bits are all equal to the 4th bit of the mask vector; when the precision of the input mask vector is 64 bits, compared with the mask vector with precision of 64 bits, all the bits of the single-precision mask vector are equal to the 0th bit of the mask vector.

[0059] In the embodiment of the present application, by setting the precision conversion module, mask vectors with different precisions can be converted into single-precision mask vectors, so that a vector decompression structure can be used to realize vector decompression with different precisions.

[0060] Further, referring to Figure 6 , in order to realize the function of the delay chain module defined above, in the embodiment of the present application, the delay chain module comprises: a plurality of buffers connected in sequence, and the input of the first buffer is used for receiving an input pulse, and the outputs of the plurality of buffers jointly constitute the output of the delay chain module.

[0061] In the delay chain module, the number of buffers is determined according to the actual number of elements contained in the decompressed vector, and the number of buffers is the same as the number of elements contained in the vector.

[0062] In the embodiment of the present application, based on the delay chain module structure defined above, after one pulse is input into the first buffer, a delayed pulse can be obtained at the output of each buffer, and the plurality of pulses obtained through the plurality of buffers do not overlap in time and have equal time intervals.

[0063] Suppose the number of elements of the decompressed vector is N, and the number of buffers is set to N. Through the delay chain module, N continuous pulses, i.e., the pulses 1-pulse N shown in Figure 6 , can be obtained.

[0064] Further, referring to Figure 6In order to realize the function of the pulse elimination module defined above, in the embodiment of the present application, the pulse elimination module comprises: a plurality of first AND gates, one input end of each of the plurality of first AND gates is connected with the output end of a corresponding one of the plurality of buffers, the other input end of each of the plurality of first AND gates is connected with the output end of the precision conversion module, the other input end of each of the plurality of first AND gates is used for receiving a corresponding one of the plurality of elements of the single-precision mask vector, and the output ends of the plurality of first AND gates jointly constitute the output end of the pulse elimination module.

[0065] The number of the first AND gates in the pulse elimination module is determined according to the number of the elements contained in the actually decompressed vector, and the number of the first AND gates is the same as the number of the elements contained in the vector.

[0066] In the embodiment of the present application, based on the structure of the pulse elimination module defined above, one end of each of the first AND gates inputs one pulse in the continuous pulses, and the other end inputs one element in the single-precision mask vector. If the input element of the single-precision mask vector is 0, the pulse signal output by the corresponding first AND gate is 0. If the input element of the single-precision mask vector is 1, the pulse signal output by the corresponding first AND gate remains unchanged. The pulse signal with 0 is an invalid sampling pulse, and the pulse signal remaining unchanged is a valid sampling pulse.

[0067] Suppose the number of the elements of the decompressed vector is N, the number of the first AND gates is set to N, one end of each of the N first AND gates inputs the pulse output by a corresponding one of the N buffers, i.e. pulse 1-pulse N, and the other end of each of the N first AND gates inputs a corresponding one of the N elements in the single-precision mask vector, i.e. single-precision mask vector element 1-single-precision mask vector element N. The input of the Nth first AND gate is the pulse output by the Nth buffer and the Nth element in the single-precision mask vector.

[0068] Further, referring to Figure 6 In order to realize the function of the pulse elimination module defined above, in the embodiment of the present application, the pulse elimination module comprises: a plurality of first AND gates, one input end of each of the plurality of first AND gates is connected with the output end of a corresponding one of the plurality of buffers, the other input end of each of the plurality of first AND gates is connected with the output end of the precision conversion module, the other input end of each of the plurality of first AND gates is used for receiving a corresponding one of the plurality of elements of the single-precision mask vector, and the output ends of the plurality of first AND gates jointly constitute the output end of the pulse elimination module.

[0069] Further, referring to Figure 6In the embodiment of the present application, the pulse merging circuit comprises a first OR gate tree, a plurality of inputs of the first OR gate tree are connected with outputs of a plurality of first AND gates respectively, the first OR gate tree is used for merging the valid sampling pulses output by the plurality of first AND gates into one signal, and the merged signal is output to the pulse separation circuit.

[0070] In the embodiment of the present application, the first OR gate tree merges the input valid sampling pulses into one signal, and the signal has all the valid sampling pulses which are not overlapped in time.

[0071] Further, referring to Figure 6 In the embodiment of the present application, the pulse separation circuit comprises a plurality of registers, a plurality of NOT gates and a positive power supply voltage.

[0072] The data input of the first register is connected with the positive power supply voltage, the data output of the first register is connected with the data input of the second register through a NOT gate, the data input and the data output of the second register to the last register are connected in sequence, the data output of the second register is also connected with the clock input of the first register, the data output of the last register is also connected with the reset input of the previous register through a NOT gate, the data output of the second register to the last register is also connected with a data serial module respectively, the clock input of the second register to the last register is connected with the output of the first OR gate tree respectively, and the second register to the last register outputs a separated pulse respectively.

[0073] In the embodiment of the present application, the number of registers in the pulse separation circuit is determined according to the number of elements contained in the actual decompressed vector, and the number of registers is one more than the number of elements contained in the vector.

[0074] In the embodiment of the present application, based on the above defined pulse separation circuit structure, the clock signal of the register in the pulse separation circuit comes from the output signal of the first OR gate tree, when the next register outputs a rising edge, the previous register is reset, the output of the previous register is pulled low, and thus a separated pulse is generated; through the above defined pulse separation circuit, the merged signal output by the pulse merging circuit is split into a plurality of separated pulses in the pulse separation circuit, and the plurality of separated pulses are continuous in space and separated in time.

[0075] Further, referring to Figure 6 In order to realize the function of the above defined data serial module, in the embodiment of the present application, the data serial module comprises a plurality of second AND gates and a second OR gate tree.

[0076] The input end of the plurality of second AND gates is connected with the data output end of the second register to the last register in the pulse merging and separating module respectively, the other input end of the plurality of second AND gates is used for receiving a plurality of elements of the source vector respectively, the output end of the plurality of second AND gates is connected with the plurality of input ends of the second OR gate tree respectively, and the output end of the second OR gate tree is connected with the destination vector sampling module.

[0077] The number of the second AND gates in the data serial module is determined according to the number of elements contained in the actually decompressed vector, and the number of the second AND gates is the same as the number of elements contained in the vector.

[0078] In the embodiment of the application, based on the structure of the data serial module defined above, the separated pulses output by the second register to the last register in the pulse merging and separating module can be ANDed with the corresponding elements in the source vector through the second AND gates respectively to obtain the separated source vector elements, the second OR gate tree converts a plurality of separated source vector elements into a single vector element changing over time to obtain serial data and output.

[0079] Further, referring to Figure 6 In order to realize the function of the destination vector sampling module defined above, in the embodiment of the application, the destination vector sampling module comprises: a plurality of multi-bit registers, the data input end of the plurality of multi-bit registers is connected with the output end of the second OR gate tree in the data serial module respectively, and the clock input end of the plurality of multi-bit registers is connected with the output end of the plurality of first AND gates in the pulse elimination module respectively.

[0080] The number of the multi-bit registers in the destination vector sampling module is determined according to the number of elements contained in the actually decompressed vector, and the number of the multi-bit registers is the same as the number of elements contained in the vector. The data bit width of the multi-bit register is determined according to the actual situation.

[0081] In the embodiment of the application, based on the structure of the destination vector sampling module defined above, the multi-bit register of each element is driven by the same sampling clock, the serial data is connected to all the elements at the same time, and the sampling pulse aligned with the serial data can obtain the correct value, so that the destination vector is obtained, and the vector decompression process is completed.

[0082] It should be noted that, in the attached Figure 7 In the attached

[0083] Further, referring to Figure 8For example, the working principle of the vector decompression system provided by the embodiment of the present application is illustrated by taking a mask vector with a precision of 16 bits, a mask vector precision of 16 bits, and a source vector of "hgfedcba" as an example, to perform vector decompression with a precision of 16 bits:

[0084] First, the precision conversion module converts the mask vector "01001101" with a precision of 16 bits into a single-precision mask vector "11001111". The delay chain module generates 8 continuous pulses that are not overlapped in time and have equal time intervals according to an input pulse. Since the single-precision mask vector is "11001111", the 5th and 6th pulses in the 8 continuous pulses are invalid sampling pulses (dashed part), and the 1st, 2nd, 3rd, 4th, 7th and 8th pulses are valid sampling pulses (solid part) after passing through the pulse elimination module. Since the 1st, 2nd, 3rd, 4th, 7th and 8th pulses are valid sampling pulses, the 1st, 2nd, 3rd, 4th, 7th and 8th pulses are respectively put into separated pulses 1, 2, 3, 4, 5 and 6 in the pulse merging and separation module, and the falling edge of the previous pulse is aligned with the rising edge of the next pulse. Since the 1st, 2nd, 3rd, 4th, 7th and 8th pulses are valid sampling pulses, a, b, c, d, e and f become serial data in the data serial module. In the destination vector sampling module, the 1st valid sampling pulse samples element a, the 2nd valid sampling pulse samples element b, the 3rd valid sampling pulse samples element c, the 4th valid sampling pulse samples element d, the 5th valid sampling pulse samples element e, and the 6th valid sampling pulse samples element f, thereby completing the entire vector decompression process.

[0085] Reference ​ In a second aspect, the embodiment of the present application further provides a vector decompression method, which comprises the following steps 1-6:

[0086] Step 1: converting the mask vector into a single-precision mask vector;

[0087] In the embodiment of the present application, the given mask vector for vector decompression is converted into a single-precision mask vector. The precision of the given mask vector for vector decompression can be the same as or different from the precision of the single-precision mask vector.

[0088] Step 2: generating a series of continuous pulses;

[0089] In the embodiment of the present application, the number of continuous pulses is the same as the number of elements contained in the actual decompressed vector.

[0090] Step 3: eliminating part of the continuous pulses according to the single-precision mask vector to obtain valid sampling pulses;

[0091] In the embodiment of the present application, the pulse corresponding to the position where the element in the single-precision mask vector is 0 is removed.

[0092] Step 4: combine all the valid sampling pulses into one signal, and separate the combined signal into a plurality of separated pulses which are continuous in space and separated in time;

[0093] Step 5: convert the plurality of vector elements in the source vector which are in parallel into a single vector element which changes over time according to the separated pulses, to obtain serial data;

[0094] Step 6: sample the serial data by using the valid sampling pulses to obtain the target vector.

[0095] The vector decompression method provided by the embodiment of the present application can perform vector decompression based on a time domain calculation mode, and when performing vector decompression, data is sampled by using pulses, and by using the characteristic that the pulse has only one bit, the required selector tree and control logic circuit can be reduced, the hardware overhead can be reduced, the power consumption can be reduced, and the energy efficiency can be improved; by converting all the elements in the source vector into serial data and then sending the serial data to the target vector, only a data path from multiple to one and then to multiple needs to be established, and the hardware overhead can be further reduced, the power consumption can be reduced, and the energy efficiency can be improved; by converting the mask vectors of different precisions into single-precision mask vectors, vector decompression of different precisions can be realized, independent design of components corresponding to different precisions can be avoided, the hardware overhead can be reduced, the power consumption can be reduced, and the energy efficiency can be improved.

[0096] It should be noted that, in this document, relational terms such as“first” and“second”, and the like, are used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms“comprises”,“comprising”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Furthermore, the terms“front”,“rear”,“left”,“right”,“up”, and“down”, and the like, are used in this document for the purpose of description and reference only, and do not necessarily have to be in accordance with the practical placement or arrangement of the described or illustrated objects.

[0097] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A vector decompression system, characterized by, include: A precision conversion module, connected to the input of the pulse rejection module, is used to convert the input mask vector into a single-precision mask vector and output it to the pulse rejection module. The delay chain module is connected to the input terminal of the pulse rejection module and is used to generate a series of continuous pulses based on the input pulse and output them to the pulse rejection module. The pulse rejection module is connected to the input of the pulse merging and separating module and the input of the destination vector sampling module, respectively. It is used to reject part of the pulses in the received continuous pulses according to multiple vector elements of the input single-precision mask vector, so as to obtain effective sampled pulses and output them to the pulse merging and separating module and the destination vector sampling module, respectively. The pulse combining and separating module is connected to the input terminal of the data serialization module. It is used to combine all the received valid sampled pulses into one signal, separate the combined signal into multiple separate pulses that are spatially continuous and temporally separated, and output the multiple separate pulses to the data serialization module. The data serialization module is connected to the input terminal of the destination vector sampling module and is used to convert multiple parallel vector elements in the input source vector into a single vector element that changes over time according to the received separation pulse, so as to obtain serial data and output it to the destination vector sampling module. The destination vector sampling module is used to simultaneously sample the received serial data using the received valid sampling pulses to obtain the destination vector.

2. The vector decompression system of claim 1, wherein, The precision conversion module includes a selector, which has multiple data input ports, a control port, and a data output port. The multiple data input ports are used to receive mask vectors of different precisions, the control port is used to control the precision, and the data output port is used to output a single-precision mask vector.

3. The vector decompression system of claim 2, wherein, The delay chain module includes: a plurality of buffers connected in sequence, wherein the input of the first buffer is used to receive an input pulse, and the outputs of the plurality of buffers together constitute the output of the delay chain module.

4. The vector decompression system of claim 3, wherein, The pulse rejection module includes: a plurality of first AND gates, one input of each of the plurality of first AND gates being connected to the output of a plurality of buffers, another input of each of the plurality of first AND gates being connected to the output of the precision conversion module, another input of each of the plurality of first AND gates being used to receive multiple elements of a single-precision mask vector, and the outputs of the plurality of first AND gates together constituting the output of the pulse rejection module.

5. The vector decompression system of claim 4, wherein, The pulse combining and separating module includes a pulse combining circuit and a pulse separating circuit. The input terminal of the pulse combining circuit is connected to the output terminal of the pulse rejection module, the output terminal of the pulse combining circuit is connected to the input terminal of the pulse separating circuit, and the output terminal of the pulse separating circuit is connected to the input terminal of the data serialization module. The pulse combining circuit is used to combine all received valid sampled pulses into one signal and output the combined signal to the pulse separating circuit. The pulse separating circuit is used to separate the combined signal into multiple separate pulses that are spatially continuous and temporally separated, and output the multiple separate pulses to the data serialization module.

6. The vector decompression system of claim 5, wherein, The pulse combination circuit comprises a first OR gate tree, a plurality of inputs of the first OR gate tree are connected with outputs of a plurality of first AND gates respectively, and the first OR gate tree is used for combining valid sampling pulses output by the plurality of first AND gates into one signal and outputting the combined signal to the pulse separation circuit.

7. The vector decompression system of claim 6, wherein, The pulse separation circuit comprises a plurality of registers, a plurality of NOT gates and a positive power supply voltage; A data input of a first register is connected with the positive power supply voltage, a data output of the first register is connected with a data input of a second register through a NOT gate, data inputs and data outputs of the second register to a last register are connected in sequence, a data output of the second register is also connected with a clock input of the first register, data outputs of the second register to the last register are also connected with reset inputs of previous registers through NOT gates respectively, the data outputs of the second register to the last register are also connected with the data serial module respectively, clock inputs of the second register to the last register are connected with outputs of the first OR gate tree respectively, and the second register to the last register outputs separation pulses respectively.

8. The vector decompression system of claim 7, wherein, The data serial module comprises a plurality of second AND gates and a second OR gate tree. One input of each of the plurality of second AND gates is connected with a data output of the second register to the last register in the pulse combination and separation module, another input of each of the plurality of second AND gates is used for receiving a plurality of elements of a source vector, and outputs of the plurality of second AND gates are connected with a plurality of inputs of the second OR gate tree respectively, and an output of the second OR gate tree is connected with the destination vector sampling module.

9. The vector decompression system of claim 8, wherein, The destination vector sampling module comprises a plurality of multi-bit registers, data inputs of the plurality of multi-bit registers are connected with an output of the second OR gate tree in the data serial module respectively, and clock inputs of the plurality of multi-bit registers are connected with outputs of the plurality of first AND gates in the pulse elimination module respectively.

10. A method of vector decompression, the method comprising: The method applies the vector decompression system according to any one of claims 1-9, and the method comprises: Converting a mask vector into a single-precision mask vector; Generating a series of continuous pulses; Eliminating part of the pulses in the continuous pulses according to a plurality of vector elements of the single-precision mask vector to obtain valid sampling pulses; Combining all the valid sampling pulses into one signal, and separating the combined signal into a plurality of separation pulses which are spatially continuous and temporally separated; Converting a plurality of vector elements in a source vector which are parallel in time into a single vector element which changes over time according to the separation pulses to obtain serial data; Sampling the serial data simultaneously by using the valid sampling pulses to obtain a destination vector.

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