Chip system, debugging method and electronic equipment

Abstract

The embodiment of the invention provides a chip system, a debugging method and electronic equipment, and is applied to the technical field of chip data security design. The chip system comprises a processor and a read-only memory. The processor includes a JTAG interface and a first data interface. The read-only memory comprises a second data interface. Wherein the processor is used for performing JTAG debugging based on the JTAG interface when a data reading path between the first data interface and the second data interface is in a closed state. And when the data reading path is in the open state, keeping the JTAG interface in the closed state. According to the embodiment of the invention, the JTAG interface and the data reading path are set to be mutually exclusive, so that the risk of reading important data in the read-only memory based on JTAG access is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip data security design, and particularly relates to a chip system, a debugging method and an electronic device. BACKGROUND

[0002] The chip system includes a processor and a read-only memory (ROM). The ROM can store important data such as a firmware program, a key running code, and an encryption key of encrypted data required for running. Generally, the important information has certain security requirements, and in many cases, it is necessary to ensure that the important information is not acquired by a user or other unauthorized person. In the design of the chip, all processor devices need to be provided with a Joint Test Action Group (JTAG) interface, and a debugging function is provided for a user based on the JTAG interface. At this time, when the processor is debugged based on the JTAG interface, there is a risk that the important data in the ROM is illegally accessed and acquired through the JTAG interface of the processor. SUMMARY

[0003] Embodiments of the present application provide a chip system, a debugging method and an electronic device, which avoid the risk of reading important data in the ROM based on the JTAG interface of the processor.

[0004] To achieve the above object, embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a chip system is provided, which includes a processor and a read-only memory. The processor includes a JTAG interface and a first data interface. The read-only memory includes a second data interface. The processor is configured to perform JTAG debugging based on the JTAG interface when a data reading path between the first data interface and the second data interface is in a closed state. When the data reading path is in an open state, the JTAG interface is kept in a closed state.

[0006] In the embodiments of the present application, the opening of the JTAG interface and the opening of the data reading path are enabled to be mutually exclusive, that is, when the JTAG interface is opened for JTAG debugging, the data reading path is controlled to be closed. When the data reading path is opened, the JTAG interface is controlled to be closed. In this way, reading of important data in the ROM cannot be performed when debugging based on the JTAG interface. Through this enabled mutual exclusion, the risk of reading important data in the ROM based on the JTAG interface is avoided.

[0007] In a possible implementation, different schemes can be designed to realize the enablement mutual exclusion between the JTAG interface and the data reading path in different application scenarios, which are illustrated in the following several manners:

[0008] For example one, in a possible implementation, the important data to be protected includes a firmware program in a read-only memory. At this time, before JTAG debugging based on the JTAG interface, the processor is further configured to read the firmware program from the read-only memory based on the data reading path, and run the firmware program. Before the firmware program is run completely, a first indication signal is output to the read-only memory, and the first indication signal is used to instruct the read-only memory to control the data reading path to keep in a closed state. In the embodiment of the present application, the processor needs to run the firmware program when starting to perform relevant parameter configuration and the like. At this time, the data reading path is in an open state, and the processor keeps the JTAG interface in a closed state. Before the firmware program is about to be run completely (for example, when running to the last few lines of code or the last line of code of the firmware program), the processor outputs the first indication signal to the read-only memory. After receiving the first indication signal, the read-only memory controls the data reading path to keep in a closed state. At this time, the processor has jumped out of the running of the firmware program, and the JTAG interface can be set to an open state to perform JTAG testing.

[0009] In some examples, in the above example one, the read-only memory is configured to output, to the JTAG interface, a first control signal of a first value when the data reading path is in an open state, the first control signal of the first value being used to control the JTAG interface to keep in a closed state. When the data reading path is in a closed state, the read-only memory is configured to output, to the JTAG interface, a first control signal of a second value, the first control signal of the second value being used to control the JTAG interface to keep in an open state. In the embodiment of the present application, the enablement mutual exclusion between the JTAG interface and the data reading path can be realized by the read-only memory outputting the first control signal of the opposite value.

[0010] Exemplarily, the read-only memory comprises an enable register and an inverter. An output terminal of the enable register is connected with an input terminal of the inverter and an enable terminal of the second data interface respectively; and an output terminal of the inverter is used for outputting the first control signal. In the embodiment of the present application, the first value and the second value are two values which are inversed. The read-only memory can output the first control signal with different values according to the state of the second data interface. When the enable register of the read-only memory outputs the first control signal with the first value to the second data interface, the first control signal with the first value will also be inversed by the inverter to output the first control signal with the second value to the JTAG interface. Similarly, when the enable register of the read-only memory outputs the first control signal with the second value to the second data interface, the first control signal with the second value will also be inversed by the inverter to output the first control signal with the first value to the JTAG interface. Through the implementation, it can be ensured that the control signals with opposite values are always received between the JTAG interface and the second data interface as the enable signals, so as to realize the enable mutual exclusion between the JTAG interface and the data reading path.

[0011] In one example, the first control signal comprises a plurality of value bits. In the embodiment of the present application, the first control signal with a plurality of value bits can increase the safety reliability of the scheme implementation, and it is more difficult to simulate the first control signal with a plurality of value bits than the first control signal with one value bit.

[0012] Exemplarily, the first value can be 5, which is 0101 in binary expression; and when the first control signal is 4 value bits, the second value can be 1010 (i.e. 10 in decimal). In one example, the first value can be 10, which is 1010 in binary expression; and when the first control signal is 4 value bits, the second value can be 0101 (i.e. 5 in decimal). In the embodiment of the present application, compared with the value 1 or the value 0, the value 5 or the value 10 selected as the first value can improve the safety reliability.

[0013] In the second example, in a possible implementation, the state of the JTAG interface can be detected, and the state of the data read path is determined according to the state of the JTAG interface. At this time, the chip system further includes a first digital control circuit. The first digital control circuit is connected with the JTAG interface and the second data interface respectively. The first digital control circuit is configured to: in response to the processor starting JTAG debugging based on the JTAG interface, output a second control signal to the second data interface, and the second control signal is used to instruct the read-only memory to control the data read path to keep in a closed state. In the embodiment of the present application, the working state of the second data interface can be controlled based on the working state of the JTAG interface, so as to realize the enablement mutual exclusion between the JTAG interface and the data read path. Specifically, when the first digital control circuit detects that the JTAG interface is performing JTAG debugging, the second data interface can be instructed to be in a closed state by the second control signal, so as to control the data read path to keep in a closed state.

[0014] In one example, the first digital control circuit is further configured to: output a third control signal to the second data interface when the processor is not performing JTAG debugging based on the JTAG interface, and the third control signal is used to instruct the read-only memory to control the data read path to keep in an open state. In the embodiment of the present application, when the first digital control circuit detects that the JTAG interface is not performing JTAG debugging, the second data interface can be instructed to be in an open state by the third control signal, so as to control the data read path to keep in an open state.

[0015] In one example, the first digital control circuit can determine whether the JTAG interface is performing JTAG debugging based on the level state change of the JTAG interface. For example, the JTAG interface includes a TMS line. The first digital control circuit is further configured to: determine whether the processor is performing JTAG debugging based on the JTAG interface according to the level state of the TMS line. In the embodiment of the present application, the state change of the TMS line is used to control the state of the JTAG debugging. When the level of the TMS line is 0, it indicates that the next state is switched. Therefore, whether the JTAG interface starts JTAG debugging work can be determined by the level state change of the TMS line. For another example, when the JTAG interface further includes a TRST line, when the first digital control circuit detects that the level of the TMS line is 0 for the first time after the TRST line is reset, it is determined that the JTAG interface starts JTAG debugging.

[0016] In the third example, in a possible implementation, the JTAG debugging permission can be reserved once, and the JTAG debugging function is closed after the JTAG debugging permission. At this time, the chip system further includes a second digital control circuit. The second digital control circuit is configured to: output a fourth control signal to the JTAG interface and output a fifth control signal to the second data interface when the processor performs JTAG debugging based on the JTAG interface for the first time, the fourth control signal being used to control the JTAG interface to keep in an open state, and the fifth control signal being used to instruct the ROM to control the data reading path to keep in a closed state. After the processor performs JTAG debugging based on the JTAG interface for the first time, output a sixth control signal to the JTAG interface and output a seventh control signal to the second data interface, the sixth control signal being used to control the JTAG interface to keep in a closed state, and the seventh control signal being used to instruct the ROM to control the data reading path to keep in an open state. In the embodiment of the present application, the JTAG debugging permission can be reserved once in the processor, and the user can perform JTAG debugging based on the JTAG interface once. During the JTAG debugging, the JTAG interface is controlled to keep in an open state based on the fourth control signal, and the second data interface is controlled to keep in a closed state based on the fifth control signal. After the JTAG debugging, the JTAG interface is controlled to keep in a closed state based on the sixth control signal, the JTAG debugging permission is disabled, and the second data interface is controlled to keep in an open state based on the seventh control signal. In the embodiment of the present application, the fourth control signal, the fifth control signal, the sixth control signal and the seventh control signal can be used to realize the enablement exclusion between the JTAG interface and the data reading path. At the same time, according to different use stages of the processor, the JTAG debugging permission is reserved, and the JTAG debugging permission is disabled after the JTAG debugging is performed.

[0017] In one example, the second digital control circuit runs with an otpc_jtag_disable program field. The control of enabling mutual exclusion can be implemented based on the value of the otpc_jtag_disable program field. At this time, the second digital control circuit is specifically configured to: when the processor first performs JTAG debugging based on the JTAG interface, maintain the value of the otpc_jtag_disable program field as a third value to output a fourth control signal and a fifth control signal. After the processor first performs JTAG debugging based on the JTAG interface, set the value of the otpc_jtag_disable program field to a fourth value to output a sixth control signal and a seventh control signal. In the embodiments of the present application, otpc_jtag_disable is a program field for controlling whether the JTAG function in the one-time programmable area is disabled. When the otpc_jtag_disable field is set to a certain value, it indicates that the JTAG function is disabled, that is, the chip cannot be tested and debugged through the JTAG interface. In this way, the security of the chip can be improved to prevent unauthorized access and attacks. The embodiments of the present application can set the otpc_jtag_disable program field to different values at different stages. For example, when the processor is first shipped, the otpc_jtag_disable program field in the second digital control circuit is a third value, at this time, the second digital control circuit can output the fifth control signal and the sixth control signal to control the JTAG interface to remain in an open state, and control the second data interface to remain in a closed state. After the first JTAG debugging after shipment, the second digital control circuit modifies the value of the otpc_jtag_disable program field based on the one-time programming function to a fourth value, and the value of the otpc_jtag_disable program field after one-time programming cannot be changed. In the subsequent running stage of the processor, the second digital control circuit outputs the sixth control signal and the seventh control signal to control the JTAG interface to remain in a closed state, and control the second data interface to remain in an open state. In the subsequent stage, the processor can normally access and read the data in the read-only memory, but the JTAG interface is completely disabled.

[0018] Exemplarily, the processor is specifically configured to: disable the permission of JTAG debugging when the JTAG interface is in the closed state; and open the permission of JTAG debugging when the JTAG interface is in the open state. The read-only memory is specifically configured to: disable the data access permission of the second data interface when the data reading path is in the closed state; and open the data access permission of the second data interface when the data reading path is in the open state. In the embodiments of the present application, the permission control of whether the processor is subjected to JTAG debugging can be realized by controlling the closing and opening of the JTAG interface. The opening or closing of the data reading path between the first data interface of the processor and the second data interface of the read-only memory can be realized by opening and closing the data access permission of the second data interface of the read-only memory. When the data access permission of the second data interface is open, data can be read from the read-only memory through the second data interface; otherwise, when the data access permission of the second data interface is closed, data cannot be read from the second data interface.

[0019] In a second aspect, the embodiments of the present application further provide a debugging method applied to a chip system, the chip system comprising a processor and a read-only memory. The processor comprises a JTAG interface and a first data interface. The read-only memory comprises a second data interface. The method comprises: the processor performing JTAG debugging based on the JTAG interface when a data reading path between the first data interface and the second data interface is in a closed state. The processor keeps the JTAG interface in a closed state when the data reading path is in an open state.

[0020] In a possible implementation, before performing JTAG debugging based on the JTAG interface, the method further comprises: the processor reading a firmware program from the read-only memory based on the data reading path. Running the firmware program. Outputting a first indication signal to the read-only memory before the firmware program is run completely, the first indication signal being used to instruct the read-only memory to control the data reading path to keep in the closed state.

[0021] In a possible implementation, the method further comprises: the read-only memory outputting a first control signal of a first value to the JTAG interface when the data reading path is in the open state, the first control signal of the first value being used to control the JTAG interface to keep in the closed state. The read-only memory outputting a first control signal of a second value to the JTAG interface when the data reading path is in the closed state, the first control signal of the second value being used to control the JTAG interface to keep in the open state.

[0022] In a possible implementation, the first control signal comprises a plurality of value bits.

[0023] In a possible implementation, the second value is 5 or 10.

[0024] In a possible implementation, the method further includes: in response to the processor starting JTAG debugging based on the JTAG interface, outputting a second control signal to the second data interface, the second control signal being used to instruct the read-only memory to keep the data read path in a closed state.

[0025] In a possible implementation, the method further includes: when the processor is not performing JTAG debugging based on the JTAG interface, outputting a third control signal to the second data interface, the third control signal being used to instruct the read-only memory to keep the data read path in an open state.

[0026] In a possible implementation, the JTAG interface includes a TMS line. The method further includes: determining whether the processor is performing JTAG debugging based on the JTAG interface according to a level state of the TMS line.

[0027] In a possible implementation, the method further includes: when the processor performs JTAG debugging based on the JTAG interface for the first time, outputting a fourth control signal to the JTAG interface and outputting a fifth control signal to the second data interface, the fourth control signal being used to control the JTAG interface to keep in an open state, and the fifth control signal being used to instruct the read-only memory to keep the data read path in a closed state. After the processor performs JTAG debugging based on the JTAG interface for the first time, outputting a sixth control signal to the JTAG interface and outputting a seventh control signal to the second data interface, the sixth control signal being used to control the JTAG interface to keep in a closed state, and the seventh control signal being used to instruct the read-only memory to keep the data read path in an open state.

[0028] In a possible implementation, the method specifically includes: when the processor performs JTAG debugging based on the JTAG interface for the first time, keeping the value of the otpc_jtag_disable program field as a third value to output the fourth control signal and the fifth control signal. After the processor performs JTAG debugging based on the JTAG interface for the first time, setting the value of the otpc_jtag_disable program field as a fourth value to output the sixth control signal and the seventh control signal.

[0029] Exemplarily, the method specifically includes: disabling the permission of performing JTAG debugging when the JTAG interface is in a closed state; enabling the permission of performing JTAG debugging when the JTAG interface is in an open state. Disabling the data access permission of the second data interface when the data read path is in a closed state; enabling the data access permission of the second data interface when the data read path is in an open state.

[0030] In a third aspect, the embodiments of the present application further provide an electronic device, which comprises a circuit board and the chip system as described in the first aspect above, and the chip system is arranged on the circuit board.

[0031] In a fourth aspect, the embodiments of the present application further provide a computer readable storage medium, which comprises instructions, when the instructions are executed on the chip system, causing the chip system to perform the debugging method as described in the second aspect above.

[0032] The technical principles and beneficial effects of the second aspect, the third aspect and the fourth aspect above can refer to the related description of the first aspect above, and will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 A schematic diagram of reading data in a read-only memory based on a JTAG interface according to an embodiment of the present application;

[0034] Figure 2 A structural schematic diagram of a chip system according to an embodiment of the present application Figure 1 ;

[0035] Figure 3 A structural schematic diagram of a chip system according to an embodiment of the present application Figure 2 ;

[0036] Figure 4 A structural schematic diagram of a chip system according to an embodiment of the present application Figure 3 ;

[0037] Figure 4 A structural schematic diagram of a chip system according to an embodiment of the present application Figure 6 ;

[0038] Figure 5 A structural schematic diagram of a chip system according to an embodiment of the present application Figure 7 ;

[0039] Figure 8 A flowchart of a first debugging method according to an embodiment of the present application;

[0040] Figure 9 A flowchart of a second debugging method according to an embodiment of the present application;

[0041] Figure 1 A flowchart of a third debugging method according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] It should be noted that the terms "first", "second", etc. used in the embodiments of the present application are only used for the purpose of distinguishing the same type of features, and should not be interpreted as indicating relative importance, quantity, order, etc.

[0043] The term "exemplary" or "for example" used in the embodiments of the present application is used to represent that an embodiment or example is an example or illustration, and should not be interpreted as meaning that the embodiment or example is preferred or superior to other embodiments or examples. In fact, the term "exemplary" or "for example" is used to present relevant concepts in a specific manner.

[0044] The term "coupling" or "connection" used in the embodiments of the present application should be interpreted in a broad sense, for example, it can refer to a direct connection in a physical sense, or an indirect connection through an electronic device, for example, a connection through a resistor, inductor, capacitor or other electronic device.

[0045] A chip system includes a processor and a read-only memory (ROM). The read-only memory is used to store fixed data and instructions. Unlike a memory such as a random access memory (RAM), the data in the ROM is written during the product design and manufacturing process, and these data cannot be modified or erased during normal operation. The main feature of the ROM is that the data stored therein is permanent, i.e., the stored content remains unchanged even after power-off or restart. This makes the ROM very suitable for storing some critical important data required for the processor to run, such as firmware programs, critical running codes, encryption keys for encrypted data, etc. Due to various considerations such as product operation safety, economy, etc., these critical important data are usually not accessible to unauthorized persons.

[0046] In the design of chips, basically all processing devices need to be provided with a Joint Test Action Group (JTAG) interface. The JTAG interface is a standard interface for testing and debugging integrated circuits. It can provide programmable access to internal signals and states of the chip, for verifying and debugging the correctness of the circuit and conducting fault diagnosis. The JTAG interface is usually composed of four signal lines, including a test clock input (TCK) line, a test mode selection input (TMS) line, a test data input (TDI) line and a test data output (TDO) line. Optionally, the JTAG interface can also include a test reset input (TRST) line, a return test clock (RTCK) line and a clock reset signal feedback (nSRST) line, etc. Through these signal lines, the JTAG interface can operate on the scan chain inside the chip, including reading and writing registers, triggering specific test modes, etc. The JTAG interface has a wide range of applications in hardware design and embedded system development. It can be used for chip production testing, fault diagnosis, firmware program download and debugging, etc.

[0047] A JTAG (Joint Test Action Group) emulator is a tool used for testing and debugging integrated circuits. It communicates with the target device (such as a processor) through a JTAG interface, enabling control, data reading and writing, and debugging functions. A JTAG emulator typically consists of both hardware and software. The hardware part includes JTAG interface circuits and related logic circuits for communication with the JTAG interface of the target device. The software part provides a graphical interface or command line interface for user interaction with the emulator and implements control and debugging operations on the target device. Using a JTAG emulator can achieve debugging, burning, and emulation functions, etc. Among them, based on the debugging function, single-step execution, breakpoint setting, register viewing and modification, etc. can be performed on the target device through the JTAG interface, helping developers locate and fix problems in the code. Based on the burning function, programs or firmware programs can be burned into the memory of the target device through the JTAG interface, realizing the function of firmware program update or software loading. Based on the emulation function: external signals can be simulated through the JTAG interface to verify the functionality and performance of the target device. Through the JTAG interface of the JTAG emulator and the processor, engineers can non-invasively access the internal signals and states of the chip, improving the efficiency of debugging and testing. However, in actual application, there is a risk of accessing important data in the ROM through the JTAG emulator and the JTAG interface of the processor during JTAG debugging. For example, the processor manufacturer sells products to secondary product manufacturers, and the secondary product manufacturers debug the processor based on the JTAG interface or burn new service function programs, etc. In this process, the secondary product manufacturers may obtain some important data written by the processor manufacturer in the ROM based on the JTAG interface, causing the leakage of important assets of the processor manufacturer. Alternatively, after purchasing the processor product, the illegal user obtains important data in the ROM based on the JTAG interface of the processor, and destroys some basic running functions or security service functions of the processor based on these important data, thereby causing the use safety risk of the product.

[0048] In a related technology, the relevant operation instructions for controlling the interception of accessing important data in the read-only memory can be realized by using the relevant indication signal when the processor enters the debugging mode as an enabling signal. At this time, when debugging the processor based on the JTAG interface, the processor will enter the debugging mode (debug_mode). The indication signal generated when the debugging mode is entered is used as an enabling signal to control the read-only memory storage address. In this state, the relevant instructions for accessing the read-only memory storage address issued by the processor will be intercepted, thereby avoiding accessing and reading important data in the read-only memory during the debugging process based on the JTAG interface. However, in this implementation, there are still security vulnerabilities, such asFigure 1 As shown in (a) of FIG. 1, the processor 100 is debugged by the JTAG emulator 400 and the JTAG interface 110 of the processor 100. When the processor 100 enters the debug mode, the processor 100 takes the storage address of the read-only memory 200 as the enable signal based on the enable signal when entering the debug mode. In theory, the processor 100 cannot access the read-only memory 200 in the debug mode. However, as shown in (a) of FIG. 1, the user can modify the RAM program code stored in the random access memory (RAM) 300 configured by the processor 100 through the JTAG emulator 400 and the JTAG interface 110 after entering the debug mode, and modify the RAM program code stored in the random access memory 300 into the code for accessing the read-only memory 200. Then, as shown in (b) of FIG. 1, the user controls the processor 100 to jump to the code in the random access memory 300 through the JTAG emulator 400, and then exits the test mode of the JTAG test. Then, as shown in (c) of FIG. 1, the processor 100 runs the program code for accessing the read-only memory 200 in the random access memory 300 in the normal working mode after exiting the debug mode, and realizes reading of the important data in the read-only memory 200. Then, the JTAG emulator 400 obtains the important data read by the processor 100 based on the JTAG interface 110. Therefore, the related art cannot completely avoid the leakage of the important data. Figure 1 Figure 1 Figure 1 Figure 2 In the embodiments, the random access memory 300 is set outside the processor 100. However, although not shown in the figure, in another example, the random access memory 300 can also be a storage device inside the processor 100.

[0049] ​​​In another related technology, a processor's JTAG debugging permissions can be graded, for example, into three different levels: completely prohibited, secure access, and fully permitted. The processor's JTAG debugging permissions can be adjusted by programming different program fields based on the processor's product stage (e.g., pre-shipment setup, post-shipment redesign, and fully designed use). Users at different use stages correspond to different debugging permissions. For example, a processor manufacturer can design and debug a processor with fully permitted permissions. After design and debugging, they can modify some program fields in the processor, changing the processor's JTAG debugging permissions to secure access. The processor can then be sold to a secondary product manufacturer. The secondary product manufacturer verifies the processor using a corresponding verification key and, if verified, performs JTAG debugging based on the secure access level. After the secondary product manufacturer completes JTAG debugging, subsequent users who purchase the product are completely prohibited from using the JTAG debugging function. However, this implementation only prevents unauthorized users who completely disable the JTAG debugging function from accessing important data in the ROM; it cannot completely prevent users with other permission levels from accessing important data in the ROM.

[0050] In order to solve the problem that users read important data (such as codes and keys) in read-only memory during JTAG debugging, the embodiment of the present application provides a chip system, such as Figure 2 As shown, the chip system 1000 includes a processor 100 and a read-only memory 200. The processor 100 includes a JTAG interface 110 and a first data interface 120, and the read-only memory 200 includes a second data interface 210. The first data interface 120 of the processor 100 is connected to the second data interface 210 of the read-only memory 200 to establish a data read path between the first data interface 120 of the processor 100 and the second data interface 210 of the read-only memory 200. The processor 100 is configured to: when the data read path between the first data interface 120 and the second data interface 210 is in a closed state, perform JTAG debugging based on the JTAG interface 110; when the data read path is in an open state, keep the JTAG interface 110 in a closed state. That is, the JTAG interface 110 and the data read path maintain mutual exclusion.

[0051] Exemplarily, the processor 100 is specifically configured to: disable the permission of JTAG debugging when the JTAG interface 110 is in the closed state; and open the permission of JTAG debugging when the JTAG interface 110 is in the open state. The read-only memory 200 is specifically configured to: disable the data access permission of the second data interface 210 when the data reading path is in the closed state; and open the data access permission of the second data interface 210 when the data reading path is in the open state. In the embodiment of the present application, by controlling the closing and opening of the JTAG interface 110, the permission control of whether the processor 100 is subjected to JTAG debugging can be realized. By opening and closing the data access permission of the second data interface 210 of the read-only memory 200, the opening or closing of the data reading path between the first data interface 120 of the processor 100 and the second data interface 210 of the read-only memory 200 can be realized. When the data access permission of the second data interface 210 is open, data can be read from the read-only memory 200 through the second data interface 210; otherwise, when the data access permission of the second data interface 210 is closed, data cannot be read from the second data interface 210.

[0052] In the embodiment of the present application as shown in the figure, Figure 3 In the embodiment of the present application as shown in the figure,

[0053] According to different application scenarios and implementation manners, different ways can be adopted to realize the enablement mutual exclusion between the JTAG interface 110 and the data reading path, and the following is exemplarily described in several implementation manners:

[0054] In the first example, in some possible implementation manners, when the important data to be protected is a firmware program in the read-only memory 200, the processor 100 needs to obtain the firmware program from the read-only memory 200 in the case of booting or restarting, and the like. At this time, the processor 100 needs to keep the JTAG interface 110 closed and keep the data read path open. The processor 100 is configured to read the firmware program from the read-only memory 200 based on the data read path. The firmware program is run. Before the firmware program is run, a first indication signal is output to the read-only memory 200, and the first indication signal is used to instruct the read-only memory 200 to control the data read path to keep a closed state. In the embodiment of the present application, the processor 100 needs to run the firmware program to perform relevant parameter configuration, and the like when booting. At this time, the data read path is in an open state, and the processor 100 keeps the JTAG interface 110 in a closed state. Before the firmware program is about to be run (for example, when the firmware program is run to the last few lines of code or the last line of code), the processor 100 outputs the first indication signal to the read-only memory 200. After the read-only memory 200 receives the first indication signal, the read-only memory 200 controls the data read path to keep a closed state. At this time, the processor 100 has jumped out of the running of the firmware program, and the JTAG interface 110 can be set to an open state to perform JTAG testing.

[0055] In one example, the working state of the JTAG interface 110 can be controlled based on a first control signal output as an enable signal by the read-only memory 200. At this time, the read-only memory 200 is configured to: output, to the JTAG interface 110, the first control signal as a first value when the data read path is in an open state, the first control signal as the first value being used to control the JTAG interface 110 to keep a closed state; and output, to the JTAG interface 110, the first control signal as a second value when the data read path is in a closed state, the first control signal as the second value being used to control the JTAG interface 110 to keep an open state.

[0056] Exemplarily, as Figure 4As shown, the read-only memory 200 includes an enable register 220 and an inverter 230; an output terminal of the enable register 220 is connected with an input terminal of the inverter 230 and an enable terminal of the second data interface 210 respectively; and an output terminal of the inverter 230 is configured to output a first control signal. In the embodiment of the present application, the first value and the second value are two values which are inversed. The read-only memory 200 can output the first control signal with different values according to the state of the second data interface 210. When the enable register 220 of the read-only memory 200 outputs the first control signal with the first value to the second data interface 210, the first control signal with the first value is also inversed by the inverter 230 to output the first control signal with the second value to the JTAG interface 110. Similarly, when the enable register 220 of the read-only memory 200 outputs the first control signal with the second value to the second data interface 210, the first control signal with the second value is also inversed by the inverter 230 to output the first control signal with the first value to the JTAG interface 110. Through the implementation, it can be ensured that the control signals with opposite values are always received between the JTAG interface 110 and the second data interface 210 as the enable signals, so as to realize the enable mutual exclusion between the JTAG interface 110 and the data reading path.

[0057] For example two, in some possible embodiments, the state of the JTAG interface 110 can be detected, and the state of the data reading path is determined according to the state of the JTAG interface 110. As shown in FIG. 1, the chip system 1000 further includes a first digital control circuit 500A. The first digital control circuit 500A is connected with the JTAG interface 110 and the second data interface 210 respectively. The first digital control circuit 500A is configured to: in response to that the processor 100 starts the JTAG debugging based on the JTAG interface 110, output a second control signal to the second data interface 210, the second control signal being used to instruct the read-only memory 200 to control the data reading path to keep in the closed state. Figure 5

[0058] In some possible embodiments, the first digital control circuit 500A is further configured to: when the processor 100 does not perform the JTAG debugging based on the JTAG interface 110, output a third control signal to the second data interface 210, the third control signal being used to instruct the read-only memory 200 to control the data reading path to keep in the open state.

[0059] ​In some possible embodiments, some wires of the JTAG interface 110 change in level when the JTAG interface 110 is in JTAG debugging. The change in level of the wires can be used to determine whether the JTAG interface 110 is in JTAG debugging. In one example, the JTAG interface 110 includes a TMS wire. The first digital control circuit 500A is further configured to determine whether the processor 100 is in JTAG debugging based on the JTAG interface 110 based on the level state of the TMS wire.

[0060] For example, when the level state of the TMS wire is detected to be 0 for the first time in a period of time, the first digital control circuit 500A outputs a second control signal to the second data interface 210 to control the data reading path to remain in the closed state. In the embodiments of the present application, the change in state of the TMS wire is used to control the state of JTAG debugging. When the level of the TMS wire is 0, it indicates that the next state is to be switched to. Therefore, whether the JTAG interface 110 starts JTAG debugging work can be determined by the change in level state of the TMS wire.

[0061] For example, when the JTAG interface 110 further includes a TRST wire, whether the JTAG interface 110 is in JTAG debugging can also be determined based on the TRST wire and the TMS wire. For example, when the level of the TMS wire is detected to be 0 for the first time after the TRST wire is reset, it is determined that the JTAG interface 110 starts JTAG debugging, and at this time, the first digital control circuit 500A outputs a second control signal to the second data interface 210.

[0062] For example, the first digital control circuit 500A can be a digital control circuit that performs digital logic operation based on the input level signal of the wire, and thus outputs a second control signal with a corresponding value. In the embodiments of the present application, the control signal of the control enable register is obtained through digital logic operation based on the change in level of the wire. When the JTAG interface 110 is in the open working state, the second data interface 210 is controlled to be in the closed state based on the control signal.

[0063] In some possible embodiments, in the example two of the above embodiments, after the processor 100 is powered on, the JTAG debugging can be performed after the processor 100 reads the related firmware program from the read-only memory 200 and executes it, so that the implementation of the example two can be ensured not to affect the execution of the related firmware program.

[0064] Example three, in some possible embodiments, one JTAG debugging permission can be reserved, and after the one JTAG debugging permission, the JTAG debugging function is closed. At this time, for example, Figure 6As shown, the chip system 1000 further comprises a second digital control circuit 500B. The second digital control circuit 500B is configured to: output a fourth control signal to the JTAG interface 110 and output a fifth control signal to the second data interface 210 when the processor 100 performs JTAG debugging based on the JTAG interface 110 for the first time, the fourth control signal being used to control the JTAG interface 110 to keep in an open state, and the fifth control signal being used to instruct the ROM 200 to control the data reading path to keep in a closed state. After the processor 100 performs JTAG debugging based on the JTAG interface 110 for the first time, output a sixth control signal to the JTAG interface 110 and output a seventh control signal to the second data interface 210, the sixth control signal being used to control the JTAG interface 110 to keep in a closed state, and the seventh control signal being used to instruct the ROM 200 to control the data reading path to keep in an open state.

[0065] In the embodiment of the present application, the JTAG debugging permission can be reserved in the processor 100 once, and the user can perform JTAG debugging based on the JTAG interface 110 once, during which the JTAG interface 110 is controlled to keep in an open state based on the fourth control signal and the second data interface 210 is controlled to keep in a closed state based on the fifth control signal. After the JTAG debugging, the JTAG interface 110 is controlled to keep in a closed state based on the sixth control signal, the JTAG debugging permission is disabled, and the second data interface 210 is controlled to keep in an open state based on the seventh control signal. In the embodiment of the present application, the enablement of the JTAG interface 110 and the data reading path can be achieved by the fourth control signal, the fifth control signal, the sixth control signal and the seventh control signal. Meanwhile, according to different use stages of the processor 100, the JTAG debugging permission is reserved, and after the reserved JTAG debugging is performed, the JTAG debugging permission is disabled.

[0066] Exemplarily, the second digital control circuit 500B runs the otpc_jtag_disable program field. The second digital control circuit 500B is specifically configured to: when the processor 100 performs JTAG debugging based on the JTAG interface 110 for the first time, maintain the value of the otpc_jtag_disable program field as a third value to output a fourth control signal and a fifth control signal. After the processor 100 performs JTAG debugging based on the JTAG interface 110 for the first time, set the value of the otpc_jtag_disable program field to a fourth value to output a sixth control signal and a seventh control signal. In the embodiment of the present application, otpc_jtag_disable is a program field for controlling whether the JTAG function in the one-time programmable (OTP) area is disabled. When the otpc_jtag_disable field is set to a certain value, it means that the JTAG function is disabled, that is, the chip cannot be tested and debugged through the JTAG interface. In this way, the security of the chip can be improved to prevent unauthorized access and attacks. The embodiment of the present application can set the otpc_jtag_disable program field to different values at different stages. For example, as shown in Figure 6 , when the processor 100 is initially shipped, the otpc_jtag_disable program field in the second digital control circuit 500B has a third value, at this time, the second digital control circuit 500B can output a fourth control signal and a fifth control signal to control the JTAG interface 110 to remain in an open state, and control the second data interface 210 to remain in a closed state. After the first JTAG debugging after shipment, as shown in Figure 2 , the second digital control circuit 500B modifies the value of the otpc_jtag_disable program field based on the one-time programming function to a fourth value, and the value of the otpc_jtag_disable program field after one-time programming cannot be changed. In the subsequent running stage of the processor 100, the second digital control circuit 500B outputs a sixth control signal and a seventh control signal to control the JTAG interface 110 to remain in a closed state, and control the second data interface 210 to remain in an open state. In the subsequent stage, the processor 100 can normally access and read the data in the read-only memory 200, but the JTAG interface 110 is completely disabled.

[0067] Based on the chip system with the structure shown in Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 , a debugging method including the following step S100 can be performed:

[0068] S100, enabling mutual exclusion between the JTAG interface 110 of the control processor 100 and the data read path.

[0069] Exemplarily, the processor 100 performs JTAG debugging based on the JTAG interface 110 when the data read path between the first data interface 120 and the second data interface 210 is in the closed state. The processor 100 keeps the JTAG interface 110 in the closed state when the data read path is in the open state.

[0070] In some possible implementation manners, when the important data accessed based on the JTAG interface 110 needs to be prevented from being a firmware program, as shown in FIG. 1, the debugging mode can be a first debugging method including steps S110A-S140A. Figure 2

[0071] S110A, the processor 100 keeps the JTAG interface 110 in the closed state when the data read path is in the open state.

[0072] In the embodiment of the present application, in the processor 100 startup stage, it is necessary to ensure that the data read path is in the open state, so that the processor 100 can normally obtain the relevant firmware program from the read-only memory 200 after power-on, to complete the parameter configuration and the like in the startup.

[0073] Exemplarily, as shown in FIG. 1 and FIG. 2, the read-only memory 200 outputs the first control signal with the first value to the JTAG interface 110 when the data read path is in the open state, and the first control signal with the first value is used to control the JTAG interface 110 to keep in the closed state. In the embodiment of the present application, the first control signal with the first value output by the read-only memory 200 can be used to ensure that the JTAG interface 110 is kept in the closed state when the data read path is in the open state. Specifically, as shown in FIG. 2, the read-only memory 200 can output the first control signal with the same value to the second data interface 210 and the inverter 230 based on the enable register 220 in the read-only memory 200, output the first control signal after the inversion processing to the JTAG interface 110 through the inverter 230, and realize the enabling mutual exclusion between the second data interface 210 and the JTAG interface 110. Figure 3 Figure 3 Figure 2

[0074] ​​​​Exemplarily, the first control signal can include multiple value bits. If the first control signal has only one value bit, the first control signal has only two choices of 0 and 1. The value 1 and the value 0 are replaced by different value voltages, in this case, an unauthorized user can easily design a voltage signal to simulate the first control signal, and achieve the cracking of the enable mutual exclusive design scheme. However, in the embodiment of the present application, the first voltage signal with multiple value bits has more value choices, and the first control signal is more difficult to be simulated. In one example, the first value can be 5, expressed in binary as 0101, and when the first control signal has 4 value bits, the second value can be 1010 (i.e. 10 in decimal). In one example, the first value can be 10, expressed in binary as 1010, and when the first control signal has 4 value bits, the second value can be 0101 (i.e. 5 in decimal).

[0075] S120A, the processor 100 reads the firmware program from the read-only memory 200 based on the data reading path.

[0076] S130A, the processor 100 runs the firmware program.

[0077] S140A, the processor 100 outputs the first indication signal to the read-only memory 200 before the firmware program is run.

[0078] In the embodiment of the present application, when the firmware program is about to be run (for example, when the firmware program runs to the last few lines or the last line of code), the processor 100 outputs the first indication signal to the read-only memory 200, and the first indication signal is used to instruct the read-only memory 200 to control the data reading path to remain in the closed state.

[0079] After the processor 100 jumps out of the running of the firmware program, the read-only memory 200 controls the second data interface 210 to be closed, so as to control the data reading path to remain in the closed state. The processor 100 can keep the JTAG interface 110 open to normally perform subsequent JTAG debugging.

[0080] Exemplarily, as shown in Figure 3 and Figure 8 When the data reading path is in the closed state, the read-only memory 200 outputs the first control signal with the second value to the JTAG interface 110, and the first control signal with the second value is used to control the JTAG interface 110 to remain in the open state. For the technical principles and beneficial effects of the read-only memory 200 outputting the first control signal with the second value, reference can be made to the related description of the first control signal with the first value, which will not be described here.

[0081] In some possible implementation, in the use stage after the processor 100 is shipped, the enablement mutual exclusion between the JTAG interface 110 and the data reading path can be implemented based on the working state of the JTAG interface 110. At this time, as shown in Figure 4 illustrated, the debugging mode can be a second debugging method including steps S110B-S120B:

[0082] S110B, in response to the processor 100 starting JTAG debugging based on the JTAG interface 110, outputting a second control signal to the second data interface 210 of the read-only memory 200.

[0083] Exemplarily, as shown in Figure 8 illustrated, the first digital control circuit 500A detects the working state of the JTAG interface 110. When it is detected that the JTAG interface 110 starts JTAG debugging work, a second control signal is outputted to the second data interface 210, and the second control signal is used to instruct the read-only memory 200 to control the data reading path to keep in the closed state. The read-only memory 200 controls the second data interface 210 to be in the closed state according to the second control signal, so as to close the data reading path.

[0084] In some examples, as shown in Figure 8 illustrated, the second debugging method further includes the following operation of S120B:

[0085] S120B, outputting a third control signal to the second data interface 210 when the processor 100 does not perform JTAG debugging based on the JTAG interface 110. In the embodiment of the present application, when the first digital control circuit 500A detects that the JTAG interface 110 does not perform JTAG debugging, a third control signal can be outputted to the second data interface 210, and the third control signal is used to instruct the read-only memory 200 to control the data reading path to keep in the open state. The read-only memory 200 controls the second data interface 210 to keep the data reading path in the open state according to the third control signal, so as to keep the data reading path in the open state.

[0086] In some possible implementation, in steps S110B and S120B, the detection and determination of the working state of the JTAG interface 110 can be implemented based on the level state of the JTAG interface 110. Exemplarily, the JTAG interface 110 includes a TMS line, and whether the processor 100 performs JTAG debugging based on the JTAG interface 110 is determined according to the level state of the TMS line. For related technical principles and beneficial effects of determining whether the JTAG interface 110 performs JTAG debugging according to the level state of the TMS line, reference can be made to the related description of the above embodiment, which will not be repeated here.

[0087] Figure 8In the embodiment shown, the processor 100 is first in the JTAG debugging state and then in the non-JTAG debugging state. Although not shown, in actual applications, the processor 100 can first be in the non-JTAG debugging state and then in the JTAG debugging state. Therefore, there is no sequential limitation between the step S110B and the step S120B. The above Figure 9 The embodiment shown is only one possible example.

[0088] In some possible embodiments, one-time JTAG debugging permission can be reserved, and after the one-time JTAG debugging permission, the JTAG debugging function is closed. At this time, as shown in Figure 5 The debugging mode can be a third debugging method including the steps S110C-S120C.

[0089] S110C, when the processor 100 is first based on the JTAG interface 110 for JTAG debugging, outputting a fourth control signal to the JTAG interface 110 of the processor 100 and outputting a fifth control signal to the second data interface 210 of the read-only memory 200.

[0090] Exemplarily, as shown in Figure 6 and Figure 5 When the processor 100 is first debugged after being manufactured, the value of the otpljtag disable program field in the second digital control circuit 500B is a third value. In the third value otpljtag disable program field, the second digital control circuit 500B outputs the fourth control signal to the JTAG interface 110 and outputs the fifth control signal to the second data interface 210. The fourth control signal is used to control the JTAG interface 110 to remain in the open state, and the fifth control signal is used to instruct the read-only memory 200 to control the data reading path to remain in the closed state. At this time, the processor 100 can be based on the JTAG interface 110 for JTAG debugging, but the function of accessing the read-only memory 200 is disabled.

[0091] S120C, after the processor 100 is first based on the JTAG interface 110 for JTAG debugging, outputting a sixth control signal to the JTAG interface 110 of the processor 100 and outputting a seventh control signal to the second data interface 210 of the read-only memory 200.

[0092] Exemplarily, as shown in Figure 6 and Figure 2As shown, after the first JTAG debugging, the second digital control circuit 500B modifies the value of the otpc_jtag_disable program field to a fourth value based on the one-time programming function, and the value of the otpc_jtag_disable program field cannot be changed after the one-time programming. In the subsequent running stage of the processor 100, the second digital control circuit 500B outputs a sixth control signal and a seventh control signal, the sixth control signal is used to control the JTAG interface 110 to remain in the closed state, and the seventh control signal is used to instruct the read-only memory 200 to control the data reading path to remain in the open state. The JTAG interface 110 is controlled to remain in the closed state, and the second data interface 210 is controlled to remain in the open state. In the subsequent stage, the processor 100 can normally access the data in the read-only memory 200, but the JTAG interface 110 is completely disabled.

[0093] In the embodiments of the present application, theoretically, the application of the first debugging method, the second debugging method and the third debugging method does not conflict with each other, so one or more of the above-mentioned first debugging method, second debugging method and third debugging method can be applied in the chip system 1000.

[0094] The embodiments of the present application also provide an electronic device, which includes a circuit board and the chip system 1000 as described in the above Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 embodiments. The chip system 1000 is arranged on the circuit board.

[0095] Exemplarily, the electronic device can be a mobile phone, a smart watch, a VR glasses, an AR glasses, a communication device, a tablet computer and the like, which includes a processor with a JTAG interface.

[0096] The embodiments of the present application also provide a computer readable storage medium, when the computer readable storage medium is running on a chip system, the chip system executes the debugging method as described in the above embodiments (for example, the debugging method as described in the above Figure 8 、 Figure 9 and ​ embodiments).

[0097] The processor involved in the embodiments of the present application can be a chip. For example, it can be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD) or other integrated chip.

[0098] It should be understood that the size of the sequence number of each process described above does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0099] Those of ordinary skill in the art can realize that the modules and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0100] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working process of the system, device and module described above can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0101] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the modules is only a logical function division, and actual implementation can have another division manner, for example, a plurality of modules or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed each other can be through some interface, indirect coupling or communication connection between devices or modules, which can be electrical, mechanical or other forms.

[0102] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, i.e., may be located in one device or distributed over multiple devices. Some or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment.

[0103] In addition, the functional modules in each embodiment of the present application can be integrated in one device, or each module can be physically present alone, or two or more modules can be integrated in one device.

[0104] In the above embodiments, all or part can be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium that can be accessed by a computer or data storage device including one or more servers, data centers, etc. integrated with one or more media. The available media can be magnetic media (such as floppy disk, hard disk, magnetic tape), optical media (such as DVD), or semiconductor media (such as solid state disk (Solid State Disk, SSD)) and the like.

[0105] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip system, characterized by The chip system comprises a processor and a read-only memory; the processor comprises a JTAG interface and a first data interface; the read-only memory comprises a second data interface; wherein: The processor is configured to: when a data reading path between the first data interface and the second data interface is in a closed state, perform JTAG debugging based on the JTAG interface; and when the data reading path is in an open state, keep the JTAG interface in a closed state.

2. The chip system according to claim 1, characterized by Before the JTAG debugging based on the JTAG interface, the processor is further configured to: read a firmware program from the read-only memory based on the data reading path; and run the firmware program; before the firmware program is run completely, output a first indication signal to the read-only memory, the first indication signal being used to instruct the read-only memory to control the data reading path to keep in a closed state.

3. The chip system according to claim 1 or 2, characterized by The read-only memory is configured to: when the data reading path is in an open state, output a first control signal of a first value to the JTAG interface, the first control signal of the first value being used to control the JTAG interface to keep in a closed state; and when the data reading path is in a closed state, output a first control signal of a second value to the JTAG interface, the first control signal of the second value being used to control the JTAG interface to keep in an open state.

4. The chip system according to claim 3, characterized by The read-only memory comprises an enable register and an inverter; an output end of the enable register is connected with an input end of the inverter and an enable end of the second data interface respectively; and an output end of the inverter is used to output the first control signal.

5. The chip system according to claim 3 or 4, characterized in that The first control signal comprises a plurality of value bits.

6. The chip system according to claim 5, characterized by The second value is 5 or 10.

7. The chip system according to claim 1, characterized by The chip system further comprises a first digital control circuit; the first digital control circuit is connected with the JTAG interface and the second data interface respectively; wherein the first digital control circuit is configured to: in response to the processor starting to perform the JTAG debugging based on the JTAG interface, output a second control signal to the second data interface, the second control signal being used to instruct the read-only memory to control the data reading path to keep in a closed state.

8. The chip system according to claim 7, characterized by The first digital control circuit is further configured to: when the processor does not perform the JTAG debugging based on the JTAG interface, output a third control signal to the second data interface, the third control signal being used to instruct the read-only memory to control the data reading path to keep in an open state.

9. The chip system according to claim 7 or 8, characterized in that The JTAG interface comprises a TMS line; the first digital control circuit is further configured to: determine whether the processor is performing the JTAG debugging based on the JTAG interface according to a level state of the TMS line.

10. The chip system according to claim 1, characterized by The chip system further comprises a second digital control circuit; the second digital control circuit is configured to: outputting a fourth control signal to the JTAG interface and a fifth control signal to the second data interface when the processor performs JTAG debugging based on the JTAG interface for the first time, the fourth control signal being used to control the JTAG interface to keep in an open state, and the fifth control signal being used to instruct the read-only memory to control the data reading path to keep in a closed state; outputting a sixth control signal to the JTAG interface and a seventh control signal to the second data interface after the processor performs JTAG debugging based on the JTAG interface for the first time, the sixth control signal being used to control the JTAG interface to keep in a closed state, and the seventh control signal being used to instruct the read-only memory to control the data reading path to keep in an open state.

11. The chip system according to claim 10, characterized by The second digital control circuit runs an otpc_jtag_disable program field; and the second digital control circuit is specifically used for: keeping a third value of the otpc_jtag_disable program field to output the fourth control signal and the fifth control signal when the processor performs JTAG debugging based on the JTAG interface for the first time; setting a fourth value of the otpc_jtag_disable program field to output the sixth control signal and the seventh control signal after the processor performs JTAG debugging based on the JTAG interface for the first time.

12. The chip system according to any one of claims 1-11, wherein the processor is further configured to disable the right to perform the JTAG debugging when the JTAG interface is in the closed state, and enable the right to perform the JTAG debugging when the JTAG interface is in the open state; and the read-only memory is further configured to disable the data access right of the second data interface when the data reading path is in the closed state, and enable the data access right of the second data interface when the data reading path is in the open state.

13. A debugging method characterized by, The method is applied to a chip system, the chip system comprising a processor and a read-only memory, the processor comprising a JTAG interface and a first data interface, and the read-only memory comprising a second data interface; the method comprising: the processor performing JTAG debugging based on the JTAG interface when a data reading path between the first data interface and the second data interface is in a closed state, and keeping the JTAG interface in a closed state when the data reading path is in an open state.

14. The commissioning method of claim 13, wherein, Before the JTAG debugging based on the JTAG interface, the method further comprises: the processor reading a firmware program from the read-only memory based on the data reading path, running the firmware program, and outputting a first instruction signal to the read-only memory before the firmware program is run completely, the first instruction signal being used to instruct the read-only memory to control the data reading path to keep in the closed state.

15. The commissioning method of claim 13 or 14, wherein, The method further comprises: The read-only memory outputs a first control signal with a first value to the JTAG interface when the data read path is in an open state, and the first control signal with the first value is used to control the JTAG interface to remain in a closed state. The read-only memory outputs a first control signal with a second value to the JTAG interface when the data read path is in a closed state, and the first control signal with the second value is used to control the JTAG interface to remain in an open state.

16. The commissioning method of claim 15, wherein, The first control signal includes multiple value bits.

17. The commissioning method of claim 16, wherein, The second value is 5 or 10.

18. The commissioning method of claim 13, wherein, The method further includes: In response to the processor starting the JTAG debugging based on the JTAG interface, outputting a second control signal to the second data interface, and the second control signal is used to instruct the read-only memory to control the data read path to remain in a closed state.

19. The commissioning method of claim 18, wherein, The method further includes: When the processor is not performing the JTAG debugging based on the JTAG interface, outputting a third control signal to the second data interface, and the third control signal is used to instruct the read-only memory to control the data read path to remain in an open state.

20. The commissioning method of claim 18 or 19, wherein, The JTAG interface includes a TMS line; the method further includes: Determining whether the processor is performing the JTAG debugging based on the JTAG interface according to the level state of the TMS line.

21. The commissioning method of claim 13, wherein, The method further includes: When the processor first performs the JTAG debugging based on the JTAG interface, outputting a fourth control signal to the JTAG interface and a fifth control signal to the second data interface, the fourth control signal is used to control the JTAG interface to remain in an open state, and the fifth control signal is used to instruct the read-only memory to control the data read path to remain in a closed state; after the processor first performs the JTAG debugging based on the JTAG interface, outputting a sixth control signal to the JTAG interface and a seventh control signal to the second data interface, the sixth control signal is used to control the JTAG interface to remain in a closed state, and the seventh control signal is used to instruct the read-only memory to control the data read path to remain in an open state.

22. The commissioning method of claim 21, wherein, The method specifically includes: When the processor first performs the JTAG debugging based on the JTAG interface, maintaining the value of the otpc_jtag_disable program field as a third value to output the fourth control signal and the fifth control signal; After the processor first performs the JTAG debugging based on the JTAG interface, set the value of the otpc_jtag_disable program field to a fourth value to output the sixth control signal and the seventh control signal.

23. The commissioning method of any of claims 13-22, wherein, The method specifically includes: When the JTAG interface is in a closed state, disable the permission to perform the JTAG debugging; when the JTAG interface is in an open state, enable the permission to perform the JTAG debugging; disable data access to the second data interface when the data read path is in the closed state; and enable data access to the second data interface when the data read path is in the open state.

24. An electronic device, comprising: A chip system as claimed in any of claims 1 to 12, and a circuit board, the chip system being arranged on the circuit board.

25. A computer readable storage medium, characterized in that, A computer readable storage medium having stored thereon instructions which, when executed by a chip system, cause the chip system to perform a debugging method as claimed in any of claims 13 to 23.

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