Model architecture generation method and device, electronic equipment and storage medium

Abstract

The invention provides a model architecture generation method and device, electronic equipment and a storage medium, and the method comprises the steps: determining model architecture information of a first processing model for a to-be-processed task from a target search space according to a task type of the to-be-processed task and a model limiting condition; according to the model architecture information and the model score of the first processing model, performing N times of optimization strategy generation and model architecture adjustment through a network analysis model, and updating a model experience library to obtain a model experience library after N times of updating; performing P rounds of model screening and model architecture generation through a network analysis model according to the model experience library updated for N times, and updating the model experience library to obtain a model experience library updated for P rounds; and training the target processing model with the highest model score in the model experience library after P rounds of updating to obtain a trained target processing model. According to the embodiment of the invention, the accuracy and generalization ability of model architecture search can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, and particularly relates to a model architecture generation method and device, electronic equipment, computer readable storage medium and computer program product. BACKGROUND

[0002] Neural Architecture Search (NAS) is a method of automatically designing neural network architecture, aiming to improve the model performance of neural networks and reduce the need for manual design. Traditional NAS methods usually rely on reinforcement learning or evolutionary algorithms to search for the optimal architecture, but these methods are computationally expensive and have low search efficiency.

[0003] In addition, One-Shot NAS reduces the search cost by constructing a super network (supernet) to share weights, so that multiple architectures can be evaluated in one training. However, these methods still face problems such as complex search space and easy to fall into local optimum. SUMMARY

[0004] The present disclosure provides a model architecture generation method and device, electronic equipment, computer readable storage medium and computer program product.

[0005] In a first aspect, the present disclosure provides a model architecture generation method, which comprises: determining model architecture information of a first processing model for a to-be-processed task from a target search space according to a task type of the to-be-processed task and a model restriction condition, wherein the model architecture information comprises an operation type of a network layer in the model, a feature fusion rule and a connection mode between network layers; generating N times of optimization strategies and adjusting the model architecture by a preset network analysis model according to the model architecture information and a model score of the first processing model, and updating a model experience library to obtain N times of updated model experience libraries, wherein the N times of updated model experience libraries comprise model architecture information and model scores of M second processing models, M and N are integers greater than 1 and M < N; performing P rounds of model screening and model architecture generation by the network analysis model according to the N times of updated model experience libraries, and updating the model experience library to obtain P rounds of updated model experience libraries, P is an integer greater than 1; training a target processing model with the highest model score in the P rounds of updated model experience libraries to obtain a trained target processing model, and the target processing model is used to execute the to-be-processed task.

[0006] In a second aspect, the present disclosure provides a model architecture generation apparatus, comprising: a model searching module configured to determine model architecture information of a first processing model for a to-be-processed task from a target search space according to a task type of the to-be-processed task and a model restriction condition, wherein the model architecture information comprises an operation type of a network layer in the model, a feature fusion rule, and a connection manner between network layers; a feedback optimization module configured to perform N times of optimization strategy generation and model architecture adjustment through a preset network analysis model according to the model architecture information of the first processing model and a model score, and update a model experience library to obtain N times of updated model experience library, wherein the N times of updated model experience library comprises model architecture information and model scores of M second processing models, M and N are integers greater than 1 and M < N; an architecture generation module configured to perform P rounds of model screening and model architecture generation through the network analysis model according to the N times of updated model experience library, and update the model experience library to obtain P rounds of updated model experience library, P is an integer greater than 1; and a model training module configured to train a target processing model with the highest model score in the P rounds of updated model experience library to obtain a trained target processing model, wherein the target processing model is used to execute the to-be-processed task.

[0007] In a third aspect, the present disclosure provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the model architecture generation method described above.

[0008] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the model architecture generation method described above.

[0009] In a fifth aspect, the present disclosure provides a computer program product comprising computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the model architecture generation method described above.

[0010] The embodiments provided by the present disclosure can determine the model architecture of the initial first model from the target search space, generate optimization strategies multiple times through the network analysis model and adjust the model architecture, thereby rapidly iteratively optimizing the architecture and forming a model experience library, perform multiple rounds of model screening on the model experience library and generate a new model architecture through the network analysis model to extract knowledge from the historical high-performance architecture, thereby reducing the computational overhead of repeated trial and error, accelerating the search process and improving the search efficiency, and then select the optimal processing model from the model experience library after multiple rounds of updates to perform training, so as to execute the to-be-processed task and improve the task processing effect. According to the embodiments of the present disclosure, the computational overhead can be reduced, the dependence on large-scale computing resources can be reduced, and the accuracy and generalization ability of model architecture search can be improved.

[0011] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, which together with the embodiments of the present disclosure serve to explain the present disclosure, and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0013] Figure 1 A flowchart of a model architecture generation method provided by an embodiment of the present disclosure.

[0014] Figure 2 A schematic diagram of a processing process of a model architecture generation method provided by an embodiment of the present disclosure.

[0015] Figure 3 A block diagram of a model architecture generation apparatus provided by an embodiment of the present disclosure.

[0016] Figure 4 A block diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] In order for those skilled in the art to better understand the technical solutions of the present disclosure, exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, which include various details of the embodiments of the present disclosure to help understanding, and should be considered only as exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, in order to be clear and concise, the description in the following description omits the description of well-known functions and structures.

[0018] Embodiments of the present disclosure and respective features in embodiments can be combined, if not in conflict. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0019] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. "Coupled" or "connected" or similar terms are not restricted to physical or mechanical connections or associations, but can also include electrical connections, whether direct or indirect.

[0020] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0021] As mentioned before, traditional NAS methods are inefficient or ineffective. In recent years, large language models (LLMs) have been introduced into the field of NAS to enhance the automation of architecture design. For example, GPT-4 is used to generate convolutional neural network (CNN) and graph neural network (GNN) architectures, and attempts are made to use LLM as a performance predictor to accelerate the NAS process. Although LLMs have shown potential in NAS, the methods in the related art still mainly rely on traditional search strategies and do not fully exploit the knowledge extraction and induction capabilities of LLMs. The methods in the related art mainly include:

[0022] 1. Directly generating architecture based on LLM: directly generating neural network architecture using LLM and evaluating its performance through training. This method has certain potential in exploring new architectures, but due to the lack of explicit optimization strategy for LLM-generated architectures, the performance is unstable and the search direction may not be accurate, resulting in unstable quality of generated architectures, making it difficult to ensure that a high-performance neural network is always obtained. Moreover, the architecture is usually generated at one time, without fully utilizing the high-quality architecture experience accumulated in the past search process, lacking an effective knowledge accumulation mechanism, resulting in low efficiency of the search process.

[0023] 2. Method of using LLM for performance prediction: using LLM as a performance predictor to predict the performance of an architecture after inputting it, in order to reduce dependence on real training. However, this method relies on a large amount of historical data for training, but due to the complexity of the search space, the prediction accuracy of LLM is limited, which may lead to incorrect search direction, and the accuracy of the prediction is difficult to guarantee. Moreover, a large amount of labeled data is required during training, and when the search space changes, its prediction ability often decreases, affecting the adaptability of NAS, making it difficult to be applied to new search tasks, and the generalization ability is limited.

[0024] 3. Evolution or reinforcement learning combined with LLM: combining evolutionary algorithms or reinforcement learning to optimize architecture with LLM as an auxiliary module. Although this method improves the explainability of the search, evolutionary algorithms and reinforcement learning usually require a large number of architecture evaluations, resulting in large computational overhead and high computational cost, making it difficult to be applied to scenarios with limited computing resources. Moreover, the randomness of the search direction of evolutionary algorithms and reinforcement learning is strong, and it is easy to fall into local optimum during the search process, lacking a global optimization strategy, which limits the search efficiency, while lacking an efficient long-term knowledge accumulation and reuse mechanism.

[0025] According to the model architecture generation method of the embodiments of the present disclosure, the model architecture of the initial first model can be determined from the target search space; the optimization strategy is generated multiple times through the network analysis model and the model architecture is adjusted, so as to quickly iterate and optimize the architecture, forming a model experience library; the model experience library is subjected to multiple rounds of model screening and a new model architecture is generated through the network analysis model, so as to extract knowledge from historical high-performance architectures, thereby reducing the computational overhead of repeated trial and error, accelerating the search process, and improving the search efficiency; and then, the optimal processing model is selected from the model experience library after multiple rounds of updates for training, so as to execute the to-be-processed task and improve the task processing effect. According to the embodiments of the present disclosure, the computational overhead can be reduced, the dependence on large-scale computing resources can be reduced, and the precision and generalization ability of the model architecture search can be improved.

[0026] The model architecture generation method according to the embodiments of the present disclosure can be executed by an electronic device such as a terminal device or a server, and the terminal device can be a vehicle-mounted device, a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. The method can be implemented by a processor invoking computer readable program instructions stored in a memory. Alternatively, the method can be executed by a server.

[0027] Figure 1 A flowchart of a model architecture generation method according to an embodiment of the present disclosure is provided. Referring to FIG. 1, Figure 1 The method includes:

[0028] In step S11, model architecture information of a first processing model for a to-be-processed task is determined from a target search space according to a task type of the to-be-processed task and a model restriction condition, wherein the model architecture information includes an operation type of a network layer in the model, a feature fusion rule, and a connection manner between network layers.

[0029] In step S12, N times of optimization strategy generation and model architecture adjustment are performed by a preset network analysis model according to the model architecture information and the model score of the first processing model, and a model experience library is updated to obtain N times of updated model experience library, wherein the N times of updated model experience library includes model architecture information and model scores of M second processing models, and M and N are integers greater than 1 and M < N.

[0030] In step S13, P rounds of model screening and model architecture generation are performed by the network analysis model according to the N times of updated model experience library, and the model experience library is updated to obtain P rounds of updated model experience library, and P is an integer greater than 1.

[0031] In step S14, a target processing model with the highest model score in the P rounds of updated model experience library is trained to obtain a trained target processing model, and the target processing model is used to execute the to-be-processed task.

[0032] For example, a target search space can be pre-set, such as a search space of differentiable architecture search (DARTS). In this case, DARTS focuses on the search of a "cell" (or network layer), rather than directly searching a complete network which is stacked by multiple cells of the same structure, and thus the core of the search space is the connection mode and operation selection within the cell. It should be understood that a person skilled in the art can set the target search space according to actual conditions, and the disclosure does not limit the specific type of the target search space.

[0033] In some possible implementation manners, the task type of the to-be-processed task and the model limitation condition can also be pre-determined. The task type includes any one of an image processing task, a speech processing task, a text processing task and a multi-modal processing task, and the image processing task can include any one of an image classification task, an object detection task and a semantic segmentation task. The disclosure does not limit the specific type of the to-be-processed task.

[0034] In some possible implementation manners, the model limitation condition includes at least one of a network layer number, an operation number, an operation type and a network parameter number of the processing model. The model limitation condition can be a specific number and type, or a number range and operation type range. For example, the model limitation condition can be set as the network layer number is 3, the first network layer includes two 3x3 separable convolution operations (sep_conv_3x3), the second network layer includes five 3x3 regular convolution operations, and the third network layer includes two 3x3 max-pooling operations (max_pool_3x3). For another example, the model limitation condition can be set as the network layer number range is 5-10 layers, the total operation number range is 50-80, and the operation type includes convolution, pooling, full connection and the like. It should be understood that a person skilled in the art can set the model limitation condition according to actual conditions, and the disclosure does not limit the specific setting of the model limitation condition.

[0035] In some possible implementation manners, according to the task type of the to-be-processed task and the model limitation condition, the model architecture information of the initial first processing model can be determined from the target search space in step S11. The model architecture information includes an operation type of a network layer in the model, a feature fusion rule and a connection mode between network layers.

[0036] In an example, the model architecture information can be represented as Genotype (normal=[('sep_conv_3x3', 1), ('skip_connect', 0),...], normal_concat=[2, 3, 4, 5], reduce=[('max_pool_3x3',0),...], reduce_concat=[2, 3, 4, 5]).

[0037] wherein, Genotype() represents a genotype data structure; normal represents a normal layer (or normal cell), the normal layer includes 1 separable convolution operation (sep_conv_3x3) corresponding to node 1 and 1 skip connection (skip_connect) corresponding to node 0, and node 0, 1 is the node of the input data of the normal layer; normal_concat is used to define the output feature fusion rule of the normal layer, and normal_concat=[2, 3, 4, 5] represents that the corresponding features of intermediate nodes 2, 3, 4, and 5 are fused. reduce represents a down-sampling layer (or down-sampling cell), the down-sampling layer includes 1 3x3 max-pooling operation (max_pool_3x3) corresponding to node 0, and node 0 is the node of the input data of the down-sampling layer; reduce_concat is used to define the output feature fusion rule of the down-sampling layer, and reduce_concat=[2, 3, 4, 5] represents that the corresponding features of intermediate nodes 2, 3, 4, and 5 of the down-sampling layer are fused.

[0038] It should be understood that the above is only an example of model architecture information, and a person skilled in the art can set the specific representation form of the model architecture information according to the actual situation, and the present disclosure does not limit this.

[0039] In some possible implementations, after obtaining the first processing model, the performance of the first processing model can be verified on a verification set of the to-be-processed task to obtain a model score of the first processing model. For example, in the case where the to-be-processed task is an image classification task, the verification set is CIFAR-10 (a commonly used image classification benchmark data set).

[0040] wherein, the samples in the verification set can be input into the first processing model to obtain the processing result, and the processing result is compared with the annotation result of the sample to obtain the accuracy rate of the processing result of the first processing model on the verification set as the model score of the first processing model. For example, the accuracy rate of the first processing model corresponding to the model architecture information in the above example on the verification set CIFAR-10 is 83.52%, that is, the model score is 83.52% (or 83.52).

[0041] In some possible implementation manners, in step S12, according to the model architecture information and the model score of the first processing model, N times of optimization strategy generation and model architecture adjustment can be performed by using a preset network analysis model. The network analysis model can be a large language model (LLM).

[0042] In some possible implementation manners, a first prompt word template corresponding to the task type can be preset, and in the first processing, the model architecture information and the model score of the first processing model are added to the first prompt word template to obtain a first prompt word (Prompt). For example, the first prompt word is expressed as: the model architecture of the processing model is "A", the verification accuracy of the architecture on the "CIFAR-10 data set" is 83.52%, the historical optimization strategy is "none", please analyze the model architecture and propose an optimization strategy, and the optimization strategy includes an adjustment manner of the model architecture information and an optimization reason. The first prompt word is input into the network analysis model, and an optimization strategy can be output, for example, "this adjustment manner: reduce one skip_connect operation and add one sep_conv_3x3 operation; optimization reason: too many skip_connect operations can cause network collapse, and adding a sep_conv_3x3 operation can achieve better processing effect"; according to the optimization strategy, the model architecture information of the first processing model is adjusted to obtain the model architecture information of the first adjusted processing model; and then the model architecture information of the first adjusted processing model is added to the initial model experience library to obtain the first updated model experience library.

[0043] In this way, N times of optimization strategy generation and model architecture adjustment can be performed by using the above processing manner. For the nth processing (1 < n ≤ N), if n ≤ M, the nth adjusted processing model is directly added to the current model experience library; if n > M, the M processing models with the highest model scores are retained according to the model scores. In this way, after N times of processing, when a set iteration number or a performance standard is reached, N times of updated model experience libraries are obtained, which include the model architecture information and the model scores of the M second processing models, and M and N are integers greater than 1 and M < N.

[0044] The NAS (such as the differentiable architecture search DARTS) in the related art adopts a symmetric gradient update, is easy to fall into a local optimum, and thus causes poor model architecture search effect. According to the processing manner of the embodiment of the present disclosure, through the chain-of-thought of the LLM, single architecture evaluation is divided into three steps of "bottleneck positioning-strategy generation-local fine tuning", and an asymmetric iteration mechanism is formed, for example, only the third layer convolution kernel is replaced instead of global resampling. In this way, not only the interpretability of iteration can be improved, but also the exploration ability of the LLM can be fully utilized to explore the whole, and the efficiency of model architecture search is greatly improved.

[0045] In some possible implementation manners, in step S13, P rounds of model screening and model architecture generation can be performed on the N times updated model experience library by using the network analysis model, and the model experience library is updated to obtain a P times updated model experience library.

[0046] In some possible implementation manners, in the first round of processing, K third processing models with the highest model scores can be selected from the M second processing models in the N times updated model experience library, K is an integer and 1 < K < M; then, Q fourth processing models can be selected from the K third processing models by using a screening method such as random sampling, non-uniform sampling, or clustering, Q is an integer and 1 < Q < K. For example, K is 16 and Q is 8, and the disclosure does not limit the specific values of K and Q.

[0047] In some possible implementation manners, a second prompt word template corresponding to the task type can be preset, and the model architecture information and the model score of the Q fourth processing models can be added to the second prompt word template to generate a second prompt word of the first round of processing. For example, the second prompt word is expressed as: generate a new optimization architecture according to the following Q model architectures and model scores; the processing models for reference include model architecture “A1” and model score “B1”; model architecture “A2” and model score “B2”; …; model architecture “AQ” and model score “BQ”. Then, the second prompt word is input into the network analysis model to obtain the model architecture information of the processing model generated in the first round; according to the model scores of the M second processing models and the model score of the processing model generated in the first round, the model architecture information of the M processing models with the highest model scores is retained in the model experience library to obtain a first round updated model experience library.

[0048] In this way, P rounds of model screening and model architecture generation can be performed by using the above processing method, and a P times updated model experience library is obtained when a preset iteration number or a performance improvement threshold is reached.

[0049] In some possible implementation manners, in step S14, a target processing model with the highest model score can be selected from the P times updated model experience library, and the target processing model is trained based on a preset training set to obtain a trained target processing model, which is used to execute the to-be-processed task.

[0050] According to the embodiments of the present disclosure, the optimization strategy can be generated multiple times by the network analysis model, and the model architecture can be adjusted, so that the architecture is quickly iteratively optimized to form a model experience library; the model experience library is subjected to multiple rounds of model screening, and a new model architecture is generated by the network analysis model to extract knowledge from historical high-performance architectures, thereby reducing the computational overhead of repeated trial and error, accelerating the search process, and improving the search efficiency. According to the embodiments of the present disclosure, the computational overhead can be reduced, the dependence on large-scale computing resources can be reduced, and the precision and generalization ability of the model architecture search can be improved.

[0051] The model architecture generation method according to the embodiments of the present disclosure will be described below.

[0052] As described above, in step S11, the model architecture information of the first processing model for the to-be-processed task can be determined from the target search space according to the task type of the to-be-processed task and the model restriction condition. The model architecture information includes information such as the operation type of the network layer in the model, the feature fusion rule, and the connection mode between the network layers.

[0053] In some possible implementation manners, after step S11, the model architecture generation method according to the embodiments of the present disclosure further includes: performing performance verification on the first processing model according to a verification set of the to-be-processed task to obtain a model score of the first processing model.

[0054] That is, the corresponding verification set can be determined according to the task type of the to-be-processed task, for example, in the case where the to-be-processed task is an image classification task, the verification set is CIFAR-10 (a commonly used image classification benchmark data set). The samples in the verification set can be input into the first processing model to obtain the processing result, and the processing result is compared with the annotation result of the samples to obtain the accuracy of the processing result of the first processing model on the verification set.

[0055] In some possible implementation manners, the accuracy can be directly used as the model score; or the accuracy can be combined with other model performance indicators to be used as the model score, or the weighted sum of multiple indicators can be used as the model score. The present disclosure does not limit this.

[0056] In step S12, according to the model architecture information and the model score of the first processing model, N times of optimization strategy generation and model architecture adjustment can be performed by a preset network analysis model, and the model experience library is updated. The network analysis model can be a large language model LLM, for example, Qwen2.5-32B (a large language model developed by the Qwen team, with a model parameter amount of 32 billion), and the present disclosure does not limit the specific model type of the network analysis model.

[0057] In some possible implementation manners, the first processing in the N times of optimization strategy generation and model architecture adjustment in step S12 by the preset network analysis model comprises: generating a first prompt word of the first processing model according to model architecture information and model score of the first processing model and a first prompt word template corresponding to the task type; inputting the first prompt word of the first processing model into the network analysis model to obtain an optimization strategy of the first processing model, the optimization strategy comprising an adjustment manner of the model architecture information; and adjusting the model architecture information of the first processing model according to the optimization strategy of the first processing model to obtain model architecture information of a first adjusted processing model; and adding the model architecture information of the first adjusted processing model into an initial model experience library to obtain a first updated model experience library.

[0058] For example, a first prompt word template corresponding to the task type is preset, and in the first processing, the model architecture information and the model score of the first processing model are added to the first prompt word template to obtain a first prompt word (Prompt). For example, the first prompt word is expressed as: the model architecture of the processing model is “A”, the verification accuracy of the architecture on the “CIFAR-10 data set” is 83.52%, the historical optimization strategy is “none”, please analyze the model architecture and propose an optimization strategy, the optimization strategy comprising an adjustment manner of the model architecture information and an optimization reason.

[0059] In some possible implementation manners, the first prompt word is input into the network analysis model, and an optimization strategy can be output, for example, “this adjustment manner: reduce one skip_connect operation and increase one sep_conv_3x3 operation; optimization reason: too many skip_connect operations can cause network collapse, and increasing the sep_conv_3x3 operation has better processing effect”; the first processing model is adjusted according to the optimization strategy to obtain model architecture information of a first adjusted processing model; and then the model architecture information of the first adjusted processing model is added to the initial model experience library to obtain a first updated model experience library.

[0060] The model adjustment manner can be re-searching in a target search space according to the optimization strategy to determine the model architecture information of the first adjusted processing model, or directly modifying the model architecture information of the first processing model according to the optimization strategy to obtain the model architecture information of the first adjusted processing model. The present disclosure does not limit this.

[0061] In this way, the thinking chain capability of the large language model can be fully utilized, an asymmetric iteration mechanism is formed, and the efficiency of model architecture search is improved.

[0062] In some possible implementation manners, the n-th processing in the N times of optimization strategy generation and model architecture adjustment in step S12 by the preset network analysis model comprises: generating a first prompt word for the n-th processing according to model architecture information and a model score of the n-1-th adjusted processing model, an optimization strategy of the n-1-th processing, and a first prompt word template of the task type; n is an integer and 1 < n ≤ N; inputting the first prompt word for the n-th processing into the network analysis model to obtain an optimization strategy of the n-th processing; adjusting the model architecture information of the n-1-th adjusted processing model according to the optimization strategy of the n-th processing to obtain model architecture information of an n-th adjusted processing model; in the case of n ≤ M, adding the model architecture information of the n-th adjusted processing model to the model experience library to obtain an n-th updated model experience library; in the case of n > M, retaining model architecture information of M processing models with the highest model scores in the model experience library according to the model scores of the processing models in the current model experience library and the model score of the n-th adjusted processing model to obtain an n-th updated model experience library.

[0063] For example, for any 1 time after the 1st processing, referred to as the n-th processing, a first prompt word for the n-th processing can be generated according to model architecture information and a model score of the n-1-th adjusted processing model, an optimization strategy of the n-1-th processing, and a first prompt word template of the task type. For example, the model architecture of the processing model is “B”, the verification accuracy of the architecture on the “CIFAR-10 data set” is X, the historical optimization strategy is “change the convolution kernel size of the 3rd layer from 3x3 to 5x5, the optimization reason: increase the receptive field of the convolution operation by increasing the convolution kernel size, which can improve the processing effect”, “add a residual connection between the 5th layer and the 7th layer, the optimization reason: add a residual connection to reduce the loss of image details”, please analyze the model architecture and propose an optimization strategy, which includes the adjustment mode of the model architecture information and the optimization reason.

[0064] In some possible implementation manners, in the first prompt word template, a corresponding association field or coupling index can be set according to the task type of the task to be processed. For example, in the scene of an image detection task, an “anchor box density-recall rate” association field (such as “the recall rate of the current processing model decreases by 5% when the anchor box density = 100”) is added in the first prompt word template; for example, in the scene of a natural language processing task, a “vocabulary size-bafflement degree” coupling index (such as “when the vocabulary size > 50k, it is suggested to increase the LSTM unit gating dimension”) is added in the first prompt word template. It should be understood that a person skilled in the art can set the first prompt word template according to the actual situation, and the disclosure does not limit this.

[0065] In some possible implementations, the constructed first prompt word can include content for guiding the LLM to analyze the architecture bottleneck in real time. For example, when the accuracy of the first processing model on a certain data set is low, the first prompt word can describe the accuracy data, the operation types and connection manners of the current layers of the first processing model, and possible clues related to the bottleneck position, so that the LLM can more accurately analyze the problem. The specific construction manner of the first prompt word is not limited in the present disclosure.

[0066] In some possible implementations, a certain processing window can also be set to utilize the historical information of multiple processing, for example, the processing window is set to 3, and the model architecture information, model score and optimization strategy of the processing model adjusted in the n-1th, n-2th and n-3th times can be included in the first prompt word at the same time. In this way, the historical information can be better utilized, and the effect of the optimization strategy generated by the network analysis model can be further improved.

[0067] In some possible implementations, the first prompt word of the n th processing is input into the network analysis model to obtain the optimization strategy of the n th processing; and the model architecture information of the processing model adjusted in the n-1th time is adjusted according to the optimization strategy of the n th processing to obtain the model architecture information of the processing model adjusted in the n th time. The model adjustment manner is not described herein again.

[0068] In some possible implementations, the maximum number of processing models in the model experience library is M. In the case of n≤M, the model architecture information of the processing model adjusted in the n th time can be directly added to the model experience library. In the case of n>M, the model experience library is full, and the model architecture information of the M processing models with the highest model scores in the current model experience library and the model score of the processing model adjusted in the n th time are retained in the model experience library to obtain the n th updated model experience library. In this way, the model experience library can always retain the optimal model architecture, and the quality of the model architecture in the model experience library can be improved.

[0069] In the case of n=N, the model architecture information of the processing model adjusted in the N th time can be expressed as Genotype(normal=[('dil_conv_5x5', 1), ('avg_pool_3x3', 0),...], normal_concat=[2, 3, 4, 5], reduce=[('avg_pool_3x3', 0),...], reduce_concat=[2, 3, 4, 5]) for example, and the validation set accuracy is improved to 97.71%. Wherein, dil_conv_5x5 represents a 5x5 dilated convolution, and avg_pool_3x3 represents a 3x3 average pooling.

[0070] According to the model scores of the processing models in the current model experience library and the model scores of the Nth adjusted processing models, the model architecture information of the M processing models with the highest model scores is retained in the model experience library, and thus the Nth updated model experience library is obtained.

[0071] This processing method only relies on the historical information of one or several previous processes to generate the optimization strategy, and the previous experience does not affect the generation process of the current optimization strategy. Therefore, the global exploration capability of the LLM can be fully utilized to explore different model architectures, greatly improving the efficiency of model architecture search and supporting the diversity of the subsequent experience library. In each process, the performance feedback of the new processing model can be combined to immediately correct the search direction, ensuring the dynamics and efficiency of the optimization process. By setting conditions such as the number of iterations or the performance improvement threshold, the termination of the iteration process is controlled, and problems such as overfitting caused by overfitting are reduced or even avoided.

[0072] In some possible implementations, after obtaining the Nth updated model experience library, P rounds of model screening and model architecture generation can be performed on the network analysis model in step S13, and the model experience library is updated to obtain a Pth updated model experience library.

[0073] In some possible implementations, the first round of processing in the P rounds of model screening and model architecture generation in step S13 includes: selecting K third processing models with the highest model scores from the M second processing models, K being an integer and 1 < K < M; screening Q fourth processing models from the K third processing models according to a preset screening manner, Q being an integer and 1 < Q < K; generating a second prompt word for the first round of processing according to the model architecture information and the model scores of the Q fourth processing models and the second prompt word template of the task type; inputting the second prompt word for the first round of processing into the network analysis model to obtain model architecture information of a processing model generated in the first round; and retaining model architecture information of M processing models with the highest model scores in the model experience library according to the model scores of the M second processing models and the model scores of the processing model generated in the first round, to obtain a first round of updated model experience library.

[0074] For example, in the first round of processing, K third processing models with the highest model scores can be selected from the M second processing models in the Nth updated model experience library, K being an integer and 1 < K < M; and then Q fourth processing models can be screened from the K third processing models by random sampling, non-uniform sampling, or clustering, Q being an integer and 1 < Q < K. For example, K is 16 and Q is 8, and the disclosure does not limit the specific values of K and Q.

[0075] In some possible implementation manners, the model score not only includes the accuracy of the processing model, but also includes the calculation complexity, the parameter quantity and other performance indicators of the processing model in multiple dimensions. The weights of the respective performance indicators can be respectively set, and the weighted sum of the respective performance indicators is taken as the final model score. In this way, a high-performance model architecture that is more in line with the actual application requirements can be selected.

[0076] In some possible implementation manners, in the scenario of an image classification task, the performance indicators can include the channel-accuracy mode indicators of CIFAR / ImageNet (both are commonly used image classification benchmark data sets); in the scenario of an object detection task, the performance indicators can include the inflation rate-mIoU (intersection over union) correlation indicators of PASCAL VOC / Cityscapes (both are commonly used object detection benchmark data sets); and in the scenario of a text processing task or a natural language processing task, the performance indicators can include the gating mechanism-baffling degree regularity indicators of PTB / WikiText (both are commonly used text processing benchmark data sets).

[0077] In some possible implementation manners, the model experience library can be layered, and the image classification layer corresponds to the image classification task; the object detection layer corresponds to the object detection task; and the NLP layer corresponds to the text processing task. Each layer is indexed by a task ID hash, and when sampling, the model experience library in the same field is preferentially matched, for example, the object detection task only calls the model experience library of the detection layer.

[0078] In some possible implementation manners, after the K third processing models with the highest model scores are obtained, the K third processing models can be filtered according to a preset filtering manner. The filtering manner includes clustering filtering. In this case, the step of filtering Q fourth processing models from the K third processing models includes: clustering the K third processing models to obtain Q model categories; and determining the third processing model with the minimum distance to the clustering center in each model category as the fourth processing model to obtain Q fourth processing models.

[0079] For example, the K third processing models filtered out can be analyzed by using a preset clustering algorithm, for example, a K-means algorithm, to extract common features of the respective processing models in aspects such as operation type distribution, connection mode pattern and channel number change regularity, thereby forming a basis for experience learning. For example, it is found that most high-performance architectures tend to use a certain specific convolution operation combination at a certain specific position, or the channel number presents a certain increasing or decreasing regularity at a certain stage.

[0080] In this way, Q model categories can be obtained after clustering processing; and the third processing model with the smallest distance from the clustering center in each model category is determined as the fourth processing model, thereby obtaining Q fourth processing models.

[0081] In this way, the diversity of the architecture of the selected processing model can be improved, so that the network analysis model obtains more comprehensive information when generating a new model architecture through subsequent network analysis, thereby improving the effect of model generation.

[0082] In some possible implementation manners, the screening manner includes non-uniform sampling, and in this case, the step of screening Q fourth processing models from the K third processing models includes: performing Q times of non-uniform sampling on the K third processing models to obtain Q fourth processing models; and in each time of non-uniform sampling, the probability of sampling the processing model with the highest model score is greater than the probability of sampling a random processing model.

[0083] For example, the probability of sampling the processing model with the highest model score can be set to 80% and the probability of sampling a random processing model can be set to 20% in each time of non-uniform sampling. In this way, the K third processing models are subjected to Q times of non-uniform sampling to obtain Q fourth processing models, so that the sampled processing models are a mixture of optimal processing models and random processing models.

[0084] In this way, the probability of overfitting the optimal solution can be reduced. This processing manner is superior to the screening manner of uniform sampling or directly selecting the optimal processing model, and can adapt to the exploration-exploitation balance of different search stages.

[0085] In some possible implementation manners, after obtaining the Q fourth processing models, the model architecture information and the model scores of the Q fourth processing models can be added to the second prompt word template to generate a second prompt word of the first round of processing. For example, the second prompt word is expressed as: generate a new optimized architecture with reference to the following multiple model architectures and model scores; the processing models for reference include model architecture “A1” and model score “B1”, model architecture “A2” and model score “B2”, …, and model architecture “AQ” and model score “BQ”. Then, the second prompt word is input into the network analysis model to obtain model architecture information of a processing model generated in the first round; and according to the model scores of the M second processing models and the model score of the processing model generated in the first round, the model architecture information of the M processing models with the highest model scores is retained in the model experience library, thereby obtaining an updated model experience library in the first round.

[0086] Through this way of learning from experience feedback, the processing models in the model experience library can be summarized by the LLM, and combined with the understanding of the current search progress and target requirements (such as whether the current search stage focuses more on accuracy improvement or computational efficiency optimization, etc.), a new processing model with higher potential performance can be generated. Based on inheriting the excellent features of the model experience library, the new processing model also has certain innovation to explore new architecture possibilities. In this way, the new processing model is incorporated into the experience library to form a feedback loop, continuously improving the architecture quality; moreover, the new architecture can be labeled to record its generation source and features for subsequent further analysis and optimization, further improving the efficiency and accuracy of network architecture search.

[0087] In some possible implementation manners, the p-th round of processing in the P-round model screening and model architecture generation through the network analysis model in step S13 includes: selecting the K processing models with the highest model scores from the model experience library updated in the (p - 1)-th round; p is an integer and 1 < p ≤ P; screening out Q processing models from the K processing models according to a preset screening method; generating the second prompt word for the p-th round of processing according to the model architecture information and model scores of the Q processing models, and the second prompt word template of the task type; inputting the second prompt word for the p-th round of processing into the network analysis model to obtain the model architecture information of the processing model generated in the p-th round; and retaining the model architecture information of the M processing models with the highest model scores in the model experience library according to the model scores of the processing models in the model experience library updated in the (p - 1)-th round and the model scores of the processing model generated in the p-th round, to obtain the model experience library for the p-th round of processing.

[0088] For example, for any round after the first round of processing, it is called the p-th round of processing, where p is an integer and 1 < p ≤ P. The K processing models with the highest model scores can be selected from the model experience library updated in the (p - 1)-th round; and Q processing models can be screened out from the K processing models according to a preset screening method. The specific processing manner is the same as that in the first round of processing and will not be elaborated here.

[0089] In some possible implementation manners, the model architecture information and model scores of the Q processing models can be added to the second prompt word template to generate the second prompt word for the p-th round of processing. Inputting this second prompt word into the network analysis model can obtain the model architecture information of the processing model generated in the p-th round; furthermore, according to the model scores of the processing models in the model experience library updated in the (p - 1)-th round and the model scores of the processing model generated in the p-th round, the model architecture information of the M processing models with the highest model scores is retained in the model experience library to obtain the model experience library updated in the p-th round.

[0090] In the case of p = P, the model architecture information of the Pth round generated processing model can be expressed as Genotype (normal=[('sep_conv_3x3', 1), ('skip_connect', 0),...], normal_concat=[2, 3, 4, 5], reduce=[('max_pool_3x3', 0),...], reduce_concat=[2, 3, 4, 5]) for example, and the validation set accuracy is 97.79%.

[0091] According to the model scores of the processing models in the current model experience library and the model score of the Pth round generated processing model, the model architecture information of the M processing models with the highest model scores in the model experience library is retained, that is, the Pth round updated model experience library is obtained.

[0092] In this way, the processing models in the LLM summary model experience library can be summarized to generate new processing models with higher potential performance, and the new processing models are included in the experience library to form a feedback loop, continuously improve the architecture quality, and further improve the efficiency and accuracy of network architecture search.

[0093] In some possible implementation ways, in step S14, a target processing model with the highest model score can be selected from the Pth round updated model experience library, and the target processing model is trained based on a preset training set to obtain a trained target processing model for executing a to-be-processed task. In the case of an image classification task, the training set can include CIFAR-10, CIFAR-100, ImageNet, and the like. The training manner in related technologies can be used to train and evaluate the target processing model to obtain the trained target processing model. For example, the final architecture has a test set accuracy of 97.79% on CIFAR-10, a test set accuracy of 84.14% on CIFAR-100, and a test set accuracy of 75.8% on ImageNet.

[0094] Figure 2 A schematic diagram of a processing process of a model architecture generation method provided by an embodiment of the present disclosure is shown in FIG. 1. As shown in FIG. 1, an immediate feedback optimization module 21 is configured to perform N times of optimization strategy generation and model architecture adjustment; an experience learning feedback module 22 is configured to perform P rounds of model screening and model architecture generation; and a model experience library 23 is configured to store model architecture information and model scores of processing models. Figure 2

[0095] As shown in FIG. 2, the immediate feedback optimization module 21 is configured to perform N times of optimization strategy generation and model architecture adjustment; the experience learning feedback module 22 is configured to perform P rounds of model screening and model architecture generation; and the model experience library 23 is configured to store model architecture information and model scores of processing models. Figure 2 ​As shown, in step S11 , a first processing model is determined from the target search space, and the model architecture information and model score of the first processing model are input into the instant feedback optimization module 21 .

[0096] In the example, in step S12, the instant feedback optimization module 21 generates a first prompt word based on the first prompt word template and inputs the network analysis model, outputs the optimization strategy 1, and generates the model architecture information of the processing model adjusted for the first time according to the optimization strategy 1; the model architecture information and model score of the processing model adjusted for the first time are added to the model experience library 23.

[0097] In the example, the instant feedback optimization module 21 generates the first prompt word for the second processing based on the model architecture information and model score of the processing model adjusted for the first time, the optimization strategy of the first processing model and the first prompt word template, and inputs the first prompt word into the network analysis model, and outputs optimization strategy 2; generates the model architecture information of the processing model adjusted for the second time according to the optimization strategy 2; and adds the model architecture information and model score of the processing model adjusted for the second time to the model experience library.

[0098] This process is repeated until the optimization strategy N is reached. The instant feedback optimization module 21 generates optimization strategies and adjusts the model architecture N times to obtain the model experience library after N updates.

[0099] In the example, in step S13, the experience learning feedback module 22 selects K third processing models with the highest model scores, and selects Q fourth processing models from the K third processing models according to a preset screening method; the Q fourth processing models ( Figure 2 The model architecture information and model scores of the processing models 1, 2, ..., Q) in the first round are added to the second prompt word template to summarize and generate the second prompt words of the first round of processing; the second prompt words are input into the network analysis model to obtain the model architecture information of the processing models generated in the first round; based on the model scores of the M second processing models and the model scores of the processing models generated in the first round, the model architecture information of the M processing models with the highest model scores is retained in the model experience library to obtain the model experience library updated in the first round.

[0100] By analogy, the experience learning feedback module 22 performs P rounds of model screening and model architecture generation to obtain a P rounds of updated model experience library.

[0101] In the example, in step S14, the target processing model with the highest model score is selected from the model experience library after P rounds of updates, and the target processing model is trained based on a preset training set to obtain a trained target processing model for executing the task to be processed.

[0102] In this way, the entire model architecture generation process is realized.

[0103] Application examples.

[0104] 1. The to-be-processed task is an object detection task, which is used for realizing pixel-level segmentation of PCB defect (scratch, false soldering), and the false detection rate is required to be less than 1%.

[0105] In the example, the industrial detection special experience (such as “the false soldering area needs 5x5 expansion convolution to enhance the edge feature”) is added in the prompt word template of the experience library; in the N-time optimization strategy generation and model architecture adjustment of step S12, the matching rule of the dilatation rate-receptive field in the first prompt word is adjusted according to the defect type label.

[0106] In the example, through the processing of steps S11-S14 of the embodiment of the present disclosure, a lightweight target processing model is generated by zero-shot inference in the case of no historical defect data, which is a neural network after U-Net variation.

[0107] In the example, the target processing model obtained according to the embodiment of the present disclosure has a very competitive performance in mIoU on the self-built PCB defect dataset, and the false detection rate is less than 8%, which is significantly improved compared with the manually designed model.

[0108] 2. The to-be-processed task is an object detection task, which is used for multi-organ segmentation of medical images. 3D segmentation of liver / kidney / spleen in CT scan images is realized, and the explainability requirement of CFDA Class III medical devices (according to the Chinese “Medical Device Classification Catalogue”, it belongs to the highest risk level of medical devices) needs to be met.

[0109] In the example, the medical image special experience (such as “liver segmentation needs 3x3x3 hollow convolution + jump connection”) is added in the experience library layer and the prompt word template of the experience library; in the N-time optimization strategy generation and model architecture adjustment of step S12, the annotation layer meeting the DICOM standard (medical image interoperability: DICOM (Digital Imaging and Communications in Medicine) is an internationally recognized medical image standard) is added in the model architecture information generated by the LLM to meet the review requirements; in the P-round model screening and model architecture generation of step S13, the liver segmentation experience is reused and migrated to the kidney segmentation task to realize cross-organ knowledge migration. Through the processing of steps S11-S14 of the embodiment of the present disclosure, the trained target processing model is obtained.

[0110] In the example, the target processing model has outstanding performance in Dice (a core index for measuring segmentation accuracy) on the LITS dataset (a globally authoritative liver tumor segmentation dataset), and the architecture explainability passes the CFDA pre-examination, which has more clinical application value than the traditional method.

[0111] According to the model architecture generation method of the embodiment of the present disclosure, the model architecture of the initial first model can be determined from the target search space; the optimization strategy is generated multiple times by the network analysis model, and the model architecture is adjusted, so that the architecture is quickly iteratively optimized to form a model experience library; the model experience library is subjected to multiple rounds of model screening, and a new model architecture is generated by the network analysis model to extract knowledge from the historical high-performance architecture, thereby reducing the computational overhead of repeated trial and error, accelerating the search process, and improving the search efficiency; and then, the optimal processing model is selected from the model experience library after multiple rounds of updating for training to perform the to-be-processed task, thereby improving the task processing effect. According to the embodiment of the present disclosure, the computational overhead can be reduced, the dependence on large-scale computing resources can be reduced, and the precision and generalization ability of the model architecture search can be improved.

[0112] The beneficial effects of the model architecture generation method according to the embodiment of the present disclosure include:

[0113] 1. No need for domain-specific data: No need to rely on a large amount of domain-specific data for training or preprocessing, significantly reducing the time and cost of data preparation. Through the instant feedback and experience learning mechanism, the knowledge extraction ability of the large language model is directly utilized to optimize the neural network architecture, reducing the complexity of data collection and preprocessing, saving time and cost, and improving the universality and applicability of the method. The defect that related technologies (such as SEKI and LAPT-NAS) need to rely on historical data when cold starting a new task can be solved.

[0114] 2. Efficiency: Related technologies, such as reinforcement learning and evolutionary algorithms, usually require a large number of architecture evaluations, resulting in high computational overhead and making it difficult to apply to scenarios with limited computing resources. Compared with traditional neural architecture search methods, the embodiment of the present disclosure significantly reduces the consumption of computing resources. For example, the traditional method NASNet-A requires 3150 GPU days, while the embodiment of the present disclosure only requires 0.05 GPU days of search cost, significantly reducing the consumption of computing resources and improving the search efficiency. This makes it possible to efficiently optimize the neural network architecture in a resource-limited scenario, greatly reducing the research and development cost and improving the feasibility of research and application.

[0115] 3. Dynamic optimization and global search capability: The instant feedback optimization process (N times of optimization strategy generation and model architecture adjustment) can quickly adjust the optimization direction according to the performance of the current architecture in each iteration, avoiding the local optimum problem commonly seen in traditional methods. Through continuous instant feedback and optimization, the embodiment of the present disclosure can gradually improve the architecture performance and improve the stability and reliability of the optimization.

[0116] 4. Efficient utilization of empirical learning: Related technologies lack effective utilization mechanisms for historical optimization results, leading to repeated calculations and resource waste. The empirical learning feedback process (P-round model screening and model architecture generation) of the embodiments of the present disclosure generates new optimization architectures by analyzing the common characteristics of historical high-performance architectures. This mechanism not only avoids repeated calculations, but also learns from past search experience, further improving architecture performance and significantly improving optimization efficiency.

[0117] 5. Fast iteration and adaptability: Related technologies usually perform well on specific tasks or datasets, lacking broad applicability. The instant feedback mechanism of the present disclosure enables embodiments of the present disclosure to quickly respond to performance evaluation results and adjust architecture design strategies in a timely manner. This fast iteration capability makes the search process more agile and better adapts to the needs of different tasks and datasets. In addition, the embodiments of the present disclosure have also achieved excellent performance on natural language processing tasks (such as the Penn Treebank dataset), demonstrating their potential for wide application in different fields.

[0118] 6. Knowledge accumulation and reuse: The empirical learning feedback process accumulates a large number of high-performance architectures and their characteristics by building an experience library. This knowledge can be reused in subsequent search tasks, further accelerating the architecture search process for new tasks and improving overall efficiency.

[0119] It can be understood that the above-mentioned various method embodiments of the present disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to the limited space, the present disclosure will not be repeated. Those skilled in the art can understand that in the above-mentioned method of the specific embodiment, the specific execution order of each step should be determined by its function and possible internal logic.

[0120] In addition, the present disclosure also provides a model architecture generation device, an electronic device, and a computer readable storage medium, which can be used to implement any one of the model architecture generation methods provided by the present disclosure. The corresponding technical solutions and descriptions are described in the method section and are not repeated.

[0121] Figure 3 A block diagram of a model architecture generation device provided by an embodiment of the present disclosure.

[0122] Referring to Figure 3 , the embodiment of the present disclosure provides a model architecture generation device, which comprises:

[0123] The model searching module 31 is configured to determine model architecture information of a first processing model for the to-be-processed task from a target search space according to a task type of the to-be-processed task and a model restriction condition, wherein the model architecture information comprises an operation type of a network layer in the model, a feature fusion rule, and a connection manner between network layers.

[0124] The feedback optimization module 32 is configured to perform N times of optimization strategy generation and model architecture adjustment by using a preset network analysis model according to the model architecture information and the model score of the first processing model, and update a model experience library to obtain N times of updated model experience libraries, wherein the N times of updated model experience libraries comprise model architecture information and model scores of M second processing models, and M and N are integers greater than 1 and M < N.

[0125] The architecture generation module 33 is configured to perform P rounds of model screening and model architecture generation by using the network analysis model according to the N times of updated model experience libraries, and update the model experience library to obtain P rounds of updated model experience libraries, wherein P is an integer greater than 1.

[0126] The model training module 34 is configured to train a target processing model with the highest model score in the P rounds of updated model experience libraries to obtain a trained target processing model, and the target processing model is used to execute the to-be-processed task.

[0127] In some possible implementation manners, the first processing in the N times of optimization strategy generation and model architecture adjustment by the feedback optimization module 32 comprises the following steps: generating a first prompt word of the first processing model according to the model architecture information and the model score of the first processing model and a first prompt word template of the task type; inputting the first prompt word of the first processing model into the network analysis model to obtain an optimization strategy of the first processing model, wherein the optimization strategy comprises an adjustment manner of the model architecture information; adjusting the model architecture information of the first processing model according to the optimization strategy of the first processing model to obtain model architecture information of a first adjusted processing model; and adding the model architecture information of the first adjusted processing model into an initial model experience library to obtain a first updated model experience library.

[0128] In some possible implementation manners, the feedback optimization module 32 performs the n th processing in the N times of optimization strategy generation and model architecture adjustment by the preset network analysis model, including: generating a first prompt word for the n th processing according to model architecture information and a model score of the model adjusted in the n-1 th processing, an optimization strategy of the n-1 th processing, and a first prompt word template of the task type; n is an integer and 1 < n ≤ N; inputting the first prompt word for the n th processing into the network analysis model to obtain an optimization strategy of the n th processing; adjusting the model architecture information of the model adjusted in the n-1 th processing according to the optimization strategy of the n th processing to obtain model architecture information of a model adjusted in the n th processing; in a case where n ≤ M, adding the model architecture information of the model adjusted in the n th processing into the model experience library to obtain an n th updated model experience library; in a case where n > M, retaining, according to model scores of the models in the current model experience library and the model score of the model adjusted in the n th processing, model architecture information of M models with the highest model scores in the model experience library to obtain an n th updated model experience library.

[0129] In some possible implementation manners, the architecture generation module 33 performs the first round processing in the P rounds of model screening and model architecture generation by the network analysis model, including: selecting K third processing models with the highest model scores from the M second processing models; K is an integer and 1 < K < M; screening Q fourth processing models from the K third processing models according to a preset screening manner, Q is an integer and 1 < Q < K; generating a second prompt word for the first round processing according to model architecture information and a model score of the Q fourth processing models, and a second prompt word template of the task type; inputting the second prompt word for the first round processing into the network analysis model to obtain model architecture information of a processing model generated in the first round; retaining, according to model scores of the M second processing models and the model score of the processing model generated in the first round, model architecture information of M processing models with the highest model scores in the model experience library to obtain a first round updated model experience library.

[0130] In some possible implementation manners, the pth-round processing in the P-round model screening and model architecture generation by the architecture generation module 33 through the network analysis model includes: selecting K processing models with the highest model scores from the model experience library updated in the (p-1)th-round processing; p is an integer and 1 < p ≤ P; screening Q processing models from the K processing models according to a preset screening manner; generating a second prompt word for the pth-round processing according to the model architecture information and the model scores of the Q processing models and the second prompt word template of the task type; inputting the second prompt word for the pth-round processing into the network analysis model to obtain model architecture information of a processing model generated in the pth-round processing; and retaining, in the model experience library, model architecture information of M processing models with the highest model scores according to the model scores of the processing models in the model experience library updated in the (p-1)th-round processing and the model scores of the processing model generated in the pth-round processing, to obtain a model experience library for the pth-round processing.

[0131] In some possible implementation manners, the screening manner includes clustering screening, and the architecture generation module 33 is configured to: perform clustering on the K third processing models to obtain Q model categories; and determine, as a fourth processing model, a third processing model with the smallest distance to a clustering center in each model category, to obtain Q fourth processing models.

[0132] In some possible implementation manners, the screening manner includes non-uniform sampling, and the architecture generation module 33 is configured to: perform Q times of non-uniform sampling on the K third processing models to obtain Q fourth processing models; and in each time of non-uniform sampling, a probability of sampling a processing model with the highest model score is greater than a probability of sampling a random processing model.

[0133] In some possible implementation manners, the apparatus further includes a model verification module configured to perform performance verification on the first processing model according to a verification set of the to-be-processed task to obtain a model score of the first processing model.

[0134] In some possible implementation manners, the task type of the to-be-processed task includes any one of an image processing task, a speech processing task, a text processing task and a multi-modal processing task; the image processing task includes any one of an image classification task, an object detection task and a semantic segmentation task; the network analysis model includes a large language model (LLM); and the model restriction condition includes at least one of a network layer quantity, an operation quantity, an operation type and a network parameter quantity of a processing model.

[0135] Figure 4 A block diagram of an electronic device is provided for the embodiments of the present disclosure.

[0136] Reference is made to Figure 4The electronic device provided by the embodiment of the present disclosure includes: at least one processor 501; at least one memory 502, and one or more I / O interfaces 503 connected between the processor 501 and the memory 502; wherein the memory 502 stores one or more computer programs executable by the at least one processor 501, and the one or more computer programs are executed by the at least one processor 501 to enable the at least one processor 501 to perform the model architecture generation method described above.

[0137] The embodiment of the present disclosure further provides a computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the model architecture generation method described above. The computer readable storage medium can be a volatile or non-volatile computer readable storage medium.

[0138] The embodiment of the present disclosure further provides a computer program product including computer readable code or a non-volatile computer readable storage medium carrying computer readable code, when the computer readable code is run in the processor of the electronic device, the processor in the electronic device performs the model architecture generation method described above.

[0139] Those skilled in the art can understand that all or some steps in the method disclosed above, the functions of the modules / units in the system and the device can be implemented as software, firmware, hardware and their appropriate combinations. In the hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on a computer readable storage medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media).

[0140] As those skilled in the art will appreciate, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable program instructions, data structures, program modules or other data. Computer storage media include, but are not limited to, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), static random access memory (SRAM), flash memory or other memory technology, portable compact disc read only memory (CD-ROM), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, as those skilled in the art will appreciate, communication media typically embodies computer readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term "modulated data signal" means a signal that has one or more of its characteristics changed or set in a manner so as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as wireless networks, cellular telephone networks, code division multiple access (CDMA) networks, and other terrestrial and satellite radio frequency communication networks. Thus the computer readable program instructions and / or other program modules can be embodied in a computer readable storage medium, which can be any device or article that is enab!ed to store and / or carry computer readable program instructions and / or data structures. The computer readable storage medium can also be distributed over networked computer systems so that the computer readable program instructions and / or other program modules are stored and executed in a distributed fashion.

[0141] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0142] Computer readable program instructions for carrying out operations of the present disclosure can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, or any combination of one or more of the above in any combination, written in any combination of one or more programming languages, including object oriented programming languages such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0143] The computer program product described herein can be embodied in a specific manner by hardware, software, or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium. In another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK), and the like.

[0144] The various aspects of the present disclosure are described herein with reference to flow diagrams and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer readable program instructions.

[0145] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include a non-transitory computer readable storage medium that can be a computer- readable storage medium having no data storage cycles that change state. The instructions can be executed by one or more processors of a computer, other programmable data processing apparatus, or other devices to produce a computer-implemented process such that the instructions which execute via the one or more processors of the computer or other programmable data processing devices create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0146] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0147] The flow and block diagrams in the drawings show architectural, functional, and operational representations of possible implementations of systems, methods, and computer program products according to the present disclosure. In this regard, each block in the flow and block diagrams can represent a module, a segment, or a portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may

[0148] Example embodiments have been disclosed and, although a specific terminology is employed, it is merely for the convenience of the reader and is not intended to be limiting. In some instances, specific details have been included for the purpose of providing a thorough understanding of the embodiments presented, but it will be apparent to those skilled in the art that embodiments of the application can be practiced without these specific details. In some instances, features, characteristics and / or elements described in connection with a particular embodiment can be used in conjunction with, or switched to, features, characteristics and / or elements described in connection with other embodiments, unless otherwise explicitly stated. Accordingly, it will be understood that various changes in form and details can be made without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A model architecture generation method, characterized by, include: Determining, from a target search space, model architecture information of a first processing model for the task to be processed based on the task type and model constraints of the task to be processed; wherein the model architecture information includes operation types of network layers in the model, feature fusion rules, and connection methods between network layers; According to the model architecture information and model score of the first processing model, N optimization strategies are generated and model architecture is adjusted through the preset network analysis model, and the model experience library is updated to obtain the N updated model experience library, wherein the N updated model experience library includes the model architecture information and model scores of M second processing models, where M and N are integers greater than 1 and M <N; According to the N-times updated model experience library, performing P rounds of model screening and model architecture generation through the network analysis model, and updating the model experience library to obtain a P-round updated model experience library, where P is an integer greater than 1; The target processing model with the highest model score in the model experience library after the P rounds of updates is trained to obtain a trained target processing model, and the target processing model is used to execute the task to be processed.

2. The method of claim 1, wherein, The first process of performing N optimization strategy generation and model architecture adjustment using a preset network analysis model includes: generating a first prompt word for the first processing model according to the model architecture information and the model score of the first processing model and the first prompt word template of the task type; inputting the first prompt word of the first processing model into the network analysis model to obtain an optimization strategy for the first processing model, the optimization strategy including an adjustment method for model architecture information; Adjusting the model architecture information of the first processing model according to the optimization strategy of the first processing model to obtain the model architecture information of the processing model adjusted for the first time; The model architecture information of the processing model adjusted for the first time is added to the initial model experience library to obtain the first updated model experience library.

3. The method of claim 2, wherein, The nth processing of performing N optimization strategy generation and model architecture adjustment by using a preset network analysis model includes: Generate the first prompt word for the nth processing according to the model architecture information and model score of the processing model adjusted for the n-1th time, the optimization strategy for the n-1th processing, and the first prompt word template for the task type; n is an integer and 1 <n≤N; Inputting the first prompt word of the n-th processing into the network analysis model to obtain an optimization strategy for the n-th processing; Adjusting the model architecture information of the processing model adjusted for the nth time according to the optimization strategy for the nth processing to obtain the model architecture information of the processing model adjusted for the nth time; In the case of n≤M, the model architecture information of the processing model adjusted for the nth time is added to the model experience library to obtain an nth updated model experience library; In the case that n>M, according to the model scores of the processing models in the current model experience library and the model score of the n th adjusted processing model, the model architecture information of the M processing models with the highest model scores in the model experience library is retained to obtain an n th updated model experience library.

4. The method of claim 1, wherein, The first round of processing in the P rounds of model screening and model architecture generation by the network analysis model comprises: selecting K third processing models with the highest model scores from the M second processing models; K is an integer and 1 According to the preset screening method, Q fourth processing models are screened from the K third processing models; Q is an integer and 1 According to the model architecture information and the model scores of the Q fourth processing models and the second prompt word template of the task type, a second prompt word of the first round of processing is generated; The second prompt word of the first round of processing is input into the network analysis model to obtain model architecture information of the first round of generated processing models; According to the model scores of the M second processing models and the model score of the first round of generated processing models, the model architecture information of the M processing models with the highest model scores in the model experience library is retained to obtain a first round of updated model experience library.

5. The method of claim 4, wherein, The p th round of processing in the P rounds of model screening and model architecture generation by the network analysis model comprises: selecting K third processing models with the highest model scores from the M second processing models; K is an integer and 1 According to the preset screening method, Q fourth processing models are screened from the K third processing models; Q is an integer and 1 According to the model architecture information and the model scores of the Q fourth processing models and the second prompt word template of the task type, a second prompt word of the first round of processing is generated; The second prompt word of the first round of processing is input into the network analysis model to obtain model architecture information of the first round of generated processing models; According to the model architecture information and the model scores of the Q fourth processing models and the second prompt word template of the task type, a second prompt word of the first round of processing is generated; 6. The method of claim 4, wherein, According to the model architecture information and the model scores of the Q fourth processing models and the second prompt word template of the task type, a second prompt word of the first round of processing is generated; The screening method comprises clustering screening, and the screening of the Q fourth processing models from the K third processing models according to the preset screening method comprises The K third processing models are clustered to obtain Q model categories; 7. The method of claim 4, wherein, The third processing model with the smallest distance to the cluster center in each model category is determined as the fourth processing model to obtain Q fourth processing models. The screening method comprises non-uniform sampling, and the screening of the Q fourth processing models from the K third processing models according to the preset screening method comprises: The K third processing models are subjected to Q times of non-uniform sampling to obtain Q fourth processing models; 8. The method of claim 1, wherein, In each non-uniform sampling, the probability of sampling the processing model with the highest model score is greater than the probability of sampling a random processing model. The method further comprises: According to the validation set of the to-be-processed task, performance verification is performed on the first processing model to obtain a model score of the first processing model.

9. The method of claim 1, wherein, The task type of the to-be-processed task includes any one of an image processing task, a speech processing task, a text processing task, and a multi-modal processing task; and the image processing task includes any one of an image classification task, an object detection task, and a semantic segmentation task. The network analysis model includes a large language model (LLM). The model restriction condition includes at least one of a network layer number, an operation number, an operation type, and a network parameter quantity of a processing model.

10. A model architecture generation apparatus characterized by comprising: Comprise: a model search module configured to determine model architecture information of a first processing model for a to-be-processed task from a target search space according to a task type of the to-be-processed task and a model restriction condition, wherein the model architecture information includes an operation type of a network layer in the model, a feature fusion rule, and a connection manner between network layers; a feedback optimization module configured to perform N times of optimization strategy generation and model architecture adjustment through a preset network analysis model according to the model architecture information and the model score of the first processing model, and update a model experience library to obtain N times of updated model experience libraries, wherein the N times of updated model experience libraries include model architecture information and model scores of M second processing models, M and N are integers greater than 1 and M < N; an architecture generation module configured to perform P rounds of model screening and model architecture generation through the network analysis model according to the N times of updated model experience libraries, and update the model experience library to obtain P rounds of updated model experience libraries, P is an integer greater than 1; a model training module configured to train a target processing model with the highest model score in the P rounds of updated model experience libraries to obtain a trained target processing model, and the target processing model is used to execute the to-be-processed task.

11. An electronic device, comprising: Comprise: at least one processor; and a memory in communication with the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the model architecture generation method of any one of claims 1-9.

12. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by the processor, implements the model architecture generation method of any one of claims 1-9.

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