Display device and electronic device

Abstract

A display device and an electronic device are disclosed. The display device may include: a display panel in which a plurality of pixels may be arranged in a display area to display an image; a scan driver driving gate lines of the display area; a data driver driving data lines of the display area; a display driver that sorts interpolated image data according to a resolution of the display region, the display driver supplies the sorted interpolated image data to the data driver, and the display driver controls a driving timing of the scan driver and a driving timing of the data driver; and a data interpolator that modulates and interpolates image data of pixels that can be input from outside in accordance with driving characteristics of the display panel, and that generates and outputs the interpolated image data.

Description

TECHNICAL FIELD

[0001] One or more embodiments of the present disclosure relate to a display device and an electronic device. BACKGROUND

[0002] As the information society develops, the demand for display devices capable of presenting (displaying) images in various suitable forms is increasing. For example, display devices can be applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and / or smart televisions.

[0003] Display devices can be flat panel display devices such as liquid crystal display devices, field emission display devices, and / or organic light emitting display devices. Among these flat panel display devices, organic light emitting display devices can include light emitting elements that enable each pixel of a display panel to independently (by itself) emit light. Accordingly, organic light emitting display devices can display images without a backlight unit (that provides light to the display panel).

[0004] Display devices can include a display panel including a data line, a scan signal line, a plurality of pixels connected to the data line and the scan signal line, a scan driver supplying a scan signal to the scan signal line, a data driver supplying a data voltage to the data line, and a timing controller controlling a driving timing of the scan driver and a driving timing of the data driver. In addition, display devices can further include an image data interpolator interpolating and modulating digital image data input from an external source such as a graphic driver according to driving characteristics of the display panel such as resolution and driving frequency. SUMMARY

[0005] One or more aspects of embodiments of the present disclosure relate to display devices capable of controlling operations of an image data interpolator that can interpolate and modulate image data input from the outside according to identity, similarity, and / or repetition characteristics of the image data.

[0006] One or more aspects of embodiments of the present disclosure relate to display devices capable of comparing image data for pixels of red, green, blue, and white in units of at least one bit of data, and / or partially or completely controlling on / off operations of an image data interpolator based on a comparison result.

[0007] However, aspects of embodiments of the present disclosure are not limited to the aspects set forth herein. The above and other aspects and features of certain embodiments of the present disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, given by way of illustration and by way of non-limitation, wherein like references refer to like portions of the disclosure.

[0008] One or more embodiments of the present disclosure provide a display apparatus including a display panel in which a plurality of pixels are arranged in a display area to display an image, a scan driver to drive gate lines of the display area, a data driver to drive data lines of the display area, a display driver to order interpolated image data according to a resolution of the display area, to supply the ordered interpolated image data to the data driver, and to control a driving timing of the scan driver and a driving timing of the data driver, and a data interpolator to modulate and interpolate image data of pixels inputted from the outside according to driving characteristics of the display panel, and to generate and output the interpolated image data, wherein the data interpolator is arranged to compare image data of adjacent pixels in a process of interpolating the image data of the pixels inputted sequentially, and if the image data of the adjacent pixels are substantially the same (e.g., when the image data of the adjacent pixels are substantially the same), the data interpolator is arranged to apply previously generated interpolated image data as or to serve as interpolated image data for the image data of the adjacent pixels.

[0009] One or more embodiments of the present disclosure provide a display apparatus including a display panel in which a plurality of pixels are arranged in a display area to display an image, a scan driver to drive gate lines of the display area, a data driver to drive data lines of the display area, a display driver to control a driving timing of the scan driver and a driving timing of the data driver, and the display driver to sequentially supply interpolated image data to the data driver, and a data interpolator to modulate and interpolate image data of pixels inputted from the outside according to driving characteristics of the display panel, and the data interpolator to generate and output the interpolated image data, wherein the data interpolator is arranged to interpolate a gray scale value and a luminance value of the image data of the pixels according to at least one selected from among resolution characteristics, chroma characteristics, and driving frequency characteristics of the display area, the data interpolator is arranged to compare image data of adjacent pixels in a process of interpolating the image data of the pixels, and if the image data of the adjacent pixels are substantially the same (e.g., when the image data of the adjacent pixels are substantially the same), the data interpolator is arranged to apply previously generated interpolated image data as or to serve as interpolated image data for the image data of the adjacent pixels.

[0010] One or more embodiments of the disclosure provide an electronic device including a display device, wherein the display device includes a display panel, display pixels in a display area of the display panel, light sensing pixels together with the display pixels in the display area, infrared light emitting pixels together with the display pixels in the display area, a display scan driver driving the display pixels and the light sensing pixels to emit light, a light sensing scan driver driving the light sensing pixels to detect light, and a main driving circuit detecting a pulse wave signal of a user using a light sensing signal received through the light sensing pixels and measuring biometric information, wherein the main driving circuit is configured to separate and generate blood vessel image data from image data for a touch area during a user's touch position detection period, and the main driving circuit receives the light sensing signal of a light reception area by distinguishing the light reception area according to the blood vessel image data in the display area during a user's biometric information detection period.

[0011] The display device according to one or more embodiments of the disclosure can interpolate and modulate digital image data inputted from the outside according to driving characteristics (such as resolution and driving frequency) of a display panel, and display the interpolated and modulated digital image data as or as an image. Accordingly, image display quality can be improved or enhanced, and user satisfaction can be improved.

[0012] The display device according to one or more embodiments of the disclosure can selectively control an operation timing of an image data interpolator according to identity, similarity, and / or repetition characteristics of image data of red, green, blue, and white pixels. Accordingly, power consumption (or the degree or occurrence of power consumption) due to an image data interpolation operation can be reduced / decreased.

[0013] However, aspects, effects, and / or embodiments of the disclosure are not limited to those set forth in the disclosure. The above and other aspects, effects, and / or embodiments of the disclosure will become more apparent to one of ordinary skill in the art from the following description of one or more embodiments of the disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0014] The above and other aspects and features of certain embodiments of the disclosure will become more apparent from the following description of one or more embodiments of the disclosure taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 is a plan view of a display device according to one or more embodiments of the disclosure;

[0016] Figure 2 is a detailed lateral cross-sectional view of the display device of Figure 1 ​

[0017] Figure 3 is a waveform diagram illustrating image data operations and interpolation characteristics of a data interpolator according to one or more embodiments;

[0018] Figure 4 is a waveform diagram illustrating Figure 1 and Figure 2 is a block diagram illustrating an electrical connection relationship between a display panel and a driver shown in

[0019] Figure 5 is a detailed block diagram of Figure 4 the data interpolator shown in

[0020] Figure 6 is a waveform diagram illustrating Figure 5 data output timings of the first to fourth data modulation circuit units shown in

[0021] Figure 7 is a detailed block diagram of Figure 5 the first serial comparison circuit unit shown in

[0022] Figure 8 is a waveform diagram illustrating Figure 5 data interpolation operations of the first data modulation circuit unit shown in

[0023] Figure 9 is a detailed block diagram of Figure 5 the second embodiment of the first serial comparison circuit unit shown in

[0024] Figure 10 is a waveform diagram illustrating Figure 5 data interpolation operations of the first data modulation circuit unit shown in; and

[0025] Figure 11 is a waveform diagram illustrating power consumption reduction effects according to on / off and data interpolation operations of the first to nth data modulation circuit units. DETAILED DESCRIPTION

[0026] The subject matter of the present disclosure is described more fully by reference to the following drawings, in which embodiments of the present disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art.

[0027] It will also be understood that, if a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present. Throughout the specification, like reference numerals designate like elements in the drawings. Conversely, if an element is referred to as being "directly on" another element, then there are no intervening elements present.

[0028] It will be understood that, although the terms "first" and / or "second" etc. can be used herein to describe one or more suitable elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element discussed can later be referred to as a second element. Similarly, a second element can also be referred to as a first element.

[0029] Each of the features of one or more suitable embodiments of the present disclosure can be partially or wholly combined or combined with each other, and can be technically interlocked and driven in one or more suitable ways. Each embodiment can be implemented independently of each other, or can be implemented together in association.

[0030] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0031] Figure 1 is a plan view of a display device 10 according to one or more embodiments of the present disclosure. Figure 2 is Figure 1 is a detailed lateral cross-sectional view of the display device 10 of

[0032] Referring to Figure 1 and Figure 2 The display device 10 according to one or more embodiments can be applied to a portable electronic device such as a flat panel personal computer (PC), a portable multimedia player (PMP), a navigation device, an ultra mobile PC (UMPC), an electronic book, an electronic notebook, a mobile phone, a smart phone, and / or a mobile communication terminal, etc. For example, the display device 10 can be applied as a display unit that functions or serves as a television, a notebook computer, a monitor, a billboard, and / or an Internet of Things (IoT) device, etc.

[0033] An organic light emitting display device will be described in more detail as an example of the display device 10 according to one or more embodiments. The organic light emitting display device applied to one or more embodiments can be simply referred to as the display device 10 unless a particular distinction is desired or required. However, the display device 10 according to one or more embodiments is not limited to the organic light emitting display device, and other display devices listed above or suitable in the art can also be applied within the scope of sharing the technical spirit.

[0034] The display device 10 according to one or more embodiments can have a rectangular shape (e.g., a substantially rectangular shape), a square shape (e.g., a substantially square shape), a circular shape (e.g., a substantially circular shape), an elliptical shape (e.g., a substantially elliptical shape), or other quadrilateral shape (e.g., a substantially other quadrilateral shape) in a plan view. If the display device 10 is a mobile device such as a tablet PC (e.g., when the display device 10 is a mobile device such as a tablet PC), the display device 10 can have a rectangular shape (e.g., a substantially rectangular shape) with its long side positioned or arranged in a horizontal direction (X-axis direction). However, embodiments of the present disclosure are not limited thereto, and the long side can also be positioned or arranged in a vertical direction (Y-axis direction), or the display device 10 can be rotatably mounted or arranged such that the long side can be variably positioned or arranged in the horizontal direction or the vertical direction.

[0035] The display device 10 can include a display panel 100, a touch sensing unit TSU, a first scan driver 210, a second scan driver 211, a data driver 200, a display driver 400, and / or a data interpolator 500.

[0036] The display panel 100 of the display device 10 can include a display unit DU which can be configured to display an image and / or a touch sensing unit TSU which can be configured to detect a touch of a human body portion such as a finger and / or an electronic pen. As shown in FIG. 1, the display unit DU can include a substrate SUB, a thin film transistor layer TFTL, an emission layer EML, and a sealing layer TFEL which are sequentially stacked in a thickness direction (Z-axis direction). Figure 2 The display unit DU of the display panel 100 can include a plurality of pixels SP which can be configured to respectively display red, green, and blue, and the display unit DU of the display panel 100 can be configured to display an image through the pixels SP. In one or more embodiments, the display unit DU can also include a plurality of pixels SP which are arranged to respectively display red, green, blue, and white. Each three pixels SP which respectively display red, green, and blue can be defined as one unit pixel. In one or more embodiments, each four pixels SP which respectively display red, green, blue, and white can be defined as one unit pixel.

[0037] The touch sensing unit TSU can be mounted on a front of the display panel 100, or can be integrally formed or arranged with the display panel 100. The touch sensing unit TSU can include a plurality of touch electrodes, and the touch sensing unit TSU can be configured to capacitively detect a touch of a user using the touch electrodes.

[0038] The first scan driver 210 can be configured to supply a first gate scan signal to the pixels SP for each horizontal line through a first gate line for each horizontal line of the display unit DU based on a gate control signal from the display driver 400. The first scan driver 210 can be configured to drive the pixels SP arranged for each horizontal line so that the pixels SP can be sequentially charged with a data voltage by sequentially supplying the first gate scan signal to the first gate line for the horizontal line. The second scan driver 211 can be configured to supply a second gate scan signal to a second gate line for the horizontal line of the display unit DU based on the gate control signal. The second scan driver 211 can be configured to control a pixel driving voltage of the pixels SP to be output to the light emitting element on a horizontal line-by-horizontal line basis by sequentially supplying the second gate scan signal to the second gate line for the horizontal line.

[0039] The data driver 200 can include a plurality of data driving integrated circuits. The data driver 200 can be configured to output a data voltage according to image data to the pixels SP of the display unit DU based on a data driving control signal from the display driver 400. The data driving integrated circuits can be configured to supply the data voltage to a data line to which the pixels SP can be connected on a horizontal line-by-horizontal line basis at each horizontal period.

[0040] The display driver 400 can be configured to operate as a master processor (e.g., can act or function as a master processor), or can be integrated with or provided with a master processor. In one or more embodiments, the display driver 400 can be configured to control an overall function of the display apparatus 10. For example, the display driver 400 can be configured to sort image data that can be modulated and interpolated by the data interpolator 500 according to a resolution of the display unit DU, and supply the sorted image data to the data driving integrated circuits of the data driver 200. In one or more embodiments, the display driver 400 can be configured to control a data voltage output timing of the data driver 200 and a gate scan signal output timing of the first scan driver 210 and the second scan driver 211. In one or more embodiments, the display driver 400 can be configured to generate a data driving control signal to control a data voltage output timing of the data driving integrated circuits included in the data driver 200.

[0041] The display driver 400 can be configured to detect touch coordinate information included in touch data of the touch sensing unit TSU, and then generate digital video data according to the touch coordinate information. In one or more embodiments, the display driver 400 can be configured to execute an application indicated by an icon displayed at a touch coordinate of the user. For another example, the display driver 400 can be configured to receive coordinate data from an electronic pen, determine a touch coordinate of the electronic pen, and then generate digital video data according to the touch coordinate or execute an application indicated by an icon displayed at the touch coordinate of the electronic pen.

[0042] The data interpolator 500 can be configured to modulate and interpolate digital image data input from an external source such as a graphic system according to driving characteristics such as resolution and driving frequency of the display panel 100, and supply the modulated and interpolated digital image data to the display driver 400. For example, the data interpolator 500 can be configured to interpolate a gray scale value and a brightness value of digital image data of each pixel SP according to resolution characteristics and chroma characteristics of the display unit DU, and sequentially supply the interpolated image data to the display driver 400. In this process, 8-bit digital image data of each pixel SP can be modulated and interpolated into 10-bit image data, and the 10-bit image data can be sequentially supplied to the display driver 400.

[0043] If the data interpolator 500 modulates and interpolates all of the digital image data of the pixels SP and outputs the modulated and interpolated data (for example, when the data interpolator 500 modulates and interpolates all of the digital image data of the pixels SP and outputs the modulated and interpolated data), the data interpolator 500 can continuously (for example, substantially continuously) consume power during a driving period of the display panel 100. To reduce / reduce the power consumption (or to reduce the degree of power consumption or reduce the occurrence of power consumption), the data interpolator 500 can be configured to compare image data of adjacent pixels SP, and duplicate and output substantially the same interpolated image data for substantially the same image data. The data interpolator 500 can be configured to interpolate image data of the pixels SP while comparing image data of adjacent pixels SP, and if the image data of the adjacent pixels SP is substantially the same (for example, when the image data of the adjacent pixels SP is substantially the same), can be configured to duplicate and apply substantially the same interpolated image data and output substantially the same interpolated image data. In other words, to save power, the data interpolator 500 compares image data of adjacent pixels SP. If the data is substantially the same (for example, the same), the data interpolator 500 reuses the same interpolation data instead of reprocessing the interpolation data, thereby reducing power consumption during operation of the display panel.

[0044] For example, the data interpolator 500 can be configured to sequentially compare image data of red, green, and blue (or red, green, blue, and white) pixels SP that can be input in series and in parallel from the outside in the series state and the parallel state, and detect identical, similar, and / or repetitive features of image data of adjacent pixels SP in the series structure and the parallel structure. The data interpolator 500 can be configured to compare image data of adjacent pixels SP that can be input in the series structure and the parallel structure in units of at least one bit of data, and detect substantially identical image data for adjacent pixels SP of substantially the same color. Then, for image data of adjacent pixels SP of substantially the same color among which image data of pixels SP can be substantially identical, the data interpolator 500 can be configured to copy previously generated interpolation image data of pixels SP having substantially the same color and image data, and apply the copied interpolation image data as or to function as interpolation image data. In this way, the data interpolator 500 can stop the modulation and interpolation operation for pixels SP among which their image data can be substantially identical, and can copy and output previously generated interpolation image data of adjacent pixels SP having substantially identical image data. Accordingly, this can reduce (or reduce the degree of or reduce the occurrence of) power consumption for each cycle during which the modulation and interpolation operation is stopped. In other words, the data interpolator 500 compares image data of red, green, and blue (or red, green, blue, and white) pixels SP that are input in series and in parallel. If it is found that adjacent pixels SP have substantially identical (e.g., identical) image data, the data interpolator 500 reuses previously generated interpolation data instead of processing new data. By stopping unnecessary modulation and interpolation operations for pixels having similar data, this approach helps reduce power consumption.

[0045] In one or more embodiments and another aspect, for image data of pixels SP among which their image data are not substantially identical for adjacent pixels SP of substantially the same color for each of red, green, and blue, the data interpolator 500 can be configured to generate interpolation image data by interpolating a gray scale value or a luminance value and / or a number of bits according to a pre-set interpolation characteristic. In other words, when adjacent pixels SP of the same color have different image data (e.g., substantially different image data), the data interpolator 500 creates new interpolation image data by modifying a gray scale value or a luminance value and a number of bits according to a pre-defined setting.

[0046] Figure 3 is a graph showing image data operations and interpolation characteristics of the data interpolator 500 (see FIG. 1) according to one or more embodiments. Figure 1 ) according to one or more embodiments.

[0047] Reference is made to Figure 3 Reference is also made to Figure 1 For the image data of substantially different pixels SP among the image data of substantially same color adjacent pixels SP for each of red, green and blue, the gray scale value or luminance value and / or the number of bits can be interpolated by performing calculation according to a preset mathematical formula.

[0048] Table 1

[0049]

[0050] For example, the red modulation data (T_r), the green modulation data (T_g) and the blue modulation data (T_b) can be generated according to Figure 3 and Table 1, respectively, according to Equations 1-3. In one or more embodiments, TLUT_R, TLUT_G, TLUT_B, TLUT_C, TLUT_M, TLUT_Y, TLUT_K and TLUT_W can all be set to 8-bit data values. For example, data values can include 256 gray scale levels.

[0051] T_r = TLUT K_r + C1_r x i_r / r_step (e.g., action or task) + C2_r x i_g / g_step (e.g., action or task) + C3_r x i_b / b_step (e.g., action or task)

[0052] … (Equation 1).

[0053] T_g = TLUT K_g + C1_g x i_r / r_step (e.g., action or task) + C2_g x i_g / g_step (e.g., action or task) + C3_g x i_b / b_step (e.g., action or task)

[0054] … (Equation 2).

[0055] T_b = TLUT K_b + C1_b x i_r / r_step (e.g., action or task) + C2_b x i_g / g_step (e.g., action or task) + C3_b x i_b / b_step (e.g., action or task)

[0056] … (Equation 3).

[0057] g_r, g_g, and g_b shown in Table 1 represent condition information for each case (A1 to A6) and can include a gray scale value or a brightness value of image data according to an image feature such as a moving image. In one or more embodiments, in the above-described equation, r_step (e.g., an action or a task), g_step (e.g., an action or a task), and b_step (e.g., an action or a task) can be preset to an arbitrary gray scale value of 128.

[0058] Referring to Table 1, the data interpolator 500 can be configured to receive and store TLUT_R, TLUT_G, TLUT_B, TLUT_C, TLUT_M, TLUT_Y, TLUT_K, and TLUT_W data values within a preset range. In one or more embodiments, the data interpolator 500 can be configured to receive TLUTR_r / g / b, TLUTG_r / g / b, TLUTB_r / g / b, TLUTC_r / g / b, TLUTM_r / g / b, TLUTY_r / g / b, TLUTK_r / g / b, and TLUTW_r / g / b data values as or to function as image data values for each of red, green, and blue. In one or more embodiments, the data interpolator 500 can be configured to output red modulation data (T_r), green modulation data (T_g), and blue modulation data (T_b) as or to function as result data, which can include, respectively, red data values, green data values, and blue data values according to the results of calculations using Equations 1 to 3 within a range of interpolation data values shown as a cube in Figure 3 The red data values, green data values, and blue data values, which are the results of calculations using Equations 1 to 3 within a range of interpolation data values shown as a cube in

[0059] Referring also to Figure 2 The display panel 100 can be divided into a main area MA and a sub area SBA. The main area MA can include a display area DA having pixels SP displaying an image and a non-display area NDA arranged around the display area DA. In the display area DA, light can be emitted from an emission area or an opening area of each pixel SP to display an image. To this end, each pixel SP of the display area DA can include a pixel circuit including a switching element, a pixel definition layer defining an emission area or an opening area, and a self-emission element.

[0060] The non-display area NDA can be a peripheral area of the display area DA or an area outside the display area DA. The non-display area NDA can be defined as an edge area of the main area MA of the display panel 100. In the non-display area NDA, fan-out lines connecting the first scan driver 210, the second scan driver 211, the data driver 200, and the display driver 400 to the display area DA can be formed or arranged.

[0061] The sub-area SBA can extend from one side of the main area MA. The sub-area SBA can be a flexible film that can be bent, folded, and / or curled, etc. For example, if the sub-area SBA is bent (e.g., when the sub-area SBA is bent), the sub-area SBA can overlap the main area MA in the thickness direction (Z-axis direction). The sub-area SBA can include the data driver 200 and the pad unit connected to the circuit board 300. In one or more embodiments, the sub-area SBA can not be provided, and the data driver 200 and / or the pad unit can be disposed in the non-display area NDA.

[0062] The data driver 200 can be formed or configured to function or serve as a plurality of integrated circuits, and mounted on the display panel 100 using a glass on chip (COG) method, a plastic on chip (COP) method, and / or an ultrasonic bonding method. For example, the data driver 200 can be disposed in the sub-area SBA, and can overlap the main area MA in the thickness direction (Z-axis direction) by bending of the sub-area SBA. For another example, the data driver 200 can be mounted on the circuit board 300.

[0063] The circuit board 300 can be electrically connected with the pad unit of the display panel 100 through anisotropic conductive film (ACF). In one or more embodiments, a lead of the circuit board 300 can be electrically connected with the pad unit of the display panel 100. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, and / or a flexible film such as a chip on film.

[0064] The display driver 400 and the data interpolator 500 can be mounted on the circuit board 300. The display driver 400 and the data interpolator 500 can be formed or disposed to function or serve as integrated circuits.

[0065] Figure 4 is a block diagram illustrating an electrical connection relationship between the display panel 100 and the driver shown in Figure 1 and Figure 2 .

[0066] Referring to Figure 4 , also referring to Figure 1 , a plurality of pixels SP can be arranged in a matrix structure in the display area DA. In one or more embodiments, a plurality of first gate lines GL each connected to the pixels SP for a horizontal line and a plurality of second gate lines CL each connected to the pixels SP for a horizontal line can be arranged in the display area DA and / or the non-display area NDA.

[0067] The first gate lines GL and the second gate lines CL can extend in an X-axis direction (the X-axis direction can be a first horizontal direction) and can be spaced and / or separated (e.g., spaced apart or separated) from each other in a first vertical direction (Y-axis direction) intersecting the first horizontal direction. The first gate lines GL and the second gate lines CL can be arranged with regular gaps (e.g., substantially regular gaps) along the first vertical direction.

[0068] The first scan driver 210 can be configured to supply a first gate scan signal to the pixels SP for each horizontal line through the first gate lines GL for each horizontal line based on a gate driving control signal GCS from the display driver 400. The first gate lines GL can be configured to sequentially supply the first gate scan signal, which can be sequentially generated from the first scan driver 210 in each horizontal period, to the pixels SP on a horizontal line-by-horizontal line basis.

[0069] The second scan driver 211 can be configured to control a pixel driving voltage of the pixels SP to be respectively output to the light emitting elements on a horizontal line-by-horizontal line basis by sequentially supplying a second gate scan signal to the second gate lines CL for the horizontal lines. The second gate lines CL can be configured to sequentially supply the second gate scan signal, which can be sequentially generated from the second scan driver 211 in each horizontal period, to the pixels SP on a horizontal line-by-horizontal line basis.

[0070] The first gate scan signal of the first scan driver 210 and the second gate scan signal of the second scan driver 211 can be alternately generated in different timings in each horizontal period. For example, according to a driving order of thin film transistors formed or arranged in each pixel SP, the first gate scan signal can be first supplied to the first gate lines GL and then the second gate scan signal can be supplied to the second gate lines CL in each horizontal period.

[0071] In one or more embodiments, a plurality of data lines DL each connected to the pixels SP for a vertical line can be arranged in the display area DA and / or the non-display area NDA. The data lines DL can be electrically connected to the data driver 200. A data voltage can determine an emission luminance of each of the pixels SP. In one or more embodiments, a plurality of voltage detection lines VDL each connected to the pixels SP for a vertical line can be arranged in the display area DA and / or the non-display area NDA. The voltage detection lines VDL can be electrically connected to the data driver 200.

[0072] The data interpolator 500 can be configured to interpolate the gray scale values and luminance values of the digital image data ImData of the pixels SP that can be externally input according to the resolution characteristics and chromaticity characteristics of the display unit DU, and sequentially supply the interpolated image data RGB to the display driver 400. In one or more embodiments, the data interpolator 500 can be configured to sequentially compare the digital image data ImData of the pixels SP of red, green, blue, and white that can be serially and in parallel input from the outside in a serial state and a parallel state. Then, the data interpolator 500 can be configured to generate the interpolated image data for the image data of the pixels SP whose image data can be different among the image data of the adjacent pixels SP of substantially the same color by interpolating the gray scale values or luminance values or the number of bits of the image data according to a preset interpolation characteristic. In one or more embodiments and another aspect, for the image data of the pixels SP whose image data is substantially the same among the image data of the adjacent pixels SP of substantially the same color, the data interpolator 500 can be configured to copy the interpolated image data RGB of the adjacent pixels SP having substantially the same image data, and output the copied interpolated image data RGB as or as the interpolated image data RGB. In other words, the data interpolator 500 adjusts the gray scale values and luminance values of the input digital image data based on the characteristics of the display unit, and supplies these data to the display driver 400. The data interpolator 500 compares the image data of the pixels SP of red, green, blue, and white. If the adjacent pixels SP have different data (i.e., do not have substantially the same data), the data interpolator 500 generates new interpolation data. If the adjacent pixels SP have substantially the same data, the data interpolator 500 reuses the interpolation data from the adjacent pixels SP, reducing the need for new calculations.

[0073] The display driver 400 can be configured to receive a timing synchronization signal through an external graphic system, and sequentially receive the interpolated image data RGB of the pixels SP from the data interpolator 500. The display driver 400 can be configured to sequentially order the interpolated image data RGB of the pixels SP that can be sequentially received in units of at least one frame.

[0074] The display driver 400 can be configured to control the operation timing of the data driver 200 by generating the data driving control signal DCS based on the timing synchronization signal. In one or more embodiments, the display driver 400 can be configured to control the operation timing of the data driver 200 by sequentially supplying the interpolation image data RGB, which can be ordered in units of at least one frame, to the data driver 200 and supplying the data driving control signal DCS to the data driver 200. In one or more embodiments, the display driver 400 can be configured to independently control the operation timing of the first scan driver 210 and the second scan driver 211 by generating the gate driving control signal GCS and supplying the gate driving control signal GCS to the first scan driver 210 and the second scan driver 211. In an embodiment, the display driver 400 can supply the first gate driving control signal GCS1 to the first scan driver 210 and can supply the second gate driving control signal GCS2 to the second scan driver 211.

[0075] The data driving integrated circuit of the data driver 200 can be configured to output a data voltage according to the interpolation digital data DATA to the pixels SP of the display unit DU based on the data driving control signal DCS. The data driving integrated circuit can be configured to supply the data voltage to the data line DL to which the pixel SP can be connected on a line-by-line basis in each horizontal period.

[0076] Figure 5 is Figure 4 a detailed block diagram of the data interpolator 500 shown in FIG.

[0077] Referring to Figure 5 , also referring to Figure 4 , the data interpolator 500 can include a data comparison unit CPT, a modulation circuit unit ITP, and / or a selective output unit SOT.

[0078] The data comparison unit CPT can be configured to sequentially compare the image data ImData of the pixel SP, which can be input in series and in parallel from the outside, in a serial structure and a parallel structure, and output result signal data RC0_Data, RC1, RC2, and RC3, which can be generated based on the result of comparing the image data ImData, in the serial structure and the parallel structure according to the input structure of the image data ImData.

[0079] The image data ImData of the pixel SP from the outside can be input in 8 bits [7:0] size for each of the pixels SP of red, green, and blue, and the image data ImData of the pixels SP of red, green, and blue constituting each unit pixel can be input in a serial order through each communication line. In one or more embodiments, the image data ImData of the pixels SP of red, green, and blue constituting each unit pixel (for example, 8 bits [7:0] data for red image data R0, green image data G0, and blue image data B0) can be input in a serial order through each first communication line.

[0080] In one or more embodiments, the image data ImData of the other adjacent pixels SP of red, green, and blue (for example, 8 bits [7:0] data for red image data R1, green image data G1, and blue image data B1) can be input in a serial order through the second communication lines connected in parallel. In one or more embodiments, the image data ImData of the other adjacent pixels SP of red, green, and blue (for example, 8 bits [7:0] data for red image data R2, green image data G2, and blue image data B2) can be input in a serial order through the third communication lines connected in parallel. In one or more embodiments, the image data ImData of the other adjacent pixels SP of red, green, and blue (for example, 8 bits [7:0] data for red image data R3, green image data G3, and blue image data B3) can be input in a serial order through the fourth communication line.

[0081] Referring to Figure 5 , the data comparison unit CPT can include a plurality of serial comparison circuit units TP1 to TP4, at least one parallel comparison circuit unit ST1, a plurality of first logic gate circuits LO1 to LO3, and / or a plurality of second logic gate circuits LG1, LG2, and LG3, which function as or serve as components that sequentially compare the image data ImData of the pixels SP, which can be input in a serial structure and a parallel structure, in a serial state and a parallel state. In one or more embodiments, the data comparison unit CPT can further include a plurality of compression circuits CP1, CP2, CP3, and CP4, which can respectively compress the number of bits of the image data ImData of the pixels SP input in a serial structure through the communication lines.

[0082] The serial comparison circuit units TP1 to TP4 can be configured to sequentially receive the compressed image data RGB_0[9:0], RGB_1[9:0], RGB_2[9:0], and RGB_3[9:0] of the pixels SP through the compression circuits CP1 to CP4 connected in series thereto, respectively. Each of the serial comparison circuit units TP1 to TP4 can be configured to sequentially compare adjacent image data of substantially the same color among the compressed image data RGB_0[9:0], RGB_1[9:0], RGB_2[9:0], or RGB_3[9:0] sequentially input in a serial structure.

[0083] The serial comparison circuit units TP1 to TP4 can also be configured to sequentially receive the image data ImData of the pixels SP through the communication lines in a serial structure, respectively. In one or more embodiments, each of the serial comparison circuit units TP1 to TP4 can be configured to sequentially compare adjacent image data of substantially the same color among the image data ImData sequentially input in a serial structure. In one or more embodiments, each of the serial comparison circuit units TP1 to TP4 can be configured to separate and classify the image data ImData sequentially input in a serial structure into red image data, green image data, and blue image data, and sequentially compare adjacent image data of substantially the same color. In one or more embodiments, each of the serial comparison circuit units TP1 to TP4 can be configured to use a memory such as a plurality of lookup tables. Each of the serial comparison circuit units TP1 to TP4 can be configured to sequentially output a result signal data RC0_Data, RC1_Data, RC2_Data, or RC3_Data according to a result of comparing adjacent image data of substantially the same color in a serial structure.

[0084] For example, a first serial comparison circuit unit TP1 among the serial comparison circuit units TP1 to TP4 can be configured to separate and classify image data ImData that can be sequentially input through a first communication line into red image data R0[7:0], green image data G0[7:0], and blue image data B0[7:0], and sequentially compare image data for adjacent pixels SP of substantially the same color for each of red, green, and blue. The first serial comparison circuit unit TP1 can be configured to output result signal data RC0_Data for each of red, green, and blue according to a result of comparing adjacent image data of substantially the same color for each of red, green, and blue. In one or more embodiments, a high logic level bit data "1", "11", "111",... can be output if the image data is substantially the same (e.g., when the image data is substantially the same), and a low logic level bit data "0", "00", "000",... can be output if the image data is different (e.g., when the image data is different).

[0085] A second serial comparison circuit unit TP2 among the serial comparison circuit units TP1 to TP4 can be configured to separate and classify image data ImData that can be sequentially input through a second communication line into red image data R1[7:0], green image data G1[7:0], and blue image data B1[7:0], and sequentially compare adjacent image data of substantially the same color for each of red, green, and blue. The second serial comparison circuit unit TP2 can be configured to output result signal data RC0_Data or RC1_Data for each of red, green, and blue according to a result of comparing adjacent image data of substantially the same color for each of red, green, and blue.

[0086] A third serial comparison circuit unit TP3 among the serial comparison circuit units TP1 to TP4 can be configured to separate and classify image data ImData that can be sequentially input through a third communication line into red image data R2[7:0], green image data G2[7:0], and blue image data B2[7:0], and sequentially compare adjacent image data of substantially the same color for each of red, green, and blue. The third serial comparison circuit unit TP3 can be configured to output result signal data RC0_Data or RC2_Data for each of red, green, and blue according to a result of comparing adjacent image data of substantially the same color for each of red, green, and blue.

[0087] The fourth serial comparison circuit unit TP4 among the serial comparison circuit units TP1 to TP4 can be configured to separate and classify the image data ImData that can be sequentially input through the fourth communication line into red image data R3[7:0], green image data G3[7:0], and blue image data B3[7:0], and sequentially compare adjacent image data of substantially the same color for each of red, green, and blue. The fourth serial comparison circuit unit TP4 can be configured to output the result signal data RC0_Data or RC3_Data for each of red, green, and blue according to the result of comparing adjacent image data of substantially the same color for each of red, green, and blue.

[0088] The at least one parallel comparison circuit unit ST1 can be configured to sequentially compare the image data ImData of the pixels SP of red, green, and blue that can be input in a parallel structure through the second to fourth communication lines with the image data ImData of the pixels SP of red, green, and blue that can be input through the first communication line for each color. Then, the parallel comparison circuit unit ST1 can be configured to output the substantially identical data judgment signals In_C1, In_C2, and In_C3 for the second to fourth communication lines, respectively, based on the comparison result.

[0089] For example, the parallel comparison circuit unit ST1 can be configured to separate and classify the red image data, the green image data, and the blue image data that can be input through the second to fourth communication lines in a parallel structure by communication line and color, and compare the red image data, the green image data, and the blue image data with the red image data R0[7:0], the green image data G0[7:0], and the blue image data B0[7:0] that are sequentially input through the first communication line. Then, based on the comparison result, the substantially identical data judgment signals In_C1, In_C2, and In_C3 for the red image data, the green image data, and the blue image data can be output for the second to fourth communication lines, respectively. The substantially identical data judgment signals In_C1, In_C2, and In_C3 can be separated and classified by color and output accordingly. In one or more embodiments, the substantially identical data judgment signals In_C1, In_C2, and In_C3 can be mixed such that they can alternate by color (red, green, and blue) and can be output accordingly.

[0090] The first logic gate circuits LO1 to LO3 can be configured to output the synchronization signals R1(01), R2(01), and R3(01) indicating whether the image data of the pixels SP are substantially the same, respectively, based on the results of comparing the image data of the pixels SP in the serial structure and the parallel structure by the serial comparison circuit units TP1 to TP4 and the parallel comparison circuit unit ST1.

[0091] The first logic gate circuits LO1 to LO3 can be configured to output the synchronization signals R1(01), R2(01), and R3(01) indicating that the image data can be substantially the same, respectively, when it is determined that the image data are substantially the same based on the result of comparing the image data in at least any one of the structures among the results of comparing the image data in the serial structure and the parallel structure. In one or more embodiments, each of the first logic gate circuits LO1 to LO3 can be configured to compare and analyze any one of the result signal data RC0_Data, RC1_Data, RC2_Data, and RC3_Data of the serial comparison circuit units TP1 to TP4 with any one selected from among the substantially identical data judgment signals In_C1, In_C2, and In_C3 for the second to fourth communication lines. Then, the first logic gate circuits LO1 to LO3 can be configured to output the synchronization signals R1(01), R2(01), and R3(01) of the image data of the pixels SP according to the result of comparing the high logic level bit data or the low logic level bit data, respectively.

[0092] The second logic gate circuits LG1 to LG3 can be configured to match the output timing of the synchronization signals R1(01), R2(01), and R3(01) with the timing of the clock signal CLK and sequentially output the matching results, and the synchronization signals R1(01), R2(01), and R3(01) can be generated if it is determined that the image data is substantially the same based on the comparison results selected from at least one of the serial structure and the parallel structure (e.g., when it is determined that the image data is substantially the same based on the comparison results selected from at least one of the serial structure and the parallel structure). In one or more embodiments, each of the result signal data RC0_Data, RC1_Data, RC2_Data, and RC3_Data can be output as (e.g., can function as or serve as) a combination of the synchronization signals R1(01), R2(01), or R3(01) indicating that the image data can be substantially the same and the asynchronous signal indicating that the image data can be different. In one or more embodiments, the result signal data RC0_Data, RC1, RC2, and RC3 can be bit data in which a high logic level bit data "1" indicating that the image data can be substantially the same and a low logic level bit data "0" indicating that the image data can be different can be combined. In other words, the second logic gate circuits LG1 to LG3 align the synchronization signals indicating that the image data is the same with the timing of the clock signal and sequentially output the results. The result signal data combines the synchronization signals indicating that the image data is the same with the asynchronous signal indicating the difference. The high logic level bit data "1" indicates similar image data, and the low logic level bit data "0" indicates a difference.

[0093] The modulation circuit unit ITP can be configured to interpolate the image data of the pixels SP that can be different among the image data of the adjacent pixels SP of substantially the same color according to a preset interpolation characteristic in response to the result signal data RC0_Data, RC1, RC2, and RC3 input through the first serial comparison circuit unit TP1 and the second logic gate circuits LG1 to LG3, respectively. For example, the modulation circuit unit ITP can be configured to generate the interpolated image data RGB for only the pixels SP whose image data can be different from the image data of the adjacent pixels SP in response to the input result signal data RC0_Data, RC1, RC2, and RC3. In one or more embodiments, the modulation circuit unit ITP can include a plurality of data modulation circuit units IT1 to IT4, which can be configured to be turned on or off by being sequentially and respectively responsive to the result signal data RC0_Data, RC1, RC2, and RC3 input from the data comparison unit CPT and, if turned on (e.g., when turned on), can be configured to generate and output the interpolated image data RGB by interpolating each of the input image data according to a preset interpolation characteristic.

[0094] Figure 6 is a waveform diagram showing Figure 5 data output timing of the first data modulation circuit unit IT1 to the fourth data modulation circuit unit IT4 shown in

[0095] Referring to Figure 5 and Figure 6 , referring also to Figure 1 , the second logic gate circuits LG1 to LG3 can be configured to match the synchronization signals R1 (01), R2 (01), and R3 (01) to the output timing of the timing clock signal CLK and sequentially output the matching results, and the synchronization signals R1 (01), R2 (01), and R3 (01) can be generated if it is determined that the image data are substantially the same based on the comparison result in at least one selected from among the serial structure and the parallel structure (for example, when it is determined that the image data are substantially the same based on the comparison result in at least one selected from among the serial structure and the parallel structure). In Figure 6 , the timing clock signal CLK can be a clock signal that functions as or serves as the first result signal data RC0_Data of the data comparison unit CPT. In one or more embodiments, in Figure 6 , the second result signal data RC1 can be shown to function as or serve as a CLK_cg1 clock waveform, the third result signal data RC2 can be shown to function as or serve as a CLK_cg2 clock waveform, and the fourth result signal data RC3 can be shown to function as or serve as a CLK_cg3 clock waveform.

[0096] The RGBin_0 clock to the RGBin_n clock can be an output timing clock of the second data modulation circuit unit IT2, and the RGBin2_0 clock to the RGBin2_n clock can be an output timing clock of the third data modulation circuit unit IT3. In one or more embodiments, the RGBin3_0 clock to the RGBin3_n clock can be an output timing clock of the fourth data modulation circuit unit IT4.

[0097] in conjunction with Figure 5 Figure 6 ​, the first data modulation circuit unit IT1 can be configured to turn on during a low bit data input period of the first result signal data RC0_Data input from the data comparison unit CPT (e.g., during a period in which the timing clock signal CLK can act or function as a “0” input for low bits). Then, the first data modulation circuit unit IT1 can be configured to interpolate the image data R0 (Rin0), G0 (Gin0), and B0 (Bin0) input through the first communication line according to a preset interpolation characteristic, and output the interpolated image data IT1_out (ROut0, GOut0, BOut0). In one or more embodiments, the first data modulation circuit unit IT1 can be configured to turn off during a period in which the timing clock signal CLK of the first result signal data RC0_Data can act or function as a high bit data (e.g., “1”) input. In one or more embodiments, for a pixel SP having image data and color substantially the same as the image data and color of an adjacent pixel SP, the first data modulation circuit unit IT1 can be configured to copy the interpolated image data IT1_out (ROut0, GOut0, BOut0) of the adjacent pixel SP, and output the copied interpolated image data IT1_out (ROut0, GOut0, BOut0).

[0098] The second data modulation circuit unit IT2 can be configured to turn on or off in response to the CLK_cg1 clock of the second result signal data RC1 among the result signal data RC0_Data, RC1, RC2, and RC3 of the data comparison unit CPT. If turned on (e.g., when turned on), the second data modulation circuit unit IT2 can be configured to interpolate the image data R1 (Rin1), G1 (Gin1), and B1 (Bin1) input through the second communication line according to a preset interpolation characteristic, and generate and output the interpolated image data IT2_out (ROut1, GOut1, BOut1).

[0099] The second data modulation circuit unit IT2 can be configured to turn on during a period in which low logic level bit data of the CLK_cg1 clock of the second result signal data RC1 can be input. Then, the second data modulation circuit unit IT2 can be configured to interpolate the image data R1 (Rin1), G1 (Gin1), and B1 (Bin1) and generate and output the interpolated image data IT2_out (ROut1, GOut1, BOut1). In one or more embodiments, the second data modulation circuit unit IT2 can be configured to remain turned off during a period in which high logic level bit data (e.g., “1”) of the CLK_cg1 clock of the second result signal data RC1 can be input. In one or more embodiments, the second data modulation circuit unit IT2 can be configured to separately store the red valid data Rt1, the green valid data Gt1, and the blue valid data Bt1 or invalid data in a buffer or a memory according to the high level signal or the low level signal of the CLK_cg1 clock.

[0100] The third data modulation circuit unit IT3 can be configured to turn on or off in response to the CLK_cg2 clock of the third result signal data RC2 among the result signal data RC0_Data, RC1, RC2, and RC3 of the data comparison unit CPT. If turned on (e.g., when turned on), the third data modulation circuit unit IT3 can be configured to interpolate the image data R2 (Rin2), G2 (Gin2), and B2 (Bin2) input through the third communication line according to a preset interpolation characteristic and generate and output the interpolated image data IT3_out (ROut2, GOut2, BOut2).

[0101] The third data modulation circuit unit IT3 can be configured to turn on during a period in which low logic level bit data of the CLK_cg2 clock of the third result signal data RC2 can be input. Then, the third data modulation circuit unit IT3 can interpolate the image data R2 (Rin2), G2 (Gin2), and B2 (Bin2) and generate and output the interpolated image data IT3_out (Rout2, Gout2, Bout2). In one or more embodiments, the third data modulation circuit unit IT3 can remain turned off during a period in which high logic level bit data of the third result signal data RC2 can be input. In one or more embodiments, the third data modulation circuit unit IT3 can be configured to separately store the red valid data Rt2, the green valid data Gt2, and the blue valid data Bt2 or invalid data in a buffer or a memory according to the high level signal or the low level signal of the CLK_cg2 clock.

[0102] The fourth data modulation circuit unit IT4 can be configured to turn on or off in response to a CLK_cg3 clock of the fourth result signal data RC3 among the result signal data RC0_Data, RC1, RC2, and RC3 of the data comparison unit CPT. If turned on (e.g., when turned on), the fourth data modulation circuit unit IT4 can be configured to interpolate the image data R3 (Rin3), G3 (Gin3), and B3 (Bin3) input through the fourth communication line according to a preset interpolation characteristic, and generate and output the interpolated image data IT4_out (Rout3, GOut3, Bout3).

[0103] The fourth data modulation circuit unit IT4 can be configured to turn on during a period in which a low logic level CLK_cg3 clock of the fourth result signal data RC3 can be input. Then, the fourth data modulation circuit unit IT4 can interpolate the image data R3 (Rin3), G3 (Gin3), and B3 (Bin3), and generate and output the interpolated image data IT4_out (Rout3, Gout3, Bout3). In one or more embodiments, the fourth data modulation circuit unit IT4 can remain turned off during a period in which a CLK_cg3 clock of the fourth result signal data RC3 can be input in a high logic state. In one or more embodiments, the fourth data modulation circuit unit IT4 can be configured to separately store red valid data Rt3, green valid data Gt3, and blue valid data Bt3 or invalid data in a buffer or a memory according to a high level signal or a low level signal of the CLK_cg3 clock.

[0104] The selective output unit SOT can be configured to selectively output the interpolated image data of the pixel SP in response to the result signal data RC0_Data, RC1, RC2, and RC3 input from the data comparison unit CPT or the synchronization signal R1 (01), R2 (01), and R3 (01) of the image data of the pixel SP. For example, in response to the synchronization signal R1 (01), R2 (01), and R3 (01) of the image data of the pixel SP, the selective output unit SOT can replace the interpolated image data of the image data of the pixel SP that can be substantially the same as the image data of the adjacent pixel SP of substantially the same color with the interpolated image data IT1_out (Rout0, Gout0, Bout0) generated by the first data modulation circuit unit IT1, and output the replaced interpolated image data IT1_out (Rout0, Gout0, Bout0).

[0105] In one or more embodiments, the selective output unit SOT can include first to third data switching circuits MX1 to MX3, which can be configured to select the interpolated image data IT1_out (ROut0, GOut0, BOut0) generated by the first data modulation circuit unit IT1 or the interpolated image data IT2_out, IT3_out and IT4_out generated by the second to fourth modulation circuit units IT2 to IT4, respectively, and transmit the selected interpolated image data to the display driver 400. In one or more embodiments, the selective output unit SOT can further include first to third delay circuits Dy1 to Dy3, which can be configured to delay the first to third synchronization signals R1(01), R2(01) and R3(01) received from the first logic gate circuits LO1, LO2 and LO3 by one preset period, and supply the delayed first to third synchronization signals R1(01), R2(01) and R3(01) to the first to third data switching circuits MX1 to MX3, respectively. As shown in FIG. 10, the first to third data switching circuits MX1 to MX3 can be configured to select any one of the interpolated image data IT1_out and IT2_out generated by the first and second data modulation circuit units IT1 and IT2 in response to the first synchronization signal R1(01) inputted through any one selected from among the first to third logic gate circuits LO1 to LO3 and the first delay circuit Dy1, and transmit the selected interpolated image data to the display driver 400. Figure 5 In the embodiment, R0[9:0], G0[9:0], B0[9:0], R1[9:0], G1[9:0], B1[9:0], R2[9:0], G2[9:0], B2[9:0], R3[9:0], G3[9:0] and B3[9:0] are the resultant values (i.e., interpolated image data and bit values) outputted from the first to third data switching circuits MX1 to MX3, as shown in FIG. 10.

[0106] The first data switching circuit MX1 can be configured to select any one of the interpolated image data IT1_out generated by the first data modulation circuit unit IT1 and the interpolated image data IT2_out generated by the second modulation circuit unit IT2 in response to the first synchronization signal R1(01) inputted through any one selected from among the first to third logic gate circuits LO1 to LO3 and the first delay circuit Dy1, and transmit the selected interpolated image data to the display driver 400.

[0107] The first data switching circuit MX1 can be configured to transmit the interpolated image data generated by the first data modulation circuit unit IT1 to the display driver 400 during a period in which the first synchronization signal R1(01) can act or function as a high logic level bit data input. In one or more embodiments, the first data switching circuit MX1 can be configured to transmit the interpolated image data generated by the second modulation circuit unit IT2 to the display driver 400 during a period in which the first synchronization signal R1(01) can act or function as a low logic level bit data (e.g., “0”) input.

[0108] The second data switching circuit MX2 can be configured to select any one selected from among the interpolated image data IT1_out generated by the first data modulation circuit unit IT1 and the interpolated image data IT3_out generated by the third modulation circuit unit IT3 in response to the second synchronization signal R2(01) input through any one selected from among the first logic gate circuits LO1 to LO3 and the second delay circuit Dy2, and to transmit the selected interpolated image data to the display driver 400.

[0109] The second data switching circuit MX2 can be configured to transmit the interpolated image data generated by the first data modulation circuit unit IT1 to the display driver 400 during a period in which the second synchronization signal R2(01) can act or function as a high logic level bit data input. In one or more embodiments, the second data switching circuit MX2 can be configured to transmit the interpolated image data IT3_out generated by the third modulation circuit unit IT3 to the display driver 400 during a period in which the second synchronization signal R2(01) can act or function as a low logic level bit data input.

[0110] The third data switching circuit MX3 can be configured to select any one selected from among the interpolated image data IT1_out generated by the first data modulation circuit unit IT1 and the interpolated image data IT4_out generated by the fourth modulation circuit unit IT4 in response to the third synchronization signal R3(01) input through any one selected from among the first logic gate circuits LO1 to LO3 and the third delay circuit Dy3, and to transmit the selected interpolated image data to the display driver 400.

[0111] The third data switching circuit MX3 can be configured to transmit the interpolated image data generated by the first data modulation circuit unit IT1 to the display driver 400 during a period in which the third synchronization signal R3(01) can act or function as a high logic level bit data "1" input. In one or more embodiments, the third data switching circuit MX3 can be configured to transmit the interpolated image data generated by the fourth modulation circuit unit IT4 to the display driver 400 during a period in which the third synchronization signal R3(01) can act or function as a low logic level bit data "0" input.

[0112] Figure 7 is Figure 5 a detailed block diagram of the first embodiment of the first serial comparison circuit unit TP1 shown in FIG. 1.

[0113] Referring to Figure 7 , referring also to Figure 4 and Figure 5 , the first serial comparison circuit unit TP1 can include a plurality of data delay circuit units D(5n-4) to D(5n) and a plurality of data comparison circuit units CM(4n-3) to CM(4n).

[0114] The data delay circuit units D(5n-4) to D(5n) can be configured to sequentially delay and output image data R0_1[7:0], R0_2[7:0], R0_3[7:0], R0_4[7:0], R0_5[7:0], and R0_6[7:0] of pixels SP of at least any one color (e.g., red) in a serial structure among the image data ImData sequentially input through the first communication line.

[0115] The data comparison circuit units CM(4n-3) to CM(4n) can be configured to compare the image data delayed by the (5n-4)th delay circuit unit D(5n-4) and the (5n-2)th delay circuit unit D(5n-2) among the data delay circuit units D(5n-4) to D(5n), compare the image data delayed by the (5n-3)th delay circuit unit D(5n-3) and the (5n-1)th delay circuit unit D(5n-1), compare the image data delayed by the (5n-2)th delay circuit unit D(5n-2) and the (5n)th delay circuit unit D(5n), and compare the image data input through the first communication line and the image data delayed by the (5n-1)th delay circuit unit D(5n-1), and output a result signal data RC0_Data based on a comparison result.

[0116] For example, the first serial comparison circuit unit TP1 among the serial comparison circuit units TP1 to TP4 can be configured to separate and classify the image data ImData sequentially input through the first communication line into red image data R0[7:0], green image data G0[7:0] and blue image data B0[7:0], and sequentially compare the image data of adjacent pixels SP of substantially the same color for each of red, green and blue.

[0117] The first serial comparison circuit unit TP1 may include data delay circuit units D(5n-4) to D(5n) and data comparison circuit units CM(4n-3) to CM(4n) that serve as or function as components for comparing image data R0[7:0], G0[7:0], or B0[7:0] for each color among the image data ImData.

[0118] For example, the data delay circuit units D(5n-4) to D(5n) can be configured to sequentially delay and output image data R0_1[7:0] to R0_6[7:0] of pixels SP of at least any one color (e.g., red) in a serial structure among the image data ImData sequentially input through the first communication line. In one or more embodiments, n can be a positive integer.

[0119] The (4n-3)th data comparison circuit unit CM(4n-3) among the data comparison circuit units CM(4n-3) to CM(4n) can be configured to compare the image data delayed by the (5n-4)th delay circuit unit D(5n-4) and the (5n-2)th delay circuit unit D(5n-2), respectively, and output high or low logic level bit data RC_1 serving as or used as result signal data RC0_Data according to the comparison result.

[0120] The (4n-2)th data comparison circuit unit CM(4n-2) among the data comparison circuit units CM(4n-3) to CM(4n) can be configured to compare the image data delayed by the (5n-3)th delay circuit unit D(5n-3) and the (5n-1)th delay circuit unit D(5n-1), respectively, and output high or low logic level bit data RC_1 serving as or used as result signal data RC0_Data according to the comparison result.

[0121] The (4n-1)th data comparison circuit unit CM(4n-1) among the data comparison circuit units CM(4n-3) to CM(4n) can be configured to compare the image data delayed by the (5n-2)th delay circuit unit D(5n-2) and the (5n)th delay circuit unit D(5n), respectively, and output a high or low logic level bit data RC_0 acting as or serving as a result signal data RC0_Data according to a comparison result.

[0122] The (4n)th data comparison circuit unit CM(4n) among the data comparison circuit units CM(4n-3) to CM(4n) can be configured to compare the image data input through the first communication line and the image data delayed by the (5n-1)th delay circuit unit D(5n-1), and output a high or low logic level bit data RC_0 acting as or serving as a result signal data RC0_Data according to a comparison result.

[0123] The first serial comparison circuit unit TP1 can be configured to output the result signal data RC0_Data for each of red, green, and blue according to a result of comparing adjacent image data using the data comparison circuit units CM(4n-3) to CM(4n). In one or more embodiments, if the image data is substantially the same (e.g., when the image data is substantially the same), a high logic level bit data "1", "11", "111",... can be output, and if the image data is different (e.g., when the image data is different), a low logic level bit data "0", "00", "000",... can be output.

[0124] Figure 8 is Figure 5 a graph of a data interpolation operation of the first data modulation circuit unit IT1 shown in FIG. 1.

[0125] Referring to Figure 8 , also referring to Figure 4 and Figure 5 , the first data modulation circuit unit IT1 can be configured to be turned on during a period in which a low bit data (e.g., "0") of the first result signal data RC0_Data input from the data comparison unit CPT can be input. Then, the first data modulation circuit unit IT1 can interpolate the image data R0, G0, and B0 input through the first communication line according to a preset interpolation characteristic, and output the interpolated image data RGB.

[0126] The first data modulation circuit unit IT1 can be configured to be turned off during a period in which a high bit data (e.g., "1") of the first resultant signal data RC0_Data can be input. In one or more embodiments, for each pixel SP having an image data and a color substantially the same as the image data and the color of the adjacent pixel SP of the comparison, the first data modulation circuit unit IT1 can duplicate the interpolated image data R0_1[9:0] or R0_2[9:0] of the adjacent pixel SP and output the duplicated interpolated image data R0_1[9:0] or R0_2[9:0]. The description on the resultant values (i.e., the interpolated image data and the bit value) R0_6[9:0] and R0_5[9:0] will be omitted.

[0127] Figure 9 is a detailed block diagram illustrating a second embodiment of the first serial comparison circuit unit TP1 shown in Figure 5

[0128] Referring to Figure 9 , also referring to Figure 4 and Figure 5 , the first serial comparison circuit unit TP1 among the serial comparison circuit units TP1 to TP4 can be configured to separate and classify the image data ImData sequentially input through the first communication line into the red image data R0[7:0], the green image data G0[7:0], and the blue image data B0[7:0], and sequentially compare the image data of the adjacent pixels SP of substantially the same color for each of the red, green, and blue.

[0129] The first serial comparison circuit unit TP1 can include a plurality of data delay circuit units D(5n-4) to D(5n) and a plurality of data comparison circuit units CM(5n-4) to CM(5n) serving or functioning as components for comparing the image data R0[7:0], G0[7:0], or B0[7:0] for each color among the image data ImData.

[0130] For example, the data delay circuit units D(5n-4) to D(5n) can be configured to sequentially delay and output the image data R0_1[7:0] to R0_6[7:0] of the pixel SP of at least any one color (e.g., red) in a serial structure among the image data ImData sequentially input through the first communication line. In one or more embodiments, n can be a positive integer.

[0131] ​The (5n-4)th data comparison circuit unit CM(5n-4) among the data comparison circuit units CM(5n-4) to CM(5n) can be configured to compare the image data delayed by the (5n-4)th delay circuit unit D(5n-4) and the (5n-3)th delay circuit unit D(5n-3), respectively, and output a high or low logic level bit data RC_1 serving as or functioning as a result signal data RC0_Data according to a comparison result.

[0132] The (5n-3)th data comparison circuit unit CM(5n-3) among the data comparison circuit units CM(5n-4) to CM(5n) can be configured to compare the image data delayed by the (5n-3)th delay circuit unit D(5n-3) and the (5n-2)th delay circuit unit D(5n-2), respectively, and output a high or low logic level bit data RC_1 serving as or functioning as a result signal data RC0_Data according to a comparison result.

[0133] The (5n-2)th data comparison circuit unit CM(5n-2) among the data comparison circuit units CM(5n-4) to CM(5n) can be configured to compare the image data delayed by the (5n-2)th delay circuit unit D(5n-2) and the (5n-1)th delay circuit unit D(5n-1), respectively, and output a high or low logic level bit data RC_1 serving as or functioning as a result signal data RC0_Data according to a comparison result. The (5n-1)th data comparison circuit unit CM(5n-1) among the data comparison circuit units CM(5n-4) to CM(5n) can be configured to compare the image data delayed by the (5n-1)th delay circuit unit D(5n-1) and the (5n)th delay circuit unit D(5n), respectively, and output a high or low logic level bit data RC_0 serving as or functioning as a result signal data RC0_Data according to a comparison result.

[0134] The (5n)th data comparison circuit unit CM(5n) among the data comparison circuit units CM(5n-4) to CM(5n) can be configured to compare the image data input through the first communication line and the image data delayed by the (5n)th delay circuit unit D(5n), and output a high or low logic level bit data RC_0 serving as or functioning as a result signal data RC0_Data according to a comparison result.

[0135] The first serial comparison circuit unit TP1 can be configured to output result signal data RC0_Data for each of red, green, and blue according to a result of comparing adjacent image data using the data comparison circuit units CM(5n-4) to CM(5n). In one or more embodiments, if the image data is substantially the same (e.g., when the image data is substantially the same), a high logic level bit data "1", "11", "111",... can be output, and if the image data is different (e.g., when the image data is different), a low logic level bit data "0", "00", "000",... can be output.

[0136] Figure 10 is a graph illustrating a data interpolation operation of the first data modulation circuit unit IT1 shown in Figure 5

[0137] Referring to Figure 10 , referring also to Figure 4 and Figure 5 , the first data modulation circuit unit IT1 can be configured to be turned on during a period in which low bit data (e.g., "0") of the first result signal data RC0_Data input from the data comparison unit CPT can be input. Then, the first data modulation circuit unit IT1 can be configured to interpolate the image data R0, G0, and B0 input through the first communication line according to a preset interpolation characteristic, and output interpolated image data RGB.

[0138] The first data modulation circuit unit IT1 can be configured to be turned off during a period in which high bit data (e.g., "1") of the first result signal data RC0_Data can be input. In one or more embodiments, for each pixel SP having image data and color that is substantially the same as image data and color of a compared adjacent pixel SP, the first data modulation circuit unit IT1 can copy the interpolated image data R0_1[9:0] of the adjacent pixel SP, and output the copied interpolated image data R0_1[9:0].

[0139] Figure 11 is a graph illustrating a power consumption reduction effect according to turning on / off and data interpolation operations of the first data modulation circuit unit to the n-th data modulation circuit unit.

[0140] Referring to Figure 11 , referring also to Figure 4 ​, the data interpolator 500 can be configured to reduce power consumption (or reduce the degree of power consumption or reduce the occurrence of power consumption) due to the image data interpolation operation by controlling the timing of the on-off operation according to the identity characteristic caused by the repetition of the image data of the red, green, blue, and white pixels SP. In one or more embodiments, if low power is used according to the on-off control operation of the data interpolator 500 (e.g., when low power is used according to the on-off control operation of the data interpolator 500), the current consumption reduction effect can also be improved or enhanced compared to the amount of power consumed.

[0141] As can be seen, the amount of current consumed (1. consumed current) if low power is not used due to not performing the on-off control operation of the data interpolator 500 (e.g., when low power is not used due to not performing the on-off control operation of the data interpolator 500) and the amount of current consumed (2. consumed current) if low power is used due to performing the on-off control operation of the data interpolator 500 (e.g., when low power is used due to performing the on-off control operation of the data interpolator 500) can differ by the amount of delta current. For example, the current consumption reduction effect can vary according to the pattern shape of the displayed image. For example, it can be greater when a chess grid pattern (lattice pattern) is displayed than when a white pattern or a horizontal line (H-line) pattern is displayed.

[0142] In an embodiment, an electronic device including a display device is provided. The display device includes a display panel; display pixels in a display area of the display panel; light sensing pixels together with the display pixels in the display area; infrared light emitting pixels together with the display pixels in the display area; a display scan driver driving the display pixels and the light sensing pixels to emit light; a light sensing scan driver driving the light sensing pixels to detect light; and a main driving circuit detecting a pulse wave signal of a user using a light sensing signal received through the light sensing pixels, and measuring biometric information, wherein the main driving circuit is configured to separate and generate blood vessel image data from image data for a touch area during a touch position detection period of the user, and the main driving circuit receives a light sensing signal of a light reception area by distinguishing the light reception area according to the blood vessel image data in the display area during a biometric information detection period of the user.

[0143] In view of the entire disclosure of the present disclosure, those of ordinary skill in the art will appreciate that each suitable feature of various embodiments of the present disclosure can be partially or wholly combined or combined with each other, unless otherwise stated or implied, and can be technically interlocked and operated in various suitable methods, and each embodiment can be implemented independently of each other or in any suitable manner in combination with each other.

[0144] In the context of the present application and unless otherwise defined, the terms "use," "using," and "used" can be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0145] The display apparatus of embodiments according to the present application, apparatuses for manufacturing the display apparatus, and / or any other related apparatuses or components described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuits), software, or combinations thereof. For example, various components of the apparatuses can be formed on one integrated circuit (IC) chip or in separate IC chips. Also, various components of the apparatuses can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate. Further, various components of the apparatuses can be processes or threads, running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components for the purpose of performing various functions described herein. The computer program instructions can be stored in a memory which can be implemented in a computing device using standard memory devices, such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer readable media such as, for example, compact discs (CDs) or flash drives, among others. Also, those skilled in the art will appreciate that functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices, without departing from the scope of the present disclosure.

[0146] As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. In view of the discussion above, "approximately" or "about" as used herein includes the stated value and means within a range acceptable to one of ordinary skill in the art when used in connection with a measurement of the particular value. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0147] In this document, when describing embodiments of the application, the use of the term "may" means "one or more embodiments of the application."

[0148] At the end of the detailed description, those skilled in the art will appreciate that one or more changes and modifications to the embodiments described can be made without departing from the spirit and scope of the disclosure. Accordingly, the disclosed embodiments of the present disclosure are intended to be illustrative only and not limiting of the scope of the disclosure.

Claims

1. A display device, wherein, The display device includes: a display panel in which a plurality of pixels are arranged in a display area to display an image; a scan driver driving gate lines of the display area; a data driver driving data lines of the display area; a display driver: ordering interpolation image data according to a resolution of the display area; supplying the ordered interpolation image data to the data driver; and controlling a driving timing of the scan driver and a driving timing of the data driver; and a data interpolator: modulating and interpolating image data of pixels inputted from the outside according to driving characteristics of the display panel, and generating and outputting the interpolation image data, wherein the data interpolator compares image data of adjacent pixels in a process of interpolating the image data of the pixels inputted sequentially, and if the image data of the adjacent pixels are identical, the data interpolator applies previously generated interpolation image data as interpolation image data for the image data of the adjacent pixels.

2. The display device according to claim 1, wherein The data interpolator interpolates a gray scale value and a luminance value of the image data of the pixels according to at least one selected from among a resolution characteristic, a chroma characteristic, and a driving frequency characteristic of the display area, and replicates and applies the previously generated interpolation image data as interpolation image data for image data of pixels identical among the adjacent pixels according to a result of comparing the image data of the adjacent pixels.

3. The display device according to claim 2, wherein The data interpolator generates interpolation image data for image data of pixels different among image data of adjacent pixels of the same color by interpolating a gray scale value or a luminance value or a number of bits of the image data of the pixels different among the image data of the adjacent pixels of the same color according to a preset interpolation characteristic, and for image data of pixels identical among the image data of the adjacent pixels of the same color, the data interpolator replicates and applies interpolation image data of adjacent pixels having identical image data as the interpolation image data.

4. The display device according to claim 1, wherein The data interpolator includes: a data comparison unit comparing the image data of the pixels inputted in series and in parallel from the outside sequentially in a series state and a parallel state, and outputting result signal data in series and in parallel based on a comparison result; a modulation circuit unit generating interpolation image data by interpolating image data of pixels different from adjacent pixels of the same color according to a preset interpolation characteristic in response to the result signal data; and a selective output unit replacing interpolation image data for image data of pixels identical to adjacent pixels of the same color with the interpolation image data generated by the modulation circuit unit in response to the result signal data, and outputting the replaced interpolation image data.

5. The display device of claim 4, wherein, The data comparison unit includes: a plurality of serial comparison circuit units sequentially receiving the image data of the pixels in the serial structure through the compression circuit connected to the communication lines in the parallel structure or through the communication lines, sequentially comparing adjacent image data of the same color among the image data input in the serial structure, and outputting a result signal data based on a comparison result; at least one parallel comparison circuit unit sequentially comparing the image data of the pixels input in the parallel structure through the communication lines in the parallel structure with image data of the pixels input through another communication line for each color, and outputting a same data judgment signal for the communication lines in the parallel structure based on a comparison result; a plurality of first logic gate circuits each comparing any one selected from among the result signal data with any one selected from among the same data judgment signals for the communication lines in the parallel structure, and outputting a synchronization signal of the image data of the pixels of comparison in the serial and parallel structures, respectively; and a plurality of second logic gate circuits matching an output timing of the synchronization signal of the image data output through the plurality of first logic gate circuits with a timing clock signal from the outside, and outputting the result signal data based on a comparison result of adjacent image data in serial and parallel, respectively.

6. The display device of claim 5, wherein, the compression circuit is arranged one-to-one with the communication lines in the parallel structure, compresses the number of bits of the image data of the pixels input in the serial structure through the communication lines, respectively, and supplies the compressed image data to a corresponding serial comparison circuit unit among the plurality of serial comparison circuit units, respectively.

7. The display device according to claim 5, wherein a first serial comparison circuit unit among the plurality of serial comparison circuit units includes: a plurality of data delay circuit units sequentially delaying and outputting image data of pixels of at least any one color in the serial structure among image data sequentially input through a first communication line among the communication lines in the parallel structure; and a plurality of data comparison circuit units comparing image data delayed by a 5n-4 delay circuit unit and a 5n-2 delay circuit unit among the plurality of data delay circuit units, respectively, comparing image data delayed by a 5n-3 delay circuit unit and a 5n-1 delay circuit unit, respectively, comparing image data delayed by the 5n-2 delay circuit unit and a 5n delay circuit unit, respectively, comparing image data input through the first communication line with image data delayed by the 5n-1 delay circuit unit, and outputting the result signal data based on a comparison result.

8. The display device of claim 7, wherein, The first data modulation circuit unit of the modulation circuit unit is turned on during a period in which low bit data of first result signal data among the result signal data is input, to interpolate the image data of the pixel input through the first communication line and generate the interpolated image data, and the first data modulation circuit unit is turned off during a period in which high bit data of the first result signal data is input, to copy and replace the interpolated image data of the image data of adjacent pixels of the same color compared with each other, and output the copied and replaced interpolated image data.

9. The display device according to claim 5, wherein The first serial comparison circuit unit among the plurality of serial comparison circuit units includes: a plurality of data delay circuit units sequentially delaying and outputting image data of pixels of at least any one color in a serial structure among image data sequentially input through a first communication line among the communication lines in a parallel structure; and a plurality of data comparison circuit units comparing image data respectively delayed by a 5n-4th delay circuit unit and a 5n-3rd delay circuit unit among the plurality of data delay circuit units, comparing image data respectively delayed by the 5n-3rd delay circuit unit and a 5n-2nd delay circuit unit, comparing image data respectively delayed by the 5n-2nd delay circuit unit and a 5n-1st delay circuit unit, comparing image data respectively delayed by the 5n-1st delay circuit unit and a 5n-th delay circuit unit, comparing image data input through the first communication line and image data delayed by the 5n-th delay circuit unit, and outputting the result signal data based on comparison results.

10. The display device of claim 9, wherein, The first data modulation circuit unit of the modulation circuit unit is turned on during a period in which low bit data of first result signal data among the result signal data is input, to interpolate the image data of the pixel input through the first communication line and generate the interpolated image data, and the first data modulation circuit unit is turned off during a period in which high bit data of the first result signal data is input, to copy and replace the interpolated image data of the image data of adjacent pixels of the same color compared with each other, and output the copied and replaced interpolated image data.

11. A display device, wherein, The display device includes: a display panel in which a plurality of pixels are arranged in a display area to display an image; a scan driver driving gate lines of the display area; a data driver driving data lines of the display area; a display driver controlling a driving timing of the scan driver and a driving timing of the data driver, and sequentially supplying interpolated image data to the data driver; and a data interpolator modulating and interpolating image data of pixels input from the outside according to a driving characteristic of the display panel, and generating and outputting the interpolated image data, The data interpolator interpolates a gray scale value and a luminance value of the image data of the pixel according to at least one selected from among a resolution characteristic, a chroma characteristic, and a driving frequency characteristic of the display area, and compares image data of adjacent pixels in interpolating the image data of the pixel, and if the image data of the adjacent pixels are the same, applies previously generated interpolated image data as interpolated image data for the image data of the adjacent pixels. 12.An electronic device comprising a display device, wherein, The display device includes: a display panel; display pixels in a display area of the display panel; light sensing pixels together with the display pixels in the display area; infrared light emitting pixels together with the display pixels in the display area; a display scan driver driving the display pixels and the light sensing pixels to emit light; a light sensing scan driver driving the light sensing pixels to detect light; and a main driving circuit detecting a pulse wave signal of a user using a light sensing signal received through the light sensing pixels, and measuring biometric information, wherein the main driving circuit is configured to separate and generate blood vessel image data from image data for a touch area during a user's touch position detection period, and the main driving circuit receives the light sensing signal of a light reception area by distinguishing the light reception area according to the blood vessel image data in the display area during a user's biometric information detection period.

Images