Write training circuit, semiconductor device, and data processing system

Abstract

The invention relates to a write training circuit, a semiconductor device and a data processing system. The write training circuit includes a data receiving circuit, a strobe signal processing circuit, and a skew detection circuit. The data receiving circuit receives a data input according to a plurality of multi-phase clock signals to generate received data. A strobe signal processing circuit generates a plurality of multi-phase clock signals by dividing a data strobe signal into divided signals and delaying the divided signals for a predetermined period of time. The skew detection circuit generates a replica clock signal corresponding to one of the plurality of multi-phase clock signals, and generates skew information according to the replica clock signal. The skew detection circuit generates skew information under or independently of external control according to which of the plurality of external commands is received.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Application No. 10-2024-0052709 filed on April 19, 2024, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments generally relate to a semiconductor apparatus, including but not limited to a write training circuit, and a semiconductor memory device and a data processing system including the write training circuit. Background Art

[0004] Conventional semiconductor memory devices perform a write leveling operation and a write training operation separately, or do not perform the write leveling operation and the write training operation simultaneously.

[0005] The write leveling operation compensates for a time difference between a clock signal used inside the semiconductor memory device and a data strobe signal provided externally.

[0006] The write training operation is a process that includes internally multiphasing a data strobe signal provided from outside the semiconductor memory device to detect and compensate for timing variations of externally latched data.

[0007] Figure 1 is a diagram illustrating a conventional write training operation.

[0008] Reference Figure 1 In the prior art, a write training operation WTRN cannot be performed in parallel with normal operations such as a data input operation in response to a write command or a data output operation in response to a read command. The write training operation WTRN is performed in a separate time period between the data input operation and the data output operation. The frequency of performing the write training operation WTRN depends on user needs.

[0009] As described above, in the related art, the write training operation WTRN is performed in a separate interval between the data input operation and the data output operation, which increases the time required for data input and data output of the semiconductor memory device. Summary of the Invention

[0010] In an embodiment, a write training circuit can include a data receiving circuit, a strobe signal processing circuit, and a skew detection circuit. The data receiving circuit can be configured to receive a data input according to a plurality of multi-phase clock signals to generate received data. The strobe signal processing circuit can be configured to generate the plurality of multi-phase clock signals by dividing a data strobe signal into a divided signal and delaying the divided signal by a predetermined time period. The skew detection circuit can be configured to generate a replica clock signal corresponding to one of the plurality of multi-phase clock signals, and can be configured to generate skew information according to the replica clock signal. The skew detection circuit can be configured to generate the skew information under external control or independently of the external control according to which of a plurality of external commands is received.

[0011] In an embodiment, a semiconductor device can include a semiconductor memory apparatus configured to perform a normal operation upon receiving a command for the normal operation, and can be configured to perform a write training operation for a time period in which the normal operation is performed. The write training operation can include internally multi-phasing a data strobe signal provided from an external device to determine a time to latch data provided from the external device.

[0012] In an embodiment, a data processing system can include a semiconductor memory apparatus and a controller. The semiconductor memory apparatus can be configured to perform a write training operation including determining a time to latch data according to a plurality of multi-phase clock signals internally generated based on a data strobe signal and outputting the time as skew information for a time period in which a normal operation is performed; can be configured to perform the write training operation under external control upon receiving a write training enable command; and can be configured to perform the write training operation independently of the external control upon receiving a write training internal processing enable command. The controller can be configured to provide the semiconductor memory apparatus with a plurality of commands including the write training enable command and the write training internal processing enable command, data, and the data strobe signal, and can be configured to adjust a timing of the data strobe signal according to the skew information.

[0013] In an embodiment, a method can include a semiconductor memory apparatus performing a normal operation for a first time period in response to receiving a command, and the semiconductor memory apparatus performing a write training operation during a second time period of the first time period, the write training operation including multi-phasing a received data strobe signal to determine a time to latch data provided from an external device. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a diagram illustrating a write training operation of the prior art.

[0015] Figure 2is a diagram illustrating a multi-operation function including write training according to an embodiment of the disclosure.

[0016] Figure 3 is a diagram illustrating a multi-operation function including write training according to an embodiment of the disclosure.

[0017] Figure 4 is a diagram illustrating a multi-operation function including write training according to an embodiment of the disclosure.

[0018] Figure 5 is a diagram illustrating a configuration of a semiconductor memory device according to an embodiment of the disclosure.

[0019] Figure 6 is a diagram illustrating a configuration of a data processing system according to an embodiment of the disclosure.

[0020] Figure 7 is a diagram illustrating a multi-operation function including write training according to an embodiment of the disclosure.

[0021] Figure 8 is a diagram illustrating a multi-operation function including write training according to an embodiment of the disclosure.

[0022] Figure 9 is a diagram illustrating a configuration of a write training circuit according to an embodiment of the disclosure.

[0023] Figure 10 is a diagram illustrating a configuration of a data reception circuit according to an embodiment of the disclosure.

[0024] Figure 11 is a diagram illustrating a configuration of a strobe signal processing circuit according to an embodiment of the disclosure.

[0025] Figure 12 is a diagram illustrating a configuration of a strobe signal copying circuit according to an embodiment of the disclosure.

[0026] Figure 13 is a diagram illustrating a configuration of a timing control circuit according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0027] Various embodiments of the disclosure can reduce the time required for data input and data output of a semiconductor memory device. Various embodiments of the disclosure can reduce control-related load of an external device that controls a semiconductor memory device by self-processing a write training operation using a minimum or less external command.

[0028] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. The specific structural or functional descriptions in the embodiments are provided only as examples to illustrate the concepts disclosed in this application. The examples or embodiments based on the concepts may be implemented in various forms, and the scope of the present disclosure is not limited to the examples or embodiments described in this specification.

[0029] Figure 2 is a diagram illustrating a multi-operation function including write training according to an embodiment of the present disclosure. Figure 2 An example of a multi-operation function including write training when normal operations such as a data input operation in response to a write command and a data output operation in response to a read command are sequentially performed is shown.

[0030] Reference Figure 2 , the present disclosure performs the write training operation WTRN in parallel with the data input operation, for example, performing the write training operation WTRN within a predetermined time period tWTRN within a time period of performing the data input operation.

[0031] The write training operation WTRN begins after a first timing margin tMGN1 after the start of the data input operation and ends before a second timing margin tMGN2 before the end of the data input operation. The first timing margin tMGN1 and the second timing margin tMGN2 illustrate an example of a stable progress of the data input operation relative to the progress of the write training operation WTRN. Alternatively, one or both of the first timing margin tMGN1 and the second timing margin tMGN2 may be used to start or end the write training operation WTRN.

[0032] Figure 3 is a diagram illustrating a multi-operation function including write training according to an embodiment of the present disclosure. Figure 3 Another example of a multi-operation function including write training is shown, in which data input operations and data output operations are performed sequentially.

[0033] Reference Figure 3 The write training operation WTRN is performed in parallel with the data output operation, for example, the write training operation WTRN is performed within a predetermined time period tWTRN within a time period in which the data output operation is performed.

[0034] The write training operation WTRN begins after a first timing margin tMGN1 after the start of the data output operation and ends before a second timing margin tMGN2 before the end of the data output operation. With respect to the progress of the write training operation WTRN, the first timing margin tMGN1 and the second timing margin tMGN2 illustrate an example of a stable progress of the data output operation. Alternatively, one or both of the first timing margin tMGN1 and the second timing margin tMGN2 may be used to start or end the write training operation WTRN.

[0035] Figure 4 is a diagram illustrating a multi-operation function including write training according to an embodiment of the present disclosure. Figure 4 An example of a multi-operation function including write training is illustrated when an erase operation and a data output operation are sequentially performed.

[0036] Referring to Figure 4 , a write training operation WTRN is performed in parallel with an erase operation, for example, within a predetermined time period tWTRN within a time period in which the erase operation is performed.

[0037] The write training operation WTRN starts after a first timing margin tMGN1 after the start of the erase operation and ends before a second timing margin tMGN2 before the end of the erase operation. The first timing margin tMGN1 and the second timing margin tMGN2 show an example of stable progress of the erase operation with respect to the progress of the write training operation WTRN. Optionally, one or both of the first timing margin tMGN1 and the second timing margin tMGN2 can be used to start or end the write training operation WTRN.

[0038] Figure 5 is a diagram illustrating a configuration of a semiconductor memory device 100 according to an embodiment of the present disclosure.

[0039] The semiconductor memory device 100 is configured to perform a multi-operation function. The multi-operation function includes at least one of: performing a data input operation according to a write command in parallel with a write training operation; performing a data output operation according to a read command in parallel with a write training operation; and performing an erase operation in parallel with a write training operation.

[0040] For example, a write training operation is performed by detecting or determining a time at which data provided from outside the semiconductor memory device 100 is latched from a data strobe signal provided from outside the semiconductor memory device 100 through an internal multiphase processing. The write training operation is performed by notifying the semiconductor memory device 100 of the detected or determined time and adjusting a timing of the data strobe signal by an amount corresponding to a change in the detected or determined time from outside the semiconductor memory device 100 accordingly.

[0041] Referring to Figure 5 , the semiconductor memory device 100 includes a memory cell array 110, a peripheral circuit 170, and a control circuit 180.

[0042] The memory cell array 110 includes a plurality of memory cells arranged in at least one memory plane. For example, the memory cell array 110 includes a first memory plane PL1 to a kth memory plane PLk, where k is a positive integer. Each of the memory planes PL1 to PLk includes a memory block. The memory block can be formed as a two-dimensional structure or a three-dimensional structure. The memory block having the two-dimensional structure includes memory cells arranged parallel to a substrate. The memory block having the three-dimensional structure includes memory cells stacked perpendicular to the substrate. Depending on a programming method, the memory cell stores one bit, two bits, or more than two bits of data.

[0043] The peripheral circuit 170 is configured to perform a program operation to store data in the memory cell array 110, a read operation to output data stored in the memory cell array 110, and an erase operation to erase data stored in the memory cell array 110. For example, the peripheral circuit 170 includes the voltage generator 120, the row decoder set 130, the page buffer set 140, the column decoder 150, and the input / output circuit 160.

[0044] The voltage generator 120 generates various operation voltages Vop used during the program operation, the read operation, and the erase operation in response to the operation code OPCD. For example, the voltage generator 120 can be configured to generate a program voltage, a pass voltage, a turn-on voltage, a turn-off voltage, a ground voltage, a verify voltage, a read voltage, an erase voltage, etc. in response to the operation code OPCD. The program voltage is a voltage applied to a selected word line during the program operation, which can be used to increase a threshold voltage of a memory cell. The pass voltage is a voltage applied to an unselected word line during the program or read operation, which can be used to turn on an unselected memory cell. The turn-on voltage is a voltage applied to a drain select line or a source select line, which can be used to turn on a drain select transistor or a source select transistor. The turn-off voltage is a voltage applied to the drain select line or the source select line, which can be used to turn off the drain select transistor or the source select transistor. The ground voltage can be 0 V. The verify voltage is a voltage applied to a selected word line or all word lines coupled to a selected memory block during the program or erase operation, which is used to determine a threshold voltage of a selected memory cell. The read voltage is a voltage applied to a selected word line during the read operation, which can be used to determine data stored in a memory cell. The erase voltage is a voltage applied to a source line during the erase operation, which can be used to decrease a threshold voltage of a memory cell.

[0045] The row decoder group 130 is configured to transmit the operating voltage Vop to the local line LCL coupled to the selected memory block according to the row address RADD. For example, the row decoder group 130 is coupled to the voltage generator 120 through the global line and is coupled to the first memory plane PL1 to the k-th memory plane PLk through the local line LCL. The row decoder group 130 includes a plurality of row decoders (not shown), each of which is coupled to one of the memory planes PL1 to PLk. Each of the plurality of row decoders is coupled to the memory block included in the memory planes PL1 to PLk through the local line LCL. The local line LCL includes a drain select line, a word line, a source select line, a source line, etc.

[0046] The page buffer group 140 includes a plurality of page buffers PB1 to PBn, where n is a positive integer. Each of the plurality of page buffers PB1 to PBn can have the same circuit configuration. The plurality of page buffers PB1 to PBn is coupled to the memory cell array 110 through the plurality of bit lines BL. The plurality of page buffers PB1 to PBn adjusts a voltage level applied to the plurality of bit lines BL and a duration of voltage applied to the bit lines BL in response to a plurality of page buffer control signals PBSIG. The plurality of page buffers PB1 to PBn stores externally provided data in response to the plurality of page buffer control signals PBSIG. Among the plurality of page buffers PB1 to PBn, the page buffers corresponding to the remaining sub-verification operations other than the verified sub-verification operation are simultaneously pre-charged to the bit lines coupled to the respective page buffers. Each of the plurality of page buffers PB1 to PBn determines a respective sub-verification operation from the stored data. The plurality of page buffers PB1 to PBn can pre-charge the respective bit lines by applying a pre-charge voltage to the respective bit lines for each sub-verification operation in response to the plurality of page buffer control signals PBSIG.

[0047] The column decoder 150 is configured to transfer data between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 is coupled to the page buffer group 140 through the column line CL and is coupled to the input / output circuit 160 through the data line DL.

[0048] The input / output circuit 160 transfers a command CMD and an address ADD received from an external device, e.g., a controller, to the control circuit 180. The input / output circuit 160 receives data transmitted from the external device in response to a data strobe signal transmitted from the external device and transmits the data to the page buffer group 140 through the column decoder 150. The input / output circuit 160 outputs data transferred from the column decoder 150 to the external device. The input / output circuit 160 includes a write training circuit that performs a write training operation.

[0049] The control circuit 180 outputs an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to the command CMD and the address ADD. When the input command CMD identifies an erase operation, the control circuit 180 controls the peripheral circuit 170 to perform an erase operation on the memory block selected by the address ADD. When the input command CMD identifies a read operation, the control circuit 180 controls the peripheral circuit 170 to perform a read operation on the memory block selected by the address and outputs the read data. When the input command CMD identifies a program operation, the control circuit 180 controls the peripheral circuit 170 to perform a program and verify operation on the selected memory block.

[0050] The control circuit 180 includes a page buffer control circuit 180A. In response to the command CMD, the page buffer control circuit 180A generates a page buffer control signal PBSIG that adjusts a voltage level applied to the bit line BL and a duration of the voltage applied to the bit line BL. The page buffer control signal PBSIG includes various signals that adjust the voltage applied to the bit line BL and to the circuitry contained in the plurality of page buffers PB1 to PBn.

[0051] The page buffer control circuit 180A adjusts the page buffer control signal PBSIG so that an erase voltage is applied to the bit line BL during an erase operation. The page buffer control circuit 180A adjusts the page buffer control signal PBSIG so that a pre-charge voltage is applied to the bit line BL.

[0052] The page buffer control circuit 180A adjusts the value of the page buffer control signal PBSIG so that, during a program operation, a program enable voltage is applied to selected bit lines in the bit line BL and a program inhibit voltage is applied to unselected bit lines.

[0053] Figure 6 is a diagram illustrating a configuration of a data processing system 1000 according to an embodiment of the present disclosure.

[0054] Referring to Figure 6 , the data processing system 1000 includes a semiconductor device 2000 and a controller 3000.

[0055] In Figure 6 the example, the semiconductor device 2000 includes a plurality of logic units LU0 to Lun, where n is a positive integer. Each of the plurality of logic units LU0 to Lun includes at least one memory die and is also referred to as a semiconductor memory apparatus 100. One or more of the plurality of logic units LU0 to Lun 100 are implemented similarly to the semiconductor memory apparatus 100 described with reference to Figure 5 .

[0056] The semiconductor device 2000 is configured to perform a multi-operation function. The multi-operation function includes at least one of performing a data input operation in parallel with a write training operation in response to a write command, performing a data output operation in parallel with the write training operation in response to a read command, and performing an erase operation in parallel with the write training operation. The semiconductor device 2000 provides skew information detected when performing the write training operation WTRN to the controller 3000.

[0057] The controller 3000 generates and provides a plurality of control signals and commands to the semiconductor device 2000. The controller 3000 sends / receives data, commands, addresses, and status information to / from the semiconductor device 2000 according to a data input mode, a data output mode, a command input mode, an address input mode, a parameter setting mode, and a status information output mode. During the data input mode, the controller 3000 provides data and data strobe signals DQST, DQSC to the semiconductor device 2000. The controller 3000 adjusts timing of the data strobe signals DQST, DQSC according to skew information provided by the semiconductor device 2000 to the controller 3000.

[0058] Referring to Figure 7 and Figure 8 , detailed operations of the multi-operation function including the write training are described.

[0059] Figure 7 is a diagram illustrating detailed operations of the multi-operation function including the write training according to the present disclosure. Figure 7 An example of performing the multi-operation function including the write training according to external control such as an external command provided by the controller 3000 is illustrated.

[0060] Referring to Figure 7 When the controller 3000 provides a select chip enable command SCE to the semiconductor device 2000, the semiconductor device 2000 activates a logical unit 100, e.g., LU0, among a plurality of logical units LU0 to LUn, which is identified by the select chip enable command SCE.

[0061] When the controller 3000 provides a write command WT to the semiconductor device 2000, the semiconductor device 2000 performs a data input operation, e.g., a program operation, on the logical unit LU0 in response to receiving the write command WT.

[0062] When the controller 3000 provides the semiconductor device 2000 with a write training enable command DQS OSC EN, the semiconductor device 2000 performs a preparation operation for a write training operation on the logical unit LU0 in response to receiving the write training enable command DQS OSC EN.

[0063] When the controller 3000 provides the semiconductor device 2000 with a write training start command DQS OSC START, the semiconductor device 2000 starts performing a skew information generation operation on the logical unit LU0 in response to receiving the start command DQS OSC START.

[0064] When the controller 3000 provides the semiconductor device 2000 with a write training stop command DQS OSC STOP, the semiconductor device 2000 stops performing a skew information generation operation on the logical unit LU0 in response to receiving the write training stop command DQS OSC STOP. While performing the skew information generation operation, the semiconductor device 2000 generates and stores skew information. The skew information includes values corresponding to times at which the controller 3000 latches data provided using a multi-phase clock signal that is generated from a data strobe signal provided by the controller 3000 through internal multi-phase processing.

[0065] The controller 3000 provides the semiconductor device 2000 with a skew information get command DQS OSC GETFEATURE, and in response, the semiconductor device 2000 provides the controller 3000 with the skew information.

[0066] When the controller 3000 provides the semiconductor device 2000 with a select chip terminate command SCT, the semiconductor device 2000 terminates the multi-operation function including write training by disabling the logical unit LU0 in response to receiving the select chip terminate command SCT.

[0067] Figure 8 is a diagram illustrating an embodiment of detailed operations of a multi-operation function including write training according to the present disclosure. Figure 8 An example is illustrated in which the semiconductor device 2000 performs one or more operations of a multi-operation function including write training independently of an external controller.

[0068] Referring to Figure 8 When the controller 3000 provides the semiconductor device 2000 with a select chip enable command SCE, the semiconductor device 2000 activates a logical unit 100, e.g., LU0, of a plurality of logical units LU0 through LUn, e.g., LU0, that is identified by the select chip enable command SCE.

[0069] When the controller 3000 provides the semiconductor device 2000 with the write command WT, the semiconductor device 2000 performs a data input operation, such as a program operation, on the logical unit LU0 in response to receiving the write command WT.

[0070] When the controller 3000 provides the semiconductor device 2000 with the write training internal processing enable command DQS OSC ENi, the semiconductor device 2000 performs a preparation operation for a write training operation on the logical unit LU0 in response to receiving the internal processing enable command DQS OSC ENi, and the semiconductor device 2000 starts and stops the skew information generation operation for the logical unit LU0 independently of external control or input, such as without receiving specific instructions, commands, or timing hints from the controller 3000 about when to start and stop the skew information generation operation.

[0071] The controller 3000 provides the semiconductor device 2000 with the write training internal processing enable command DQS OSC ENi, and after a predetermined period of time, provides the semiconductor device 2000 with the skew information acquisition command DQS OSC GET FEATURE.

[0072] When the controller 3000 provides the semiconductor device 2000 with the skew information acquisition command DQS OSC GET FEATURE, the semiconductor device 2000 provides the controller 3000 with skew information in response to receiving the skew information acquisition command DQS OSC GET FEATURE.

[0073] When the controller 3000 provides the semiconductor device 2000 with the select chip termination command SCT, the semiconductor device 2000 terminates the multi-operation function including the write training by disabling the logical unit LU0 in response to receiving the select chip termination command SCT.

[0074] Figure 7 and Figure 8 An example is shown in which a write training operation and a data input operation are performed as a multi-operation function. A multi-operation function in which a data output operation is performed in accordance with a read command and a write training is performed in parallel, and a multi-operation function in which an erase operation and a write training operation are performed in parallel can be performed in a similar manner to Figure 7 and Figure 8 A multi-operation function in which a data output operation is performed in accordance with a read command and a write training is performed in parallel, and a multi-operation function in which an erase operation and a write training operation are performed in parallel can be performed in a similar manner to

[0075] Figure 9 is a diagram showing a configuration of a write training circuit 200 according to an embodiment of the present disclosure.

[0076] Referring to Figure 9 , the write training circuit 200 includes a data reception circuit 201, a strobe signal processing circuit 300, and a skew detection circuit 600. The write training circuit 200 is included inFigure 5 The input / output circuit 160 of the semiconductor memory device 100 shown is implemented in the semiconductor memory device 100, but can be implemented elsewhere in the semiconductor memory device 100.

[0077] The data receiving circuit 201 receives data and the multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB as inputs, and outputs the received data DQ<0:7>I / Q / IB / QB. The data receiving circuit 201 receives data input through the input / output pads DQ<0:7> in accordance with the multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB, thereby generating the received data DQ<0:7>I / Q / IB / QB.

[0078] The received data DQ<0:7>I / Q / IB / QB is transferred to the deserializing circuit 400. The deserializing circuit 400 deserializes the received data DQ<0:7>I / Q / IB / QB in accordance with the clock signals DQSIB, DQSQB of the multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB, and sends the received data DQ<0:7>I / Q / IB / QB to the page buffer 500.

[0079] The strobe signal processing circuit 300 receives the data strobe signals DQST, DQSC as inputs, and outputs the multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB. The strobe signal processing circuit 300 frequency-divides the data strobe signals DQST, DQSC, and delays the result by a predetermined period of time, to generate the multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB. The time from when the data strobe signals DQST, DQSC are input to the strobe signal processing circuit 300 to when the strobe signal processing circuit 300 generates or outputs the multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB is referred to as the first signal processing delay time tDQS2DQ.

[0080] The configuration of the skew detection circuit 600 is similar to that of the strobe signal processing circuit 300, and the skew detection circuit 600 generates a replica clock signal DQSOSC corresponding to any one of the multi-phase clock signals DQSI, DQSQ, DQSI B, DQSQB, and generates skew information CD<0:n> based on the replica clock signal DQSOSC. The skew detection circuit 600 selectively performs operations including generating the skew information CD<0:n> based on external control or internal control (independent of external control) in accordance with whether a write training internal processing enable command DQS OSC ENi is input or activated. The skew information CD<0:n> is stored in the register 700 and transmitted to a controller outside the semiconductor memory device, for example, through one of the input / output pads DQ<0:7> by the transmitter TX 800. to a controller or device outside the semiconductor memory device or the semiconductor device.

[0081] The skew detection circuit 600 includes a strobe signal replica circuit 610, a counter 630, and a timing control circuit 650.

[0082] The configuration of the strobe signal replica circuit 610 is similar to that of the circuit configuration of the strobe signal processing circuit 300. The strobe signal replica circuit 610 generates the replica clock signal DQSOSC during a period in which the oscillation enable signal EN-OSC is active. The time between the strobe signal replica circuit 610 starting the oscillation operation and generating the replica clock signal DQSOSC is referred to as a second signal processing delay time 2*tDQS2DQ. The second signal processing delay time 2*tDQS2DQ is twice the first signal processing delay time tDQS2DQ. Setting the second signal processing delay time 2*tDQS2DQ to be twice the first signal processing delay time tDQS2DQ is merely an example provided for ease of generating the skew information CD<0:n>, although the second signal processing delay time can be the same as the first signal processing delay time tDQS2DQ or can be set to an integer multiple of the first signal processing delay time tDQS2DQ.

[0083] The counter 630 generates the skew information CD<0:n> by counting edges of the replica clock signal DQSOSC during a period in which the oscillation enable signal EN-OSC is active, for example, at a logic high level. For example, counting edges of the replica clock signal DQSOSC includes counting rising edges of the replica clock signal DQSOSC, counting falling edges of the replica clock signal DQSOSC, or counting both rising and falling edges of the replica clock signal DQSOSC.

[0084] The timing control circuit 650 generates the oscillation enable signal EN-OSC in response to a plurality of timing control signals, for example, as described with respect to the timing control circuit 350. Figure 13The.

[0085] The controller 3000 sends data to the semiconductor device in accordance with rising and falling edges of each of the data strobe signals DQST, DQSC. Accordingly, at least one semiconductor memory device or logic unit 100 of the semiconductor device 2000 utilizes the data strobe signal processing circuit 300 to frequency-divide and delay the data strobe signals DQST, DQSC to generate multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB corresponding to the rising and falling edges of each of the data strobe signals DQST, DQSC. The data receiving circuit 201 receives data in accordance with the multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB to generate the received data DQ<0:7>I / Q / IB / QB.

[0086] The first signal processing delay time tDQS2DQ is a value set for optimizing data sampling timing and varies with changes in voltage and / or temperature. When the first signal processing delay time tDQS2DQ varies, skew between the data and the multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB occurs and data can not be properly received. Skew information CD<0:n> generated by the skew detection circuit 600 in response to a change in the first signal processing delay time tDQS2DQ is sent to the controller 3000, which in turn performs a write training operation during which the controller 3000 adjusts the timing of the data strobe signals DQST, DQSC in accordance with the skew information CD<0:n> provided to the controller 3000 by the semiconductor device 2000.

[0087] Figure 10 is a diagram showing, for example, Figure 9 A diagram showing the configuration of the data receiving circuit 201 shown in FIG. 2.

[0088] Referring to Figure 10 , the data receiving circuit 201 includes a plurality of data receiving units 210, 220, 230, 240, 250, 260, 270, and 280. The plurality of data receiving units 210 to 280 are connected one-to-one with different ones of the input / output pads DQ<0:7>.

[0089] The first data receiving unit 210 outputs a first received data subset DQ<0>I / Q / IB / QB of the received data DQ<0:7>I / Q / IB / QB by comparing data input through the input / output pad DQ<0> with a reference voltage VREF in timing corresponding to each of the multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB.

[0090] The second data receiving unit 220 outputs a second subset of received data DQ<1> I / Q / IB / QB of the received data DQ<0:7> I / Q / IB / QB by comparing data input through the input / output pad DQ<1> to the reference voltage VREF in a timing corresponding to each of the multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB.

[0091] The third data receiving unit 230 outputs a third subset of received data DQ<2> I / Q / IB / QB of the received data DQ<0:7> I / Q / IB / QB by comparing data input through the input / output pad DQ<2> to the reference voltage VREF in a timing corresponding to each of the multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB.

[0092] The fourth data receiving unit 240 outputs a fourth subset of received data DQ<3> I / Q / IB / QB of the received data DQ<0:7> I / Q / IB / QB by comparing data input through the input / output pad DQ<3> to the reference voltage VREF in a timing corresponding to each of the multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB.

[0093] The fifth data receiving unit 250 outputs a fifth subset of received data DQ<4> I / Q / IB / QB of the received data DQ<0:7> I / Q / IB / QB by comparing data input through the input / output pad DQ<4> to the reference voltage VREF in a timing corresponding to each of the multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB.

[0094] The sixth data receiving unit 260 outputs a sixth subset of received data DQ<5> I / Q / IB / QB of the received data DQ<0:7> I / Q / IB / QB by comparing data input through the input / output pad DQ<5> to the reference voltage VREF in a timing corresponding to each of the multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB.

[0095] The seventh data receiving unit 270 outputs a seventh subset of received data DQ<6> I / Q / IB / QB of the received data DQ<0:7> I / Q / IB / QB by comparing data input through the input / output pad DQ<6> to the reference voltage VREF in a timing corresponding to each of the multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB.

[0096] The eighth data receiving unit 280 outputs an eighth received data subset DQ<7>I / Q / IB / QB among the received data DQ<0:7>I / Q / IB / QB by comparing the data input through the input / output pad DQ<7> with the reference voltage VREF in a timing corresponding to each of the multi-phase clock signals DQSI, DQSQ, DQSIB, DQSQB.

[0097] Since the receiving units 210 to 280 are configured similarly to each other, only the configuration of the first data receiving unit 210 is shown, and the configuration of the first data receiving unit 210 is described only for simplicity.

[0098] The first data receiving unit 210 includes a plurality of comparators 211 to 214. Each of the plurality of comparators 211 to 214 includes a first input terminal (+) common to the input / output pad DQ<0> and a second input terminal (-) which commonly receives the reference voltage VREF.

[0099] The first comparator 211 compares the data input through the input / output pad DQ<0> with the reference voltage VREF in a time period in which the first phase clock signal DQSI is at a logic high level, and outputs the result as first received data DQ<0>I among the received data DQ<0:7>I / Q / IB / QB.

[0100] The second comparator 212 compares the data input through the input / output pad DQ<0> with the reference voltage VREF in a time period in which the second phase clock signal DQSQ is at a logic high level, and outputs the result as second received data DQ<0>Q among the received data DQ<0:7>I / Q / IB / QB.

[0101] The third comparator 213 compares the data input through the input / output pad DQ<0> with the reference voltage VREF in a time period in which the third phase clock signal DQSIB is at a logic high level, and outputs the result as third received data DQ<0>IB among the received data DQ<0:7>I / Q / IB / QB.

[0102] The fourth comparator 214 compares the data input through the input / output pad DQ<0> with the reference voltage VREF in a time period in which the fourth phase clock signal DQSQB is at a logic high level, and outputs the result as fourth received data DQ<0>QB among the received data DQ<0:7>I / Q / IB / QB.

[0103] Figure 11 is a diagram showing, for example, Figure 9 A diagram showing the configuration of the strobe signal processing circuit 300 shown in FIG. 3.

[0104] Referring to Figure 11 The strobe signal processing circuit 300 includes amplification circuits (also referred to as amplifiers) 301 to 305, inverters 306, 307, frequency division circuits (FD) 308, 309, and delay circuits (DLY) 310 to 313.

[0105] The first amplification circuit 301, the second amplification circuit 302, and the third amplification circuit 303 amplify a difference between the data strobe signal DQST and the data strobe signal DQSC and output an amplified signal. The fourth amplification circuit 304 receives differential output signals from the third amplification circuit 303 through opposite-phase input terminals and amplifies a difference between the received differential output signals. The fifth amplification circuit 305 receives differential output signals from the third amplification circuit 303 through similar-phase input terminals and amplifies a difference between the received differential output signals.

[0106] The first inverter 306 inverts an output of the fourth amplification circuit 304 and outputs an inverted output of the fourth amplification circuit 304. The second inverter 307 inverts an output of the fifth amplification circuit 305 and outputs an inverted output of the fifth amplification circuit 305.

[0107] The first frequency division circuit 308 frequency-divides and phase-separates the output of the first inverter 306 at a predetermined frequency division ratio (e.g., 1 / 2). The second frequency division circuit 309 frequency-divides and phase-separates the output of the second inverter 307 at a predetermined frequency division ratio (e.g., 1 / 2).

[0108] The first delay circuit 310 outputs a signal that delays a first output signal of the first frequency division circuit 308 by a first predetermined time period as a first phase clock signal DQSI. The second delay circuit 311 outputs a signal that delays a second output signal of the first frequency division circuit 308 by a second predetermined time period as a second phase clock signal DQSQ. The third delay circuit 312 outputs a signal that delays a first output signal of the second frequency division circuit 309 by a third predetermined time period as a third phase clock signal DQSIB. The fourth delay circuit 313 outputs a signal that delays a second output signal of the second frequency division circuit 309 by a fourth predetermined time period as a fourth phase clock signal DQSQB. The first predetermined time period, the second predetermined time period, the third predetermined time period, and the fourth predetermined time period can all be equal to the same time period, or can be time periods having different values.

[0109] Figure 12 is a diagram showing a configuration of the strobe signal replication circuit 610 shown in FIG. 6. Figure 9 Referring to

[0110] The configuration of the strobe signal replication circuit 610 is such that the first amplification circuit 301, the second amplification circuit 302, and the third amplification circuit 303 amplify a difference between the data strobe signal DQST and the data strobe signal DQSC and output an amplified signal, as described above with reference to FIG. 3. Figure 12 Figure 9 ​The selection signal processing circuit 300 is configured similarly to the circuit of the selection signal processing circuit 200, and includes a circuit configuration that generates a replica clock signal DQSOSC corresponding to any one of the multi-phase clock signals DQSI, DQSQ, DQSIB, and DQSQB (e.g., the first phase clock signal DQSI). The selection signal replica circuit 610 includes logic gates 611 to 616 and 618 to 620 corresponding to the amplification circuits 301 to 305, the first inverter 306, the first frequency division circuit 308, and the first delay circuit 310 of the selection signal processing circuit 300. The logic gates 615, 619 are configured to match the load of the selection signal replica circuit 610 to the load of the selection signal processing circuit 300. Figure 11 The selection signal processing circuit 300 is configured similarly to the circuit of the selection signal processing circuit 200, and includes a circuit configuration that generates a replica clock signal DQSOSC corresponding to any one of the multi-phase clock signals DQSI, DQSQ, DQSIB, and DQSQB (e.g., the first phase clock signal DQSI). The selection signal replica circuit 610 includes logic gates 611 to 616 and 618 to 620 corresponding to the amplification circuits 301 to 305, the first inverter 306, the first frequency division circuit 308, and the first delay circuit 310 of the selection signal processing circuit 300. The logic gates 615, 619 are configured to match the load of the selection signal replica circuit 610 to the load of the selection signal processing circuit 300.

[0111] The selection signal replica circuit 610 initiates the generation of the replica clock signal DQSOSC in response to activation (e.g., enabled at a logic high level) of the oscillation enable signal EN-OSC, and performs an oscillation operation to generate the replica clock signal DQSOSC. The replica clock signal DQSOSC is fed back as an input to the logic gate 611. The time between the replica clock signal DQSOSC input to the logic gate 611 and the processed signal output from the logic gate 620 is 2*tDQS2DQ, as described with respect to Figure 9

[0112] Figure 13 is a diagram illustrating a configuration of the timing control circuit 650, as shown in Figure 9

[0113] Referring to Figure 13 , the timing control circuit 650 generates the oscillation enable signal EN-OSC in response to the plurality of timing control signals CMDi-DQS OSC ENi, CMDi-DQS OSC START, and CMDi-DQS OSC STOP. The timing control circuit 650 includes a counter 651, a plurality of logic gates 652 to 655, and a multiplexing circuit 656.

[0114] The counter 651 generates the count signal CNT<0:i> by counting edges of the internal clock signal CLKi during a time period in which the first timing control signal CMDi-DQS OSC ENi is active at a logic high level. For example, counting edges of the internal clock signal CLKi includes counting rising edges of the internal clock signal CLKi, counting falling edges of the internal clock signal CLKi, or counting both rising and falling edges of the internal clock signal CLKi. The counter 651 generates a plurality of count signals CNT<0:i>, where the number of edges of the internal clock signal CLKi counted is represented by bits 0 to i, where i is a positive integer, and outputs a count signal CNT<0:i> for one bit i. ​​Each bit of the edge number corresponds to one of the plurality of count signals, for example, the most significant bit. The counter 651 initializes each of the plurality of count signals to a logic low level when the first timing control signal CMDi-DQS OSC ENi is activated, for example, when the first timing control signal CMDi-DQS OSC ENi transitions to a logic high level. The counter 651 is enabled by the first timing control signal CMDi-DQS OSC ENi.

[0115] The internal clock signal CLKi is provided by a phase-locked loop circuit PLL 900.

[0116] The first logic gate 652 and the second logic gate 653 output a result of a logic AND operation of the second timing control signal CMDi-DQS OSC START and the inverted third timing control signal CMDi-DQS OSC STOP of the plurality of timing control signals.

[0117] The third logic gate 654 and the fourth logic gate 655 output a result of a logic AND operation of the first timing control signal CMDi-DQS OSC ENi and the inverted count signal .

[0118] The multiplexing circuit 656 selects and outputs one of the output of the second logic gate 653 and the output of the fourth logic gate 655 as the oscillation enable signal EN-OSC according to a logic level of the first timing control signal CMDi-DQS OSC ENi. When the first timing control signal CMDi-DQS OSC ENi is at a logic low level, the multiplexing circuit 656 outputs the output of the second logic gate 653 as the oscillation enable signal EN-OSC, and when the first timing control signal CMDi-DQS OSC ENi is at a logic high level, the multiplexing circuit 656 outputs the output of the fourth logic gate 655 as the oscillation enable signal EN-OSC.

[0119] The first timing control signal CMDi-DQS OSC ENi, the second timing control signal CMDi-DQS OSC START, and the third timing control signal CMDi-DQS OSC STOP are generated by decoding commands, for example, external commands received from an external source such as the controller 3000. The first timing control signal CMDi-DQS OSC ENi is generated by decoding a write training internal process enable command DQS OSC ENi, the second timing control signal CMDi-DQS OSC START is generated by decoding a write training start command DQS OSC START, and the third timing control signal CMDi-DQS OSC STOP is generated by decoding a write training stop command DQS OSC STOP.

[0120] When a multi-operation function including write training is executed under the control of the controller 3000 (see Figure 7 ), the first timing control signal CMDi-DQS OSC ENi remains at a logic low level because no write training internal process enable command DQS OSC ENi is currently input.

[0121] Since the first timing control signal CMDi-DQS OSC ENi is at a logic low level, the counter 651 is disabled or not operated, and the multiplexing circuit 656 outputs the output of the second logic gate 653 as the oscillation enable signal EN-OSC. When the first timing control signal CMDi-DQS OSC ENi is at a logic low level, the timing control circuit 650 controls the generation of the skew information CD<0:n> by the strobe signal copying circuit 610 in response to commands received and supplied from the controller 3000, for example, the write training start command DQS OSC START and the write training stop command DQS OSC STOP.

[0122] When a subset of operations of a multi-operation function including write training is executed by the semiconductor device 2000 independently of external control by the controller 3000 (see Figure 8 ), the first timing control signal CMDi-DQS OSC ENi is at a logic high level when the write training internal process enable command DQS OSC ENi is input or enabled.

[0123] Since the first timing control signal CMDi-DQSOSENi is at a logic high level, the counter 651 is enabled, and the multiplexing circuit 656 outputs the output of the fourth logic gate 655 as the oscillation enable signal EN-OSC. The timing control circuit 650 independently processes the operation including the generation of the skew information CD<0:n> by controlling the strobe signal copying circuit 610. When the semiconductor memory device 100 or the semiconductor device 2000 independently performs a subset of operations of a multi-operation function from external control such as by the controller 3000, the external control load associated with controlling the semiconductor memory device 100 or the semiconductor device 2000 can be reduced, and the operation timing margin of the controller 3000 can be increased.

[0124] Those skilled in the art to which the disclosure pertains should understand that various modifications, additions and substitutions can be made to the disclosure without departing from the scope and technical concept of the disclosure. The above-described embodiments are illustrative, not restrictive. Therefore, the scope of the disclosure is not limited to the above description. All changes within the meaning and range of equivalency of the claims are intended to be embraced therein.

Claims

1. A write training circuit comprising: data receiving circuitry that receives a data input according to a plurality of multi-phase clock signals to generate received data; strobe signal processing circuitry that generates the plurality of multi-phase clock signals by dividing a data strobe signal into a divided signal and delaying the divided signal by a predetermined time period; and skew detection circuitry that generates a replica clock signal corresponding to one of the plurality of multi-phase clock signals and generates skew information according to the replica clock signal; wherein the skew detection circuitry generates the skew information under external control or independently of external control according to which of a plurality of external commands is received.

2. The write training circuit of claim 1, wherein the skew detection circuitry outputs the skew information to an external device in response to external control.

3. The write training circuit of claim 1, wherein the skew detection circuitry comprises: strobe signal replica circuitry configured similarly to the strobe signal processing circuitry and that generates the replica clock signal for a time period in which an oscillation enable signal is active; a counter that generates the skew information by counting edges of the replica clock signal for the time period in which the oscillation enable signal is active; and timing control circuitry that generates the oscillation enable signal in response to a plurality of timing control signals.

4. The write training circuit of claim 3, wherein the plurality of timing control signals are generated by decoding the plurality of external commands.

5. The write training circuit of claim 1, further comprising deserializing circuitry that deserializes the received data according to at least one of the plurality of multi-phase clock signals.

6. A semiconductor device comprising: a semiconductor memory device that performs a normal operation when a command to perform the normal operation is received and that performs a write training operation for a time period in which the normal operation is performed; wherein the write training operation includes internal multi-phase processing of a data strobe signal provided from an external device to determine a time to latch data provided from the external device.

7. The semiconductor device of claim 6, wherein the normal operation includes at least one of a data input operation, a data output operation, and an erase operation.

8. The semiconductor device of claim 6, wherein the write training operation is performed under external control or independently of external control according to which of a plurality of external commands is received.

9. The semiconductor device of claim 6, wherein the semiconductor device further: performs a preparation operation for the write training operation for a corresponding logic unit when a write training enable command is received from the external device; enables generation of skew information when a write training start command is received from the external device; disables generation of the skew information when a write training stop command is received from the external device; and provides the skew information to the external device when a skew information acquisition command is received from the external device.

10. The semiconductor device of claim 6, wherein ​ When a write training enable command is received from the external device, the semiconductor memory device performs a preparation operation of the write training operation for a corresponding logical unit, and starts and stops a skew information generation operation independently of external control for a predetermined period of time.

11. The semiconductor device according to claim 6, further comprising: data receiving circuitry that receives data input according to a plurality of multi-phase clock signals to generate received data; strobe signal processing circuitry that generates the plurality of multi-phase clock signals by dividing a data strobe signal into a divided signal and delaying the divided signal by a predetermined period of time; and skew detection circuitry that generates a replica clock signal corresponding to one of the plurality of multi-phase clock signals according to one of a plurality of external commands, and generates skew information according to the replica clock signal.

12. The semiconductor device according to claim 11, wherein the skew detection circuitry includes: strobe signal replica circuitry that is configured similarly to the strobe signal processing circuitry, and generates the replica clock signal for a period of time in which an oscillation enable signal is active; a counter that generates the skew information by counting edges of the replica clock signal for the period of time in which the oscillation enable signal is active; and timing control circuitry that generates the oscillation enable signal in response to a plurality of timing control signals.

13. The semiconductor device according to claim 12, wherein the plurality of timing control signals are generated by decoding the plurality of external commands.

14. The semiconductor device according to claim 11, further comprising deserializing circuitry that deserializes the received data according to at least one of the plurality of multi-phase clock signals.

15. A data processing system comprising: a semiconductor memory device that performs a write training operation including determining a time of latching data according to a plurality of multi-phase clock signals that are internally generated based on a data strobe signal for a period of time in which a normal operation is performed and outputting the time as skew information, and performing the write training operation under external control when a write training enable command is received; and performing the write training operation independently of external control when a write training internal processing enable command is received; and a controller that provides a plurality of commands including the write training enable command and the write training internal processing enable command, the data, and the data strobe signal to the semiconductor memory device, and adjusts timing of the data strobe signal according to the skew information.

16. The data processing system according to claim 15, wherein the normal operation includes at least one of a data input operation, a data output operation, and an erase operation.

17. The data processing system according to claim 15, wherein the semiconductor memory device further: performs a preparation operation of the write training operation for a corresponding logical unit when the write training enable command is received; starts the operation of generating the skew information when a write training start command is received from the controller; when a write training stop command is received from the controller, stopping the operation of generating the skew information; and when a skew information acquisition command is received from the controller, providing the skew information to the controller.

18. The data processing system of claim 15, wherein, the semiconductor memory device: when the write training enable command is received from the controller, performing a preparation operation of the write training operation for a corresponding logical unit; and independently of the control of the controller, starting and stopping the generation of the skew information within a predetermined period of time.

19. The data processing system of claim 15, wherein, the semiconductor memory device includes: data reception circuitry that receives data input according to the plurality of multi-phase clock signals to generate reception data; strobe signal processing circuitry that generates the plurality of multi-phase clock signals by dividing the data strobe signal into a divided signal and delaying the divided signal by a predetermined period of time; and skew detection circuitry that generates a replica clock signal corresponding to one of the plurality of multi-phase clock signals according to the write training internal processing enable command, and generates the skew information according to the replica clock signal.

20. The data processing system according to claim 19, wherein: the skew detection circuitry includes: strobe signal replica circuitry that is configured similarly to the strobe signal processing circuitry, and generates the replica clock signal within a period of time in which an oscillation enable signal is active; a counter that generates the skew information by counting edges of the replica clock signal within the period of time in which the oscillation enable signal is active; and timing control circuitry that generates the oscillation enable signal in response to a plurality of timing control signals generated by decoding the plurality of commands.

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