Memory device and method for applying pass voltage

Abstract

The present technology relates to a memory device and a method for applying a pass voltage. A memory device according to the present technology may include: a memory cell array including memory cells connected by a plurality of word lines; a peripheral circuit configured to apply a pass voltage to the plurality of word lines in a period in which the program operation is performed, and configured to apply a program voltage to a selected word line selected from among the plurality of word lines after applying the pass voltage to the plurality of word lines, where the pass voltage includes a first pass voltage and a second pass voltage; and a control logic configured to control the peripheral circuit so as to apply the second pass voltage to the selected word line and apply the first pass voltage to an unselected word line that is not selected among the plurality of word lines.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0052115 filed on April 18, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a memory device, and more particularly, to a memory device and method for applying a pass voltage during a program operation. Background Art

[0004] Memory devices are classified into volatile memory devices and non-volatile memory devices. Volatile memory devices store data only when power is supplied, and the stored data is destroyed when power is cut off. Non-volatile memory devices are memory devices in which data is not destroyed even when power is cut off.

[0005] A memory device may perform a programming operation by applying a program voltage via a word line connected to a memory cell. The memory device may apply a pass voltage to a word line before applying the program voltage to a selected word line. As the difference between the program voltage and the pass voltage increases, the time required to increase the program voltage increases, and the efficiency of the programming operation may decrease. Summary of the Invention

[0006] According to an embodiment of the present disclosure, a memory device may include: a memory cell array including memory cells, which are connected through multiple word lines; a peripheral circuit configured to apply a pass voltage to the multiple word lines during a period of performing a programming operation, and after applying the pass voltage to the multiple word lines, configured to apply a programming voltage to a selection word line selected from the multiple word lines, wherein the pass voltage includes a first pass voltage and a second pass voltage, and wherein the second pass voltage is higher than the first pass voltage; and control logic configured to control the peripheral circuit during a pass voltage increase period of applying the pass voltage so as to apply the second pass voltage to the selection word line and apply the first pass voltage to an unselected word line, which is a word line that is not selected from the multiple word lines.

[0007] According to an embodiment of the disclosure, a memory device can include: a first pass voltage regulator configured to generate a first pass voltage in a period in which a program operation is performed, the first pass voltage being applied to an unselected word line among a plurality of word lines connected to a memory cell; a second pass voltage regulator configured to generate a second pass voltage, the second pass voltage being higher than the first pass voltage, the second pass voltage being applied to a selected word line among the plurality of word lines; a program voltage regulator configured to generate a program voltage, the program voltage being applied to the selected word line after the second pass voltage is applied to the selected word line; a switch circuit connecting the first pass voltage regulator, the second pass voltage regulator, and the program voltage regulator to the plurality of word lines, respectively; and control logic configured to control the switch circuit so as to apply the first pass voltage to the unselected word line and to apply the second pass voltage to the selected word line during a pass voltage increase period in which a pass voltage applied to the plurality of word lines is increased.

[0008] According to an embodiment of the disclosure, a method of operating a memory device can include: generating a pass voltage applied to a plurality of word lines connected to a memory cell while a program operation is performed, wherein the pass voltage includes a first pass voltage and a second pass voltage, and wherein the second pass voltage is higher than the first pass voltage; applying the second pass voltage to a selected word line selected from among the plurality of word lines during a pass voltage increase period in which a pass voltage applied to the plurality of word lines is increased; and applying a program voltage to the selected word line after the pass voltage increase period. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a diagram illustrating a memory device according to an embodiment of the disclosure.

[0010] Figure 2 is a diagram illustrating a connection between a voltage regulator and a word line according to an embodiment of the disclosure.

[0011] Figure 3 is a diagram illustrating a word line voltage changed according to an operation of a switch of Figure 2

[0012] Figure 4 is a diagram illustrating a selected word line voltage corresponding to a pass voltage application according to an embodiment of the disclosure.

[0013] Figure 5 is a diagram illustrating Figure 1 a difference in program speed between memory cells included in a memory cell array of

[0014] Figure 6 is a diagram illustrating an increase speed of a program voltage corresponding to a pass voltage application according to an embodiment of the disclosure. ​

[0015] Figure 7 is a flowchart illustrating a method of applying a pass voltage and a program voltage according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0016] Only specific structures or functional descriptions of embodiments according to the concepts disclosed in the specification or application are shown to describe the embodiments of the concepts according to the disclosure. Embodiments of the concepts according to the disclosure can be implemented in various forms and should not be understood as being limited to the embodiments described in the specification or application.

[0017] Embodiments of the disclosure provide a memory device and a method of applying a pass voltage, which improve performance of a program operation by applying only an increased pass voltage to a selected word line during a program operation.

[0018] Figure 1 is a diagram illustrating a memory device according to an embodiment of the disclosure.

[0019] REFERENCE Figure 1 The memory device 100 can store data. The memory device 100 can include a memory cell array 110 having memory cells that store data, an address decoder 120 that decodes a column address, an input / output circuit 130 that transmits and receives data to and from an external device outside the memory device 100, control logic 140, and a voltage generator 150 that generates a plurality of voltages having various voltage levels.

[0020] Each of the memory cells included in the memory cell array 110 can be a single-layer cell (SLC) that stores 1-bit data or a memory cell that stores multi-bit data. The memory cell that stores multi-bit data can be a multi-layer cell (MLC) that stores 2-bit data, a triple-layer cell (TLC) that stores 3-bit data, or a quad-layer cell (QLC) that stores 4-bit data according to the number of bits of the multi-bit data.

[0021] The address decoder 120 can be connected to the memory cell array 110 through a word line. The address decoder 120 can select a word line by decoding an address received from the input / output circuit 130. The address decoder 120 can apply a voltage received from the voltage generator 150 to the selected word line. The address decoder 120 can operate in response to a control signal received from the control logic 140.

[0022] The input / output circuit 130 can include a page buffer that reads data stored in the memory cells and temporarily stores the data. The input / output circuit 130 can output the data stored in the page buffer to an external device outside the memory device 100, or can store data received from the external device in the page buffer and then store the data in the memory cells.

[0023] The control logic 140 can control overall operations of the memory device 100. The control logic 140 can generate a control signal that controls the address decoder 120, the input / output circuit 130, and the voltage generator 150 to perform a read operation, a program operation, and an erase operation on the memory cell array 110.

[0024] The voltage generator 150 can generate voltages required for operations of the memory device 100. The voltage generator 150 can include voltage regulators that generate voltages having various potentials. The voltage generator 150 can generate a program voltage, a verify voltage, and a read voltage required for the memory device 100. The voltages generated by the voltage generator 150 can be supplied to the memory cells included in the memory cell array 110 through the address decoder 120.

[0025] In an embodiment of the disclosure, the address decoder 120, the input / output circuit 130, and the voltage generator 150 can be referred to as a peripheral circuit 160. The control logic 140 can control the peripheral circuit 160 in order to perform operations on the memory cells included in the memory cell array 110.

[0026] In an embodiment of the disclosure, the voltage generator 150 can generate a pass voltage that is applied to a word line before a program voltage is applied to a selected word line. The potentials of the pass voltages generated by the voltage regulators included in the voltage generator 150 can be different from each other.

[0027] The address decoder 120 can include a switching circuit that connects the voltage regulators included in the voltage generator 150 to the word lines, respectively. Through a switching operation, a selected word line and an unselected word line can be connected to different voltage regulators.

[0028] The control logic 140 can control the peripheral circuit 160 in order to apply a pass voltage to the word lines before a program voltage is applied to a selected word line from among the word lines. A period in which the pass voltage is applied can be referred to as a pass voltage increase period. The control logic 140 can control the peripheral circuit 160 in order to apply a pass voltage higher than a pass voltage applied to an unselected word line to a selected word line during the pass voltage increase period.

[0029] Figure 2is a diagram illustrating a connection between a voltage regulator and a word line according to an embodiment of the disclosure.

[0030] Referring to Figure 2 The memory cell array 110 can be connected to the address decoder 120 through a plurality of word lines. The address decoder 120 can receive a voltage from the voltage generator 150, and can transmit the received voltage to the memory cells of the memory cell array 110 through the plurality of word lines.

[0031] For convenience of description, it can be assumed that a selected word line among the plurality of word lines is an Nth word line WLn. Figure 2 The (N-1)th word line WLn-1 shown in FIG. 1 can represent an unselected word line, which is a word line that is not selected among the plurality of word lines.

[0032] The address decoder 120 can include a switching circuit connecting the voltage regulators included in the voltage generator 150 to the word lines, respectively. In Figure 2 In FIG. 1, as an example, a first switching circuit 121 connected to the selected word line and a second switching circuit 122 connected to the unselected word line are illustrated. The first switching circuit 121 can include a first switch SW1, a second switch SW2, and a third switch SW3. Similarly, the second switching circuit 122 can include a fourth switch SW4, a fifth switch SW5, and a sixth switch SW6. The address decoder 120 can change the states (on / off) of the first switch SW1, the second switch SW2, the third switch SW3, the fourth switch SW4, the fifth switch SW5, and the sixth switch SW6 based on a control signal received from the control logic 140.

[0033] The voltage generator 150 can include a program voltage regulator 151, a first pass voltage regulator 152, and a second pass voltage regulator 153. The program voltage regulator 151 can generate a program voltage applied to the selected word line. The first pass voltage regulator 152 can generate a first pass voltage applied to the unselected word line. The second pass voltage regulator 153 can generate a second pass voltage higher than the first pass voltage. In an embodiment of the disclosure, the second pass voltage can be applied to the selected word line before the program voltage is applied to the selected word line.

[0034] The first switch circuit 121 can select one of the programming voltage regulator 151, the first pass voltage regulator 152, and the second pass voltage regulator 153, and can connect the selected regulator to the selected word line. For example, when the first switch SW1 is turned on, the second switch SW2 and the third switch SW3 can be turned off, such that the programming voltage regulator 151 and the selected word line are connected. In this case, the programming voltage generated by the programming voltage regulator 151 can be applied to the selected word line. Similarly, when only the third switch SW3 is turned on, the second pass voltage can be applied to the selected word line. When the selected word line and the first switch circuit 121 are connected, the second switch SW2 can remain in an off state.

[0035] The second switch circuit 122 can select one of the programming voltage regulator 151, the first pass voltage regulator 152, and the second pass voltage regulator 153, and can connect the selected regulator to the unselected word line. When the unselected word line and the second switch circuit 122 are connected, the fourth switch SW4 and the sixth switch SW6 can remain in an off state, and only the fifth switch SW5 can be turned on.

[0036] Figure 2 The structures of the illustrated first switch circuit 121 and second switch circuit 122 are merely examples, and the structures of the switch circuits can vary. When the selected word line to which the programming voltage is applied is changed from the Nth word line WLn to another word line, the first switch circuit 121 and the second switch circuit 122 can select another voltage regulator, and can connect the selected voltage regulator to the word line.

[0037] Figure 3 is a graph showing a word line voltage that is changed according to the operation of a switch according to Figure 2

[0038] Referring to Figure 3 , according to the operations of the first switch SW1, the second switch SW2, the third switch SW3, the fourth switch SW4, the fifth switch SW5, and the sixth switch SW6, the selected word line voltage 310 and the unselected word line voltage 320 are shown. From a time point t0, a pass voltage can be applied to the word line, and from a time point t1, a programming voltage can be applied to the selected word line.

[0039] ​The pass voltage increase period P1 can be a period between t0 and t1, and the program voltage application period P2 can be a period between t1 and t2. At t0, the second switch SW2 and the sixth switch SW6 can be turned on, and the first switch SW1, the third switch SW3, the fourth switch SW4, and the fifth switch SW5 can remain in an off state. During the pass voltage increase period P1, the first pass voltage Vpass1 can be applied to unselected word lines, and the second pass voltage Vpass2 can be applied to a selected word line. During the pass voltage increase period P1, the selected word line voltage 310 can reach the second pass voltage Vpass2, and the unselected word line voltage 320 can reach the first pass voltage Vpass1.

[0040] At t1, the first switch SW1 can be turned on, and the second switch SW2 can be turned off. The third switch SW3, the fourth switch SW4, and the fifth switch SW5 can remain in an off state, and the sixth switch SW6 can remain in an on state. During the program voltage application period P2, the program voltage Vp can be applied to the selected word line, and the first pass voltage Vpass1 can be maintained in the unselected word lines. The program voltage application period P2 can include an increase period of the selected word line voltage 310. The selected word line voltage 310 can reach the program voltage Vp.

[0041] In an embodiment of the disclosure, during the pass voltage increase period P1, the second pass voltage Vpass2 higher than the first pass voltage Vpass1 can be applied to the selected word line before the program voltage Vp is applied to the selected word line. Because the selected word line voltage 310 increases to the second pass voltage Vpass2 due to the application of the second pass voltage Vpass2, the time for the selected word line voltage 310 to increase to the program voltage Vp in the program voltage application period P2 can be reduced.

[0042] In an embodiment of the disclosure, the control logic can generate a first control signal for applying a pass voltage to a corresponding word line during the pass voltage increase period P1. In response to the first control signal, the second switch SW2 and the sixth switch SW6 can be turned on, and the remaining switches SW1, SW3, SW4, and SW5 can remain in an off state. The selected word line can be connected to the second pass voltage regulator 153, and the unselected word line can be connected to the first pass voltage regulator 152.

[0043] The control logic can generate a second control signal for applying the program voltage Vp to the selected word line during a program voltage application period P2 after the pass voltage increase period P1. In response to the second control signal, the first switch SW1 can be turned on, the second switch SW2 can be turned off, the third switch SW3, the fourth switch SW4, and the fifth switch SW5 can remain in an off state, and the sixth switch SW6 can remain in an on state. The program voltage regulator 151 can be connected to the selected word line and can release the connection of the second pass voltage regulator 153 connected during the pass voltage increase period P1. The connection between the unselected word line and the first pass voltage regulator 152 can be maintained.

[0044] Figure 4 is a graph illustrating a voltage of a selected word line corresponding to a pass voltage application according to an embodiment of the disclosure.

[0045] Referring to Figure 4 , a comparison between a voltage 410 and a voltage 420 of a selected word line is illustrated. Specifically, according to an embodiment of the disclosure, the voltage 410 can represent a change in the voltage of the selected word line when the initial pass voltage is the second pass voltage Vpass2, and the voltage 420 can represent a change in the voltage of the selected word line when the initial pass voltage is the first pass voltage Vpass1. In Figure 4 the description, portions corresponding to Figure 3 described can be omitted.

[0046] At t1, during a pass voltage increase period P1 corresponding to Figure 3 , the voltage 410 of the selected word line can be higher than the voltage 420 of the selected word line. In an embodiment of the disclosure, 410 can differ from 420 by up to 5 V.

[0047] When the program voltage Vp is applied at t1, the time at which the voltage of the selected word line reaches the program voltage Vp can be different for 410 and 420 due to the different initial voltage levels of Vpass1 and Vpass2. In Figure 4 , a first period T1 can represent the time required for the voltage 410 of the selected word line to reach the program voltage Vp, and a second period T2 can represent the time required for the voltage 420 of the selected word line to reach the program voltage Vp. The first period T1 and the second period T2 can represent an increase period in which the voltage of the selected word line increases after the program voltage Vp is applied.

[0048] In Figure 4In the middle, since the difference between the programming voltage Vp at t1 and 410 is smaller than the difference between the programming voltage Vp at t1 and 420, the first period T1 can be shorter than the second period T2. According to an embodiment of the disclosure, since the voltage increase period of the selected word line is shorter for 410, the time required for programming can be shorter than when the first pass voltage Vpass1 is applied to the selected word line. The efficiency of the programming operation can be improved by applying the second pass voltage Vpass2 before applying the programming voltage Vp.

[0049] Figure 5 is a graph illustrating a difference in programming speed of memory cells included in a memory cell array of Figure 1 .

[0050] Referring to Figure 5 , a memory cell array 110 and memory cells connected by word lines are illustrated. It can be assumed that M word lines are connected to the memory cells, and the number of memory cells connected to one word line is k.

[0051] The memory cells can be connected in series between a bit line and a source line. The gates of a plurality of memory cells can be connected to one word line. For convenience of description, it can be assumed that the Nth word line WLn among the M word lines is a selected word line. In Figure 5 , memory cells C1 to Ck connected to the selected word line are illustrated.

[0052] The programming speed of each of the memory cells C1 to Ck connected to the selected word line can differ according to the distance from the address decoder 120. The programming speed can be related to the potential increase speed of the word line voltage applied to the memory cell. It can be assumed that, among the memory cells C1 to Ck connected to the selected word line, the first memory cell C1 is closest to the address decoder 120, and the kth memory cell Ck is farthest from the address decoder 120. Among the memory cells C1 to Ck connected to the selected word line, the programming speed or the potential increase speed of the word line voltage of the first memory cell C1 can be the fastest, and the programming speed or the potential increase speed of the word line voltage of the kth memory cell Ck can be the slowest.

[0053] Figure 6 is a graph illustrating the increase speed of the programming voltage corresponding to the pass voltage application according to an embodiment of the disclosure.

[0054] Referring to Figure 6 , the selected word line voltage is illustrated according to the pass voltage applied before the programming voltage Vp is applied and the position of the memory cell on the selected word line. In Figure 6 the description, the part corresponding to Figure 3 and Figure 4 described can be omitted.

[0055] In conjunction Figure 5 When the programming voltage Vp is applied to the select word line after the second pass voltage Vpass2 is applied to the select word line, 610 can represent the select word line voltage of the first memory cell C1 closest to the address decoder 120 in the select word line. T1 can represent the voltage increase period of the select word line of the first memory cell C1 to which the second pass voltage Vpass2 is applied. 620 can represent the select word line voltage of the kth memory cell Ck farthest from the address decoder 120 in the select word line. T1' can represent the voltage increase period of the select word line of the kth memory cell Ck to which the second pass voltage Vpass2 is applied. Due to the positions of the first memory cell C1 and the kth memory cell Ck, T1' can be longer than T1.

[0056] When the programming voltage Vp is applied to the select word line after the first pass voltage Vpass1 is applied to the select word line, 630 can represent the select word line voltage of the first memory cell C1 closest to the address decoder 120 in the select word line. T2 can represent the voltage increase period of the select word line of the first memory cell C1 to which the first pass voltage Vpass1 is applied. When the programming voltage Vp is applied to the select word line after the first pass voltage Vpass1 is applied to the select word line, 640 can represent the select word line voltage of the kth memory cell Ck farthest from the address decoder 120 in the select word line. T2' can represent the voltage increase period of the select word line of the kth memory cell Ck to which the first pass voltage Vpass1 is applied. Due to the positions of the first memory cell C1 and the kth memory cell Ck, T2' is longer than T2.

[0057] In an embodiment of the disclosure, the first pass voltage Vpass1 can be 5V or less, and the second pass voltage Vpass2 can be 10V or less. When the second pass voltage Vpass2 is applied to the select word line before the programming voltage Vp is applied, the voltage increase period of the select word line can be reduced. As the voltage increase period of the select word line is reduced, the effect of the programming speed difference based on the different positions of the memory cells in the select word line can be reduced. That is, the efficiency of the programming operation can be improved, and the number of verification operations can be reduced.

[0058] On the other hand, when the first pass voltage Vpass1 is applied equally to all word lines before the programming voltage Vp is applied, the voltage increase period of the select word line can increase. As the voltage increase period increases, the effect of the programming speed difference according to the positions of the memory cells in the select word line can increase.

[0059] Furthermore, when a second pass voltage Vpass2 is equally applied to all word lines before a program voltage Vp is applied, the program speed of the selected word line can be increased, but the voltage of the unselected word line can be increased. Disturb and current can be increased due to the voltage increase of the unselected word line. Power consumption can be increased due to the current increase.

[0060] In embodiments of the disclosure, the voltage increase period of the selected word line can be reduced by increasing only the magnitude of the pass voltage applied to the selected word line. The memory device can include a separate pass voltage regulator that generates a pass voltage applied to the selected word line before a program voltage is applied. The effect on the program speed due to the location of the memory cell connected to the selected word line can be reduced by reducing the voltage increase period. Disturb and current increase due to the pass voltage can be minimized since the pass voltage is applied only to the selected word line. Power consumption can also be reduced by minimizing the current increase.

[0061] Figure 7 is a flowchart illustrating a method of applying a pass voltage and a program voltage according to embodiments of the disclosure.

[0062] Referring to Figure 7 When performing a program operation, the memory device can apply a program voltage to a selected word line selected from among a plurality of word lines, and can apply a pass voltage to the remaining unselected word lines. The pass voltage can be similarly applied to the unselected word lines before the program voltage is applied to the selected word line. The memory device can increase the voltage of the selected word line by applying a pass voltage higher than the pass voltage applied to the unselected word lines to the selected word line to which the program voltage is to be applied. The voltage increase of the selected word line can improve the efficiency of the program operation.

[0063] In step S710, the memory device can generate a pass voltage to be applied to a plurality of word lines to which memory cells are connected. A first pass voltage regulator can generate a first pass voltage applied to unselected word lines that are not selected among the plurality of word lines. A second pass voltage regulator can generate a second pass voltage higher than the first pass voltage.

[0064] In step S720, the memory device can distinguish between a selected word line and an unselected word line among the plurality of word lines. In the case of the selected word line, step S730 can be performed, and in the case of the unselected word line, step S740 can be performed.

[0065] In step S730, the address decoder can apply a second pass voltage to the selected word line. The second pass voltage can be applied to the selected word line during the pass voltage increase period. Switching circuitry included in the address decoder can connect the second pass voltage regulator to the selected word line.

[0066] In step S740, the address decoder can apply a first pass voltage to the unselected word line. Switching circuitry included in the address decoder can connect the first pass voltage regulator to the unselected word line. The first pass voltage can be applied to the unselected word line even during a period in which a program voltage is applied to the selected word line after the pass voltage increase period. The connection of the first pass voltage regulator to the unselected word line can be maintained.

[0067] In step S750, a program voltage can be applied to the selected word line. Control logic can generate a control signal for applying the program voltage to the selected word line. The program voltage regulator can generate the program voltage, and the switching circuitry can disconnect the second pass voltage regulator from the selected word line and can connect the program voltage regulator to the selected word line.

[0068] Figure 7 Each of the steps of FIG. 7 can correspond to the description of Figures 2 to 6 FIG. 6.

Claims

1. A memory device comprising: an array of memory cells including memory cells connected by a plurality of word lines; peripheral circuitry to apply a pass voltage to the plurality of word lines in a period of time in which a program operation is performed, and to apply a program voltage to a selected word line selected from among the plurality of word lines after the pass voltage is applied to the plurality of word lines, wherein the pass voltage includes a first pass voltage and a second pass voltage, and the second pass voltage is higher than the first pass voltage; and control logic to control the peripheral circuitry to apply the second pass voltage to the selected word line and to apply the first pass voltage to unselected word lines that are word lines among the plurality of word lines that are not selected during a pass voltage increase period in which the pass voltage is applied. The peripheral circuitry includes:

2. The memory device of claim 1, wherein, a voltage generator including a first pass voltage regulator to generate the first pass voltage and a second pass voltage regulator to generate the second pass voltage; and an address decoder to connect the plurality of voltage regulators included in the voltage generator to the plurality of word lines. The control logic generates a first control signal to apply the pass voltage to respective word lines among the plurality of word lines during the pass voltage increase period, and 3. The memory device of claim 2, wherein, wherein the address decoder connects the first pass voltage regulator to the unselected word lines and the second pass voltage regulator to the selected word line in response to the first control signal. The voltage generator further includes a program voltage regulator to generate the program voltage, and 4. The memory device of claim 2, wherein, wherein the control logic generates a second control signal to apply the program voltage to the selected word line after the pass voltage increase period. The address decoder connects the selected word line to the program voltage regulator in response to the second control signal.

5. The memory device of claim 4, wherein, The address decoder maintains the connection between the first pass voltage regulator and the unselected word lines and disengages the connection between the second pass voltage regulator and the selected word line.

6. The memory device of claim 5, wherein, The address decoder includes a switch circuit to connect the plurality of voltage regulators to the plurality of word lines, respectively.

7. The memory device of claim 2, wherein, The switch circuit connects each of the plurality of word lines to one of the plurality of voltage regulators.

8. The memory device of claim 7, wherein, 9. A memory device comprising: a first pass voltage regulator to generate a first pass voltage to be applied to unselected word lines that are word lines among a plurality of word lines connected to memory cells that are not selected in a period of time in which a program operation is performed; a second pass voltage regulator to generate a second pass voltage that is higher than the first pass voltage to be applied to a selected word line among the plurality of word lines; and a program voltage regulator to generate a program voltage to be applied to the selected word line after the first pass voltage is applied to the unselected word lines. a program voltage regulator to generate a program voltage, the program voltage to be applied to the selected word line after the second pass voltage is applied to the selected word line; a switch circuit to connect the first pass voltage regulator, the second pass voltage regulator, and the program voltage regulator to the plurality of word lines, respectively; and control logic to control the switch circuit to apply the first pass voltage to the unselected word lines and the second pass voltage to the selected word line during a pass voltage increase period when a pass voltage is applied to the plurality of word lines.

10. The memory device of claim 9, wherein, The control logic to generate a first control signal to apply the first pass voltage and the second pass voltage to respective word lines among the plurality of word lines during the pass voltage increase period.

11. The memory device of claim 10, wherein, The switch circuit to connect the first pass voltage regulator to the unselected word lines and the second pass voltage regulator to the selected word line in response to the first control signal.

12. The memory device of claim 10, wherein, The control logic to generate a second control signal to apply the program voltage to the selected word line after the pass voltage increase period.

13. The memory device of claim 12, wherein, The switch circuit to connect the program voltage regulator to the selected word line in response to the second control signal.

14. The memory device of claim 13, wherein, The switch circuit to maintain the connection between the first pass voltage regulator and the unselected word lines and to disengage the connection between the second pass voltage regulator and the selected word line.

15. A method of operating a memory device, comprising: generating a pass voltage to be applied to a plurality of word lines connected to memory cells when performing a program operation, wherein the pass voltage includes a first pass voltage and a second pass voltage, and the second pass voltage is higher than the first pass voltage; applying the second pass voltage to a selected word line selected from among the plurality of word lines during a pass voltage increase period when the pass voltage is applied to the plurality of word lines; and applying a program voltage to the selected word line after the pass voltage increase period.

16. The method of claim 15, wherein, The generating of the pass voltage includes: generating the first pass voltage by a first pass voltage regulator; and generating the second pass voltage by a second pass voltage regulator.

17. The method of claim 16, wherein, The applying of the second pass voltage further includes applying the first pass voltage to unselected word lines that are word lines not selected among the plurality of word lines during the pass voltage increase period.

18. The method of claim 17, wherein, The applying of the program voltage further includes disengaging the connection between the second pass voltage regulator and the selected word line.

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