Semiconductor memory device and operating method thereof

Abstract

The invention provides a semiconductor memory device and an operating method thereof. The semiconductor memory device may include: a memory block including a plurality of memory cells; a voltage generation circuit configured to generate a read voltage and a pass voltage to be applied to a word line of the memory block during a read operation on the memory block; a temperature measurement circuit configured to measure a temperature before or after the read operation is performed, and output a temperature code corresponding to the measured temperature; and a block read counter configured to determine a read count increment of the memory block related to the read operation based on the temperature code, and update the read count value of the memory block by adjusting the read count value according to the read count increment.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0054790, filed on April 24, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate generally to an electronic device, and more particularly, to a semiconductor memory device and a method of operating the semiconductor memory device. Background Art

[0004] A semiconductor memory device is a memory device implemented using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices.

[0005] Volatile memory devices lose stored data when power is interrupted. Representative examples of volatile memory devices include static random access memory (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). Non-volatile memory devices retain stored data even when power is interrupted. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory is primarily categorized into NOR and NAND types. Summary of the Invention

[0006] Various embodiments of the present disclosure relate to a semiconductor memory device having improved operational reliability and a method of operating the semiconductor memory device.

[0007] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include: a memory block including a plurality of memory cells; a voltage generation circuit configured to generate a read voltage and a pass voltage to be applied to a word line of the memory block during a read operation on the memory block; a temperature measurement circuit configured to measure a temperature before or after performing a read operation and output a temperature code corresponding to the measured temperature; and a block read counter configured to determine a read count increment of the memory block related to the read operation based on the temperature code and update the read count value of the memory block by adjusting the read count increment.

[0008] Embodiments of the disclosure can provide a method of operating a semiconductor memory device. The method can include performing N number of read operations on a selected memory block among a plurality of memory blocks, where N is an integer of 1 or more; measuring a first internal temperature by performing a first temperature measurement operation; determining a new read count increment of the selected memory block by correcting the read count increment of the selected memory block related to the N number of read operations based on the measured first internal temperature; and updating a read count value of the selected memory block by adjusting the read count value of the selected memory block based on the new read count increment.

[0009] Embodiments of the disclosure can provide a method of operating a semiconductor memory device. The method can include measuring a temperature by performing a temperature measurement operation; performing N number of read operations on a selected memory block among a plurality of memory blocks, where N is an integer of 1 or more; determining a new read count increment of the selected memory block by correcting the read count increment based on the measured temperature; and updating a read count value of the selected memory block by adding the new read count increment to the read count value of the selected memory block. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the disclosure.

[0011] Figure 2 is a block diagram illustrating an embodiment of a memory cell array of Figure 1 .

[0012] Figure 3 is a diagram illustrating an embodiment of a memory cell array of Figure 1 .

[0013] Figure 4 is a diagram illustrating an embodiment of a memory cell array of Figure 1 .

[0014] Figure 5 is a diagram illustrating an embodiment of a memory cell array of Figure 1 .

[0015] Figure 6 is a diagram illustrating an embodiment of a block read counter of Figure 1 .

[0016] Figure 7 is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the disclosure.

[0017] Figure 8 is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the disclosure.

[0018] Figure 9 is a block diagram illustrating a memory system including Figure 1 a semiconductor memory device.

[0019] Figure 10 is a block diagram illustrating an application of the memory system of Figure 9 .

[0020] Figure 11 is a block diagram illustrating a computing system including the memory system described with reference to Figure 10 . DETAILED DESCRIPTION

[0021] Advantages and features of the present disclosure and methods for achieving the same will be described with reference to the accompanying drawings and later detailed description of embodiments. However, the present disclosure is not limited to the following embodiments, but can be embodied in other forms. Instead, various embodiments of the present disclosure are provided to describe the present disclosure in detail so that those skilled in the art to which the present disclosure pertains can easily practice the technical spirit of the present disclosure.

[0022] Figure 1 is a block diagram illustrating a semiconductor memory device 100 according to an embodiment of the present disclosure.

[0023] Referring to Figure 1 , the semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read and write circuit 130, control logic 140, a voltage generator 150, a block read counter 160, and a temperature measurement circuit 170.

[0024] The memory cell array 110 can include a plurality of memory blocks BLK1 to BLKz. The memory blocks BLK1 to BLKz are connected to the address decoder 120 through a word line WL. The plurality of memory blocks BLK1 to BLKz are connected to the read and write circuit 130 through bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells can be non-volatile memory cells, and can be embodied as non-volatile memory cells having a vertical channel structure. The memory cell array 110 can be embodied as a memory cell array having a two-dimensional (2D) structure. In an embodiment, the memory cell array 110 can be embodied as a memory cell array having a three-dimensional (3D) structure.

[0025] Each of the memory cells included in the memory cell array can store at least 2 bits of data. In an embodiment, each of the memory cells included in the memory cell array 110 can be a multi-level cell (MLC) storing 2 bits of data. In an embodiment, each of the memory cells included in the memory cell array 110 can be a triple-level cell (TLC) storing 3 bits of data. In an embodiment, each of the memory cells included in the memory cell array 110 can be a quad-level cell storing 4 bits of data. According to an embodiment, the memory cell array 110 can include a plurality of memory cells each of which stores 5 bits or more of data.

[0026] The address decoder 120, the read and write circuit 130, and the voltage generator 150 operate as a peripheral circuit for driving the memory cell array 110. The address decoder 120 is connected to the memory cell array 110 through a word line WL. The address decoder 120 can operate under the control of the control logic 140. The address decoder 120 receives an address through an input / output buffer (not shown) provided in the semiconductor memory device 100.

[0027] The address decoder 120 can decode a block address among the received address. The address decoder 120 selects at least one memory block according to the decoded block address. When a read voltage application operation is performed during a read operation, the address decoder 120 can apply a read voltage Vread generated by the voltage generator 150 to a selected word line of the selected memory block, and can apply a pass voltage Vpass to the remaining word lines, i.e., unselected word lines. During a program verify operation, the address decoder 120 can apply a verify voltage generated by the voltage generator 150 to a selected word line of the selected memory block, and can apply a pass voltage Vpass to the remaining word lines, i.e., unselected word lines.

[0028] The address decoder 120 can decode a column address among the received address. The address decoder 120 can transfer the decoded column address to the read and write circuit 130.

[0029] The read operation and the program operation of the semiconductor memory device 100 are each performed based on a page. An address received when each of the read operation and the program operation is requested can include a block address, a row address, and a column address. The address decoder 120 can select one memory block and one word line according to the block address and the row address. The column address can be decoded by the address decoder 120 and then can be provided to the read and write circuit 130.

[0030] The address decoder 120 can include a block decoder, a row decoder, a column decoder, an address buffer, etc.

[0031] The read and write circuit 130 includes a plurality of page buffers PB1 to PBm. The read and write circuit 130 can operate as a "read circuit" during a read operation on the memory cell array 110 and as a "write circuit" during a program operation. The plurality of page buffers PB1 to PBm are connected to the memory cell array 110 through bit lines BL1 to BLm. In order to sense a threshold voltage of a memory cell during a read operation or a program verify operation, each of the page buffers PB1 to PBm can sense a change in an amount of current flowing through a sensing node according to a program state of a corresponding memory cell while continuously supplying a sensing current to a bit line connected to the memory cell, and can latch the sensed change as sensed data. The read and write circuit 130 can operate in response to a page buffer control signal output from the control logic 140.

[0032] During a read operation, the read and write circuit 130 can sense data stored in the memory cell and temporarily store read data, and then can output the data DATA to an input / output buffer (not shown) of the semiconductor memory device 100. In an embodiment, the read and write circuit 130 can include a page buffer (or a page register) as well as a column selection circuit or the like.

[0033] The control logic 140 can be connected to the address decoder 120, the read / write circuit 130, and the voltage generator 150. The control logic 140 can receive a command CMD and a control signal CTRL through an input / output buffer (not shown) of the semiconductor memory device 100. The control logic 140 can control overall operations of the semiconductor memory device 100 in response to the control signal CTRL. Further, the control logic 140 can output a control signal for controlling a pre-charge potential level at a sensing node of the plurality of page buffers PB1 to PBm. The control logic 140 can control the read and write circuit 130 to perform a read operation on the memory cell array 110. Further, the control logic 140 can control a read recovery operation performed on each of the plurality of memory blocks BLK1 to BLKz based on a read count value of each of the memory blocks BLK1 to BLKz stored in the block read counter 160. In order to prevent a read failure from occurring on a related memory block due to a repeated read operation on the memory block, an operation of reading data from the related memory block and storing the read data in a new memory block is referred to as a read recovery operation. For example, the control logic 140 can control the peripheral circuit to perform a read recovery operation on a memory block whose read count value exceeds a set value.

[0034] The voltage generator 150 can generate a read voltage Vread and a pass voltage Vpass in response to a voltage generator control signal output from the control logic 140 during a read operation.

[0035] The block read counter 160 can count and store the number of read operations performed on each of the plurality of memory blocks BLK1 to BLKz in the memory cell array 110. The number of read operations can be referred to as a "read count value." For example, the read count value of each memory block can be reset when the corresponding memory block is erased or programmed. Hereinafter, the read count value is increased each time a read operation is performed on the corresponding memory block. The block read counter 160 can receive a temperature code temp_code corresponding to the internal temperature of the semiconductor memory device 100 measured by the temperature measurement circuit 170. The block read counter 160 can adjust the increment of the read count value based on the received temperature code temp_code. In some embodiments, according to the received temperature code temp_code, when the temperature of the semiconductor memory device 100 falls within a preset normal temperature range, the block read counter 160 can increase the read count value of the corresponding memory block by N times when N read operations are performed on the corresponding memory block, where N is an integer of 1 or more. According to the received temperature code temp_code, when the temperature of the semiconductor memory device 100 is lower than the preset normal temperature range, the block read counter 160 can increase the read count value by (X x N). Here, X can be a number greater than 0 and less than 1. According to the received temperature code temp_code, when the temperature of the semiconductor memory device 100 is higher than the preset normal temperature range, the block read counter 160 can increase the read count value by (Y x N). Here, Y can be a number greater than 1. That is, when the temperature of the semiconductor memory device 100 is high, the block read counter 160 can increase the read count value of the corresponding memory block by a number greater than the normal increment (i.e., N), and when the temperature is low, the block read counter 160 can increase the read count value of the corresponding memory block by a number less than the normal increment (i.e., N).

[0036] When a command CMD corresponding to a read operation is received, the control logic 140 can set a read voltage to be used in the read operation based on the temperature of the semiconductor memory device 100 measured by the temperature measurement circuit 170 and the read count value of the memory block on which the read operation is to be performed stored in the block read counter 160, and can control the voltage generator 150 to generate the set read voltage.

[0037] The temperature measurement circuit 170 can measure the internal temperature of the semiconductor memory device 100 before and after a read operation is performed on a selected memory block, can generate a temperature code temp_code corresponding to the measured internal temperature, and can output the generated temperature code temp_code to the control logic 140 and the block read counter 160. The temperature measurement circuit 170 can be physically disposed near the memory cell array 110.

[0038] Although in Figure 1 the block read counter 160 is shown as a component implemented separately from the control logic 140, the block read counter 160 can be implemented as included in the control logic 140.

[0039] Figure 2 is a block diagram illustrating an embodiment of the memory cell array of Figure 1 .

[0040] Referring to Figure 2 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks can have a three-dimensional (3D) structure. Each of the memory blocks includes a plurality of memory cells stacked on a substrate. The plurality of memory cells are arranged in +X, +Y, and +Z directions. The structure of each memory block configured in a 3D structure will be described later in detail with reference to Figure 4 and Figure 5 . In some embodiments, each memory block of the memory cell array 110 can have a 2D structure, which is different from the structure shown in Figure 2 . The memory block having a 2D structure will be described in detail below with reference to Figure 3 .

[0041] Figure 3 is a diagram illustrating an embodiment 110_1 of the memory cell array 110 of Figure 1 .

[0042] Referring to Figure 3 , the first memory block BLK1 to the z-th memory block BLKz included in the memory cell array 110_1 are commonly connected to the first bit line BL1 to the m-th bit line BLm. In Figure 3 , for convenience of description, elements included in the first memory block BLK1 among the plurality of memory blocks BLK1 to BLKz are shown, and elements included in each of the remaining memory blocks BLK2 to BLKz are omitted. It will be understood that the remaining memory blocks BLK2 to BLKz are configured in the same manner as the first memory block BLK1.

[0043] The memory block BLK1 includes a plurality of cell strings CS1_1 to CS1_m. The first cell string CS1_1 to the m-th cell string CS1_m are connected to the first bit line BL1 to the m-th bit line BLm, respectively.

[0044] Each of the first to mth cell strings CS1_1 to CS1_m includes a drain select transistor DST, a plurality of memory cells MC1 to MCn connected in series with each other, and a source select transistor SST. The drain select transistor DST is connected to a drain select line DSL1. The first to nth memory cells MC1 to MCn are connected to first to nth word lines WL1 to WLn, respectively. The source select transistor SST is connected to a source select line SSL1. A drain of the drain select transistor DST is connected to a corresponding bit line. The drain select transistors DST of the first to mth cell strings CS1_1 to CS1_m are connected to first to mth bit lines BL1 to BLm, respectively. A source of the source select transistor SST is connected to a common source line CSL. In an embodiment, the common source line CSL can be commonly connected to the first to zth memory blocks BLK1 to BLKz.

[0045] The drain select line DSL1, the first to nth word lines WL1 to WLn, and the source select line SSL1 can be controlled by the address decoder 120. The common source line CSL can be controlled by the control logic 140. The first to mth bit lines BL1 to BLm can be controlled by the read and write circuit 130.

[0046] According to Figure 3 the configuration shown, the memory cell array 110 of the semiconductor memory device 100 according to an embodiment of the present disclosure can be implemented as a memory cell array 110_1 having a 2D structure. However, according to another embodiment, the memory cell array 110 of the semiconductor memory device 100 can be implemented as a memory cell array having a 3D structure. The memory cell array having a 3D structure will be described in detail below with reference to Figure 4 and Figure 5 The memory cell array having a 3D structure will be described in detail below with reference to

[0047] Figure 4 is a diagram illustrating an embodiment 110_2 of the memory cell array 110 of Figure 1

[0048] Referring to Figure 4 , the memory cell array 110_2 includes a plurality of memory blocks BLK1 to BLKz. In Figure 4 , for ease of description, the internal configuration of the first memory block BLK1 is illustrated, while the internal configurations of the remaining memory blocks BLK2 to BLKz are omitted. It will be understood that the second to zth memory blocks BLK2 to BLKz are configured in the same manner as the first memory block BLK1.

[0049] Referring to Figure 4 ​The first memory block BLK1 includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment, each of the cell strings CS11 to CS1m and CS21 to CS2m can be formed in a "U" shape. In the first memory block BLK1, m cell strings are arranged along a row direction (i.e., a positive (+) X direction). In Figure 4 In the embodiment, two cell strings are shown as being arranged along a column direction (i.e., a positive (+) Y direction). However, this illustration is for ease of description, and it will be understood that three or more cell strings can be arranged along the column direction.

[0050] Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source select transistor SST, first to n-th memory cells MC1 to MCn, a pass transistor PT, and at least one drain select transistor DST.

[0051] The select transistors SST and DST and the memory cells MC1 to MCn can have similar structures. In an embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn can include a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. In an embodiment, a pillar for providing the channel layer can be provided in each cell string. In an embodiment, a pillar for providing at least one of the channel layer, the tunnel insulating layer, the charge storage layer, and the blocking insulating layer can be provided in each cell string.

[0052] The source select transistor SST of each cell string is connected between a common source line CSL and the memory cells MC1 to MCp.

[0053] In an embodiment, the source select transistors of the cell strings arranged in the same row are connected to a source select line extending along the row direction, and the source select transistors of the cell strings arranged in different rows are connected to different source select lines. In Figure 4 In the embodiment, the source select transistors of the cell strings CS11 to CS1m in the first row are connected to a first source select line SSL1. The source select transistors of the cell strings CS21 to CS2m in the second row are connected to a second source select line SSL2.

[0054] In an embodiment, the source select transistors of the cell strings CS11 to CS1m and CS21 to CS2m can be commonly connected to one source select line.

[0055] The first to n-th memory cells MC1 to MCn in each cell string are connected between the source select transistor SST and the drain select transistor DST.

[0056] The first through nth memory cells MC1 through MCn can be divided into first through pth memory cells MC1 and (p+1)th through MCp+1 memory cells MCn. The first through pth memory cells MC1 through MCp are arranged sequentially in a direction opposite to the positive (+) Z direction and are connected in series between a source select transistor SST and a pipe transistor PT. The (p+1)th through MCn memory cells are arranged sequentially in the +Z direction and are connected in series between the pipe transistor PT and the drain select transistor DST. The first through pth memory cells MC1 and (p+1)th through MCp+1 memory cells MCn are interconnected via the pipe transistor PT. The gates of the first through nth memory cells MC1 through MCn in each cell string are connected to the first through nth word lines WL1 through WLn, respectively.

[0057] The gate of the pipe transistor PT of each cell string is connected to the pipe PL.

[0058] The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MCp+1 to MCn. The cell strings arranged along the row direction are connected to the drain select lines extending along the row direction. The drain select transistors of the cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0059] The cell strings arranged along the column direction may be connected to the bit lines extending along the column direction. Figure 4 , cell strings CS11 and CS21 in the first column are connected to the first bit line BL1. Cell strings CS1m and CS2m in the m-th column are connected to the m-th bit line BLm.

[0060] Memory cells connected to the same word line in cell strings arranged along a row form a single page. For example, in the first row of cell strings CS11 to CS1m, the memory cells connected to the first word line WL1 form a single page. In the second row of cell strings CS21 to CS2m, the memory cells connected to the first word line WL1 form another single page. Cell strings arranged along a row can be selected by selecting one of the drain select lines DSL1 and DSL2. A page can be selected from the selected cell string by selecting one of the word lines WL1 to WLn.

[0061] Figure 5 It shows Figure 1 1 is a diagram of an embodiment 110_3 of a memory cell array 110 .

[0062] ReferenceFigure 5 The memory cell array 110_3 includes a plurality of memory blocks BLK1' to BLKz'. In Figure 5 In the following description, the internal configuration of the first memory block BLK1' is shown for ease of description, while the internal configurations of the remaining memory blocks BLK2' to BLKz' are omitted. It will be understood that each of the second memory block BLK2' to the z-th memory block BLKz' has the same configuration as the first memory block BLK1'.

[0063] The first memory block BLK1' includes a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the cell strings CS11' to CS1m' and CS21' to CS2m' extends in the +Z direction. In the first memory block BLK1', m cell strings are arranged in the +X direction. In Figure 5 In the following description, two cell strings are shown as being arranged in the +Y direction. However, this illustration is for ease of description, and it will be understood that three or more cell strings can be arranged in the column direction.

[0064] Each of the cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source select transistor SST, first to n-th memory cells MC1 to MCn, and at least one drain select transistor DST.

[0065] The source select transistor SST of each cell string is connected between a common source line CSL and the memory cells MC1 to MCn. The source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of the cell strings CS11' to CS1m' arranged in the first row can be connected to a first source select line SSL1. The source select transistors of the cell strings CS21' to CS2m' arranged in the second row can be connected to a second source select line SSL2. In an embodiment, the source select transistors of the cell strings CS11' to CS1m' and CS21' to CS2m' can be commonly connected to a single source select line.

[0066] The first to n-th memory cells MC1 to MCn in each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first to n-th memory cells MC1 to MCn are connected to first to n-th word lines WL1 to WLn, respectively.

[0067] The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged along the row direction can be connected to the drain select line extending along the row direction. The drain select transistors of the cell strings CS11′ to CS1m′ in the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21′ to CS2m′ in the second row can be connected to the second drain select line DSL2.

[0068] Therefore, in addition to not including the pipe transistor PT in each cell string, Figure 5 The memory block BLK1′ has Figure 4 The equivalent circuit of the memory block BLK1 is similar.

[0069] Figure 6 It shows Figure 1 FIG. 1 is a diagram of an embodiment of a block read counter 160 .

[0070] Reference Figure 6 , the block read counter 160 may include a read count corrector 161 and a read count storage device 162 .

[0071] The read count corrector 161 can read the temperature from the temperature measurement circuit (e.g., Figure 1 170) receives a temperature code temp_code and may correct and count a read count increment RCV based on the received temperature code temp_code. The read count increment RCV may refer to the number by which the read count value of the selected memory block increases when N read operations are performed on the selected memory block, where N is an integer of 1 or greater. For example, when the temperature code temp_code corresponds to a temperature within a preset normal temperature range and N read operations are performed on the selected memory block, the read count corrector 161 may count the read count increment RCV of the selected memory block to N. When the received temperature code temp_code corresponds to a temperature below the preset normal temperature range and N read operations are performed on the selected memory block, the read count corrector 161 may count the read count increment RCV by correcting the read count increment RCV of the selected memory block to a number less than N. When the received temperature code temp_code corresponds to a temperature above the preset normal temperature range and N read operations are performed on the selected memory block, the read count corrector 161 may count the read count increment RCV by correcting the read count increment RCV of the selected memory block to a number greater than N.

[0072] The read count storage device 162 can store Figure 1the read count values of the plurality of memory blocks BLK1 to BLKz included in the memory cell array 110. The read count storage 162 can receive the read count increment RCV from the read count corrector 161, and can update the read count values of the selected memory blocks on which the read operation is performed based on the received read count increment RCV. The read count values corresponding to each of the memory blocks stored in the read count storage 162 can be stored in at least one memory block designated as a system block or a content addressable memory (CAM) block among the plurality of memory blocks BLK1 to BLKz at a regular time or at each idle time. During a power-on operation of the semiconductor memory device, the read count values of each of the plurality of memory blocks BLK1 to BLKz stored in the system block or the CAM block can be read, and then stored in the read count storage 162.

[0073] Figure 7 is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the disclosure.

[0074] A method of operating a semiconductor memory device according to an embodiment of the disclosure will be described below with reference to Figures 1 to 7

[0075] At S710, the semiconductor memory device 100 receives a read command for the first memory block from an external device. For example, the semiconductor memory device 100 can receive a read command and an address corresponding to the first memory block from a controller external to the semiconductor memory device 100.

[0076] At S720, the temperature measurement circuit 170 can perform a first temperature measurement operation of measuring the internal temperature T1 of the semiconductor memory device 100.

[0077] The control logic 140 can set a read voltage to be used in the read operation with reference to the internal temperature T1 of the semiconductor memory device 100 measured in the first temperature measurement operation and the read count value of the first memory block stored in the read count storage 162.

[0078] At S730, a read operation can be performed on the first memory block. The read operation on the first memory block can be performed N times, where N is an integer of 1 or more.

[0079] For example, the voltage generator 150 can generate the set read voltage Vread and the pass voltage Vpass under the control of the control logic 140. The address decoder 120 can apply the read voltage Vread generated by the voltage generator 150 to a selected word line of the first memory block, and apply the pass voltage Vpass to an unselected word line of the first memory block.

[0080] ​The plurality of page buffers PB1 through PBm of the read and write circuit 130 can latch data by sensing a current or a potential of the corresponding bit line BL1 through BLm.

[0081] At S740, when the read operation on the first memory block is completed, the temperature measuring circuit 170 can measure the internal temperature T2 of the semiconductor memory device 100 by performing a second temperature measurement operation, and can generate and output a temperature code temp_code corresponding to the measured internal temperature T2.

[0082] At S750, the read count corrector 161 can determine whether the internal temperature T2 corresponding to the temperature code temp_code received from the temperature measuring circuit 170 as a result of the second temperature measurement operation is lower than a first temperature α. The first temperature α can be a lowest temperature falling within a preset normal temperature range.

[0083] When it is determined that the internal temperature T2 measured in the second temperature measurement operation is lower than the first temperature α (S750, "Yes"), at S760, the read count corrector 161 can count the read count increment by correcting the read count increment to N×X, where N is the number of read operations performed, and 0 < X < 1.

[0084] When it is determined that the internal temperature T2 measured in the second temperature measurement operation is higher than or equal to the first temperature α (S750, "No"), at S770, the read count corrector 161 can determine whether the internal temperature T2 corresponding to the temperature code temp_code received from the temperature measuring circuit 170 as a result of the second temperature measurement operation is higher than a second temperature β. The second temperature β can be higher than the first temperature α and a highest temperature falling within a preset normal temperature range.

[0085] When it is determined that the internal temperature T2 measured in the second temperature measurement operation is higher than the second temperature β (S770, "Yes"), at S780, the read count corrector 161 can count the read count increment by correcting the read count increment to N×Y, where N is the number of read operations performed, and 1 < Y.

[0086] When it is determined that the internal temperature T2 measured in the second temperature measurement operation is lower than the second temperature β (S770, "No"), at S790, the read count corrector 161 can determine that the internal temperature T2 corresponding to the temperature code temp_code received from the temperature measuring circuit 170 as a result of the second temperature measurement operation falls within a preset normal temperature range, and can count the read count increment as N, where N is the number of read operations performed.

[0087] At S800, the read count storage device 162 may update the read count value of the first memory block based on the read count increment counted in the above-mentioned operation S760, S780, or S790. That is, the read count value of the first memory block may be updated by adding the read count increment to the read count value of the first memory block. During a new read operation on the first memory block, the updated read count value of the first memory block may be referenced. For example, during a new read operation, the control logic 140 may set a read voltage based on the internal temperature of the semiconductor memory device 100 and the updated read count value of the first memory block.

[0088] The control logic 140 may control peripheral circuits, ie, the address decoder 120 , the read and write circuit 130 , and the voltage generator 150 , to perform a read reclaim operation based on a read count value of each of the plurality of memory blocks BLK1 to BLKz.

[0089] As described above, according to embodiments of the present disclosure, the internal temperature of the semiconductor memory device 100 can be measured after a read operation is performed, and read count increments can be counted by assigning weights to the read count values ​​of the memory blocks performing the read operation based on the measured internal temperature. Therefore, the reliability of the read operation can be improved by more accurately quantifying the read stress of the corresponding memory blocks based on the number of read operations (read count) and temperature.

[0090] In the embodiments of the present disclosure, although the process of performing N read operations on a selected memory block and then measuring the internal temperature of the semiconductor memory device 100 has been described by way of example, the embodiments of the present disclosure are not limited thereto. For example, at least one temperature measurement operation may be performed while continuously performing N read operations, and the read count increment may be counted by correcting the read count increment of the selected memory block based on the average temperature obtained as a result of the at least one temperature measurement operation.

[0091] In an embodiment of the present disclosure, after performing the second temperature measurement operation at S740, it is possible to determine at S750 and S770 whether the measured temperature is lower than the first temperature α, falls within the range between the first temperature α and the second temperature β, or is higher than the second temperature β, and then correct and count the read count increments, but the embodiments of the present disclosure are not limited thereto. For example, the read count increments may be corrected and counted in different ways depending on whether the measured temperature is lower than or higher than the first temperature α.

[0092] Figure 8 is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0093] The following will refer to Figures 1 to 6 and Figure 8A method of operating a semiconductor memory device according to an embodiment of the present disclosure is described.

[0094] At S810, the semiconductor memory device 100 receives a read command for the first memory block from an external device. For example, the semiconductor memory device 100 can receive a read command and an address corresponding to the first memory block from a controller external to the semiconductor memory device 100.

[0095] At S820, the temperature measurement circuit 170 can perform a temperature measurement operation of measuring the internal temperature T1 of the semiconductor memory device 100. The temperature measurement circuit 170 can generate and output a temperature code temp_code corresponding to the measured internal temperature T1.

[0096] The control logic 140 can set a read voltage to be used in a read operation with reference to the internal temperature T1 of the semiconductor memory device 100 measured in the temperature measurement operation and the read count value of the first memory block stored in the read count storage 162.

[0097] At S830, a read operation can be performed on the first memory block. The read operation on the first memory block can be performed N times, where N is an integer of 1 or more.

[0098] For example, the voltage generator 150 can generate the set read voltage Vread and the pass voltage Vpass under the control of the control logic 140. The address decoder 120 can apply the read voltage Vread generated by the voltage generator 150 to a selected word line of the first memory block and apply the pass voltage Vpass to an unselected word line of the first memory block.

[0099] The plurality of page buffers PB1 to PBm of the read and write circuit 130 can latch data by sensing a current or a potential of the corresponding bit line BL1 to BLm.

[0100] At S840, the read count corrector 161 can determine whether the internal temperature T1 corresponding to the temperature code temp_code received from the temperature measurement circuit 170 as a result of the temperature measurement operation is lower than a first temperature α. The first temperature α can be a lowest temperature falling within a preset normal temperature range.

[0101] When it is determined that the internal temperature T1 measured in the temperature measurement operation is lower than the first temperature α (S840, "Yes"), at S850, the read count corrector 161 can count the read count increment by correcting the read count increment to N×X, where N is the number of read operations performed, and 0X<1.

[0102] When it is judged that the internal temperature T1 measured in the temperature measurement operation is higher than or equal to the first temperature a (S840, "No"), the read count corrector 161 can judge whether the internal temperature T1 corresponding to the temperature code temp_code received from the temperature measurement circuit 170 as a result of the temperature measurement operation is higher than the second temperature β at S860. The second temperature β can be higher than the first temperature a and be the highest temperature falling within the preset normal temperature range.

[0103] When it is judged that the internal temperature T1 measured in the temperature measurement operation is higher than the second temperature β (S860, "Yes"), the read count corrector 161 can count the read count increment by correcting the read count increment to N×Y at S870, where N is the number of read operations performed, and 1 < Y.

[0104] When it is judged that the internal temperature T1 measured in the temperature measurement operation is lower than or equal to the second temperature β (S860, "No"), the read count corrector 161 can judge that the internal temperature T1 corresponding to the temperature code temp_code received from the temperature measurement circuit 170 as a result of the temperature measurement operation falls within the preset normal temperature range, and can count the read count increment as N, where N is the number of read operations performed, at S880.

[0105] The read count storage 162 can update the read count value of the first storage block based on the read count increment counted in the above-described operations S850, S870, or S880 at S890. That is, the read count value of the first storage block can be updated by adding the read count increment to the read count value of the first storage block. During a new read operation on the first storage block, the updated read count value of the first storage block can be referred to. For example, during the new read operation, the control logic 140 can set a read voltage based on the internal temperature of the semiconductor memory device 100 and the updated read count value of the first storage block.

[0106] In an embodiment of the disclosure, after the read operation on the first storage block at S830, it can be judged whether the measured temperature is lower than the first temperature a, falls within a range between the first temperature a and the second temperature β, or is higher than the second temperature β at operations S840 and S860, and then the read count increment can be corrected and counted, but embodiments of the disclosure are not limited thereto. For example, the read count increment can be corrected and counted differently according to whether the measured temperature is lower than or higher than the first temperature a.

[0107] As described above, according to embodiments of the present disclosure, the internal temperature of the semiconductor memory device 100 can be measured before a read operation is performed, and the read count increment can be counted by assigning a weight to a read count value of a memory block for which the read operation is performed based on the measured internal temperature. Accordingly, the reliability of the read operation can be improved by quantifying the read stress of the corresponding memory block more accurately according to the number of read operations (read count) and the temperature.

[0108] Figure 9 is a block diagram illustrating a memory system 1000 including a semiconductor memory device. Figure 1

[0109] Referring to Figure 9 , the memory system 1000 includes a semiconductor memory device 100 and a controller 1100. The semiconductor memory device 100 can be the semiconductor memory device described with reference to Figure 1 . Hereinafter, repetitive descriptions will be omitted.

[0110] The controller 1100 is connected to a host Host and the semiconductor memory device 100. The controller 1100 can access the semiconductor memory device 100 in response to a request from the host Host. For example, the controller 1100 can control a read operation, a write operation, an erase operation, and a background operation of the semiconductor memory device 100. The controller 1100 can provide an interface between the semiconductor memory device 100 and the host Host. The controller 1100 can run a firmware for controlling the semiconductor memory device 100.

[0111] The controller 1100 includes a random access memory (RAM) 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. The RAM 1110 can be used as at least one of a working memory of the processing unit 1120, a cache memory between the semiconductor memory device 100 and the host Host, and a buffer memory between the semiconductor memory device 100 and the host Host. The processing unit 1120 controls the overall operation of the controller 1100. In addition, the controller 1100 can temporarily store program data provided from the host Host during a write operation.

[0112] ​The host interface 1130 includes a protocol for performing data exchange between the host Host and the controller 1100. In an embodiment, the controller 1100 can communicate with the host Host through at least one of various communication standards or interfaces such as a Universal Serial Bus (USB) protocol, a Multi-Media Card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a Peripheral Component Interconnect Express (PCI-e or PCIe) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a proprietary protocol.

[0113] The memory interface 1140 interfaces the semiconductor memory device 100. For example, the memory interface 1140 can include a NAND interface or a NOR interface.

[0114] The error correction block 1150 can detect and correct errors in data received from the semiconductor memory device 100 using an error correction code (ECC). The processing unit 1120 can adjust a read voltage based on an error detection result of the error correction block 1150, and can control the semiconductor memory device 100 to re-perform a read operation using the adjusted read voltage. In an embodiment, the error correction block can be provided as an element of the controller 1100.

[0115] The controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device. In an embodiment, the controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. For example, the controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device and form a memory card such as a Personal Computer Memory Card International Association (PCMCIA) card, a CompactFlash (CF), a Smart Media card (SM or SMC), a Memory Stick, a Multi-Media Card (MMC, RS-MMC, or micro-SD), a Secure Digital (SD) card (SD, mini-SD, micro-SD, or SDHC), or a Universal Flash Storage (UFS).

[0116] The controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a solid state drive (SSD). The SSD includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as an SSD, the operating speed of a host Host connected to the memory system 2000 can be significantly improved.

[0117] In an embodiment, the memory system 1000 can be provided as one of various elements of an electronic device such as a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a wireless phone, a mobile phone, a smartphone, a wearable device, an e-book, a portable multimedia player (PMP), a game device, a navigation device, a black box, a digital camera, a 3-dimensional (3D) television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting / receiving information in a wireless environment, one of various devices forming a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID device, or one of various elements constituting a computing system.

[0118] In an embodiment, the semiconductor memory device 100 or the memory system 1000 can be mounted in various types of packages. For example, the semiconductor memory device 100 or the memory system 1000 can be packaged or mounted in a type such as a package on package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic leaded chip carrier (PLCC), a plastic dual-in-line package (PDIP), a wafer-level chip scale package (W-CSP), a wafer-level process package (WFP), or a wafer-level stack package (WSP).

[0119] Figure 10 is a block diagram illustrating an application of the memory system. Figure 9

[0120] Referring to Figure 10 , the memory system 2000 includes a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 can include a plurality of semiconductor memory chips. The semiconductor memory chips are divided into a plurality of groups.

[0121] In Figure 10 , the plurality of groups are illustrated as communicating with the controller 2200 through first to k-th channels CH1 to CHk, respectively. Each semiconductor memory chip can be configured and operated in the same manner as the semiconductor memory device 100 described with reference to Figure 1

[0122] ​​Each group can communicate with the controller 2200 through one common channel. The controller 2200 can be configured in the same manner as the controller 1100 described with reference to Figure 9 and can be configured to control the plurality of memory chips of the semiconductor memory device 2100 through the plurality of channels CH1 to CHk.

[0123] Figure 11 is a block diagram illustrating a computing system 3000 including the memory system 2000 described with reference to Figure 10 The computing system 3000 can include a central processing unit (CPU) 3100, a RAM 3200, a user interface 3300, a power supply 3400, a system bus 3500, and the memory system 2000.

[0124] with reference to Figure 11 The computing system 3000 can include a central processing unit (CPU) 3100, a RAM 3200, a user interface 3300, a power supply 3400, a system bus 3500, and the memory system 2000.

[0125] The memory system 2000 is electrically connected to the CPU 3100, the RAM 3200, the user interface 3300, and the power supply 3400 through the system bus 3500. Data provided through the user interface 3300 or processed by the CPU 3100 can be stored in the memory system 2000.

[0126] In Figure 11 , the semiconductor memory device 2100 is illustrated as being connected to the system bus 3500 through the controller 2200. However, the semiconductor memory device 2100 can be directly connected to the system bus 3500. Here, the functions of the controller 2200 can be performed by the CPU 3100 and the RAM 3200.

[0127] In Figure 11 , the memory system 2000 described with reference to Figure 10 is illustrated as being provided. However, the memory system 2000 can be replaced with the memory system 1000 described with reference to Figure 9 In an embodiment, the computing system 3000 can include both the memory systems 1000 and 2000 described with reference to Figure 9 and Figure 10

[0128] According to embodiments of the present disclosure, the reliability of a semiconductor memory device can be improved by adjusting an increment of a read count based on a temperature.

[0129] ​The embodiments of the present disclosure disclosed in the specification and drawings are merely intended to present specific examples in order to easily describe the technical details of the present disclosure, and thus are not intended to limit the scope of the present disclosure. It will be obvious to those skilled in the art to which the present disclosure pertains that various modifications can be made based on the technical spirit of the present disclosure, in addition to the disclosed embodiments. Furthermore, the embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor memory device, comprising: a memory block including a plurality of memory cells; a voltage generation circuit that generates a read voltage and a pass voltage to be applied to a word line of the memory block during a read operation on the memory block; a temperature measurement circuit that measures a temperature before or after the read operation is performed and outputs a temperature code corresponding to the measured temperature; and a block read counter that determines a read count increment of the memory block related to the read operation based on the temperature code and updates a read count value of the memory block by adjusting the read count value according to the read count increment.

2. The semiconductor memory device of claim 1, further comprising: control logic that controls the voltage generation circuit, wherein the control logic sets a level of a read voltage to be used in the read operation based on the read count value of the memory block.

3. The semiconductor memory device of claim 2, wherein: the temperature measurement circuit measures the temperature before the read operation, and the control logic sets the level of the read voltage to be used in the read operation based on the temperature and the read count value. the control logic determines whether to perform a read recovery operation on the memory block based on the read count value of the memory block.

4. The semiconductor memory device according to claim 1, wherein, the block read counter determines the read count increment by:

5. The semiconductor memory device of claim 1, wherein, correcting the read count increment to a first value when the temperature is lower than a reference temperature and to a second value greater than the first value when the temperature is higher than the reference temperature according to N times of read operations performed on the memory block, where N is a positive integer of 1 or greater.

6. The semiconductor memory device of claim 1, wherein: according to N times of read operations performed on the memory block, N being an integer of 1 or greater, the block read counter: increases the read count value of the memory block by a read count increment N when the temperature falls within a preset temperature range, increases the read count value of the memory block by a read count increment X x N when the temperature is lower than the preset temperature range, where X is greater than 0 and less than 1, and increases the read count value of the memory block by a read count increment Y x N when the temperature is higher than the preset temperature range, where Y is a number greater than 1. the block read counter includes:

7. The semiconductor memory device of claim 6, wherein, a read count corrector that corrects and counts the read count increment based on the temperature code; and a read count storage that updates and stores the read count value of the memory block on which the read operation is performed based on the read count increment. the read count corrector:

8. The semiconductor memory device of claim 7, wherein, corrects the read count increment by decreasing a value of the read count increment when a temperature corresponding to the temperature code is lower than a first temperature, the first temperature being a lowest temperature within the preset temperature range, and corrects the read count increment by increasing the value of the read count increment when the temperature corresponding to the temperature code is higher than a second temperature, the second temperature being a highest temperature within the preset temperature range. correcting the read count increment by increasing a value of the read count increment when a temperature corresponding to the temperature code is higher than a second temperature, the second temperature being a highest temperature within the preset temperature range.

9. The semiconductor memory device of claim 1, further comprising: a system block or a content addressable memory (CAM) block that stores the read count value.

10. The semiconductor memory device of claim 9, wherein, reading the read count value stored in the system block or the CAM block during a power-on operation and storing the read count value in the block read counter.

11. A method of operating a semiconductor memory device, comprising: performing N number of read operations on a selected memory block among a plurality of memory blocks, where N is an integer of 1 or more; measuring a first internal temperature by performing a first temperature measurement operation; determining a new read count increment for the selected memory block by correcting a read count increment for the selected memory block related to the N number of read operations based on the measured first internal temperature; and updating a read count value for the selected memory block by adjusting the read count value for the selected memory block based on the new read count increment.

12. The method of claim 11, wherein, determining the new read count increment includes: correcting the read count increment by decreasing the read count increment from N when the measured first internal temperature is lower than a preset temperature range; and correcting the read count increment by increasing the read count increment from N when the measured first internal temperature is higher than the preset temperature range.

13. The method of claim 12, wherein, determining the new read count increment further includes: determining the new read count increment as N when the first internal temperature falls within the preset temperature range.

14. The method of claim 11, further comprising: performing a second temperature measurement operation before performing the read operations and setting a level of a read voltage to be used in the read operations based on a temperature measured in the second temperature measurement operation.

15. The method of claim 11, wherein, the first temperature measurement operation is performed after termination of the N number of read operations or at least once while the N number of read operations are being performed.

16. The method of claim 11, further comprising: setting a read voltage for a new read operation of the selected memory block based on the updated read count value.

17. A method of operating a semiconductor memory device, comprising: measuring a temperature by performing a temperature measurement operation; performing N number of read operations on a selected memory block among a plurality of memory blocks, where N is an integer of 1 or more; determining a new read count increment for the selected memory block by correcting a read count increment based on the measured temperature; and updating a read count value for the selected memory block by adding the new read count increment to the read count value for the selected memory block.

18. The method of claim 17, wherein, determining the new read count increment includes: correcting the read count increment by decreasing the read count increment to a value less than N when the measured temperature is lower than a preset temperature range; and correcting the read count increment by increasing the read count increment to a value greater than N when the measured temperature is higher than the preset temperature range.

19. The method of claim 18, wherein, determining the new read count increment further comprises: determining the new read count increment as N when the temperature falls within the preset temperature range.

20. The method of claim 17, further comprising: setting a read voltage to be used in the read operation based on the temperature before performing the read operation on the selected memory block.

21. The method of claim 17, further comprising: setting a read voltage for a new read operation of the selected memory block based on the updated read count value.

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