Memory device and control method thereof
By counting pause and restart events in an erase action in a memory device and executing a soft programming action when a threshold is reached, the problem of over-erasure of a memory block is solved and the accuracy and reliability of data reading are improved.
Patent Information
- Application Number
- CN202410664797.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-04-18
- Filing Date
- 2024-05-27
- Publication Date
- 2025-10-24
AI Technical Summary
In memory devices, over-erasure of memory blocks leads to read errors and reduced data reliability, which is difficult to effectively avoid using existing technologies.
By counting the number of pause and restart events in the erase operation and performing a soft programming operation when a threshold is reached, the possibility of over-erase is reduced.
Effectively reduce the over-erasure phenomenon of memory blocks and improve the accuracy and reliability of data reading.
Smart Images
Figure CN120833832A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a memory device and a control method thereof, and more particularly, to a non-volatile memory device and a control method thereof. BACKGROUND
[0002] In an erase operation of a memory block of a memory device, when the number of erase cycles is too many, over-erase phenomenon of the memory block is likely to occur. When a data read operation is performed on the memory block in a case where the over-erase phenomenon occurs in the memory block, data read error can occur due to a leakage current of an over-erased memory cell, and data reliability of the memory device can be reduced. SUMMARY
[0003] The present application is directed to a memory device and a control method thereof, which can prevent over-erase phenomenon from occurring.
[0004] According to an embodiment of the present application, a control method of a memory device includes receiving an erase command, performing an erase operation on a memory block, when a plurality of pause events occur in the erase operation, counting a number of restarts of a plurality of restart events corresponding to the pause events or a number of pauses of the pause events, and when the number of restarts or the number of pauses is greater than or equal to a threshold value in the erase operation, performing a first soft program operation on the memory block.
[0005] According to an embodiment of the present application, a memory device includes a memory block and a logic circuit. The logic circuit is coupled to the memory block. The logic circuit is configured to receive an erase command, perform an erase operation on the memory block, when a plurality of pause events occur in the erase operation, count a number of restarts of a plurality of restart events corresponding to the pause events or a number of pauses of the pause events, and when the number of restarts or the number of pauses is greater than or equal to a threshold value in the erase operation, perform a first soft program operation on the memory block.
[0006] Based on the above, the memory device of the present application can count the number of restarts or the number of pauses of the memory block in the erase operation, and when the number of restarts or the number of pauses reaches or exceeds a predetermined threshold value, perform a soft program operation on the memory block, thereby reducing the possibility of over-erase phenomenon of the memory block. BRIEF DESCRIPTION OF DRAWINGS
[0007] Figure 1 A flowchart showing a memory device control method according to an embodiment of the present application;
[0008] Figure 2 An action flowchart showing a memory device control method according to another embodiment of the present application;
[0009] Figure 3A schematic diagram of a memory device according to an embodiment of the present application. DETAILED DESCRIPTION
[0010] Reference will now be made in detail embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
[0011] Reference will now be made in detail embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. Figure 1 , Figure 1 A flow chart of a memory device control method according to an embodiment of the present application is shown. The control method of the present embodiment is suitable for an erase operation of a memory device. The memory device can be any form of non-volatile memory device. In step S110, the memory device can receive an erase command and perform an erase operation on a memory block selected by the erase command. In step S120, when a plurality of pause events occur during the erase operation, the memory device can count a number of restarts of a restart event performed for the corresponding pause event. Also, in step S130, the memory device can determine whether the number of restarts is greater than or equal to a pre-set threshold value and perform a soft-program operation on the selected memory block when the number of restarts is greater than or equal to the pre-set threshold value.
[0012] When the memory device performs an erase operation on a memory block, the erase operation can be paused due to a requirement of use, thus generating a pause event. When the memory device generates a pause event, the erase operation of the memory device needs to be paused and the memory block is restored to an accessible state. Then, when an access operation on the memory block is completed, the incomplete erase operation of the memory block needs to be restarted to continue the incomplete erase operation of the memory block.
[0013] If the erase operation of the memory block is interrupted too many times, an over-erase phenomenon of the memory block can occur. Therefore, in the present embodiment, an engineer can pre-set a threshold value. In this way, the memory device can count the number of restarts of the erase operation of the memory block by step S120. The memory device can compare the threshold value and the number of restarts and perform an additional soft-program operation by step S130 when the number of restarts is greater than or equal to the threshold value, thus reducing the possibility of the over-erase phenomenon of the memory block.
[0014] The memory block is, for example, a flash memory block. The memory device can have a logic circuit to perform a counting operation of the number of restarts, a comparison operation of the number of restarts and a threshold value, and a control operation of performing a soft programming operation. The logic circuit can be a finite-state machine (FSM) circuit or any other form of logic control circuit without specific limitation.
[0015] In the present embodiment, the memory block can also count the number of pause events that occur during the erasing operation of the memory block and obtain the number of pause events. The memory block can compare the number of pause events with a threshold value and perform a soft programming operation on the memory block when the number of pause events is greater than or equal to the threshold value to reduce the possibility of over-erasing of the memory block.
[0016] The soft programming operation described above is an operation that provides a relatively low programming energy compared to a general programming operation. For example, the soft programming voltage provided in the soft programming operation can be lower than the programming voltage of the general programming operation. In addition, the pulse width of the soft programming voltage provided in the soft programming operation can be shorter than the pulse width of the programming voltage of the general programming operation. In the present embodiment, any form of soft programming operation known to one of ordinary skill in the art can be applied to the present embodiment without specific limitation.
[0017] Please refer to Figure 2 , Figure 2 A flowchart of a control method of a memory device according to another embodiment of the present application is shown. In step S210, the memory device can perform a pre-program operation on a selected memory block. Next, in step S220, the memory device can perform an erasing operation on the selected memory block. In the present embodiment, the erasing operation can be performed by any erasing method of a non-volatile memory known to one of ordinary skill in the art without specific limitation.
[0018] In step S230, the memory device can determine whether a pause command is received and decide whether the erasing operation needs to be paused. When the result of the determination in step S230 is yes, the memory device can stop the erasing operation of the memory block and make the memory block accessible (step S231). When the memory block is accessible, the memory block can provide at least one of a data read operation and a programming operation. When the memory block does not need to provide an access service based on the fact that the erasing operation of the memory block is not completed, the memory block can generate a restart event (step S290) to restart the erasing operation and exit the accessible state.
[0019] Further, when the result of the step S230 is NO, the memory device can determine the relationship between the restart count RC and the threshold N, and when the restart count RC is equal to the threshold N, the step S241 can be performed; when the restart count RC is not equal to the threshold N, the step S250 can be performed. Note that the restart count RC can have an initial value of 0 when the erase operation is initially started. On the other hand, after the step S290 is performed, the memory device can perform the restart counting operation through the step S242, and the restart count RC can be incremented by 1. The threshold N is an integer greater than 0.
[0020] When the restart count RC is incremented to equal the threshold N in the step S240, it indicates that the number of suspend and restart events in the current erase operation of the memory block is too high, and the soft programming operation of the memory block can be performed through the step S241. Through the soft programming operation, the degree of erasure of the memory block can be reduced, and the possibility of over-erase of the memory block can be reduced.
[0021] After the soft programming operation of the step S241 is completed, the step S210 can be entered to perform the incomplete erase operation, and the memory device can reset the restart count RC, for example, to equal 0. Note that the restart count RC of the present embodiment can be incremented from the initial value of 0, and reset to 0 when the restart count RC equals N, corresponding to the completion of the soft programming operation. Therefore, the restart count RC will not be greater than N.
[0022] On the other hand, when the step S240 determines that the restart count RC is not equal to (i.e., less than) the threshold N, the step S250 can be performed to perform the erase verify operation of the memory block. The erase verify operation is used to verify whether the threshold voltage of the erased memory cell has reached a predetermined voltage value. In the present embodiment, any erase verify operation known to those skilled in the art can be applied to the present embodiment without specific limitation.
[0023] When the result of the erase verify operation of the step S250 is failed, it indicates that the erase operation of the memory block is not completed, and the step S220 can be performed to continue the erase operation. On the contrary, when the result of the erase verify operation of the step S250 is passed, it indicates that the erase operation of the memory block is completed, and the step S260 can be performed.
[0024] The soft programming operation can be performed on the memory block whose erase operation is completed in the step S260, and the refresh operation of the memory block can be performed in the step S270. Then, the memory block can be made accessible in the step S280.
[0025] It is worth mentioning that in the present embodiment, the threshold value N can be set by the designer according to the number of restarts corresponding to the possibility of the occurrence of the erase phenomenon in the memory block. The number of restarts can be known through a test action of actually performing the erase and repeated suspend operations on the memory block.
[0026] Please refer to Figure 3 , Figure 3 A schematic diagram of a memory device according to an embodiment of the present application is shown. The memory device 300 includes a memory block 310 and a logic circuit 320. The memory block 310 is coupled to the logic circuit 320. The logic circuit 320 is used to perform the steps of the control method of the memory device 300 in Figure 1 and Figure 2 . The relevant details have been described in the foregoing embodiments, and will not be described here.
[0027] It is worth mentioning that in the present embodiment, the logic circuit 320 can include a counter 321 and a comparator 322. The counter 321 can perform the counting action of the number of restarts RC of the restart event. The comparator 322 is coupled to the counter 321 and is used to compare the number of restarts RC with the threshold value N and perform the soft programming action according to the comparison result.
[0028] In other embodiments of the present application, the counter 321 can also be used to perform the counting action of the number of suspends of the suspend event. The comparator 322 can be used to compare the number of suspends with the threshold value N and perform the soft programming action according to the comparison result.
[0029] The counter 321 and the comparator 322 can be implemented by the counting circuit and the comparison circuit commonly known to those skilled in the art in the digital circuit, without certain limitations.
[0030] It is worth mentioning that the logic circuit 320 can be a state machine circuit. In other embodiments of the present application, the logic circuit 320 can be implemented by a controller. The controller can perform the steps of the control method of the memory device 300 by executing an application. Figure 1 and Figure 2The steps of the control method of the memory device 300 are shown in the flowchart of FIG. 6. The controller can be designed by a hardware description language (HDL) or any other design method of digital circuits known to those skilled in the art, and implemented as a hardware circuit by a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or an application-specific integrated circuit (ASIC).
[0031] In summary, in the erasing operation of the memory blocks, the number of suspensions or restarts is calculated, and compared with a predetermined threshold. When the number of suspensions or restarts reaches a certain number, the soft programming operation of the memory blocks is performed. In this way, the possibility of over-erasing of the memory blocks is reduced, and the accuracy of data reading of the memory device is maintained.
[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalents. The modification or replacement does not change the essence of the corresponding technical solution from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A method for controlling a memory device, comprising: receiving an erase command and performing an erase operation on a memory block; counting a number of restarts corresponding to a number of restart events or a number of pauses corresponding to a number of pause events when a plurality of pause events occur during the erase operation; and performing a first soft program operation on the memory block when the number of restarts or the number of pauses is greater than or equal to a threshold during the erase operation.
2. The method of claim 1, further comprising: starting the counting of the number of restarts or the number of pauses when a first pause event occurs during the erase operation, including: incrementing the number of restarts by one for each of the restart events or incrementing the number of pauses by one for each of the pause events.
3. The method of claim 1, wherein performing the soft program operation on the memory block when the number of restarts or the number of pauses is greater than or equal to the threshold comprises: comparing the number of restarts or the number of pauses to the threshold, and performing the first soft program operation on the memory block when the number of restarts or the number of pauses is equal to the threshold.
4. The method of claim 1, further comprising: performing an erase verify operation on the memory block; completing the erase operation when a result of the erase verify operation is pass; and continuing the erase operation when the result of the erase verify operation is fail.
5. The method of claim 4, further comprising: performing a second soft program operation on the memory block after the erase operation is completed; and performing a refresh operation on the memory block after the second soft program operation is completed.
6. A memory device, comprising: a memory block; and a logic circuit coupled to the memory block and configured to: receive an erase command and perform an erase operation on a memory block; count a number of restarts corresponding to a number of restart events or a number of pauses corresponding to a number of pause events when a plurality of pause events occur during the erase operation; and perform a first soft program operation on the memory block when the number of restarts or the number of pauses is greater than or equal to a threshold during the erase operation.
7. The memory device of claim 6, wherein the logic circuit includes a counter, and the logic circuit is further configured to: start the counting of the number of restarts or the number of pauses when a first pause event occurs during the erase operation; and the counter is configured to increment the number of restarts by one for each of the restart events or increment the number of pauses by one for each of the pause events.
8. The memory device of claim 7, wherein the logic circuit further includes a comparator, and the comparator is configured to compare the threshold to the number of restarts or the number of pauses, and the logic circuit is configured to perform the first soft program operation on the memory block when the number of restarts or the number of pauses is equal to the threshold. 9. The memory device of claim 7, wherein the logic circuit is further to: perform an erase verify action on the memory block; complete the erase action when a result of the erase verify action is a pass; and continue performing the erase action when the result of the erase verify action is a fail.
10. The memory device of claim 9, wherein the logic circuit is further to: perform a second soft program action on the memory block after the erase action is completed; and perform a refresh action on the memory block after the second soft program action is completed.