Method of manufacturing semiconductor device and semiconductor device

Abstract

The embodiment of the invention relates to a method for manufacturing semiconductor equipment and the semiconductor equipment. The write driver writes one of the binary data to the OTP memory cell using the boost voltage or the regulator voltage. The OTP voltage selection register causes the write driver to select one of the two voltages. The trim register holds voltage settings that define amplitudes of the two voltages, respectively. The OTP voltage trimming step is a step of sequentially changing voltage setting values in a high voltage direction while performing write-by-write on the plurality of OTP memory cells using one of two voltage setting values as a trimming target until write-in at the same voltage setting value succeeds successively, writing at the same voltage setting value succeeds in succession at the N OTP memory cells.

Description

[0001] Cross Reference to Related Applications

[0002] The disclosures of U.S. Provisional Application No. 63 / 634,839 filed on April 16, 2024 and Japanese Patent Application No. 2024-184974 filed on October 21, 2024, including specifications, drawings, and abstracts, are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, and, for example, to a technology of a one-time programmable (OTP) memory. Background Art

[0004] The disclosed techniques are listed below.

[0005] [Non-patent document 1] "Highly Reliable Anti-Fuse Technology in sub-16nmTechnologies for Security Applications", 2016 IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

[0006] [Non-patent document 2] "Design Challenges and Solutions of Emerging NonvolatileMemory for Embedded Applications)", 2021 IEEE International Electron Devices Meeting (IEDM)

[0007] [Non-patent document 3] "33.1A 16nm 32Mb Embedded STT-MRAM with a6ns Read-AccessTime, a 1M-Cycle Write Endurance, 20-Year Retention at 150℃ and MTJ-OTPSolutions for Magnetic Immunity)", 2023 IEEE International Solid-State Circuits Conference (ISSCC)

[0008] NPL 1 discloses a logic NVM cell that uses a fuse-protected programming mechanism to achieve high density and excellent data storage lifetime. NPL 2 discloses that trim data or the like is written into a magnetic tunnel junction (MTJ)-OTP memory cell before wafer level chip scale packaging (WLCSP). NPL 3 discloses that a reference current for logically determining a cell current of the MTJ-OTP memory cell is set between a cell current (I P ) in a parallel state and a cell current (I BD ) in a dielectric breakdown state. SUMMARY

[0009] In recent years, in a semiconductor device such as a microcontroller unit (MCU) or a system on chip (SoC), the need to write, for example, security information, boot information, or the like into an OTP in addition to trim data, repair data, or the like is increasing. In this case, for example, it is necessary to increase the capacity of the OTP, such as tens of kB to hundreds of kB. As a method for realizing a large-capacity OTP in a small area, it is beneficial to use an MTJ-OTP memory cell as disclosed in NPL 2 and NPL 3 instead of a fuse-protected OTP as disclosed in NPL 1.

[0010] An MTJ-OTP memory cell is realized by using some memory cells to cause dielectric breakdown of an MTJ element in the memory cells in a spin-torque transfer magnetic RAM (STT-MRAM). At the time of dielectric breakdown of the MTJ element, a higher voltage than that used at the time of normal writing is applied. As a result, there can be a problem of reliability such as a withstand voltage. When the MTJ-OTP memory cell is used to write trim data or the like, the writing to the OTP memory cell is performed in a test step of the STT-MRAM. Therefore, even when a defect occurs due to the writing to the OTP memory cell, the defect can be detected in the test step, and a defective product can be prevented from flowing to a user.

[0011] Further, when the MTJ-OTP memory cell is used to write security information, boot information, or the like, the writing to the OTP memory cell is performed by the user. Therefore, it is necessary to ensure that the user performs a reliable writing operation to the OTP memory cell. In addition, it is necessary to ensure that no defect occurs due to the writing operation to the OTP memory cell performed by the user.

[0012] The embodiments described below were conceived in view of these circumstances, and other problems and novel features will be apparent from the description of the specification and the accompanying drawings.

[0013] According to one embodiment, a method for manufacturing a semiconductor device includes a wafer processing step of forming a nonvolatile memory on a semiconductor wafer and a wafer testing step of testing the semiconductor wafer. The wafer testing step includes an OTP voltage trimming step. In addition to a plurality of word lines, a plurality of bit lines, a plurality of source lines, and a plurality of OTP memory cells, a charge pump circuit, a voltage regulator circuit, a write driver, an OTP voltage selection register, a first trimming register, and a second trimming register are also formed in the nonvolatile memory. The plurality of OTP memory cells include MTJ elements that store binary data depending on the presence or absence of dielectric breakdown. The charge pump circuit generates a boost voltage by boosting a supply voltage. The voltage regulator circuit generates a regulator voltage by gradually reducing the supply voltage. The write driver writes one of the binary data into the OTP memory cells by applying either the boost voltage or the regulator voltage between the bit lines and the source lines. The OTP voltage selection register enables the write driver to select either the boost voltage or the regulator voltage. The first trimming register and the second trimming register respectively maintain a first voltage setting value defining the magnitude of the boost voltage and a second voltage setting value defining the magnitude of the regulator voltage. The OTP voltage trimming step is a step of using one of the first voltage setting value and the second voltage setting value as a voltage setting value to be trimmed and sequentially changing the voltage setting value in a high voltage direction until writing to N OTP memory cells with the same voltage setting value succeeds successively while writing to the plurality of OTP memory cells is performed one by one.

[0014] According to this embodiment, it is possible to ensure that the user can perform a reliable write operation on the MTJ-OTP memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram illustrating a configuration example of a semiconductor device according to one embodiment.

[0016] Figure 2 It's a picture Figure 1 A circuit block diagram showing a schematic configuration example of a nonvolatile memory in FIG.

[0017] Figure 3 It's a picture Figure 2 Schematic diagram of a configuration example and an operation example of a memory cell in .

[0018] Figure 4 is a flowchart illustrating an example of a method of manufacturing a semiconductor device according to one embodiment.

[0019] Figure 5 It's a picture Figure 2 A circuit block diagram of a configuration example of main components focusing on a write operation to the OTP memory area.

[0020] Figure 6 is an example of a flowchart of detailed processing content of the OTP voltage trimming step in Figure 4

[0021] Figure 7 is a schematic diagram of a specific operation example of the flow illustrated in Figure 6

[0022] Figure 8 is a circuit diagram of a detailed configuration example of the voltage regulator circuit in Figure 5

[0023] Figure 9 is a circuit diagram of a schematic configuration example of the charge pump circuit in Figure 5

[0024] Figure 10A is a schematic diagram illustrating a layout configuration example of the OTP memory region in Figure 5

[0025] Figure 10B is a schematic diagram illustrating a layout configuration example of the OTP memory region in Figure 5

[0026] Figure 11 is a flowchart of detailed processing content of the screening step in Figure 4

[0027] Figure 12 is a supplementary view of a part of the processing content in Figure 11

[0028] Figure 13 is a circuit block diagram illustrating a configuration example obtained by modifying Figure 5 DETAILED DESCRIPTION

[0029] In the following embodiments, for the sake of convenience, the description will be divided into a plurality of chapters or embodiments, if necessary, but unless otherwise specified, these chapters or embodiments are not mutually irrelevant, and some or all of the modifications, details, supplementary explanations, etc. of one chapter or embodiment are related to another chapter or embodiment. In addition, in the following embodiments, when referring to the number of elements, etc. (including number, numerical value, quantity, range, etc.), unless otherwise specified or obviously limited to a specific number in principle, the number of elements is not limited to a specific number, and the number of elements can be greater than or equal to or less than or equal to a specific number.

[0030] ​​​​​​​​​Further, in the following embodiments, it is clear that components (including elements, steps, etc.) are not necessarily essential unless otherwise specified or considered inherently essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is assumed that components including substantially similar or analogous shapes, etc. are included unless otherwise specified or otherwise explicitly considered in principle. The above numerical values and ranges apply equally.

[0031] In the following embodiments, a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) and an n-channel MOSFET are referred to as a pMOS transistor and an nMOS transistor, respectively. Hereinafter, various embodiments of the present application are described in detail in conjunction with the drawings. Note that in all the drawings illustrating the embodiments, the same components are denoted by the same reference numerals in principle, and repeated description of these components is omitted.

[0032] <Overview of Semiconductor Device>

[0033] Figure 1 is a schematic diagram illustrating a configuration example of a semiconductor device according to one embodiment. Figure 1 The semiconductor device DEV illustrated in FIG. 1 is, for example, an MCU or an SoC including one semiconductor chip. The semiconductor device DEV includes internal units that are connected to each other via a bus BS. Examples of the internal units include a processor PRC, a volatile memory RAM, a non-volatile memory NVM, and a peripheral circuit PERI.

[0034] The volatile memory RAM is, for example, a static random access memory (SRAM). The non-volatile memory NVM is an STT-MRAM. The processor PRC includes a central processing unit (CPU) and can further include a digital signal processor (DSP), a graphics processing unit (GPU), and the like. The processor PRC executes a predetermined program stored in the STT-MRAM while using, for example, an SRAM as a work memory.

[0035] The peripheral circuit PERI is a circuit provided in accordance with the application of the semiconductor device DEV. Examples of the peripheral circuit PERI include a communication interface, an analog / digital converter, a digital / analog converter, various timer circuits, and various analog circuits. Although not illustrated, the semiconductor device DEV further includes a power supply circuit that generates an internal power supply from an external power supply, a clock generation circuit that generates an internal clock signal, and the like.

[0036] Figure 2 is a circuit block diagram illustrating a schematic configuration example of the non-volatile memory NVM in Figure 1 Figure 3 is a circuit block diagram illustrating a schematic configuration example of the non-volatile memory NVM in Figure 2 ​a configuration example and an operation example of a memory cell in the memory array MARY. As Figure 2 The illustrated non-volatile memory NVM (in particular, STT-MRAM) includes a memory array MARY, a word line control circuit WLC, J (= j + 1) read / write control circuits RWC[0] to RWC[j], and a memory control circuit MCTL. The memory array MARY includes a plurality of word lines WL, a plurality of bit lines BL, a plurality of source lines SL, and a plurality of memory cells MC.

[0037] The plurality of bit lines BL is arranged across the plurality of word lines WL. The plurality of source lines SL is arranged side by side in the plurality of bit lines BL. The plurality of memory cells MC is arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. Here, the memory array MARY includes a normal memory area ARn and an OTP memory area ARo. The normal memory area ARn includes normal memory cells MCn, which are part of the plurality of memory cells MC. The OTP memory area ARo includes OTP memory cells MCo, which are another part of the plurality of memory cells MC.

[0038] However, the normal memory cells MCn and the OTP memory cells MCo are memory cells MC substantially having the same configuration. As Figure 3 As illustrated, the memory cell MC includes a transistor switch TS and an MTJ element ME, which are connected in series between any bit line of the plurality of bit lines BL and any source line of the plurality of source lines SL. Note that, in this example, a configuration in which two bit lines BL share one source line SL is described.

[0039] The transistor switch TS is configured with, for example, an nMOS transistor. One end of the transistor switch TS is connected to the source line SL, and an on / off state of the transistor switch TS is controlled by any word line of the plurality of word lines WL. One end of the MTJ element ME is connected to the bit line BL, and the other end is connected to the transistor switch TS. The MTJ element ME is configured with a free layer FL and a pinned layer PL, which are configured with a magnetic material, and an insulating layer ISL, which is provided between the free layer FL and the pinned layer PL and functions as a tunnel barrier film.

[0040] Here, in the normal memory cell MCn, an anti-parallel (AP) write or a parallel (P) write is performed as a write operation. In the AP write, for example, in a state where 2.0 V is applied to the word line WL, the bit line BL is set to 0 V, and 1.5 V is applied to the source line SL. As a result, a write current flows from the source line SL toward the bit line BL, and the magnetization direction of the fixed layer PL and the magnetization direction of the free layer FL become an anti-parallel state (AP state). As a result, the MTJ element ME enters a high resistance state ("1" level state).

[0041] In the P write, for example, in a state where 1.6 V is applied to the word line WL, the source line SL is set to 0 V, and 1.4 V is applied to the bit line BL. As a result, a write current flows from the bit line BL toward the source line SL, and the magnetization direction of the fixed layer PL and the magnetization direction of the free layer FL enter a parallel state (P state). As a result, the MTJ element ME enters a low resistance state ("0" level state). In a read operation, for example, in a state where 1.1 V is applied to the word line WL, the source line SL is set to 0 V, and 0.2 V is applied to the bit line BL. A read current of different amplitudes flows through the memory cell MC according to the AP state or the P state. A determination of binary data is performed based on the difference in the read current.

[0042] Further, in the OTP memory cell MCo, that is, in the MTJ-OTP memory cell, an OTP write is performed as a write operation. In the OTP write, for example, in a state where 2.0 V is applied to the word line WL, the source line SL is set to 0 V, and 2.5 V is applied to the bit line BL. As a result, dielectric breakdown occurs in the insulating layer ISL. As a result, the MTJ element ME enters an irreversible dielectric breakdown state (BD state) and another low resistance state ("0" level state).

[0043] The MTJ element ME in the OTP memory cell MCo stores binary data depending on the presence or absence of dielectric breakdown (i.e., the AP state / P state or the BD state). Note that, in the OTP write, a larger write current is required compared to the AP write or the P write. Therefore, more specifically, unlike the normal memory cell MCn, the OTP memory cell MCo can be configured with a plurality of transistor switches TS connected in parallel.

[0044] Returning to Figure 2The memory control circuit MCTL inputs a command signal CMD, an address signal ADR, and the like, and controls the entire nonvolatile memory NVM in accordance with the input contents. In particular, the memory control circuit MCTL performs control so that J bits of a data signal DT[0:j] (DTi[0:j]) from the outside can be written to the memory cells MC specified by the address signal ADR in accordance with a write command signal CMD. Further, the memory control circuit MCTL performs control so that J bits of a data signal DT[0:j] (DTi[0:j]) from the memory cells MC specified by the address signal ADR can be read to the outside in accordance with a read command signal CMD.

[0045] The word line control circuit WLC controls activation / deactivation of the plurality of word lines WL. In particular, the word line control circuit WLC includes an address decoder ADEC and a word line driver WLD. The address decoder ADEC selects any of the plurality of word lines WL based on the address signal ADR. The word line driver WLD applies a predetermined voltage to a selected word line WL to activate the word line WL in accordance with the contents of the command signal CMD, as described with reference to Figure 3 Figure 3 As illustrated, the word line driver WLD can apply a negative voltage to unselected word lines WL.

[0046] The J read / write control circuits RWC[0] to RWC[j] are provided, which correspond to J bits of the data signal DT[0] to DT[j], respectively. Each of the read / write control circuits RWC[0] to RWC[j] drives a predetermined number of bit lines BL and source lines SL assigned to the read / write control circuit. As a result, each of the read / write control circuits RWC[0] to RWC[j] controls a read operation and a write operation with respect to the memory cells MC connected to the predetermined number of bit lines BL and source lines SL.

[0047] Each of the read / write control circuits RWC[0] to RWC[j] includes a column selector CSEL, a sense amplifier SA, and a write driver WTD. Here, the read / write control circuit RWC[0] is described as a representative example. The column selector CSEL selects any of the bit lines BL and the source lines SL from the predetermined number of bit lines BL and source lines SL, for example, based on a signal from the address decoder ADEC and the address signal ADR. Then, the column selector CSEL connects the selected bit line BL and the source line SL to the global bit line GBL and the global source line GSL, respectively.

[0048] ​In a write operation of the data signal DT[0] (DTi[0]), the write driver WTD applies a predetermined voltage as described with reference to FIG. 2 via the global bit line GBL and the global source line GSL between the selected bit line BL and the source line SL. As a result, a write current flows between the global bit line GBL and the global source line GSL via the memory cell MC to be written. The write driver WTD determines the binary data in the data signal DT[0] (DTi[0]) by amplifying a difference between the write current and a predetermined reference current. Figure 3 Note that, more specifically, the write driver WTD includes a bit line driver that drives the bit line BL and a source line driver that drives the source line SL.

[0049] In a read operation of the data signal DT[0] (DTo[0]), the sense amplifier SA applies a predetermined voltage as described with reference to FIG. 2 via the global bit line GBL and the global source line GSL between the selected bit line BL and the source line SL. As a result, a read current flows between the global bit line GBL and the global source line GSL via the memory cell MC to be read. The sense amplifier SA determines the binary data in the data signal DT[0] (DTo[0]) by amplifying a difference between the read current and a predetermined reference current. Figure 3

[0050] Note that, Figure 2 FIG. 2 illustrates a configuration example in which the bit line BL is shared by the normal memory area ARn and the OTP memory area ARo. However, the nonvolatile memory NVM can have a configuration in which the bit line BL is separated between the normal memory area ARn and the OTP memory area ARo. That is, the nonvolatile memory NVM can include, for example, a plurality of divided memory arrays MARY, and the OTP memory area ARo can be a part of the plurality of memory arrays MARY.

[0051] <Method of manufacturing semiconductor device>

[0052] Figure 4 is a flowchart illustrating an example of a method of manufacturing a semiconductor device according to one embodiment. The flow includes a wafer processing step (step S101), a wafer testing step (step S102), a packaging step (step S103), a shipping test step (step S104), a manufacturing step performed by a primary customer (step S105), a shipping test step (step S106), and a use step performed by an end customer (step S107). The flow from step S101 to step S104 is a flow performed by a semiconductor manufacturer. Further, the flow from step S105 to step S107 is a flow performed by a user.

[0053] The wafer processing step (step S101) is a step of forming a plurality of semiconductor devices DEV including, for example, as described with reference to FIG. 1, on a semiconductor wafer using various semiconductor manufacturing apparatuses. Figure 1 and Figure 2 ​The illustrated non-volatile memory NVM. The wafer test step (step S102) is a step of testing a semiconductor wafer on which a plurality of semiconductor devices DEV are formed, using a probe inspection apparatus. As described in more detail below, the wafer test step (step S102) includes an OTP voltage trimming step (step S102a) and a screening step (step S102b).

[0054] The packaging step (step S103) is a step of dividing the semiconductor wafer into a plurality of semiconductor devices DEV using a dicing apparatus and assembling the semiconductor devices DEV into packages using an assembly apparatus, the semiconductor devices DEV being determined to be non-defective products in the wafer test step (step S102). The shipping test step (step S104) is a step of testing the packaged semiconductor devices DEV using a semiconductor tester. Then, the semiconductor devices DEV determined to be non-defective products in the test are shipped to a main customer.

[0055] The manufacturing step (step S105) performed by the main customer is a step of manufacturing an intermediate product by mounting the shipped semiconductor devices DEV on a printed circuit board or the like together with other components. The shipping test step (step S106) is a step of testing the intermediate product. Then, the intermediate product determined to be a non-defective product in the test is shipped to an end customer. The use step (step S107) performed by the end customer is a step of assembling a final product including the intermediate product and subsequently using the final product as appropriate.

[0056] Here, Figure 2 The illustrated OTP memory region Aro is used to write trimming data, repair data, and the like. The repair data is, for example, data for replacing a word line WL or a bit line BL determined to be defective in the wafer test step (step S102) with a redundant word line or bit line provided in a redundant region. The trimming data, repair data, and the like are written in the wafer test step (step S102).

[0057] In the wafer test step, any external supply voltage Vcc can be applied to the semiconductor devices DEV from the probe inspection apparatus. Therefore, a high voltage required for writing to the OTP memory region ARo can be ensured. Furthermore, since writing (i.e., application of a high voltage to a bit line BL), for example, a defect can occur in a normal memory region ARn or the like. However, such a defect can be detected in the wafer test step (step S102) or the shipping test step (step S104). Therefore, semiconductor devices DEV to be defective products can be prevented from flowing out to a main customer.

[0058] Further, in recent years, in addition to trimming data, repair data, and the like in the OTP memory region ARo, there is an increasing demand for writing, for example, security information, boot information, and the like. In particular, examples of the security information include a "rollback prevention counter" for preventing a rollback attack that rolls back a version of a communication protocol. Examples of the boot information include a first stage boot loader (FSBL) that is code that is first executed immediately after startup.

[0059] These security information, boot information, and the like need to be written not only in the wafer test step (step S102) but also in the manufacturing step (step S105) performed by the primary customer or the usage step (step S107) performed by the end customer. At the same time, the following three points can be major problems. As a first problem: (A) Unlike a semiconductor manufacturer, a user (i.e., the primary customer or the end customer) cannot always apply any external supply voltage Vcc to the semiconductor device DEV. Therefore, there is a concern that a high voltage necessary for writing to the OTP memory region ARo cannot be ensured. For example, in Figure 3 , when the external supply voltage Vcc is lower than 2.5 V, the necessary high voltage cannot be ensured.

[0060] As a second problem: (B) Assuming that the user writes to the OTP memory region Aro, the write voltage used at that time is not necessarily appropriate. Therefore, in consideration of manufacturing variations of the semiconductor wafer, it is necessary to determine in advance an appropriate write voltage that is neither too small nor too large. In combination of (A) and (B), the semiconductor manufacturer must guarantee in advance that the user performs a reliable write operation to the MTJ-OTP memory cell.

[0061] As a third problem: (C) When the user writes to the OTP memory cell MCo, it is highly likely that a defect occurs in another memory cell MC that shares the bit line BL with the OTP memory cell MCo due to application of a high voltage to the bit line BL. Unlike the semiconductor manufacturer, the occurrence of this defect itself is a problem for the user. Therefore, the semiconductor manufacturer must guarantee in advance that such a defect does not occur.

[0062] As a complement to (A) to (C), first, in the wafer test step (step S102), the write voltage can be determined in an arbitrary manner. Therefore, for example, by using a slightly excessive write voltage or the like, it is possible to reliably perform writing in the OTP memory region ARo. Even if a defect occurs due to such a write voltage in, for example, a normal memory region ARn or the like, it is possible to repair the semiconductor device or exclude the semiconductor device as a defective product. Therefore, unlike the user, as long as the semiconductor manufacturer performs writing in the OTP memory region ARo, no specific problem occurs.

[0063] <Write operation to OTP memory area>

[0064] Figure 5 is a circuit block diagram illustrating a configuration example of main components focusing on a write operation to an OTP memory area ARo in Figure 2 Figure 5 An OTP memory area ARo having OTP memory cells Mco, J read / write control circuits RWC[0] to RWC[j] that perform a write to the OTP memory cells Mco, and a memory control circuit MCTL that controls the write operation are illustrated. In this specification, the J read / write control circuits RWC[0] to RWC[j] are collectively referred to as a read / write control circuit RWC.

[0065] The memory control circuit MCTL includes an input buffer IBF, an OTP voltage selection register REGoh, a write number selection register REGom, a write controller MWC, a voltage regulator circuit VREG, a trimming register REGtr, a charge pump circuit CP, and a trimming register REGtc. The input buffer IBF includes, for example, J flip-flops FFi[0] to FFi[j]. As a result, the input buffer IBF latches J bits of data signals DTi[0:j] input from the outside.

[0066] The charge pump circuit CP generates a boosted voltage Vcp by boosting an input supply voltage (here, an external supply voltage Vcc). The trimming register (first trimming register) REGtc holds a voltage setting value (first voltage setting value) SV1 that defines an amplitude of the boosted voltage Vcp. The voltage regulator circuit VREG generates a regulator voltage Vrg by gradually lowering the external supply voltage Vcc. The trimming register (second trimming register) REGtr holds a voltage setting value (second voltage setting value) SV2 that defines an amplitude of the regulator voltage Vrg. Note that details of the OTP voltage selection register REGoh, the write number selection register REGom, and the write controller MWC are described below.

[0067] The memory area ARo includes “m+1” word lines WL[0] to WL[m]. In addition, the memory area ARo includes “n+1” bit lines BL[0] to BL[n] and “k+1” (= (n+1) / 2) source lines SL[0] to SL[k] for one read / write control circuit RWC. Therefore, the memory area ARo includes “(m+1)*(n+1)” OTP memory cells MCo for one read / write control circuit RWC. Examples of these OTP memory cells include n = 31 and k = 15.

[0068] ​The read / write control circuit RWC includes a column selector CSEL, a write driver WTD, and a write logic circuit WLGC. As Figure 2 As described, the column selector CSEL selects one bit line BL from among "n+1" bit lines BL[0] to BL[n]. The write driver WTD (here, a bit line driver) applies a boosted voltage Vcp or a regulator voltage Vrg to the selected bit line BL via a global bit line GBL.

[0069] That is, the write driver WTD applies the boosted voltage Vcp or the regulator voltage Vrg between the selected bit line BL and the source line SL in a state where 0 V is applied to the source line SL by a source line driver (not shown). As a result, the write driver WTD writes one of binary data (for example, a "0" level) to the OTP memory cell MCo connected to the selected word line WL and the selected bit line BL.

[0070] The write driver WTD includes, for example, an nMOS transistor MNcl for clamping and two pMOS transistors MPc and MPr for voltage selection. The nMOS transistor MNcl inputs an external supply voltage Vcc to a drain and inputs a regulator voltage Vrg to a gate. As a result, the nMOS transistor MNcl outputs the regulator voltage Vrg from a source, in particular, the regulator voltage Vrg plus a drop value of a threshold voltage.

[0071] The pMOS transistor MPc inputs a boosted voltage Vcp to a source. The pMOS transistor MPr receives the regulator voltage Vrg from the nMOS transistor MNcl to a source. The on / off states of the pMOS transistors MPc and MPr are controlled by enable signals ENc and ENr, respectively. The enable signals ENc and ENr are controlled so that only one of the enable signals ENc and ENr is an "L" pulse signal, that is, an on pulse signal, having a predetermined write pulse width. Alternatively, both of the enable signals ENc and ENr are controlled to maintain an "H" level, that is, an off level.

[0072] The write logic circuit WLGC includes a flip-flop FFw and various logic gates that control the enable signals ENc and ENr using an output of the flip-flop FFw as an input. When the flip-flop FFw maintains an "L" level, the write logic circuit WLGC controls both of the enable signals ENc and ENr to an "H" level, that is, an off level. In addition, when the flip-flop FFw maintains an "H" level, the write logic circuit WLGC controls one of the enable signals ENc and ENr to an "L" level, that is, an on level, and controls the other enable signal to an "H" level, that is, an off level.

[0073] Accordingly, by appropriately controlling the value of the flip-flop FFw, the write logic circuit WLGC can perform control so that only one of the enable signals ENc and ENr becomes an "L" pulse signal. The write controller MWC in the memory control circuit MCTL appropriately controls the value of the flip-flop FFw based on the data signal DTi[0:j] latched in the input buffer IBF.

[0074] As one particular example, when the data signal DTi[0] is at the "0" level, the write controller MWC controls the value of the flip-flop FFw of the read / write control circuit RWC[0] in an appropriate manner. As a result, one of the enable signals ENc and ENr becomes an "L" pulse signal. Further, when the data signal DTi[0] is at the "1" level, the write controller MWC writes an "L" level to the flip-flop FFw of the read / write control circuit RWC[0]. As a result, both of the enable signals ENc and ENr maintain the "H" level.

[0075] Here, the OTP voltage selection register REGoh in the memory control circuit MCTL holds a selection value HVCC that defines the voltage supply source. Which of the enable signals ENc and ENr is controlled to be an "L" pulse signal is defined by the value of the selection value HVCC. That is, the OTP voltage selection register REGoh causes the write driver WTD to select the booster voltage Vcp or the regulator voltage Vrg via the write logic circuit WLGC.

[0076] In this example, when the selection value HVCC is at the "H" level, the enable signal ENr becomes an "L" pulse signal via the write logic circuit WLGC. As a result, the write driver WTD selects the regulator voltage Vrg. Further, when the selection value HVCC is at the "L" level, the enable signal Enc becomes an "L" pulse signal via the write logic circuit WLGC. As a result, the write driver WTD selects the booster voltage Vcp.

[0077] Note that, when the regulator voltage Vrg is selected, the write driver WTD can flow a large write current through the external supply voltage Vcc. In this case, the write drivers WTD in the J read / write control circuits RWC can perform simultaneous writing to the J OTP memory cells Mco. Further, when the booster voltage Vcp is selected, the write driver WTD can flow only a certain write current due to the current supply capability of the charge pump circuit CP. In this case, the number of simultaneous writings is K, which is smaller than J, for example, K = 4 or less.

[0078] However, the current supply capability of the charge pump circuit CP can vary depending on the amplitude of the external power supply voltage Vcc input to the charge pump circuit CP. For example, in the case of "Vcc < 2.0V", K = 1. Also, in the case of "2.0V < Vcc < 2.5V", for example, K = 2 or K = 4. From the viewpoint of shortening the time required for writing, the number of simultaneous writes is preferably as large as possible.

[0079] Therefore, in Figure 5 when the boosted voltage Vcp is selected, a write number selection register REGom for selecting whether the number of simultaneous writes is 1 or K (K is 2 or more) is provided. The write number selection register REGom holds a selection value MVCC which defines the number of simultaneous writes. For example, in the case of "Vcc < 2.0V", the selection value MVCC is defined to be an "L" level. Also, in the case of "2.0V < Vcc < 2.5V", the selection value MVCC is defined to be an "H" level. Note that the OTP voltage selection register REGoh and the write number selection register REGom can also be configured with another bit in one register.

[0080] The selection values HVCC and MVCC are defined in an arbitrary manner by the semiconductor manufacturer or the user. In particular, in Figure 4 In the illustrated wafer test step (step S102), for example, the semiconductor manufacturer can determine the selection values HVCC and MVCC via a probe inspection apparatus, test terminals, or the like. Also, in the manufacturing step performed by the main client (step S105) or the use step performed by the end client (step S107), the user can define the selection values HVCC and MVCC, for example, via the processor PRC and the bus BS.

[0081] At this time, the user can define the selection values HVCC and MVCC based on the amplitude of the external power supply voltage Vcc to be used. As one example, when the external power supply voltage Vcc is somewhat higher than 2.5V, the user can define the selection value HVCC for the voltage supply source to be an "H" level. Also, in the case of "2.0V < Vcc < 2.5V", the user can define the selection value HVCC for the voltage supply source to be an "L" level and the selection value MVCC for the number of simultaneous writes to be an "H" level, respectively. In the case of "Vcc < 2.0V", the user can define the selection value HVCC to be an "L" level and the selection value MVCC to be an "L" level.

[0082] The write controller MWC controls the number of simultaneous writes to the OTP of the memory area ARo in accordance with the selection values HVCC and MVCC. In particular, when the selection value HVCC is at the "H" level, the write controller MWC controls the flip-flops FFw in, for example, J read / write control circuits RWC[0] to RWC[j] in parallel based on J bits of the data signal DTi[0:j].

[0083] Further, when the selection value HVCC is at the "L" level, the write controller MWC controls the flip-flops FFw in K read / write control circuits RWC in parallel based on K bits of the corresponding data signal DTi. At this time, the write controller MWC defines the value of K based on the selection value MVCC.

[0084] As described above, in the configuration example of Figure 5 In the configuration example of

[0085] Further, by providing the OTP voltage selection register REGoh, the user can set to select the boost voltage Vcp or the regulator voltage Vrg. As one particular example, when the user can ensure the desired external supply voltage Vcc, it is preferable to have the write driver WTD select the regulator voltage Vrg. As a result, since it is possible to increase the number of simultaneous writes compared to the case of using the boost voltage Vcp, it is possible to shorten the time required for writing. Further, by providing the write number selection register REGom, it is possible to reduce the time required for writing as little as possible even when the boost voltage Vcp is used.

[0086] Further, by providing the trimming registers REGtr and REGtc, it is possible to determine in advance (B) the appropriate write voltage required when the user writes in the OTP memory area ARo. More particularly, in the configuration example of Figure 4 In the illustrated OTP voltage trimming step (step S102a), the appropriate write voltage is defined by appropriately operating the trimming registers REGtr and REGtc as described below.

[0087] <Details of the OTP voltage trimming step>

[0088] Figure 6 is a flowchart illustrating an example of the detailed processing contents of the OTP voltage trimming step (step S102a) in Figure 4 is a flowchart illustrating an example of the detailed processing contents of the OTP voltage trimming step (step S102a) inFigure 7 is a diagram illustrating a specific example of the operation of the flow illustrated in Figure 6 The specific operation example of the flow illustrated is as follows. In the OTP voltage adjustment step (step S102a), at least one of the first voltage setting value SV1 held by the trimming register REGtc and the second voltage setting value SV2 held by the trimming register REGtr is set to the voltage setting value SV to be trimmed. In the OTP voltage trimming step, the writing to the plurality of OTP memory cells MCo is performed one by one.

[0089] Then, as illustrated in Figure 7 , among the N (N is an integer of 2 or more) OTP memory cells MCo out of the plurality of OTP memory cells MCo, the voltage setting value SV is sequentially changed by +1 in the high voltage direction until the writing with the same voltage setting value SV is successively successful. In particular, as illustrated in Figure 7 , when the OTP writing fails, the voltage setting value SV is changed. In addition, in order to eliminate the influence of the accumulation of the OTP writing, the OTP address Ao (i.e., the OTP memory cell MCo to be written) is also changed.

[0090] In addition, when the OTP writing is successful, only the OTP address Ao is changed while the voltage setting value SV is maintained. Then, such processing is repeatedly performed until the OTP writing is successively successful N times. When the OTP writing is successively successful N times, a predetermined margin "+M" in the high voltage direction is added to the current voltage setting value SV so as to ensure a more reliable success in a range in which the voltage does not become excessive. The value of +M can be, for example, a small value such as +1 or +2. The voltage setting value SV to which the margin is added is the trimming result of the first voltage setting value SV1 or the second voltage setting value SV2.

[0091] Figure 6 The flow illustrated is performed using, for example, a probe inspection device. In Figure 6 , first, the probe inspection device performs an initial setting on the nonvolatile memory NVM (step S201). By the initial setting, the nonvolatile memory NVM is set to, for example, a trimming-for-test mode in which the voltage setting value SV can be changed in an arbitrary manner. In the trimming-for-test mode, the OTP writing is performed bit by bit using an OTP test region provided in the OTP memory region ARo. In this case, the OTP address Ao indicates one OTP memory cell MCo out of the plurality of OTP memory cells MCo, and the one OTP memory cell MCo is defined as a target OTP memory cell MCo.

[0092] As one specific example, in Figure 5In this case, assume that the region of the plurality of OTP memory cells MCo connected to the word line WL[0] is an OTP test region. In this case, for example, the probe inspection device sequentially controls the address signal to the column selector CSEL while setting only one bit of the data signal DTi[0] among the data signals DTi[0:j] to the "0" level. As a result, the OTP write to the "n+1" OTP memory cells MCo allocated to the column selector CSEL in the read / write control circuit RWC[0] is performed bit by bit. Thereafter, for example, similar processing can be performed while only the data signal DTi[l] is set to the "0" level.

[0093] In Figure 6 In this case, after the step S201, the probe inspection device defines the voltage setting value SV to an initial value (e.g., the minimum value) and defines the OTP address Ao to an initial value (step S202). Subsequently, the probe inspection device causes the nonvolatile memory NVM to perform the OTP write of one bit (step S203). That is, the nonvolatile memory NVM performs the write to the target OTP memory cell MCo specified by the OTP address Ao using the current voltage setting value SV.

[0094] Next, the probe inspection device causes the nonvolatile memory NVM to perform the read operation of the target OTP memory cell MCo. Then, the probe inspection device determines whether the write (i.e., the dielectric breakdown (BD)) in the target OTP memory cell MCo is successful based on the read data signal DT[0:j] (step S204).

[0095] Here, when the determination result in the step S204 fails ("No"), the probe inspection device clears the number of consecutive successes held (step S205). Then, the probe inspection device changes the voltage setting value SV in the high voltage direction (step S206), changes the OTP address Ao (i.e., the target OTP memory cell MCo), and returns to the step S203 (step S207).

[0096] Further, when the determination result in the step S204 succeeds ("Yes"), the probe inspection device up-counts the number of consecutive successes held (step S208). Then, when the number of consecutive successes does not reach the value N (step S209: No), the probe inspection device changes the OTP address Ao (i.e., the target OTP memory cell MCo) and returns to the step S203. When the number of consecutive successes reaches the value N (step S209: Yes), the probe inspection device adds the margin in the high voltage direction to the current voltage setting value SV (step S210).

[0097] As a result, the probe inspection apparatus confirms the voltage setting value SV added with the margin as a trimming result of one of the first voltage setting value SV1 or the second voltage setting value SV2. The voltage setting value SV confirmed as the trimming result is written in a trimming data storage area provided in the OTP memory area ARo. The semiconductor apparatus DEV loads the voltage setting value SV (i.e., the trimming value) written in the trimming data storage area to one of the trimming registers REGtc and REGtr at the time of normal activation.

[0098] By using the OTP voltage trimming step as described above, it is possible to define the appropriate write voltage required at this time under the premise that the user performs the writing to the OTP memory area ARo. That is, it is possible to define the appropriate write voltage that is neither too small nor too large, taking into account the manufacturing variation of the semiconductor wafer. As a result, it is possible to ensure the reliable write operation of the MTJ-OTP memory cell by the user in advance by the semiconductor manufacturer. Note that, for example, the OTP voltage trimming step can be performed on all semiconductor apparatuses DEV, or the OTP voltage trimming step can be performed on a plurality or one of the semiconductor apparatuses DEV defined as representative for each semiconductor wafer.

[0099] <Details of voltage regulator circuit and charge pump circuit>

[0100] Figure 8 is a circuit diagram illustrating a detailed configuration example of the voltage regulator circuit VREG in Figure 5 Figure 8 The illustrated voltage regulator circuit VREG includes a reference voltage generation circuit VREFG, a regulator voltage generation circuit VRGG, and a selection circuit SELv2. The reference voltage generation circuit VREFG includes a pMOS transistor MP1, a resistive divider circuit RDIV, and an amplifier circuit AMP1.

[0101] The pMOS transistor MP1 and the resistive divider circuit RDIV are connected in series between an external supply voltage Vcc and a ground supply voltage GND. The amplifier circuit AMP1 controls the gate voltage of the pMOS transistor MP1 so that the voltage at a fixed voltage node in the resistive divider circuit RDIV matches the bandgap voltage Vbg. As a result, the resistive divider circuit RDIV outputs a plurality of reference voltages Vref <p:0>the plurality of reference voltages Vref <p:0>have different voltage values with constant step width. The selection circuit SELv2 outputs a plurality of reference voltages Vref based on the voltage setting value SV2 from the trimming register REGtr <p:0>any of the reference voltages Vref <p:0>a reference voltage Vref2.

[0102] The regulator voltage generation circuit VRGG includes an nMOS transistor MNcIR, a pMOS transistor MPrR, a current source CS, and an amplifier circuit AMP2. The nMOS transistor MNcIR, the pMOS transistor MPrR, and the current source CS are connected in series between an external supply voltage Vcc and a ground supply voltage GND. The amplifier circuit AMP2 controls a gate voltage of the nMOS transistor MNcIR so that a voltage of a node Ngbl serving as a drain of the pMOS transistor MPrR matches a reference voltage Vref2 from the selection circuit SELv2. Meanwhile, the amplifier circuit AMP2 outputs the gate voltage as a regulator voltage Vrg.

[0103] The nMOS transistor MNcIR and the pMOS transistor MPrR are respectively Figure 5 The nMOS transistor MNcIR and the pMOS transistor MPrR are respectively

[0104] Thus, the node Ngbl can be regarded as a replica node of the global bit line GBL. As a result, the amplifier circuit AMP2 outputs, as the regulator voltage Vrg, a gate voltage of the nMOS transistor MNcIR required to match a voltage of the global bit line GBL with the reference voltage Vref2. Note that the pMOS transistor MPrR can be fixed, for example, to an ON state.

[0105] Figure 9 is a circuit diagram illustrating Figure 5 a schematic configuration example of a charge pump circuit CP in Figure 8 , a reference voltage generation circuit VREFG similar to the reference voltage generation circuit VREFG in the case of Figure 9 The illustrated charge pump circuit CP further includes a selection circuit SELv1, a charge pump control circuit CPCT, and a booster circuit BSTC. The reference voltage generation circuit VREFG outputs a plurality of reference voltages Vref <p:0>The reference voltage generation circuit VREFG can be shared with Figure 8 the illustrated voltage regulator circuit VREG.

[0106] The selection circuit SELv1 outputs a plurality of reference voltages Vref based on a voltage setting value SV1 from the trimming register REGtc <p:0>Any reference voltage therein is used as the reference voltage Vref1. Here, the trimming register REGtc includes two trimming registers REGtc1 and REGtc2. The trimming register (third trimming register) REGtc1 holds the voltage setting value SV1a when the selection value MVCC is at the "L" level (i.e., when the number of simultaneous writes is 1). The trimming register (fourth trimming register) REGtc2 holds the voltage setting value SV1b when the selection value MVCC is at the "H" level (i.e., when the number of simultaneous writes is K (K is 2 or greater)).

[0107] Two voltage setting values SV1a and SV1b from the two trimming registers REGtc1 and REGtc2 are selected by the selection circuit SELm. That is, the selection circuit SELm selects one of the two voltage setting values SV1a and SV1b based on the selection value MVCC, and outputs the selected voltage setting value to the selection circuit SELv1 as the voltage setting value SV1.

[0108] The booster circuit BSTC has a configuration in which, for example, multiple booster stages including diodes and capacitors are connected in cascade. The booster circuit BSTC generates the boosted voltage Vcp by alternately repeating the charging of the capacitor and the boosting operation of the capacitor. The charge pump control circuit CPCT controls, for example, the activation / deactivation of the booster circuit BSTC so that the boosted voltage Vcp (specifically, the voltage obtained by resistively dividing the boosted voltage Vcp) matches the reference voltage Vref1 from the selection circuit SELv1.

[0109] Here, in order to obtain Figure 8 the trimming value of the illustrated voltage setting value SV2, for example, it can be performed in a state where an external supply voltage Vcc higher than 2.5V is applied and the selection value HVCC is set to the "H" level Figure 6 for the illustrated process. In addition, in order to obtain Figure 9 the trimming value of the illustrated voltage setting value SV1a, for example, it can be performed in a state where an external supply voltage Vcc lower than 2.0V is applied and the selection value HVCC is set to the "L" level Figure 6 for the illustrated process.

[0110] In addition, in order to obtain Figure 9 the trimming value of the illustrated voltage setting value SV1b, for example, it can be performed in a state where an external supply voltage Vcc of "2.0V < Vcc < 2.5V" is applied and the selection value HVCC is set to the "L" level Figure 6 for the illustrated process. In this case, instead of writing in units of one bit, writing is performed in units of K bits of 2 or greater Figure 6 The illustrated process.

[0111] However, in some cases, any of the three trimming values among the voltage setting values SV2, SV1a, and SV1b can also be obtained by conversion without performing Figure 6 the illustrated process or a similar process three times. That is, when the correlation between the three trimming values is known in advance, for example, the remaining two trimming values can be calculated from one trimming value. For example, the correlation is obtained by using pre-evaluated statistical data.

[0112] <OTP memory region>

[0113] Figure 10A and Figure 10B is a schematic diagram illustrating an example of the layout configuration of the OTP memory region ARo in Figure 5 . In the example illustrated in Figure 10A , as illustrated in Figure 2 , a plurality of divided memory arrays are provided, and one of the plurality of memory arrays is the OTP memory region ARo. The plurality of memory arrays are divided by the formation region of the sense amplifier SA or the formation region of the write driver WTD.

[0114] The OTP memory region ARo includes an OTP user region ARoU and an OTP test region ARoT. The OTP user region ARoU is configured using a part of the plurality of OTP memory cells MCo and is a region that can be freely used by the user. In addition, the OTP test region ARoT is a region configured using the other part of the plurality of OTP memory cells MCo and is used for Figure 6 the OTP voltage trimming step (step S102a) illustrated in

[0115] Here, the OTP test region ARoT is set at a position separated from the write driver WTD compared to the OTP user region ARoU. That is, the OTP user region ARoU is assigned to the word line WL on the side closer to the write driver WTD. That is, the OTP test region ARoT is assigned to the word line WL on the side farther from the write driver WTD.

[0116] By using this arrangement, the write path WPt from the write driver WTD to the OTP test area ARoT becomes longer than the write path WPu to the OTP user area ARoU. Thus, the write voltage required for the OTP write to the OTP test area AroT becomes higher than the write voltage required for the OTP write to the OTP user area ARoU. As a result, the write operation to the OTP user area ARoU can be more reliably guaranteed by using the write voltage defined in the OTP voltage trimming step (step S102a).

[0117] In Figure 10B the illustrated layout configuration example, unlike the case of Figure 10A , the switch SW for connecting the source line SL to the ground supply voltage GND is provided in the formation region of the sense amplifier SA. In this case, as the write paths WPt and WPu, the paths from the OTP memory cell MCo toward the sense amplifier SA are added to the paths from the OTP memory cell MCo back to the write driver WTD, similar to the case of Figure 10A . Even in this case, generally, since the required write voltage is defined mainly on the paths from the write driver WTD to the OTP memory cell MCo, it is advantageous to use the same arrangement.

[0118] Note that, in the memory array, a dummy word line WL that is not originally used can be provided at the boundary portion with the write driver WTD and at the boundary portion with the sense amplifier SA. The dummy word line WL can be allocated to the OTP test area ARoT. This can reduce the area overhead. In Figure 10A and Figure 10B the illustrated examples, another memory array of the plurality of memory arrays is a normal memory area ARn described with reference to Figure 2 . The normal memory area ARn is configured with a user area AR-U that can be freely used by a user together with the OTP user area ARoU.

[0119] <Details of the screening step>

[0120] Figure 11 is a flowchart illustrating an example of the detailed processing content of the screening step (step S102b) in Figure 4 . The flow illustrated in Figure 12 is a supplemental view illustrating a part of the processing content in Figure 11 . The flow illustrated in Figure 11 is performed using, for example, a probe inspection device.

[0121] First, the probe inspection apparatus causes a trimming register REGtr such as a nonvolatile memory NVM to hold a voltage setting value SV2 as a trimming result in an OTP voltage trimming step (step S102a) (step S301). Next, the nonvolatile memory NVM performs a write to the OTP memory cells MCo in the OTP test area ARoT such that an OTP voltage based on the voltage setting value SV2 (i.e., a write voltage) is applied to all bit lines BL to which the plurality of OTP memory cells MCo are connected based on an instruction from the probe inspection apparatus (step S302).

[0122] Here, Figure 12 a layout configuration example similar to that in Figure 10A However, here, unlike the case in Figure 10A , a manufacturer area ARoM is also added to the OTP memory area ARo. For example, trimming data or the like is written to the manufacturer area ARoM. The voltage setting value SV2 as a trimming result in the OTP voltage trimming step (step S102a) can be written to the manufacturer area ARoM, for example, before the screening step (step S102b).

[0123] In the example illustrated in Figure 12 , the voltage setting value SV2 as a trimming result is written to the area AR1. In this case, the boosted voltage Vcp or the regulator voltage Vrg defined in the OTP voltage trimming step (step S102a) has been applied to the bit lines BL included in the area AR1, particularly, the bit lines BL on which a write is performed at the "0" level. Therefore, the OTP memory cells MCo in the OTP test area ARoT to be written in step S302, and the bit lines BL can be the OTP memory cells MCo in the area AR2 other than the bit lines BL included in the area AR1. Therefore, it is possible to shorten the test time.

[0124] Subsequently, the nonvolatile memory NVM performs a P write or an AP write to the memory cells MC for a user based on an instruction from the probe inspection apparatus (step S303), the memory cells MC for the user being connected to all the bit lines BL to which the OTP memory cells MCo are connected. The memory cells MC for the user are the OTP memory cells MCo included in the OTP user area ARoU in Figure 10A . In addition, for example, as illustrated in Figure 2 , when the bit lines BL are shared by the OTP user area ARoU and the normal memory area ARn, the memory cells MC for the user also include the normal memory cells MCn in the normal memory area ARn.

[0125] Thereafter, the probe inspection device verifies whether P-read or AP-read can be performed by causing the nonvolatile memory NVM to perform a read operation (steps S304 and S305). Figure 10A In the illustrated example, the probe inspection device determines pass / failure regarding reading a "0" level or a "1" level from the OTP memory cell MCo in the OTP user area ARoU (step S305). If the determination result is failure, the probe inspection device determines that the screening result has failed (step S307).

[0126] Furthermore, if the result of determination in step S305 is pass, the probe inspection apparatus determines that the screening result is pass (step S306). Through the processing from step S302 to step S305, (C) when the user writes to the OTP memory cell MCo, it is possible to ensure that a defect will not occur in another memory cell MC sharing the bit line BL with the OTP memory cell MCo due to the application of a high voltage to the bit line BL.

[0127] <Edit>

[0128] Figure 13 This diagram shows that by modifying Figure 5 The circuit block diagram of the configuration example obtained is shown in FIG. Figure 13 In the Memory Built-in Self-Test (BIST) circuit MBIST is added to Figure 5 The illustrated configuration example. For example, the memory BIST circuit MBIST outputs a command signal CMD, an address signal ADR, and a data signal DTi[0:j] to the memory control circuit MCTL based on a start signal from a probe inspection device, or inputs a data signal DTo[0:j] from the memory control circuit MCTL to determine a pass / fail. Furthermore, the memory BIST circuit MBIST can operate the OTP voltage selection register REGoh, the write number selection register REGom, and the trimming registers REGtr and REGtc.

[0129] As a result, the memory BIST circuit MBIST performs a self-test on the nonvolatile memory NVM instead of the probe inspection device. As one of the self-tests, the memory BIST circuit MBIST controls Figure 6 As a result, each of the plurality of semiconductor devices formed on the semiconductor wafer can autonomously obtain the optimal trimming value for its own device. In addition, the memory BIST circuit MBIST can control Figure 11 The sequence of the screening step (step S102b) is shown.

[0130] By providing the memory BIST circuit MBIST, the number of semiconductor devices DEV that can be tested at the same time can be increased within the limited resources of the probe inspection apparatus. As a result, the test cost can be reduced. Note that the memory BIST circuit MBIST can be configured with, for example, a command generation circuit, an address generation circuit, a data generation circuit, a data determination circuit, and a sequencer circuit that controls these circuits.

[0131] <Main effects of the embodiments>

[0132] As described above, in the method according to the embodiments, either the regulator voltage obtained by gradually lowering the supply voltage or the boost voltage obtained by boosting the supply voltage can be selectively used as the write voltage to the MTJ-OTP memory cell. Furthermore, the optimum value of these voltages can be defined by the semiconductor manufacturer through the OTP voltage trimming step. As a result, reliable write operation to the OTP memory cell by the user can be guaranteed. Furthermore, in the method according to the present embodiment, the screening step is provided after the OTP voltage trimming step. As a result, it can be guaranteed that no defects occur due to the write operation to the OTP memory cell by the user.

[0133] Although the present application conceived by the present inventor is particularly described based on the embodiments, the present application is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present application. For example, the above-described embodiments are described in detail in order to describe the present application in an easily understandable manner, and the embodiments are not necessarily limited to the embodiments having all the described configurations. In addition, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. In addition, to a part of the configuration of each embodiment, other configurations can be added, deleted, and replaced. ​

Claims

1. A method of manufacturing a semiconductor device, the method comprising: a wafer processing step of forming a nonvolatile memory on a semiconductor wafer; and a wafer testing step of testing the semiconductor wafer, wherein, in the nonvolatile memory, a plurality of word lines, a plurality of bit lines, a plurality of source lines, a plurality of one-time programmable (OTP) memory cells, a charge pump circuit, a voltage regulator circuit, a write driver, an OTP voltage selection register, a first trimming register, and a second trimming register are formed, the plurality of bit lines are arranged across the plurality of word lines, the plurality of source lines are arranged side by side in the plurality of bit lines, the plurality of OTP memory cells are arranged in intersections between the plurality of word lines and the plurality of bit lines, and include a transistor switch whose on / off state is controlled by any of the plurality of word lines and a magnetic tunnel junction (MTJ) element that stores binary data depending on presence or absence of dielectric breakdown, the charge pump circuit generates a boosted voltage that is obtained by boosting a supply voltage, the voltage regulator circuit generates a regulator voltage that is obtained by stepwise reducing the supply voltage, the write driver writes one of the binary data into any of the plurality of OTP memory cells by applying the boosted voltage or the regulator voltage between any of the plurality of bit lines and any of the plurality of source lines, the OTP voltage selection register causes the write driver to select either of the boosted voltage or the regulator voltage, the first trimming register holds a first voltage setting value for defining a magnitude of the boosted voltage, the second trimming register holds a second voltage setting value for defining a magnitude of the regulator voltage, wherein the wafer testing step is an OTP voltage trimming step, and wherein the OTP voltage trimming step is a step of sequentially changing the voltage setting value in a high voltage direction while one of the first voltage setting value or the second voltage setting value is used as a voltage setting value to be trimmed, and writing to the plurality of OTP memory cells is performed one by one until writing to N OTP memory cells, which are two or more of the plurality of OTP memory cells, with the same voltage setting value is successively successful.

2. The method of manufacturing a semiconductor device according to claim 1, wherein the OTP voltage trimming step includes: Step (A): defining the voltage setting value to an initial value, and defining one of the plurality of OTP memory cells as a target OTP memory cell; Step (B): writing to the target OTP memory cell using the voltage setting value; Step (C): determining whether or not writing to the target OTP memory cell is successful; Step (D): if writing to the target OTP memory cell is successful, defining the voltage setting value to the initial value, and defining another one of the plurality of OTP memory cells as a target OTP memory cell; and Step (E): repeating Steps (B) to (D) until writing to all of the plurality of OTP memory cells is successful. Step (Dl): when the determination result in the step (C) is failure, zeroing the number of consecutive successes, changing the voltage setting value in the high voltage direction, changing the target OTP memory cell, and returning to the step (B); and Step (D2): when the determination result in the step (C) is success, counting up the number of consecutive successes, when the number of consecutive successes does not reach N, changing the target OTP memory cell, and returning to the step (B).

3. The method of manufacturing a semiconductor device according to claim 2, the method further comprising: Step (E): when the number of consecutive successes in the step (D2) reaches N, adding a margin in the high voltage direction to a current voltage setting value, and confirming the voltage setting value added with the margin as a result of trimming one of the first voltage setting value or the second voltage setting value.

4. The method of manufacturing a semiconductor device according to claim 2, wherein a memory built-in self test (BIST) circuit is formed in the nonvolatile memory, the memory BIST circuit controlling a sequence of the OTP voltage trimming step.

5. The method of manufacturing a semiconductor device according to claim 1, wherein in the nonvolatile memory, an OTP user area, an OTP test area, and a normal memory area are formed, the OTP user area is an area configured with a portion of the plurality of OTP memory cells and is freely usable by a user, the OTP test area is an area configured with another portion of the plurality of OTP memory cells and is used for the OTP voltage trimming step, the normal memory area is an area configured with normal memory cells and is freely usable by a user, the normal memory cells being used to hold binary data in a parallel (P) state or an anti-parallel (AP) state.

6. The method of manufacturing a semiconductor device according to claim 5, wherein the OTP test area is formed at a position separate from the write driver compared to the OTP user area.

7. The method of manufacturing a semiconductor device according to claim 5, wherein the wafer testing step further comprises: a screening step performed after the OTP voltage trimming step, and wherein the screening step includes: Step (F): performing a write to an OTP memory cell in the OTP test area so that the boosted voltage or the regulator voltage defined in the OTP voltage trimming step is applied to all bit lines to which the plurality of OTP memory cells are connected; and Step (G): after the step (F), verifying whether a P read or an AP read is performed by performing a P write or an AP write to the plurality of memory cells in the OTP user area or the normal memory area, the plurality of memory cells in the OTP user area or the normal memory area being the plurality of memory cells connected to all the bit lines.

8. The method of manufacturing a semiconductor device according to claim 7, wherein In the step (F), a bit line to which the boost voltage or the regulator voltage defined in the OTP voltage trimming step is applied before the step (F) is excluded from the write target.

9. The method of manufacturing a semiconductor device according to claim 1, wherein the OTP voltage trimming step includes: a step of making the first voltage setting value as the trimming target; and a step of making the second voltage setting value as the trimming target.

10. A semiconductor device comprising: a word line; a plurality of bit lines arranged across the word line; a plurality of source lines arranged side by side in the bit lines; a plurality of one-time programmable (OTP) memory cells arranged at intersections between the word line and the plurality of bit lines, and including a transistor switch whose on / off state is controlled by the word line, and a magnetic tunnel junction (MTJ) element for storing binary data depending on presence or absence of dielectric breakdown; a charge pump circuit generating a boost voltage obtained by boosting a supply voltage; a voltage regulator circuit generating a regulator voltage obtained by stepwise reducing the supply voltage; a write driver writing one of the binary data to any of the plurality of OTP memory cells by applying the boost voltage or the regulator voltage between any of the plurality of bit lines and any of the plurality of source lines; and an OTP voltage selection register making the write driver select either of the boost voltage or the regulator voltage.

11. The semiconductor device according to claim 10, further comprising: a first trimming register holding a first voltage setting value defining a magnitude of the boost voltage; and a second trimming register holding a second voltage setting value defining a magnitude of the regulator voltage.

12. The semiconductor device according to claim 11, further comprising: a write number selection register selecting whether a number of simultaneous writes to the plurality of OTP memory cells is K, K being 1 or 2 or more, when the boost voltage is selected, wherein the first trimming register includes: a third trimming register holding the first voltage setting value when the number of simultaneous writes is 1, and a fourth trimming register holding the first voltage setting value when the number of simultaneous writes is K.

13. The semiconductor device according to claim 12, wherein the write driver performs simultaneous writes to J OTP memory cells when the regulator voltage is selected by the OTP voltage selection register, J being greater than K. ​

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