Etching method of semiconductor structure and semiconductor structure
By adjusting the RF power and pressure in the resist removal process and optimizing the morphology of the titanium nitride hard mask layer, the problems of sidewall tilting and bottom depression in traditional etching processes were solved, thereby improving the pattern transfer accuracy and wafer yield of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING INTEGRATED CIRCUIT EQUIPMENT INNOVATION CENTER CO LTD
- Filing Date
- 2025-07-10
- Publication Date
- 2026-05-12
Smart Images
Figure CN120834006B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and more specifically, to an etching method for a semiconductor structure and a semiconductor structure. Background Technology
[0002] With the continuous development of semiconductor manufacturing technology, the geometric dimensions of semiconductor structures are constantly shrinking, while the number of metal layers is constantly increasing. This leads to an increase in the resistance of metal wires, the parasitic capacitance between metal wires, and the parasitic capacitance between metal interconnect layers, resulting in increased signal delay time. The signal transmission delay caused by back-end interconnects in semiconductor devices limits the improvement of integrated circuit frequency performance. Using metal interconnects, such as copper interconnect technology, can effectively overcome this limitation.
[0003] Damascus structures are widely used as interconnect structures in semiconductor structures at the back end of the production line. Integrated damascus etching is a common technique for fabricating copper interconnect layers. The integrated damascus etching process mainly consists of trench and via etching. In the back-end processes of logic device manufacturing, titanium nitride hard masks, due to their high etching selectivity and mechanical strength, replace traditional silicon nitride or oxide masks for trench etching. Therefore, using titanium nitride thin films as hard mask materials for back-end metal interconnects can improve chip speed, increase etching selectivity, and optimize etching directionality.
[0004] In related technologies, titanium nitride hard masks can be etched using either dry or wet etching methods. The critical dimension obtained after etching is a crucial factor determining the size of the etching process window. However, traditional titanium nitride hard mask etching processes are prone to causing the hard mask sidewalls to tilt or bend, or the bottom to be concave. This results in a reduction in the linewidth (critical dimension CD) when the pattern is transferred to damascene etching, leading to insufficient critical dimension deviation and incomplete etching of small linewidth areas. Consequently, abnormal electrical parameters and decreased wafer yield are observed. Therefore, there is a need to find an superior process method for etching titanium nitride hard masks to increase the etching process window and improve the pattern transfer accuracy and process stability of semiconductor devices. Summary of the Invention
[0005] The purpose of this invention is to provide an etching method and a semiconductor structure that can at least alleviate the problem of small etching window in current etching processes.
[0006] In a first aspect, the present invention discloses an etching method for a semiconductor structure, the etching method comprising:
[0007] A substrate is provided on which a dielectric layer, a hard mask layer, and a patterned photolithographic structure are formed;
[0008] Using the patterned photolithography structure as a mask, the hard mask layer is etched to form a hard mask layer with an initial pattern;
[0009] The patterned photolithographic structure is removed using a resist-removal process, and a hard mask layer with a preset pattern is formed.
[0010] Specifically, the radio frequency power and the pressure of the process chamber in the resist removal process are adjusted to transform the hard mask layer with the initial pattern into the hard mask layer with the preset pattern.
[0011] In some embodiments of the present invention, adjusting the radio frequency power and the pressure of the process chamber in the adhesive removal process includes: the radio frequency power is ≥500W, and the pressure of the process chamber is ≤30mT.
[0012] In some embodiments of the present invention, adjusting the radio frequency power and the pressure of the process chamber in the adhesive removal process includes: the radio frequency power is 500W to 1200W, and the pressure of the process chamber is 5mT to 30mT.
[0013] In some embodiments of the present invention, the process conditions in the adhesive removal process further include: the process gas includes oxygen, or a mixture of nitrogen and oxygen; wherein the flow rate of the nitrogen is in the range of 0 sccm to 300 sccm; the flow rate of the oxygen is in the range of 100 sccm to 200 sccm; the bias RF voltage is in the range of 20V to 200V; and the process time is in the range of 30s to 80s.
[0014] In some embodiments of the present invention, the hard mask layer includes a titanium nitride hard mask layer.
[0015] In some embodiments of the present invention, the etching of the hard mask layer includes: performing main etching on the titanium nitride hard mask layer using a first plasma etching process; and performing over-etching on the titanium nitride hard mask layer using a second plasma etching process.
[0016] In some embodiments of the present invention, the process conditions of the first plasma etching process include: the process gas includes methane and chlorine, the flow rate of methane is in the range of 5 sccm to 30 sccm, and the flow rate of chlorine is in the range of 30 sccm to 100 sccm; the pressure of the process chamber is 3 mT to 15 mT; the radio frequency power is 400 W to 1000 W; and the bias radio frequency voltage is in the range of 20 V to 100 V.
[0017] In some embodiments of the present invention, the process conditions of the second plasma etching process include: the process gas includes methane and chlorine, the flow rate of methane is in the range of 3 sccm to 25 sccm, and the flow rate of chlorine is in the range of 30 sccm to 100 sccm; the pressure of the process chamber is 3 mT to 15 mT; the radio frequency power is 400 W to 1000 W; and the bias radio frequency voltage is in the range of 20 V to 100 V.
[0018] In some embodiments of the present invention, the patterned photolithography structure includes a patterned photoresist layer and an anti-reflective coating. An oxide layer is further disposed between the patterned photolithography structure and the hard mask layer, and the patterned photoresist layer, the anti-reflective coating, the oxide layer, and the hard mask layer are sequentially disposed. The etching method includes: using the patterned photoresist layer as a mask, etching the anti-reflective coating to form a patterned anti-reflective coating; using the patterned photoresist layer and the patterned anti-reflective coating as masks, etching the oxide layer to form a patterned oxide layer, and removing the patterned photoresist layer; using the patterned anti-reflective coating and the patterned oxide layer as masks, etching the hard mask layer to form a hard mask layer with an initial pattern; and removing the patterned anti-reflective coating using a resist stripping process to form a hard mask layer with a preset pattern.
[0019] In some embodiments of the present invention, after the resist removal process, the method further includes: using the hard mask layer with the preset pattern as a mask to etch the dielectric layer to form a hole structure in the dielectric layer; and filling the hole structure with metal to form a metal interconnect structure.
[0020] In a second aspect, the present invention discloses a semiconductor structure, which is fabricated using the etching method for semiconductor structures as described above; the semiconductor structure includes a substrate and a metal interconnect structure disposed on the substrate.
[0021] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects:
[0022] The etching method of this application forms a hard mask layer with an initial pattern after etching. The sidewalls of this initial patterned hard mask layer may have a tilted or curved morphology, and the perpendicularity of the sidewall angles may be low. Therefore, in the resist stripping process, this application transforms the initial patterned hard mask layer into the final hard mask layer with the desired preset pattern by adjusting the RF power and process chamber pressure during the resist stripping process. Thus, by optimizing this resist stripping process, the morphology of the hard mask layer is adjusted while removing the patterned photolithographic structure, improving the perpendicularity of the hard mask layer's sidewalls and eliminating the curved morphology of the hard mask layer's sidewalls. This increases the critical dimension deviation from the damascus etching, thereby improving the pattern transfer accuracy and process stability of the semiconductor device. Furthermore, the etching method of this invention is simple to implement, low in cost, and highly effective, with excellent application results. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0024] Figure 1 A schematic flowchart of an etching method for a semiconductor structure provided in an embodiment of the present invention;
[0025] Figure 2 A schematic diagram comparing the morphology of a traditional hard mask layer with that of the hard mask layer provided in the embodiments of the present invention; Figure 2 (a) shows the morphology of a traditional hard mask layer. Figure 2 (b) shows the morphology of the hard mask layer in an embodiment of the present invention;
[0026] Figure 3 This is a schematic diagram of step S100 in the semiconductor structure etching method of the present invention.
[0027] Figure 4 This is a schematic diagram of step S110 in the semiconductor structure etching method of the present invention.
[0028] Figure 5 This is a schematic diagram of step S120 in the semiconductor structure etching method of the present invention;
[0029] Figure 6 This is a schematic diagram of step S130 in the semiconductor structure etching method of the present invention.
[0030] Figure 7This is a schematic diagram of step S140 in the semiconductor structure etching method of the present invention.
[0031] Figure 8 This is a schematic diagram of step S150 in the etching method for semiconductor structures of the present invention.
[0032] Explanation of reference numerals in the attached figures:
[0033] 100 - Patterned photoresist layer;
[0034] 200-Anti-reflective coating;
[0035] 300-Oxide layer;
[0036] 400 - Hard mask layer;
[0037] 500-Dielectric antireflective layer;
[0038] 600 - Dielectric layer. Detailed Implementation
[0039] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0040] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings.
[0041] Titanium nitride hard masks are characterized by high etching selectivity and mechanical strength. x As a hard mask, titanium nitride can be used to etch smaller vias and trenches, achieving higher etching uniformity. However, in processes at 28nm and below, traditional titanium nitride hard mask etching processes (such as...) Figure 2(a) As shown, this can easily lead to bow profile tilting or undercut of the hard mask sidewalls, causing a reduction in linewidth (CD) when the pattern is transferred to damascene etching. This results in insufficient critical dimension deviations (deviations between trench CD and via CD), and incomplete etching of small linewidth areas, leading to abnormal electrical parameters, decreased wafer yield, and impacting product yield. To improve this defect, related technologies often employ methods such as adjusting mask thickness to optimize morphology or using multi-layer hard masks (a two-layer etching process using titanium nitride / tantalum nitride hard masks) to improve accuracy. However, this approach fails to address the simple morphology control issues of a single titanium nitride layer. Furthermore, this method improves the aforementioned defects by adjusting the etching gas, but the improvement effect is not significant. In addition, optimizing morphology through mask thickness or using multi-layer hard masks to improve accuracy increases costs.
[0042] In view of this, the present invention discloses an etching method for a semiconductor structure and a semiconductor structure. The etching method of the present invention mainly optimizes the morphology of the hard mask, such as a titanium nitride hard mask, by adjusting the resist removal process parameters (e.g., ...). Figure 2 (b) shows the method to improve the perpendicularity of the hard mask sidewalls, enhance the pattern transfer accuracy of semiconductor devices, and thus improve product yield. The method proposed in this invention can alleviate the problems of insignificant improvement or high cost associated with traditional methods that optimize morphology by adjusting mask thickness or improve accuracy through multilayer hard masks.
[0043] As an optional implementation of the disclosure of this invention, an embodiment of this invention discloses an etching method for a semiconductor structure, such as... Figure 1 As shown, the etching method includes:
[0044] A substrate is provided, on which a dielectric layer 600, a hard mask layer 400, and a patterned photolithographic structure are formed;
[0045] Using a patterned photolithography structure as a mask, the hard mask layer 400 is etched to form a hard mask layer 400 with an initial pattern.
[0046] The patterned photolithographic structure is removed using a photoresist stripping process, and a hard mask layer 400 with a preset pattern is formed.
[0047] In this process, the radio frequency power and the pressure of the process chamber are adjusted during the resist removal process to transform the hard mask layer 400 with the initial pattern into a hard mask layer 400 with a preset pattern.
[0048] The etching method of this application embodiment is applicable to the damascus etching process and can be used to alleviate the shortcomings of the traditional damascus trenching process. By adjusting the parameters in the resist removal process, the morphology of the etched hard mask, such as the titanium nitride hard mask, is optimized, thereby widening its process window and improving the linewidth control capability after damascus etching.
[0049] It should be noted that in the etching method of this embodiment, the material of the hard mask layer 400 can be selected from titanium nitride, but is not limited thereto. The method of this invention has strong process compatibility, and other hard mask materials with similar requirements are also applicable to this invention. For simplicity, the etching method of this invention will be described in detail below mainly using titanium nitride hard mask as an example.
[0050] In this paper, the hard mask layer 400 with the initial pattern can be understood as having certain defects in the pattern, such as the hole sidewalls and / or bottom walls, like tilted or bent sidewalls or bottom depressions, which need further improvement. The hard mask layer 400 with the preset pattern can be understood as having the pattern in the hard mask layer 400 as the target pattern or the required pattern. This preset pattern improves upon the defects in the initial pattern and can ensure the accuracy of subsequent pattern transfer.
[0051] In the etching method of this application embodiment, a hard mask layer with an initial pattern can be formed after etching the hard mask layer. During this etching process, based on the isotropic etching of the etching gas, for example, Cl radicals easily diffuse along the sidewalls and undergo lateral etching with the hard mask, such as a titanium nitride hard mask, resulting in the sidewalls being hollowed out and forming a tilted and curved morphology. Therefore, the sidewalls of the hard mask layer with the initial pattern may have a tilted and curved morphology, and the perpendicularity of the sidewall angle is low, which will affect the subsequent pattern transfer accuracy. Based on this, the embodiments of this application mainly optimize the morphology of the etched titanium nitride hard mask layer by adjusting the resist stripping process parameters. Specifically, in the resist stripping process, the RF power and the pressure of the process chamber in the resist stripping process are adjusted to transform the hard mask layer with the initial pattern into the final hard mask layer with the preset pattern. Therefore, by optimizing the resist removal process, the morphology of the hard mask layer is adjusted while removing the patterned photolithographic structure, improving the sidewall perpendicularity of the hard mask layer and eliminating the bending morphology of the hard mask layer sidewalls. This increases the critical dimension deviation from the damascus etching, thereby improving the pattern transfer accuracy and process stability of semiconductor devices. Furthermore, the etching method of this invention is simple to implement, low in cost, and highly effective, with excellent application results.
[0052] refer to Figure 2 It can be seen that, Figure 2 (a) shows a schematic diagram of the morphology of a hard mask layer formed by conventional processes, such as a titanium nitride hard mask layer. Figure 2 (b) shows a schematic diagram of the morphology of a hard mask layer, such as a titanium nitride hard mask layer, formed according to an embodiment of the present invention. Figure 2 (a) The traditional hard mask layer 400 has a tilted and curved sidewall morphology, while Figure 2 (b) The embodiment of the present invention eliminates the curved morphology of the sidewall of the hard mask layer 400 and improves the verticality of the sidewall of the hard mask layer 400.
[0053] Therefore, by using the etching method provided in this embodiment of the invention, and optimizing the morphology of the titanium nitride hard mask by adjusting the resist removal process parameters, the sidewall angle of the hard mask can be increased from 70°-80° in the traditional process to 85°-90°, thus widening the process window, significantly improving linewidth control capability, and reducing dependence on etching selectivity. Moreover, this process has strong compatibility and can be extended to other hard mask materials; that is, the etching method of this invention is not only applicable to titanium nitride hard masks, but also to other hard mask materials with similar requirements. Furthermore, the method of this invention requires no additional equipment modification, significantly reducing costs.
[0054] In some specific implementation methods, such as Figures 3-8 As shown, the etching method for this semiconductor structure includes the following steps:
[0055] S100: Provide a substrate, and form a dielectric layer 600, a hard mask layer 400, and a patterned photolithographic structure on the substrate.
[0056] Optionally, the substrate material can be silicon, or it can also be germanium, silicon germanide, silicon carbide, etc., without any special restrictions.
[0057] In some embodiments, the dielectric layer 600 includes an interlayer dielectric layer or an intermetallic dielectric layer (or interlayer dielectric layer, ILD). Optionally, the material of the interlayer dielectric layer can be a low-dielectric-constant material conventionally used in the art, particularly a material with a relative permittivity in the range of 1.5-2.5, including but not limited to, for example, silicon oxide or black diamond. Optionally, as an example, a semiconductor device layer formed thereon by a front-end process may also be disposed between the substrate and the dielectric layer 600, without particular limitation.
[0058] In some embodiments, the hard mask layer 400 includes, but is not limited to, a titanium nitride hard mask layer 400. As described above, in the etching method of this embodiment of the invention, the material of the hard mask layer 400 can be a titanium nitride hard mask layer 400, which has the expression TiN. x (x can range from 0.3 to 1.1, for example, x can be 1). Of course, the material of the hard mask layer 400 is not limited to this; for example, other similar hard mask materials such as tantalum nitride can also be used.
[0059] In some embodiments, the patterned photolithography structure includes a patterned photoresist layer 100 (PR) and an anti-reflective coating 200 (BARC), and an oxide layer 300 is further disposed between the hard mask layer 400 and the patterned photolithography structure; and the patterned photoresist layer 100, anti-reflective coating 200, oxide layer 300 and hard mask layer 400 are arranged sequentially from top to bottom.
[0060] Depending on the semiconductor structure, the resist removal process in this embodiment can be used to remove different coatings. For example, when the patterned photoresist layer 100, hard mask layer 400, and dielectric layer 600 are sequentially arranged, the resist removal process mainly refers to removing the patterned photoresist layer 100. When other coating structures are provided between the patterned photoresist layer 100 and hard mask layer 400, such as when the patterned photoresist layer 100, anti-reflective coating 200, oxide layer 300, and hard mask layer 400 are sequentially arranged from top to bottom, the resist removal process can also be used to remove coating structures such as the anti-reflective coating 200. Specifically, it can be adaptively adjusted according to the actual semiconductor structure.
[0061] It should be understood that in the later stages of the copper interconnect damascus process, titanium nitride (TiN) is used. x The trenching process, used as a hard mask, can etch small-sized vias and trenches. Optionally, in the fabrication of small-sized photolithography processes, to prevent reflections from the bottom film layer onto the sidewalls of the photoresist (PR) during exposure, which could cause a decrease in the dimensional accuracy of the PR, a bottom anti-reflective coating 200 (BARC) is generally applied before coating the PR to provide bottom anti-reflection. Furthermore, since titanium nitride reacts with organic materials such as PR and BARC used for pattern formation in photolithography, an oxide layer 300 is deposited between the titanium nitride and BARC for barrier purposes.
[0062] In some embodiments, a dielectric antireflective layer 500 (DARC) is further provided between the hard mask layer 400 and the dielectric layer 600. For example, the dielectric antireflective layer 500 can be a nitrogen-free dielectric antireflective layer 500 (N-free DARC).
[0063] refer to Figure 3 As shown, as an example, in step S100, a substrate is provided, and from bottom to top, a dielectric layer 600, a dielectric antireflective layer 500, a hard mask layer 400, an oxide layer 300, an antireflective coating 200, and a patterned photoresist layer 100 are sequentially formed on the substrate.
[0064] S110, Etched Anti-reflective Coating 200 (BARC ETCH): Reference Figure 4 As shown, the patterned photoresist layer 100 is used as a mask to etch the antireflective coating 200, forming the patterned antireflective coating 200.
[0065] Since an anti-reflective coating 200 is provided below the patterned photoresist layer 100, the anti-reflective coating 200 can be etched first in step S110 before etching the hard mask layer 400, so as to facilitate the subsequent etching process.
[0066] In an optional embodiment, during the etching step of the antireflective coating 200, the etching gas includes oxygen (O2) and chlorine (Cl2), wherein the flow rate of oxygen can be in the range of 5 sccm to 100 sccm, for example including 5 sccm, 10 sccm, 20 sccm, 30 sccm, 50 sccm, 80 sccm, 100 sccm, etc.; and the flow rate of chlorine can be in the range of 50 sccm to 200 sccm, for example including 50 sccm, 80 sccm, 100 sccm, 150 sccm, 200 sccm, etc.
[0067] In the etching step of the anti-reflective coating 200, a preferred process formulation includes:
[0068] The chamber pressure range of the process chamber is 3mT to 15mT (mTorr), including, for example, 3mT, 5mT, 8mT, 10mT, and 15mT. The source RF power range is 500W to 1000W, including, for example, 500W, 550W, 600W, 650W, 700W, 800W, and 1000W. The bias RF voltage range is 20V to 150V, including, for example, 20V, 30V, 50V, 80V, 100V, and 150V. Furthermore, the etching time range is 10s to 40s, including, for example, 10s, 20s, 30s, and 40s.
[0069] Under these process conditions, the etching gas has good etching conditions, so that the etching gas can effectively etch the anti-reflective coating 200.
[0070] S120, Etched Oxide Layer 300: Reference Figure 5 As shown, using a patterned photoresist layer 100 and a patterned anti-reflective coating 200 as masks, the oxide layer 300 is etched to form a patterned oxide layer 300, and the patterned photoresist layer 100 is removed.
[0071] It should be noted that during the etching of the anti-reflective coating 200, a portion of the patterned photoresist layer 100 will be removed. Furthermore, during the etching of the oxide layer 300, the patterned photoresist layer 100 will be completely consumed, that is, the patterned photoresist layer 100 will be completely removed.
[0072] Since an oxide layer 300 is provided between the anti-reflective coating 200 and the hard mask layer 400, the oxide layer 300 needs to be etched in step S120 after etching the anti-oxidation layer 300 and before etching the hard mask layer 400, so as to facilitate the subsequent etching process.
[0073] In an optional embodiment, during the etching step of the oxide layer 300, the etching gas includes trifluoromethane (CHF3), methane (CH4), and helium (He). The flow rate of trifluoromethane can be in the range of 5 sccm to 100 sccm, for example, 5 sccm, 10 sccm, 20 sccm, 30 sccm, 50 sccm, 80 sccm, 100 sccm, etc.; the flow rate of methane can be in the range of 50 sccm to 200 sccm, for example, 50 sccm, 80 sccm, 100 sccm, 150 sccm, 200 sccm, etc.; and the flow rate of helium can be in the range of 40 sccm to 150 sccm, for example, 40 sccm, 50 sccm, 60 sccm, 80 sccm, 100 sccm, 150 sccm, etc.
[0074] In the etching step of oxide layer 300, a preferred process formulation includes:
[0075] The chamber pressure range of the process chamber is 3mT to 15mT, including, for example, 3mT, 5mT, 8mT, 10mT, and 15mT. The source RF power range is 300W to 800W, including, for example, 300W, 400W, 500W, 600W, 700W, and 800W. The bias RF voltage range is 20V to 150V, including, for example, 20V, 30V, 50V, 80V, 100V, and 150V. Furthermore, the etching time range is 10s to 30s, including, for example, 10s, 20s, and 30s.
[0076] Under these process conditions, the etching gas has good etching conditions, so that the etching gas can effectively etch the oxide layer 300.
[0077] S130, Titanium nitride hard mask layer 400 main etching (TiN ME ETCH): Reference Figure 6 As shown, using a patterned anti-reflective coating and a patterned oxide layer as masks, the titanium nitride hard mask layer 400 is etched using a first plasma etching process.
[0078] In this embodiment of the invention, a first plasma etching process is used to perform the main etching of the titanium nitride hard mask layer 400. In this step S130, the process gas may include methane (CH4) and chlorine (Cl2).
[0079] In step S130, chlorine gas can be used as the main etching gas, and the flow rate of chlorine gas can be in the range of 30 sccm to 100 sccm, for example, including 30 sccm, 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm, 100 sccm, etc. The plasma generated by chlorine gas can react with TiN, the main component of the electrode, and finally generate volatile TiCl4 and N2, which are pumped away.
[0080] In step S130, methane can be used as the etching protective gas. The flow rate of methane can range from 5 sccm to 30 sccm, for example, 5 sccm, 10 sccm, 15 sccm, 20 sccm, 30 sccm, etc. Under the action of plasma, methane can react with substances such as Ti and O in the process chamber to generate non-volatile byproducts that adhere to the sidewalls of the hard mask layer, thus protecting the sidewalls of the hard mask layer. However, more methane is not necessarily better, because more methane generates more byproducts. Excessive byproduct accumulation can cause the titanium nitride hard mask layer to be non-perpendicular after etching, affecting subsequent metal layer etching and even affecting the copper filling process in the electrochemical plating process.
[0081] In step S130, the preferred process formulation includes:
[0082] The chamber pressure range of the process chamber is 3mT to 15mT, including, for example, 3mT, 5mT, 8mT, 10mT, and 15mT. The source RF power range is 400W to 1000W, including, for example, 400W, 500W, 600W, 700W, 800W, and 1000W. The bias RF voltage range is 20V to 100V, including, for example, 20V, 30V, 50V, 80V, and 100V. Furthermore, the etching time range is 5s to 30s, including, for example, 5s, 10s, 20s, and 30s.
[0083] In the main etching step of the titanium nitride hard mask layer 400, the main etching of titanium nitride can ensure that most areas have been etched, but the overall morphology is relatively oblique, especially the bottom (footing) is more oblique; therefore, further etching is required.
[0084] S140, Titanium nitride hard mask layer 400 over-etch (TiN OE ETCH): Reference Figure 7 As shown, the titanium nitride hard mask layer 400 is over-etched using a second plasma etching process.
[0085] In this embodiment of the invention, a second plasma etching process is used to over-etch the titanium nitride hard mask layer 400. In this step S140, the process gas may include methane (CH4) and chlorine (Cl2).
[0086] Similar to step S130 above, in step S140, chlorine gas can be used as the main etching gas, and the flow rate of chlorine gas can be in the range of 30 sccm to 100 sccm, for example, including 30 sccm, 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm, 100 sccm, etc. Methane can be used as the etching protective gas, and the flow rate of methane can be in the range of 3 sccm to 25 sccm, for example, including 3 sccm, 5 sccm, 10 sccm, 15 sccm, 20 sccm, 25 sccm, etc.
[0087] In step S140, the preferred process formulation includes:
[0088] The chamber pressure range of the process chamber is 3mT to 15mT, including, for example, 3mT, 5mT, 8mT, 10mT, and 15mT. The source RF power range is 400W to 1000W, including, for example, 400W, 500W, 600W, 700W, 800W, and 1000W. The bias RF voltage range is 20V to 100V, including, for example, 20V, 30V, 50V, 80V, and 100V. Furthermore, the etching time range is 5s to 30s, including, for example, 5s, 10s, 20s, and 30s.
[0089] In the over-etching step of the titanium nitride hard mask layer 400, over-etching ensures that all areas are completely etched. However, after over-etching, the sidewalls of the titanium nitride hard mask layer will exhibit a curved morphology. It should be understood that since titanium nitride etching often uses halogen-based plasmas such as Cl2 / BCl3, this gas is predominantly isotropic. Cl radicals easily diffuse along the sidewalls, causing lateral etching with the titanium nitride, resulting in hollowing out the sidewalls and forming a tilted, curved morphology. Furthermore, ions are scattered within the trench, and their energy is typically significantly weakened in the lower part of the sidewalls, failing to achieve effective bombardment; thus, the sidewalls of the titanium nitride hard mask layer will exhibit a curved morphology.
[0090] S150, Asher process: Reference Figure 8 As shown, an anti-reflective coating 200 is patterned using a stripping process, and a hard mask layer 400 with a preset pattern is formed.
[0091] In this embodiment of the invention, etching of the titanium nitride hard mask layer 400 is first completed to form a hard mask layer 400 with an initial pattern. Then, in the resist stripping process, adjusting the parameters of the resist stripping process can optimize the morphology of the titanium nitride hard mask layer 400. For example, by adjusting the radio frequency power and the pressure of the process chamber in the resist stripping process, the hard mask layer 400 with the initial pattern can be transformed into a hard mask layer 400 with a preset pattern.
[0092] Optionally, in this adhesive removal process, the radio frequency power (source radio frequency power) can be ≥500W; preferably, the radio frequency power range is 500W to 1200W, for example including 500W, 600W, 700W, 800W, 1000W, 1200W, etc.
[0093] In the adhesive removal process of this invention, by increasing the radio frequency power, the dissociation efficiency of O2 and N2 can be improved, the oxidation repair of titanium nitride sidewalls can be accelerated, and high-density plasma ensures that a dense protective layer is uniformly generated throughout the sidewalls.
[0094] Optionally, in this degumming process, the pressure in the process chamber is ≤30mT; preferably, the pressure range of the process chamber is 5mT to 30mT, for example, including 5mT, 8mT, 10mT, 15mT, 20mT, 25mT, 30mT, etc.
[0095] In the degumming process, this invention reduces the pressure in the process chamber, thereby decreasing the probability of collisions between ions and gas molecules, increasing the mean free path of molecules, reducing ion scattering within the tank, ensuring sufficient ion bombardment in the lower part, and thus preventing sidewall depressions.
[0096] Of particular note is that in this resist removal process, the combined effect of pressure and source RF power serves as a key means to repair the curved morphology of the hard mask layer's sidewalls. This is because, on the one hand, under low pressure, the probability of ion-gas molecule collisions decreases, and the mean free path of molecules increases, which reduces ion scattering within the trench, ensuring sufficient ion bombardment in the lower and middle parts, allowing for primarily longitudinal etching and thus preventing sidewall depressions. On the other hand, increasing the source RF power enhances the dissociation efficiency of O2 and N2, accelerating the oxidation repair of the titanium nitride sidewalls, while high-density plasma ensures the uniform formation of a dense TiON protective layer (TiN+N) throughout the sidewalls. + +O + ->TiON), filling in curved or recessed areas of the sidewalls.
[0097] In step S140, the preferred process formulation includes:
[0098] The process gas includes oxygen, or a mixture of nitrogen and oxygen; the nitrogen flow rate ranges from 0 sccm to 300 sccm, for example, 10 sccm, 50 sccm, 100 sccm, 150 sccm, 200 sccm, 250 sccm, 300 sccm, etc.; the oxygen flow rate ranges from 100 sccm to 200 sccm, for example, 100 sccm, 120 sccm, 150 sccm, 150 sccm, 200 sccm, etc. The bias RF voltage range can be from 20V to 200V, for example, 20V, 30V, 50V, 80V, 100V, 150V, 200V, etc. Furthermore, the etching time ranges from 30s to 80s, for example, 30s, 40s, 50s, 60s, 80s, etc.
[0099] For example, in one embodiment, the process formulation in step S150, the adhesive removal process, can be:
[0100] Nitrogen gas with a flow rate of 150 sccm and oxygen gas with a flow rate of 100 sccm are introduced. The pressure in the process chamber is controlled at 8 mT, the source RF power is controlled at 1000 W, the bias RF voltage is controlled at 100 V, and the time is controlled at 30 s.
[0101] For example, in another embodiment, the process formulation in step S150, the adhesive removal process, can be:
[0102] Nitrogen gas with a flow rate of 150 sccm and oxygen gas with a flow rate of 100 sccm are introduced. The pressure in the process chamber is controlled at 5 mT, the source RF power is controlled at 1200 W, the bias RF voltage is controlled at 100 V, and the time is controlled at 30 s.
[0103] Therefore, under the above-mentioned resist removal process formulation, compared with the traditional etching process, the embodiments of the present invention can increase the sidewall angle of the hard mask layer from 70°-80° in the traditional process to 85°-90°, widening the process window, significantly improving the linewidth control capability, reducing the dependence on etching selectivity, and improving the pattern transfer accuracy.
[0104] S160, Etching dielectric layer 600: Using a hard mask layer 400 with a preset pattern as a mask, the dielectric layer 600 is etched to form a hole structure in the dielectric layer 600; further, metal is filled into the hole structure to form a metal interconnect structure.
[0105] The aforementioned hole structure may include trenches and / or through holes. Through holes and trenches can form a damascus structure. Subsequently, the damascus structure is filled with metal to form an interconnect structure.
[0106] Optionally, the dielectric layer 600 is selectively etched based on the hard mask layer 400 with a preset pattern to form a through-hole through the dielectric layer 600.
[0107] Optionally, the metal filler in the above-mentioned hole structure can be any suitable metal material, such as ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), copper (Cu) or similar metals.
[0108] In this embodiment of the invention, after the resist removal step is completed, a hard mask layer 400 with a preset pattern can be formed, and then damascus etching can be performed to transfer the vertical hard mask pattern to the dielectric layer 600, which improves the pattern transfer accuracy and thus improves the product yield.
[0109] It should be noted that the present invention does not impose special restrictions on the specific process conditions for etching the dielectric layer; the operating conditions in related technologies can be referred to, and will not be repeated here.
[0110] Therefore, based on the above steps, especially the parameter optimization of the resist removal process, the morphology of the hard mask layer is optimized through low-cost parameter pressure and source RF power adjustment. No new equipment is required, the effect is significantly improved, and the cost is low. The etching method of this invention can significantly improve the linewidth uniformity of damascene etching and is suitable for more advanced processes such as 7nm / 5nm.
[0111] As another optional implementation of the disclosure of this invention, an embodiment of this invention also discloses a semiconductor structure, which is fabricated using the aforementioned etching method.
[0112] Optionally, the semiconductor structure includes a substrate and a metal interconnect structure disposed on the substrate. Optionally, the metal interconnect structure can be a copper interconnect structure.
[0113] It should be noted that this invention does not limit the specific form of the metal interconnect structure in the semiconductor structure. As an example, in this semiconductor structure, the interconnect structure includes various conductive components to connect various IC devices to the integrated circuit. For example, the interconnect structure includes contacts, metal lines, and vias. The metal lines are distributed in multiple metal layers. For example, the metal lines may include copper, aluminum-copper alloys, other suitable conductive materials, or combinations thereof. The vias may include copper, aluminum-copper alloys, other suitable conductive materials, or combinations thereof. The contacts may include tungsten, silicides, nickel, cobalt, copper, other suitable conductive materials, or combinations thereof. In some instances, the various conductive components may further include barrier layers such as tantalum and tantalum nitride, titanium and titanium nitride, without limitation.
[0114] In semiconductor structures, the ILD layer comprises one or more dielectric materials to provide isolation to various device components (such as gates) and various conductive parts (such as metal lines, contacts, and vias). The ILD layer includes dielectric materials such as silicon oxide, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Some examples of low-k dielectric materials include fluorinated silicon glass, carbon-doped silicon oxide, xylene, aerogel, amorphous fluorinated carbon, parylene, bisbenzocyclobutene, polyimide, and / or other suitable dielectric materials with a dielectric constant substantially less than that of thermally heated silicon oxide.
[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for etching a semiconductor structure, characterized in that, The etching method includes: A substrate is provided on which a dielectric layer, a hard mask layer, and a patterned photolithographic structure are formed; Using the patterned photolithography structure as a mask, the hard mask layer is etched to form a hard mask layer with an initial pattern; The patterned photolithographic structure is removed using a resist-removal process, and a hard mask layer with a preset pattern is formed. In this process, the radio frequency power and the pressure of the process chamber are adjusted to transform the hard mask layer with the initial pattern into the hard mask layer with the preset pattern. The adjustment of the radio frequency power and the pressure of the process chamber in the adhesive removal process includes: increasing the radio frequency power and decreasing the pressure of the process chamber; The radio frequency power is 500W to 1200W, and the pressure in the process chamber is 5mT to 30mT. The process conditions in the degumming process also include: the process gas includes oxygen, or a mixture of nitrogen and oxygen.
2. The etching method for a semiconductor structure according to claim 1, characterized in that, In the degumming process, the flow rate of nitrogen is in the range of 0 sccm to 300 sccm; the flow rate of oxygen is in the range of 100 sccm to 200 sccm. The bias RF voltage range is 20V to 200V; The process time ranges from 30s to 80s.
3. The etching method for a semiconductor structure according to any one of claims 1 to 2, characterized in that, The hard mask layer includes a titanium nitride hard mask layer.
4. The etching method for a semiconductor structure according to claim 3, characterized in that, The etching of the hard mask layer includes: The titanium nitride hard mask layer is etched using a first plasma etching process. The titanium nitride hard mask layer was over-etched using a second plasma etching process.
5. The etching method for a semiconductor structure according to claim 4, characterized in that, The process conditions for the first plasma etching process include: The process gases include methane and chlorine, with the flow rate of methane ranging from 5 sccm to 30 sccm and the flow rate of chlorine ranging from 30 sccm to 100 sccm; the pressure of the process chamber is 3 mT to 15 mT; the radio frequency power is 400 W to 1000 W; and the bias radio frequency voltage range is 20 V to 100 V. And / or, the process conditions for the second plasma etching process include: The process gases include methane and chlorine, with the flow rate of methane ranging from 3 sccm to 25 sccm and the flow rate of chlorine ranging from 30 sccm to 100 sccm; the pressure of the process chamber is 3 mT to 15 mT; the radio frequency power is 400 W to 1000 W; and the bias radio frequency voltage ranges from 20 V to 100 V.
6. The etching method for a semiconductor structure according to any one of claims 1 to 2, characterized in that, The patterned photolithography structure includes a patterned photoresist layer and an anti-reflective coating. An oxide layer is further disposed between the patterned photolithography structure and the hard mask layer, and the patterned photoresist layer, the anti-reflective coating, the oxide layer, and the hard mask layer are sequentially disposed; the etching method includes: Using the patterned photoresist layer as a mask, the anti-reflective coating is etched to form a patterned anti-reflective coating; Using the patterned photoresist layer and the patterned anti-reflective coating as masks, the oxide layer is etched to form a patterned oxide layer, and the patterned photoresist layer is removed. Using the patterned anti-reflective coating and the patterned oxide layer as masks, the hard mask layer is etched to form a hard mask layer with an initial pattern. The patterned anti-reflective coating is removed using a de-adhesive process, and a hard mask layer with a preset pattern is formed.
7. The etching method for a semiconductor structure according to any one of claims 1 to 2, characterized in that, Following the glue removal process, the method further includes: Using the hard mask layer with the preset pattern as a mask, the dielectric layer is etched to form a hole structure in the dielectric layer; Metal is filled into the hole structure to form a metal interconnect structure.
8. A semiconductor structure, characterized in that, The semiconductor structure is fabricated using the etching method for semiconductor structures as described in any one of claims 1 to 7; The semiconductor structure includes a substrate and a metal interconnect structure disposed on the substrate.