Battery anti-reverse connection circuit and analog power chip

Abstract

The invention provides a battery anti-reverse connection circuit and an analog power chip, and belongs to the field of battery protection. Comprising a control circuit with a power supply end connected with a first power supply end; the grid electrode of the first NMOS tube is connected with the first output end of the control circuit, and the drain electrode of the first NMOS tube is connected with the second power supply end; one end of the protection module is connected with the power end of the control circuit and the other end is grounded; the first switch unit is connected between the drain electrode of the first NMOS tube and the substrate, and the second output end of the control circuit is connected with the first switch unit; when the battery is positively connected, the source electrode of the first NMOS tube is connected with the negative electrode of the battery, and the control circuit is used for controlling the first NMOS tube to be switched on or switched off; when the battery is reversely connected, the source electrode of the first NMOS tube is connected with the positive electrode of the battery, and the control circuit controls the first switch unit to be closed. The invention aims to solve the problem that an internal circuit of a battery in the prior art does not have a reverse connection prevention function. The battery has an anti-reverse connection function so as to guarantee safety.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of battery protection, and in particular to a battery reverse connection prevention circuit and an analog power chip. BACKGROUND

[0002] With the rapid development of science and technology, chemical batteries have been widely used in many fields such as consumer electronics, electric vehicles and energy storage systems due to their high energy density, rechargeable advantages and other advantages. In the field of consumer electronics, chemical batteries provide stable power for various portable devices to support long-time operation; in the electric vehicle industry, it is the key power source to drive the vehicle to run; in the energy storage system, chemical batteries can realize the storage and rational allocation of electric energy, and improve energy utilization efficiency.

[0003] However, the safety and stability of chemical batteries have become the focus of the industry. In the production end of the battery, the production process is complex, and if not properly managed, it is easy to hide safety hazards. In the use end of the battery, there is a serious problem that needs to be solved: when the positive and negative electrodes of the battery are reversely connected in the system, since some load sources do not have the function of preventing battery reverse connection, this will cause some devices in the whole system to be damaged. In addition, during the reverse connection of the battery, it may also cause fire and explosion due to internal short circuit and other reasons, which not only causes property loss, but also may threaten personal safety. SUMMARY

[0004] The present application provides a battery reverse connection prevention circuit and an analog power chip to solve the defect that the internal circuit of the battery in the prior art does not have the function of preventing reverse connection, and to realize that the battery has the function of preventing reverse connection to ensure safety.

[0005] The first aspect of the present application provides a battery reverse connection prevention circuit, comprising a control circuit, a protection module, a first switch unit and a first NMOS tube.

[0006] The power supply end of the control circuit is connected to the first power supply end;

[0007] The gate of the first NMOS tube is connected to the first output end of the control circuit, and the drain of the first NMOS tube is connected to the second power supply end;

[0008] One end of the protection module is connected to the power supply end of the control circuit, and the other end of the protection module is grounded;

[0009] The first switch unit is connected between the drain of the first NMOS tube and the substrate of the first NMOS tube, and the second output end of the control circuit is connected to the first switch unit;

[0010] When the battery is connected in positive, the source of the first NMOS tube is connected to the negative electrode of the battery, and the control circuit is used to control the first NMOS tube to be turned on or turned off;

[0011] When the battery is reversely connected, the source of the first NMOS is connected with the positive pole of the battery, and the control circuit controls the first switch unit to be closed;

[0012] The first power supply end and the second power supply end are used for connecting a charger or a load.

[0013] In addition, the battery reverse connection prevention circuit according to the present application can further have the following additional technical features:

[0014] In some embodiments of the present application, a low-voltage comparator is further included, the low-voltage comparator is integrated on the control circuit, a first input end of the low-voltage comparator is connected with the ground, a second input end of the low-voltage comparator is connected with the power supply end of the control circuit, and an output end of the low-voltage comparator is connected with the first switch unit.

[0015] In some embodiments of the present application, the low-voltage comparator includes a minimum voltage selection circuit, a comparator circuit and a comparator output stage, a first input end of the minimum voltage selection circuit is connected with the second power supply end, a second input end of the minimum voltage selection circuit is connected with the ground, and an output end of the minimum voltage selection circuit is connected with a first input end of the comparator circuit; a second input end of the comparator circuit is connected with the power supply end of the control circuit, and an output end of the comparator circuit is connected with the first switch unit.

[0016] In some embodiments of the present application, the minimum voltage selection circuit includes a second NMOS and a third NMOS, a gate of the second NMOS is connected with the second power supply end, a gate of the third NMOS is connected with the ground, a drain of the second NMOS is connected with the ground, and a drain of the third NMOS is connected with the second power supply end; a source of the second NMOS and a source of the third NMOS are both connected with the first input end of the comparator circuit.

[0017] In some embodiments of the present application, the comparator circuit includes a first comparator module and a first triode, a first end of the first triode is connected with the output end of the minimum voltage selection circuit, a first input end of the first comparator module is connected with a second end of the first triode, a second input end of the first comparator module is connected with the power supply end of the control circuit, and an output end of the first comparator module is connected with the comparator output stage.

[0018] In some embodiments of the present application, the comparator output stage includes a first inverter, an input end of the first inverter is connected with the output end of the first comparator module, and an output end of the first inverter is connected with the first switch unit.

[0019] In some embodiments of the present application, the first comparator module includes a fourth NMOS, a fifth NMOS, a first PMOS and a second PMOS, and the first triode includes a sixth NMOS.

[0020] The gate of the fourth NMOS transistor, the gate of the fifth NMOS transistor and the source of the sixth NMOS transistor are connected with the output terminal of the lowest voltage selection circuit; the source of the fourth NMOS transistor and the source of the fifth NMOS transistor are connected with the drain of the sixth NMOS transistor; the gate of the sixth NMOS transistor is grounded;

[0021] The drain of the first PMOS transistor, the gate of the first PMOS transistor and the gate of the second PMOS transistor are connected with the drain of the fourth NMOS transistor, the drain of the fifth NMOS transistor is connected with the drain of the second PMOS transistor, the input terminal of the first inverter is connected between the drain of the fifth NMOS transistor and the drain of the second PMOS transistor, the source of the first PMOS transistor is grounded, and the source of the second PMOS transistor is connected with the power terminal of the control circuit.

[0022] In some embodiments of the present application, the comparator circuit comprises a second three-transistor and a second comparator module, the first end of the second three-transistor is connected with the output terminal of the lowest voltage selection circuit, the first input terminal of the second comparator module is connected with the second end of the second three-transistor, the second input terminal of the second comparator module is connected with the power terminal of the control circuit, and the output terminal of the second comparator module is connected with the input terminal of the comparator output stage.

[0023] In some embodiments of the present application, the comparator output stage comprises a second inverter and a third inverter, the input terminal of the second inverter is connected with the output terminal of the second comparator module, the input terminal of the third inverter is connected with the output terminal of the second inverter, and the output terminal of the third inverter is connected with the first switch unit.

[0024] In some embodiments of the present application, the second comparator module comprises a seventh NMOS transistor, an eighth NMOS transistor, a third PMOS transistor and a fourth PMOS transistor, and the second three-transistor comprises a ninth NMOS transistor.

[0025] The gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor and the source of the ninth NMOS transistor are connected with the output terminal of the lowest voltage selection circuit; the source of the seventh NMOS transistor and the source of the eighth NMOS transistor are connected with the drain of the ninth NMOS transistor; and the gate of the ninth NMOS transistor is grounded.

[0026] The source of the third PMOS transistor is grounded, and the drain of the third PMOS transistor is connected with the drain of the seventh NMOS transistor.

[0027] The gate of the third PMOS transistor, the gate of the fourth PMOS transistor, the drain of the fourth PMOS transistor and the drain of the eighth NMOS transistor are connected with node B, and the input terminal of the comparator output stage is connected between the drain of the eighth NMOS transistor and node B.

[0028] The source of the fourth PMOS transistor is connected with the power terminal of the control circuit.

[0029] The second aspect of the present application provides a simulation power chip comprising all the technical features of the battery reverse connection prevention circuit of the first aspect of the present application.

[0030] In summary, the present application has the following beneficial technical effects: when the battery is reversely connected, the control circuit controls the first switch unit to be closed, so that the parasitic diode of the first NMOS tube does not conduct, and the current flowing through the loop of the load is 0, thereby protecting the load and avoiding damage to each circuit device, and avoiding extreme dangerous situations such as fire and explosion due to internal short circuit, reducing property loss and ensuring safety performance. BRIEF DESCRIPTION OF DRAWINGS

[0031] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The detailed description is made with reference to the accompanying drawings.

[0032] Figure 1 A structural schematic diagram of the battery reverse connection prevention circuit of some embodiments of the present application is shown.

[0033] Figure 2 A structural schematic diagram of the low-voltage comparator of the battery reverse connection prevention circuit of some embodiments of the present application is shown.

[0034] Figure 3 A circuit structural schematic diagram of the low-voltage comparator of the battery reverse connection prevention circuit of some embodiments of the present application is shown.

[0035] Figure 4 Another circuit structural schematic diagram of the low-voltage comparator of the battery reverse connection prevention circuit of some embodiments of the present application is shown.

[0036] Figure 5 Another circuit structural schematic diagram of the low-voltage comparator of the battery reverse connection prevention circuit of some embodiments of the present application is shown.

[0037] Figure 6 Another circuit structural schematic diagram of the low-voltage comparator of the battery reverse connection prevention circuit of some embodiments of the present application is shown.

[0038] Figure 7 Another circuit structural schematic diagram of the low-voltage comparator of the battery reverse connection prevention circuit of some embodiments of the present application is shown.

[0039] Figure 8Another schematic diagram of the low voltage comparator of the battery reverse connection prevention circuit of some embodiments of the present application is shown.

[0040] Figure 9 Another schematic diagram of the low voltage comparator of the battery reverse connection prevention circuit of some embodiments of the present application is shown.

[0041] Figure 10 A schematic diagram of the lowest voltage selection circuit of the battery reverse connection prevention circuit of some embodiments of the present application is shown.

[0042] Figure 11 A schematic diagram of the existing circuit structure when the battery is reverse connected of some embodiments of the present application is shown.

[0043] Figure 12 A schematic diagram of the existing battery discharge plus battery analog power chip of some embodiments of the present application is shown.

[0044] Reference Signs:

[0045] 1, control circuit, 2, battery, 3, load, 4, first NMOS tube, 5, first switch unit, 6, second switch unit, 7, protection module, 8, filter resistance, 9, low voltage comparator, 91, comparator circuit, 911, first comparator module, 9111, fourth NMOS tube, 9112, fifth NMOS tube, 9113, first PMOS tube, 9114, second PMOS tube, 9115, adjusting resistance, 912, first triode, 9121, sixth NMOS tube, 913, second comparator module, 9131, seventh NMOS tube, 9132, eighth NMOS tube, 9133, third PMOS tube, 9134, fourth PMOS tube, 9135, tenth NMOS tube, 9136, eleventh NMOS tube, 9137, fifth PMOS tube, 9138, sixth PMOS tube, 914, second triode, 9141, ninth NMOS tube, 9142, twelfth NMOS tube, 9143, thirteenth NMOS tube, 92, lowest voltage selection circuit, 921, second NMOS tube, 922, third NMOS tube, 93, comparator output stage, 931, first inverter, 932, second inverter, 933, third inverter. DETAILED DESCRIPTION

[0046] Exemplary embodiments of the present disclosure will be described hereinafter with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be embodied in various forms without being limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0047] It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", "including" and "has" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order in which they are described unless specifically identified as an order dependent step. It is also to be understood that additional or alternative steps can be employed.

[0048] Although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as "first", "second", and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.

[0049] Spatially relative terms, such as "inner", "outer", "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the example term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0050] In daily use, it is a common phenomenon that the battery with load 3 is reversed. The traditional chemical battery discharge plus the model of battery analog power chip is as follows Figure 12As shown, an IC is used to detect the battery voltage and discharge current to turn on or off the first NMOS transistor 4 (NM0) to ensure safe battery operation. When a load 3 is connected between the first power terminal (P+) and the second power terminal (P-), the analog power chip controls SW0 (the second switch unit) to close. At this time, the battery is in the discharge state and operates normally with load 3.

[0051] When the battery is reversed, Figure 11 As shown, the VDD voltage, or the voltage at the first power supply terminal, is negative. The voltage at the power supply terminal of the control circuit 1, or VDD1, is also negative, meaning the analog power chip's supply voltage is negative, preventing it from turning on the first NMOS transistor 4, or NM0. Furthermore, the negative voltage at the power supply terminal, or VDD1, causes internal control chaos within the analog power chip, making it impossible to maintain the states of the first switch unit 5, or SW1, and the second switch unit 6, or SW0, shown in the figure. When switch SW0 is closed, NM0 is turned off. At this point, the parasitic diode Dnm0 of the first NMOS transistor 4, or NM0, points from ground to the second power supply terminal, or P-. Assuming the battery voltage is 4V, the forward voltage of diode D0 is 0.65V, and the forward voltage of parasitic diode Dnm0 is 0.6V. At this time, the voltage at the first power supply terminal, or VDD, is -4V, equal to P+. The voltage at the power supply terminal of the control circuit 1, or VDD1, is clamped to -0.65V by diode D0. When the power supply of the analog power chip is negative, the system logic is disordered and the output voltage is negative. At this time, the maximum drain voltage of the first NMOS transistor 4, namely NM0, is -0.65V, which is the highest voltage in the system. The parasitic diode Dnm0 of the first NMOS transistor 4, namely NM0, is turned on. At this time, a large current flows through the load 3 circuit, which may cause damage to some components of the system or cause fire and explosion.

[0052] like Figures 1 to 10 As shown, according to an embodiment of the first aspect of the present invention, a battery reverse connection protection circuit is proposed, including a control circuit 1, a protection module 7, a first switch unit 5, a low-voltage comparator 9 and a first NMOS transistor 4;

[0053] The power supply terminal of the control circuit 1 is connected to the first power supply terminal;

[0054] The gate of the first NMOS transistor 4 is connected to the first output terminal of the control circuit 1, the source of the first NMOS transistor 4 is connected to the battery 2, and the drain of the first NMOS transistor 4 is connected to the second power supply terminal;

[0055] One end of the protection module 7 is connected to the power supply end of the control circuit 1, and the other end of the protection module 7 is grounded;

[0056] The first switch unit 5 is connected between the drain of the first NMOS transistor 4 and the substrate of the first NMOS transistor 4 , and the second output end of the control circuit 1 is connected to the first switch unit 5 ;

[0057] When the battery 2 is connected in positive, the source of the first NMOS tube 4 is connected with the negative pole of the battery 2, and the control circuit 1 is used to control the first NMOS tube 4 to be turned on or turned off.

[0058] When the battery 2 is connected in reverse, the source of the first NMOS tube 4 is connected with the positive pole of the battery 2, and the control circuit 1 controls the first switch unit 5 to be closed.

[0059] The first power supply end and the second power supply end are used to connect the charger or the load 3.

[0060] In the above embodiment, it is to be noted that the control circuit 1 used to control the first NMOS tube 4 to be turned on and turned off further comprises a second switch unit 6 and a filter resistor 8, the protection module 7 is a diode or an NMOS tube or a PMOS tube or a triode, etc., the filter resistor 8 is connected in series before the control circuit 1 and the protection module 7; the filter resistor 8 can be a variable resistor, and can also be a resistor externally connected with a capacitor; the second switch unit 6 is connected in parallel between the gate and the source of the first NMOS tube 4; in addition, as shown in the figure, the first power supply end is P+ as VDD, the second power supply end is P-, and the power supply end of the battery is VDD1. Figure 1

[0061] The technical effect achieved by the above embodiment is that when the battery 2 is connected in reverse, the control circuit 1 controls the first switch unit 5 to be closed, so that the parasitic diode of the first NMOS tube 4 will not be turned on, and the current flowing through the loop of the load 3 is 0, thereby protecting the load 3, avoiding the damage of each circuit device, and avoiding the extreme dangerous situation of fire and explosion due to internal short circuit, etc., reducing the property loss and ensuring the safety performance.

[0062] Optionally, as shown in the figure, it further comprises a low-voltage comparator 9, the low-voltage comparator 9 is integrated on the control circuit 1, the first input end of the low-voltage comparator 9 is grounded, the second input end of the low-voltage comparator 9 is connected with the power supply end of the control circuit 1, and the output end of the low-voltage comparator 9 is connected with the first switch unit 5. Figures 1 to 10

[0063] The working principle of the circuit is that when the battery is connected in reverse, the control circuit 1 power supply end VDD1 is negative, which is lower than the ground voltage VSS, and the low-voltage comparator 9 outputs a relatively high logic signal to control the first switch unit 5, i.e. SW1, to be closed.

[0064] ​​When the voltage at the second power supply end of the low-voltage comparator 9 is less than the signal of the voltage to the ground, a correct logic signal is output to control the first switch unit 5, i.e. SW1, to be closed, the analog power chip controls the gate end of the first NMOS tube 4 to be a low voltage, the first NMOS tube 4 is turned off, and at this time, the direction of the parasitic diode Dnm0 of the first NMOS tube 4 is from the second power supply end P- to the ground.

[0065] Supposing that the turn-on voltage of the protection module 7 is 0.6V, only when the signal at the second power supply end P- is greater than the turn-on voltage of the protection module 7, i.e. 0.6V or above, the parasitic diode Dnm0 is turned on, and at this time, the voltage at the power supply end of the control circuit 1, i.e. VDD1, as the highest voltage in the system is near -0.6V, the parasitic diode Dnm0 is definitely not turned on, and thus the current I0 flowing through the loop of the load 3 is almost 0.

[0066] In addition to the control of the first switch unit 5 to be closed by the low-voltage comparator 9, other ways of controlling the first switch unit 5 to be closed in the state of the reverse connection of the battery 2 can also be adopted.

[0067] The above-mentioned optional embodiment has the beneficial effect that the first switch unit 5 is immediately controlled to be closed when the battery is reversely connected through the setting of the low-voltage comparator 9, and thus the parasitic diode of the first NMOS tube 4 is not turned on, and thus the current flowing through the loop of the load 3 is 0, and thus the load 3 is protected, the damage of the circuit devices is avoided, the extreme dangerous situation such as fire and explosion caused by internal short circuit is avoided, the property loss is reduced, and the safety performance is ensured.

[0068] Optionally, as shown in Figures 2 to 10 The low-voltage comparator 9 comprises a minimum voltage selection circuit 92, a comparator circuit 91 and a comparator output stage 93, the first input end of the minimum voltage selection circuit 92 is connected with the second power supply end, the second input end of the minimum voltage selection circuit 92 is grounded, the output end of the minimum voltage selection circuit 92 is connected with the first input end of the comparator circuit 91; the second input end of the comparator circuit 91 is connected with the power supply end of the control circuit 1, the output end of the comparator circuit 91 is connected with the input end of the comparator output stage 93, and the output end of the comparator output stage 93 is connected with the first switch unit 5.

[0069] Optionally, as shown in Figure 10As shown, the lowest voltage selection circuit 92 comprises a second NMOS tube 921 and a third NMOS tube 922, the gate of the second NMOS tube 921 is connected with the second power supply end, the gate of the third NMOS tube 922 is grounded, the drain of the second NMOS tube 921 is grounded, and the drain of the third NMOS tube 922 is connected with the second power supply end; the source of the second NMOS tube 921 and the source of the third NMOS tube 922 are both connected with the first input end of the comparator circuit 91.

[0070] In the above optional embodiment, it is to be noted that the working principle of the lowest voltage selection circuit 92 is that when the battery 2 is normally loaded, the ground voltage is less than the voltage of the second power supply end, i.e. VSS

[0071] When the battery is reversely connected and loaded, the ground voltage is greater than the voltage of the second power supply end, i.e. VSS>P-; the third NMOS tube 922 is turned on, and the voltage of the output end of the lowest voltage selection circuit 92 is less than the ground voltage, i.e. VB

[0072] The above optional embodiment has the beneficial effect that the low voltage comparator 9 is not controlled by the control circuit 1 and can control the closing of the first switch unit 5 according to the reverse connection of the battery 2 through the setting of the lowest voltage selection circuit 92, thereby ensuring the reliability.

[0073] Optionally, as shown in Figure 4 , Figure 6 and Figure 7 , the comparator circuit 91 comprises a first comparator module 911 and a first triode 912, the first end of the first triode 912 is connected with the output end of the lowest voltage selection circuit 92, the first input end of the first comparator module 911 is connected with the second end of the first triode 912, the second input end of the first comparator module 911 is connected with the power supply end of the control circuit 1, and the output end of the first comparator module 911 is connected with the comparator output stage 93.

[0074] The comparator output stage 93 comprises a first inverter 931, the input end of the first inverter 931 is connected with the output end of the first comparator module 911, and the output end of the first inverter 931 is connected with the first switch unit 5.

[0075] Optionally, as shown in Figure 6 and Figure 7As shown, the first comparator module 911 includes a fourth NMOS transistor 9111, a fifth NMOS transistor 9112, a first PMOS transistor 9113 and a second PMOS transistor 9114, the first triode 912 includes a sixth NMOS transistor 9121;

[0076] The gate of the fourth NMOS transistor 9111, the gate of the fifth NMOS transistor 9112 and the source of the sixth NMOS transistor 9121 are connected with the output end of the lowest voltage selection circuit 92; the source of the fourth NMOS transistor 9111 and the source of the fifth NMOS transistor 9112 are connected with the drain of the sixth NMOS transistor 9121; the gate of the sixth NMOS transistor 9121 is grounded;

[0077] The drain of the first PMOS transistor 9113, the gate of the first PMOS transistor 9113 and the gate of the second PMOS transistor 9114 are connected with the drain of the fourth NMOS transistor 9111, the drain of the fifth NMOS transistor is connected with the drain of the second PMOS transistor 9114, the input end of the first inverter 931 is connected between the drain of the fifth NMOS transistor and the drain of the second PMOS transistor 9114, the source of the first PMOS transistor 9113 is grounded, and the source of the second PMOS transistor 9114 is connected with the power supply end of the control circuit 1.

[0078] The first comparator module 911 further includes an adjusting resistor 9115 connected between the second PMOS transistor 9114 and the power supply end of the control circuit 1.

[0079] In the above optional embodiment, it should be noted that when the battery is reversely connected, assuming that the on voltage of the protection module 7 is 0.65V, at this time, the voltage of the power supply end of the control circuit 1, i.e. VDD1 is -0.65V; wherein the output voltage VB of the lowest voltage selection circuit 92 is the lowest level in the analog power chip, which is the negative voltage of the battery 2, i.e. -VBAT, assuming -4V; at this time, the sixth NMOS transistor 9121 is turned on, which plays a role of current source in the circuit, and the fourth NMOS transistor 9111, the fifth NMOS transistor 9112 and the sixth NMOS transistor 9121 are all depletion-mode NMOS transistors, which are also turned on at this time; the first PMOS transistor 9113 in diode connection is turned on, Figure 6 The voltage at point A is a threshold voltage of the first PMOS transistor 9113, assuming that the threshold voltage of the first PMOS transistor 9113 is -0.7V, then PM1 is cut off, and the voltage at point B is the output voltage of the lowest voltage selection circuit 92, i.e. the low level of the voltage VB, after the direct current to alternating current inverter of the first inverter 931, the signal_select signal output is high relative to the output voltage of the lowest voltage selection circuit 92, which controls the first switch unit 5 to be closed.

[0080] The fourth NMOS tube 9111, the fifth NMOS tube 9112 and the sixth NMOS tube 9121 can be replaced by NPN type triodes, and the specific circuit diagram can be adjusted according to actual conditions, which will not be discussed here.

[0081] The first PMOS tube 9113 and the second PMOS tube 9114 can be replaced by PNP type triodes, and the specific circuit diagram can be adjusted according to actual conditions, which will not be discussed here.

[0082] The beneficial effects of the above-mentioned optional embodiments are that the level of node B can be flexibly controlled through the cooperation of the fourth NMOS tube 9111, the fifth NMOS tube 9112, the first PMOS tube 9113, the second PMOS tube 9114 and the sixth NMOS tube 9121, and then the final output level is accurately adjusted through the first inverter 9321, which can realize the functions of signal detection, level conversion and accurate control of the closing of the first switch unit 5.

[0083] The flip threshold of the low-voltage comparator 4 can be changed by adjusting the setting of the resistor 9115, thereby adapting to different reverse connection prevention of the battery 2.

[0084] Optionally, as shown in Figure 5 , Figure 8 and Figure 9 , the comparator circuit 91 includes a second triode 914 and a second comparator module 913, the first end of the second triode 914 is connected with the output end of the lowest voltage selection circuit 92, the first input end of the second comparator module 913 is connected with the second end of the second triode 914, the second input end of the second comparator module 913 is connected with the power supply end of the control circuit 1, and the output end of the second comparator module 913 is connected with the input end of the comparator output stage 93.

[0085] Optionally, as shown in Figure 8 and Figure 9 , the comparator output stage 93 includes a second inverter 932 and a third inverter 933, the input end of the second inverter 932 is connected with the output end of the second comparator module 913, the input end of the third inverter 933 is connected with the output end of the second inverter 932, and the output end of the third inverter 933 is connected with the first switch unit 5.

[0086] As shown in Figure 8 , the second comparator module 913 includes a seventh NMOS tube 9131, an eighth NMOS tube 9132, a third PMOS tube 9133 and a fourth PMOS tube 9134, and the second triode 914 includes a ninth NMOS tube 9141.

[0087] The gate of the seventh NMOS transistor 9131, the gate of the eighth NMOS transistor 9132 and the source of the ninth NMOS transistor 9141 are connected to the output terminal of the lowest voltage selection circuit 92; the source of the seventh NMOS transistor 9131 and the source of the eighth NMOS transistor 9132 are connected to the drain of the ninth NMOS transistor 9141; the gate of the ninth NMOS transistor 9141 is grounded;

[0088] The source of the third PMOS transistor 9133 is grounded, and the drain of the third PMOS transistor 9133 is connected to the drain of the seventh NMOS transistor 9131;

[0089] The gate of the third PMOS transistor 9133, the gate of the fourth PMOS transistor 9134, the drain of the fourth PMOS transistor 9134 and the drain of the eighth NMOS transistor 9132 are connected to node B, and the input terminal of the comparator output stage 93 is connected between the drain of the eighth NMOS transistor 9132 and node B;

[0090] The source of the fourth PMOS transistor 9134 is connected to the power terminal of the control circuit 1.

[0091] In the above optional embodiment, it should be noted that the seventh NMOS transistor 9131, the eighth NMOS transistor 9132 and the ninth NMOS transistor 9141 are all depletion-mode NMOS transistors.

[0092] The structure of the comparator circuit 91 formed by the second three-transistor 914 and the second comparator module 913 utilizes the substrate bias effect of MOS transistors.

[0093] The substrate terminals of the third PMOS transistor 9133 and the fourth PMOS transistor 9134 are connected to different potentials, the level of the power terminal VDD1 of the control circuit is lower than the level of the ground terminal VSS, and then the threshold voltage of the fourth PMOS transistor 9134 is lower than the threshold voltage of the third PMOS transistor 9133; assuming that the threshold voltage of the fourth PMOS transistor 9134 is -0.2V and the threshold voltage of the third PMOS transistor 9133 is -0.7V, at this time, the fourth PMOS transistor 9134 is in diode connection, the fourth PMOS transistor 9134 is turned on, the potential of node B is around -0.2V, the third PMOS transistor 9133 cannot be turned on, and the current generated by the ninth NMOS transistor 9141 all flows to the branch of the fourth PMOS transistor 9134, B point is pulled to a relatively high level, and after passing through the second inverter 9321 and the third inverter 9322, the output signal signal_select is relatively high with respect to the output voltage VB of the lowest voltage selection circuit 92, and the first switch unit 5 is closed at this time.

[0094] The seventh NMOS tube 9131, the eighth NMOS tube 9132 and the ninth NMOS tube 9141 can be replaced by NPN type triodes, and the specific circuit diagram can be adjusted according to actual conditions, which will not be discussed here.

[0095] The third PMOS tube 9133 and the fourth PMOS tube 9134 can be replaced by PNP type triodes, and the specific circuit diagram can be adjusted according to actual conditions, which will not be discussed here.

[0096] Optionally, as shown in FIG. 9B, the second comparator module 913 includes a tenth NMOS tube 9135, an eleventh NMOS tube 9136, a fifth PMOS tube 9137 and a sixth PMOS tube 9138, and the second three-transistor 914 includes a twelfth NMOS tube 9142 and a thirteenth NMOS tube 9143. Figure 9

[0097] The source of the tenth NMOS tube 9135 and the source of the eleventh NMOS tube 9136 are connected to the drain of the thirteenth NMOS tube, the gate of the twelfth NMOS tube 9142 and the source of the thirteenth NMOS tube 9143 are connected to the output end of the lowest voltage selection circuit 92, the drain of the twelfth NMOS tube 9142 is connected to the source of the thirteenth NMOS tube, and the gate of the thirteenth NMOS tube is grounded.

[0098] The drain of the fifth PMOS tube 9137 and the gate of the fifth PMOS tube 9137 are connected to the drain of the tenth NMOS tube 9135, the drain of the sixth PMOS tube 9138 is connected to the drain of the eleventh NMOS tube 9136, and the input end of the second inverter 9231 is connected between the drain of the sixth PMOS tube 9138 and the drain of the eleventh NMOS tube 9136.

[0099] The gate of the tenth NMOS tube 9135 is grounded, the gate of the eleventh NMOS tube 9136 is connected to the power supply end of the control circuit, and the source of the fifth PMOS tube 9137 and the source of the sixth PMOS tube 9138 are connected to the power supply end of the control circuit.

[0100] In the above optional embodiment, it should be noted that the tenth NMOS tube 9135, the eleventh NMOS tube 9136 and the twelfth NMOS tube 9142 are all depletion type NMOS tubes.

[0101] The tenth NMOS tube 9135, the eleventh NMOS tube 9136, the twelfth NMOS tube 9142 and the thirteenth NMOS tube 9143 can be replaced by NPN type triodes, and the specific circuit diagram can be adjusted according to actual conditions, which will not be discussed here.

[0102] ​The fifth PMOS tube 9137 and the sixth PMOS tube 9138 can be replaced by PNP type triodes, and the specific circuit diagram can be adjusted according to the actual situation, which will not be discussed here.

[0103] By setting the size of the twelfth NMOS tube 9142 and the thirteenth NMOS tube 9143, when the power end voltage VDD1 of the control circuit 1 is less than the ground voltage VSS, the eleventh NMOS tube 9136 is turned off, and the B point output is relatively high. After passing through the second inverter 9321 and the third inverter 9322, the signal_select signal output relative to VB is high, and the first switch unit 5 is closed at this time.

[0104] The beneficial effects of the above-mentioned optional embodiments are that the above-mentioned scheme can monitor the power supply voltage state in real time, and then detect whether the battery 2 is reversed, when the power end voltage VDD1 of the control circuit 1 is abnormal, the protection mechanism is triggered quickly, the first switch unit 5 is closed, and the circuit can be prevented from being damaged due to power failure. The size of the NMOS tube is used to adjust the threshold and response characteristics of the circuit, and the precise control of the first switch unit 5 is realized, and the reliability and stability of the circuit are improved.

[0105] The embodiments of the second aspect of the present application propose a simulation power chip, which comprises all the technical features of the battery reverse connection protection circuit of the first aspect of the present application.

[0106] The above is only the preferred embodiment of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A battery reverse connection prevention circuit, characterized by comprising: The control circuit, the protection module, the first switch unit and the first NMOS tube are included. The power supply end of the control circuit is connected with the first power supply end. The gate of the first NMOS tube is connected with the first output end of the control circuit, and the drain of the first NMOS tube is connected with the second power supply end. One end of the protection module is connected with the power supply end of the control circuit, and the other end of the protection module is grounded. The first switch unit is connected between the drain of the first NMOS tube and the substrate of the first NMOS tube, and the second output end of the control circuit is connected with the first switch unit. When the battery is connected in positive, the source of the first NMOS tube is connected with the negative pole of the battery, and the control circuit is used for controlling the first NMOS tube to be turned on or turned off. When the battery is connected in reverse, the source of the first NMOS tube is connected with the positive pole of the battery, and the control circuit controls the first switch unit to be closed. The first power supply end and the second power supply end are used for connecting the charger or the load.

2. The battery reverse connection prevention circuit according to claim 1, characterized by, The low-voltage comparator is further included, the low-voltage comparator is integrated on the control circuit, the first input end of the low-voltage comparator is grounded, the second input end of the low-voltage comparator is connected with the power supply end of the control circuit, and the output end of the low-voltage comparator is connected with the first switch unit.

3. The battery reverse connection prevention circuit according to claim 2, characterized by, The low-voltage comparator includes the lowest voltage selection circuit, the comparator circuit and the comparator output stage: The first input end of the lowest voltage selection circuit is connected with the second power supply end, the second input end of the lowest voltage selection circuit is grounded, and the output end of the lowest voltage selection circuit is connected with the first input end of the comparator circuit. The second input end of the comparator circuit is connected with the power supply end of the control circuit, the output end of the comparator circuit is connected with the input end of the comparator output stage, and the output end of the comparator output stage is connected with the first switch unit.

4. The battery reverse connection prevention circuit according to claim 3, wherein The lowest voltage selection circuit includes the second NMOS tube and the third NMOS tube. The gate of the second NMOS tube is connected with the second power supply end, and the gate of the third NMOS tube is grounded. The drain of the second NMOS tube is grounded, and the drain of the third NMOS tube is connected with the second power supply end. The source of the second NMOS tube and the source of the third NMOS tube are both connected with the first input end of the comparator circuit.

5. The battery reverse connection prevention circuit according to claim 3, wherein The comparator circuit includes the first comparator module and the first three transistors. The first end of the first three transistors is connected with the output end of the lowest voltage selection circuit. The first input end of the first comparator module is connected with the second end of the first three transistors, the second input end of the first comparator module is connected with the power supply end of the control circuit, and the output end of the first comparator module is connected with the comparator output stage.

6. The battery reverse connection prevention circuit according to claim 5, wherein The comparator output stage includes the first inverter. The input end of the first inverter is connected with the output end of the first comparator module, and the output end of the first inverter is connected with the first switch unit.

7. The battery reverse connection prevention circuit according to claim 6, wherein The first comparator module comprises a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor and a second PMOS transistor, and the first three-transistor comprises a sixth NMOS transistor; The gate of the fourth NMOS transistor, the gate of the fifth NMOS transistor and the source of the sixth NMOS transistor are connected with the output terminal of the lowest voltage selection circuit; the source of the fourth NMOS transistor and the source of the fifth NMOS transistor are connected with the drain of the sixth NMOS transistor; and the gate of the sixth NMOS transistor is grounded; The drain of the first PMOS transistor, the gate of the first PMOS transistor and the gate of the second PMOS transistor are connected with the drain of the fourth NMOS transistor; the drain of the fifth NMOS transistor is connected with the drain of the second PMOS transistor; the input terminal of the first inverter is connected between the drain of the fifth NMOS transistor and the drain of the second PMOS transistor; the source of the first PMOS transistor is grounded; and the source of the second PMOS transistor is connected with the power supply terminal of the control circuit.

8. The battery reverse connection prevention circuit according to claim 3, wherein The comparator circuit comprises a second three-transistor and a second comparator module; The first end of the second three-transistor is connected with the output terminal of the lowest voltage selection circuit; The first input terminal of the second comparator module is connected with the second end of the second three-transistor; the second input terminal of the second comparator module is connected with the power supply terminal of the control circuit; and the output terminal of the second comparator module is connected with the input terminal of the comparator output stage.

9. The battery reverse connection prevention circuit according to claim 8, wherein The comparator output stage comprises a second inverter and a third inverter; The input terminal of the second inverter is connected with the output terminal of the second comparator module; The input terminal of the third inverter is connected with the output terminal of the second inverter; and the output terminal of the third inverter is connected with the first switch unit.

10. The battery reverse connection prevention circuit according to claim 8, wherein The second comparator module comprises a seventh NMOS transistor, an eighth NMOS transistor, a third PMOS transistor and a fourth PMOS transistor, and the second three-transistor comprises a ninth NMOS transistor; The gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor and the source of the ninth NMOS transistor are connected with the output terminal of the lowest voltage selection circuit; the source of the seventh NMOS transistor and the source of the eighth NMOS transistor are connected with the drain of the ninth NMOS transistor; and the gate of the ninth NMOS transistor is grounded; The source of the third PMOS transistor is grounded; and the drain of the third PMOS transistor is connected with the drain of the seventh NMOS transistor; The gate of the third PMOS transistor, the gate of the fourth PMOS transistor, the drain of the fourth PMOS transistor and the drain of the eighth NMOS transistor are connected with node B; and the input terminal of the comparator output stage is connected between the drain of the eighth NMOS transistor and node B; The source of the fourth PMOS transistor is connected with the power supply terminal of the control circuit.

11. An analog power chip, characterized by The battery reverse connection protection circuit comprises the battery reverse connection protection circuit according to any one of claims 1 to 10.

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