Fully differential peak detection AGC circuit

Abstract

The application relates to the field of feedback type automatic gain control circuits, and discloses a full-differential peak detection AGC circuit, which comprises a multi-stage variable gain amplifier, a buffer amplifier group, a first comparator EA1, a full-differential peak detection unit and an external port; the external port comprises a power supply end VDD, a ground end GND, a negative signal input end INN, a positive signal input end INP, a positive signal output end VON, a negative signal output end VOP, a plurality of bias ports and a reference voltage end VREF; the application adopts a full-differential structure design, can effectively suppress common-mode noise and external interference, and realizes continuous discharge adjustment of the capacitor C11 through the alternate discharge of the first NMOS tube NM1 and the second NMOS tube NM2 on the capacitor C11, avoids the problem of capacitor discharge interruption in traditional peak detection, improves the loop response speed and the gain adjustment precision, and even if one of the differential signals is temporarily missing, the other signal can still drive the peak detection unit and the feedback loop to work, thereby improving the reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of feedback automatic gain control circuit, and particularly relates to a full differential peak detection AGC circuit. BACKGROUND

[0002] Since the advent of radio technology, the basic module of communication technology has been updated from a simple receiving module and a sending module to a more complex and efficient one. The receiver has always been an important iterative module in the development of communication technology in a communication system. With the development of electronic devices, new use scenarios have more stringent and diversified requirements for wireless communication devices, and the performance requirements of the receiver in the wireless communication system have reached a new height. In a wireless communication system, due to the influence of various factors such as environment and noise, the strength of the communication signal may vary greatly, resulting in a wide range of amplitudes of the input signal of the receiver. In order to accurately receive the signal, the receiver usually needs to be equipped with an automatic gain control (AGC) system. As an important module of the radio frequency front end, the performance of the AGC directly affects the performance of the receiver. Therefore, it is of great research significance and practical value to design an AGC with a wide gain control dynamic range, high linearity and low noise.

[0003] The AGC structure described in this paper is easy to integrate into a system on a chip and has good performance, and because of its simple circuit structure, power consumption and response speed are advantages. The full differential structure maximally reduces the adjustment accuracy and response speed of the overall system, and has good anti-interference ability. SUMMARY

[0004] Therefore, it is necessary to propose a full differential peak detection AGC circuit in view of the technical problems of the prior art AGC circuit, such as difficulty in integration, complex structure, high power consumption and poor anti-interference ability. The full differential peak detection AGC circuit comprises a multi-stage variable gain amplifier, a buffer amplifier group, a first comparator EA1, a full differential peak detection unit and an external port. The external port comprises a power supply end VDD, a ground end GND, a negative signal input end INN, a positive signal input end INP, a positive signal output end VON, a negative signal output end VOP, a plurality of bias ports and a reference voltage end VREF.

[0005] The negative signal input end INN and the positive signal input end INP are electrically connected to the input end of the multi-stage variable gain amplifier through a resistance-capacitance network.

[0006] The output end of the multi-stage variable gain amplifier is electrically connected to the input end of the buffer amplifier group through a resistance-capacitance network, and the amplified signal is transmitted to the buffer amplifier group.

[0007] The buffer amplifier group has two-way output, one-way output positive signal output end VON and negative signal output end VOP of full differential peak value detection AGC circuit, the other way output is electrically connected with input end of full differential peak value detection unit, and signal is provided for peak value detection;

[0008] Output end of the full differential peak value detection unit is electrically connected with negative input end of the first comparator EA1, positive input end of the first comparator EA1 is electrically connected with reference voltage end VREF, and output end of the first comparator EA1 is electrically connected with each gain control end of the multi-stage variable gain amplifier, forming a negative feedback control loop.

[0009] The bias port is electrically connected with bias end of the multi-stage variable gain amplifier, the buffer amplifier group, the full differential peak value detection unit and the first comparator EA1, for providing working bias.

[0010] The power supply end VDD of the AGC circuit is electrically connected with power supply end of the multi-stage variable gain amplifier, the buffer amplifier group, the first comparator EA1 and the full differential peak value detection unit, and the grounding end GND of the AGC circuit is electrically connected with grounding end of power supply end of the multi-stage variable gain amplifier, the buffer amplifier group, the first comparator EA1 and the full differential peak value detection unit.

[0011] The all-differential peak detection AGC circuit includes a multi-stage variable gain amplifier, a buffer amplifier group, a first comparator EA1, an all-differential peak detection unit, and an external port; the external port includes a power supply end VDD, a ground end GND, a negative signal input end INN, a positive signal input end INP, a positive signal output end VON, a negative signal output end VOP, a plurality of bias ports, and a reference voltage end VREF; wherein the negative signal input end INN and the positive signal input end INP are electrically connected to the input end of the multi-stage variable gain amplifier through a resistance-capacitance network; the output end of the multi-stage variable gain amplifier is electrically connected to the input end of the buffer amplifier group through a resistance-capacitance network, and the amplified signal is transmitted to the buffer amplifier group; the buffer amplifier group has two outputs, one output being the positive signal output end VON and the negative signal output end VOP of the all-differential peak detection AGC circuit, and the other output being electrically connected to the input end of the all-differential peak detection unit to provide a signal for peak detection; the output end of the all-differential peak detection unit is electrically connected to the negative input end of the first comparator EA1, the positive input end of the first comparator EA1 is electrically connected to the reference voltage end VREF, and the output end of the first comparator EA1 is electrically connected to each gain control end of the multi-stage variable gain amplifier, forming a negative feedback control loop. The bias ports are used for electrically connecting the bias ends of the multi-stage variable gain amplifier, the buffer amplifier group, the all-differential peak detection unit, and the first comparator EA1, and are used for providing working bias; the power supply end VDD of the AGC circuit is electrically connected to the power supply ends of the multi-stage variable gain amplifier, the buffer amplifier group, the first comparator EA1, and the all-differential peak detection unit, and the ground end GND of the AGC circuit is electrically connected to the ground ends of the power supply ends of the multi-stage variable gain amplifier, the buffer amplifier group, the first comparator EA1, and the all-differential peak detection unit. The all-differential structure design can effectively suppress common-mode noise and external interference, improve detection accuracy and output signal stability; the circuit structure is simple, the number of components is reduced, there is no redundant current consumption in the working process, and the power consumption is significantly lower than that of the traditional AGC circuit; the all-differential peak detection unit in the circuit realizes continuous discharge adjustment of the capacitor C11 through the alternate discharge of the first NMOS tube NM1 and the second NMOS tube NM2, avoids the problem of capacitor discharge interruption in the traditional peak detection, improves the loop response speed and gain adjustment accuracy, and even if one of the differential signals is temporarily missing, the other signal can still drive the peak detection unit and the feedback loop to work, ensuring that the AGC circuit normally realizes the output amplitude stability function and improving the reliability of the overall circuit. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings described below are only some of the embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on these drawings without creative labor.

[0013] Wherein:

[0014] Figure 1 It is a circuit structure schematic diagram of a full differential peak detection AGC circuit in an embodiment;

[0015] Figure 2 It is a buffer amplifier schematic diagram of a full differential peak detection AGC circuit in an embodiment;

[0016] Figure 3 It is a comparator schematic diagram of a full differential peak detection AGC circuit in an embodiment. DETAILED DESCRIPTION

[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application; the description and the drawings are to be regarded as illustrative in nature and are not intended to limit the application; the terminology used in the description and the claims of the present application and the above description of the drawings includes the terms specifically mentioned above as well as their derivatives.

[0018] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to those of ordinary skill in the art, embodiments described herein can be combined with other embodiments.

[0019] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of the present application.

[0020] Please refer to Figure 1 as shown, Figure 1A circuit schematic of a full differential peak detection AGC circuit provided by an embodiment of the present application, the full differential peak detection AGC circuit comprising: a multi-stage variable gain amplifier, a buffer amplifier group, a first comparator EA1, a full differential peak detection unit, and an external port; the external port comprising a power supply end VDD, a ground end GND, a negative signal input end INN, a positive signal input end INP, a positive signal output end VON, a negative signal output end VOP, a plurality of bias ports, a reference voltage end VREF;

[0021] The negative signal input end INN and the positive signal input end INP are electrically connected to the input end of the multi-stage variable gain amplifier through a resistance-capacitance network.

[0022] The output end of the multi-stage variable gain amplifier is electrically connected to the input end of the buffer amplifier group through a resistance-capacitance network, and the amplified signal is transmitted to the buffer amplifier group.

[0023] The buffer amplifier group has two outputs, one output being the positive signal output end VON and the negative signal output end VOP of the full differential peak detection AGC circuit, and the other output being electrically connected to the input end of the full differential peak detection unit to provide a signal for peak detection.

[0024] The output end of the full differential peak detection unit is electrically connected to the negative input end of the first comparator EA1, the positive input end of the first comparator EA1 is electrically connected to the reference voltage end VREF, and the output end of the first comparator EA1 is electrically connected to each gain control end of the multi-stage variable gain amplifier, forming a negative feedback control loop.

[0025] The bias ports are used for biasing the multi-stage variable gain amplifier, the buffer amplifier group, the full differential peak detection unit, and the first comparator EA1, and are used for providing working bias.

[0026] The power supply end VDD of the AGC circuit is electrically connected to the power supply ends of the multi-stage variable gain amplifier, the buffer amplifier group, the first comparator EA1, and the full differential peak detection unit, and the ground end GND of the AGC circuit is electrically connected to the ground ends of the power supply ends of the multi-stage variable gain amplifier, the buffer amplifier group, the first comparator EA1, and the full differential peak detection unit.

[0027] In the embodiment, the full differential peak detection AGC circuit is differential input and differential output, the differential output signal of the multi-stage VGA is converted into a direct current control signal by the full differential peak detection circuit, compared with an external reference voltage, the output of the comparator controls the gain control end of the VGA, so that it is adjusted to the target gain; through the above negative feedback process, the output amplitude of the AGC can also be kept relatively stable when the input amplitude changes. The full differential peak detection circuit has stronger anti-interference and higher detection accuracy. The use of the full differential peak detection AGC circuit described in the present application can realize the function of stable output amplitude with simple structure and low power consumption.

[0028] In an embodiment, the multi-stage variable gain amplifier includes a first variable gain amplifier VGA1, a second variable gain amplifier VGA2, a third variable gain amplifier VGA3, and a fourth variable gain amplifier VGA4 connected in cascade; and the resistance-capacitance network includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10.

[0029] The negative signal input end INN is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is connected to one end of the first resistor R1 and the negative input end of the first variable gain amplifier VGA1 respectively, and the other end of the first resistor R1 is connected to the port NVB0; the positive signal input end INP is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is connected to one end of the second resistor R2 and the positive input end of the first variable gain amplifier VGA1 respectively, and the other end of the second resistor R2 is connected to the port NVB0.

[0030] The positive output end of the first variable gain amplifier VGA1 is connected to one end of the third capacitor C3, the other end of the third capacitor C3 is connected to one end of the third resistor R3 and the negative input end of the second variable gain amplifier VGA2 respectively, and the other end of the third resistor R3 is connected to the port NVB1; the negative output end of the first variable gain amplifier VGA1 is connected to one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is connected to one end of the fourth resistor R4 and the positive input end of the second variable gain amplifier VGA2 respectively, and the other end of the fourth resistor R4 is connected to the port NVB1.

[0031] The positive output end of the second variable gain amplifier VGA2 is connected with one end of the fifth capacitor C5, the other end of the fifth capacitor C5 is connected with one end of the fifth resistor R5 and the negative input end of the third variable gain amplifier VGA3 respectively, and the other end of the fifth resistor R5 is connected with the port NVB2; the negative output end of the second variable gain amplifier VGA2 is connected with one end of the sixth capacitor C6, the other end of the sixth capacitor C6 is connected with one end of the sixth resistor R6 and the positive input end of the third variable gain amplifier VGA3 respectively, and the other end of the sixth resistor R6 is connected with the port NVB2;

[0032] The positive output end of the third variable gain amplifier VGA3 is connected with one end of the seventh capacitor C7, the other end of the seventh capacitor C7 is connected with one end of the seventh resistor R7 and the negative input end of the fourth variable gain amplifier VGA4 respectively, and the other end of the seventh resistor R7 is connected with the port NVB3; the negative output end of the third variable gain amplifier VGA3 is connected with one end of the eighth capacitor C8, the other end of the eighth capacitor C8 is connected with one end of the eighth resistor R8 and the positive input end of the fourth variable gain amplifier VGA4 respectively, and the other end of the eighth resistor R8 is connected with the port NVB3;

[0033] The positive output end of the fourth variable gain amplifier VGA4 is connected with one end of the ninth capacitor C9, the other end of the ninth capacitor C9 is connected with one end of the ninth resistor R9 and the negative input end of the buffer amplifier group respectively, and the other end of the ninth resistor R9 is connected with the port NVB4; the negative output end of the fourth variable gain amplifier VGA4 is connected with one end of the tenth capacitor C10, the other end of the tenth capacitor C10 is connected with one end of the tenth resistor R10 and the negative input end of the buffer amplifier group respectively, and the other end of the tenth resistor R10 is connected with the port NVB4.

[0034] In an embodiment, the buffer amplifier group comprises a first buffer amplifier AMP1 and a second buffer amplifier AMP2; the positive input ends of the first buffer amplifier AMP1 and the second buffer amplifier AMP2 are connected with the connection point of the other end of the tenth capacitor C10 and one end of the tenth resistor R10, and the negative input ends of the first buffer amplifier AMP1 and the second buffer amplifier AMP2 are connected with the connection point of the other end of the ninth capacitor C9 and one end of the ninth resistor R9; the positive output end of the first buffer amplifier AMP1 is the positive signal output end VON of the AGC circuit, and the negative output end of the first buffer amplifier AMP1 is the negative signal output end VOP of the AGC circuit; the tail current source bias ends of the first buffer amplifier AMP1 and the second buffer amplifier AMP2 are commonly connected to the bias port VB3, the power supply ends of the first buffer amplifier AMP1 and the second buffer amplifier AMP2 are both connected to the power supply end VDD, and the grounding ends of the first buffer amplifier AMP1 and the second buffer amplifier AMP2 are both connected to the grounding end GND.

[0035] In an embodiment, the full-differential peak detection unit comprises a first NMOS transistor NM1, a second NMOS transistor NM2, a first diode D1, a second diode D2, an eleventh capacitor C11, and a first PMOS transistor PM1. The positive terminal of the first diode D1 is connected to the negative input terminal of the second buffer amplifier AMP2, and the positive terminal of the second diode D2 is connected to the positive input terminal of the second buffer amplifier AMP2. The negative terminals of the first diode D1 and the second diode D2 are commonly connected to a bias port NIB0. The source terminal of the first NMOS transistor NM1 is connected to the negative input terminal of the second buffer amplifier AMP2, and the source terminal of the second NMOS transistor NM2 is connected to the positive input terminal of the second buffer amplifier AMP2. The gate terminals of the first NMOS transistor NM1 and the second NMOS transistor NM2 are commonly connected to a bias port VB1. The drain terminal of the first NMOS transistor NM1, the drain terminal of the second NMOS transistor NM2, one terminal of the eleventh capacitor C11, and the drain terminal of the first PMOS transistor PM1 are commonly connected to the negative input terminal of the first comparator EA1. The other terminal of the eleventh capacitor C11 is connected to a ground terminal GND, the source terminal of the first PMOS transistor PM1 is connected to a power supply terminal VDD, and the tail current source bias terminal of the first comparator EA1 is connected to a bias port VB2.

[0036] In an embodiment, the gain control terminals of the first variable gain amplifier VGA1, the second variable gain amplifier VGA2, the third variable gain amplifier VGA3, and the fourth variable gain amplifier VGA4 are electrically connected to the output terminal of the first comparator EA1, so as to realize synchronous adjustment of the gains.

[0037] In an embodiment, the reference Figure 1 , Figure 2 , Figure 3The all-differential peak detection AGC circuit includes a first variable gain amplifier VGA1, a second variable gain amplifier VGA2, a third variable gain amplifier VGA3, a fourth variable gain amplifier VGA4, a first buffer amplifier AMP1, a second buffer amplifier AMP2, a first comparator EA1, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6, a seventh NMOS tube NM7, an eighth NMOS tube NM8, a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a first diode D1, and a second diode D2. The first variable gain amplifier VGA1, the second variable gain amplifier VGA2, the third variable gain amplifier VGA3, and the fourth variable gain amplifier VGA4 each have a positive input end, a negative input end, a positive output end, a negative output end, a gain control end, a power supply end, and a ground end. The first buffer amplifier AMP1 and the second buffer amplifier AMP2 each have a positive input end, a negative input end, a positive output end, a negative output end, a tail current source bias end, a power supply end, and a ground end. The first comparator EA1 has a positive input end, a negative input end, an output end, a tail current source bias end, a power supply end, and a ground end. The first NMOS tube NM1, the second NMOS tube NM2, and the first PMOS tube PM1 each have a source end, a drain end, and a gate end. The first diode D1 and the second diode D2 each have a positive end and a negative end. One end of the first capacitor C1 and one end of the second capacitor C2 are respectively a negative signal input end and a positive signal input end of the all-differential peak detection AGC circuit. The power supply end of the first variable gain amplifier VGA1, the power supply end of the second variable gain amplifier VGA2, the power supply end of the third variable gain amplifier VGA3, the power supply end of the fourth variable gain amplifier VGA4, the power supply end of the first buffer amplifier AMP1, the power supply end of the second buffer amplifier AMP2, the power supply end of the first comparator EA1, and the source end of the first PMOS tube PM1 are connected.and the connecting end of the first NMOS transistor NM1 and the connecting end of the second NMOS transistor NM2 are connected with the VB1 end of the full differential peak detection AGC circuit, the tail current source bias end of the first comparator EA1 is connected with the VB2 end of the full differential peak detection AGC circuit, the tail current source bias end of the first buffer amplifier AMP1 and the tail current source bias end of the second buffer amplifier AMP2 are connected with the VB3 end of the full differential peak detection AGC circuit, the negative end of the first diode D1 and the negative end of the second diode D2 are connected with the NIB0 end of the full differential peak detection AGC circuit, and the negative output end of the first buffer amplifier AMP1 and the positive output end of the first buffer amplifier AMP1 are connected with the positive signal output end and the negative signal output end of the full differential peak detection AGC circuit respectively.

[0038] The other end of the first capacitor C1, the other end of the first resistor R1 and the negative input end of the first variable gain amplifier VGA1 are connected, the other end of the second capacitor C2, the other end of the second resistor R2 and the positive input end of the first variable gain amplifier VGA1 are connected, the positive output end of the first variable gain amplifier VGA1 and one end of the third capacitor C3 are connected, the negative output end of the first variable gain amplifier VGA1 and one end of the fourth capacitor C4 are connected, the other end of the third capacitor C3, the other end of the third resistor R3 and the negative input end of the second variable gain amplifier VGA2 are connected, the other end of the fourth capacitor C4, the other end of the fourth resistor R4 and the positive input end of the second variable gain amplifier VGA2 are connected, the positive output end of the second variable gain amplifier VGA2 and one end of the fifth capacitor C5 are connected, the negative output end of the second variable gain amplifier VGA2 and one end of the sixth capacitor C6 are connected, the other end of the fifth capacitor C5, the other end of the fifth resistor R5 and the negative input end of the third variable gain amplifier VGA3 are connected, the other end of the sixth capacitor C6, the other end of the sixth resistor R6 and the positive input end of the third variable gain amplifier VGA3 are connected, the positive output end of the third variable gain amplifier VGA3 and one end of the seventh capacitor C7 are connected, the negative output end of the third variable gain amplifier VGA3 and one end of the eighth capacitor C8 are connected, the other end of the seventh capacitor C7, the other end of the seventh resistor R7 and the negative input end of the fourth variable gain amplifier VGA4 are connected, the other end of the eighth capacitor C8, the other end of the eighth resistor R8 and the positive input end of the fourth variable gain amplifier VGA4 are connected, the positive output end of the fourth variable gain amplifier VGA4 and one end of the ninth capacitor C9 are connected, the negative output end of the fourth variable gain amplifier VGA4 and one end of the tenth capacitor C10 are connected, the other end of the ninth capacitor C9, the other end of the ninth resistor R9, the negative input end of the first buffer amplifier AMP1 and the second buffer amplifier AMP2 are connected, the other end of the tenth capacitor C10, the other end of the tenth resistor R10, the positive input end of the first buffer amplifier AMP1 and the second buffer amplifier AMP2 are connected, the negative input end of the second buffer amplifier AMP2, the source end of the first NMOS tube NM1 and the positive end of the first diode D1 are connected, the positive input end of the second buffer amplifier AMP2, the source end of the second NMOS tube NM2 and the positive end of the second diode D2 are connected, the drain end of the first NMOS tube NM1, the drain end of the second NMOS tube NM2, the other end of the eleventh capacitor C11, the drain end of the first PMOS tube PM1 and the negative input end of the first comparator EA1 are connected,The output terminal of the first comparator EA1, the gain control terminal of the first variable gain amplifier VGA1, the gain control terminal of the second variable gain amplifier VGA2, the gain control terminal of the third variable gain amplifier VGA3, and the gain control terminal of the fourth variable gain amplifier VGA4 are connected.

[0039] like Figure 2 As shown, the first buffer amplifier AMP1 and the second buffer amplifier AMP2 include the third NMOS transistor NM3, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the second PMOS transistor PM2, the third PMOS transistor PM3, the eleventh resistor R11, and the twelfth resistor R12. The source terminal of the fifth NMOS transistor NM5 is the ground terminal of the first buffer amplifier AMP1 and the second buffer amplifier AMP2, and the gate terminal of the fifth NMOS transistor NM5 is the tail current source bias terminal of the first buffer amplifier AMP1 and the second buffer amplifier AMP2. The gate terminal of the third NMOS transistor NM3 is the negative input terminal of the first buffer amplifier AMP1 and the second buffer amplifier AMP2, and the gate terminal of the fourth NMOS transistor NM4 is the positive input terminal of the first buffer amplifier AMP1 and the second buffer amplifier AMP2. The source terminal of the third NMOS transistor NM3, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the second PMOS transistor PM2, the third PMOS transistor PM3, the eleventh resistor R11, and the twelfth resistor R12. The source terminal of MOSFET NM4 is connected to the drain terminal of the fifth NMOS transistor NM5. The source terminal of the second PMOS transistor PM2 is connected to the source terminal of the third PMOS transistor PM3, and their connection terminals are the VDD terminals of the first buffer amplifier AMP1 and the second buffer amplifier AMP2. The gate terminal of the second PMOS transistor PM2 is connected to one end of the eleventh resistor R11. The gate terminal of the third PMOS transistor PM3 is connected to one end of the twelfth resistor R12. The drain terminal of the second PMOS transistor PM2, the other end of the eleventh resistor R11, and the drain terminal of the third NMOS transistor NM3 are connected, and their connection terminals are the positive output terminals of the first buffer amplifier AMP1 and the second buffer amplifier AMP2. The drain terminal of the third PMOS transistor PM3, the other end of the twelfth resistor R12, and the drain terminal of the fourth NMOS transistor NM4 are connected, and their connection terminals are the negative output terminals of the first buffer amplifier AMP1 and the second buffer amplifier AMP2.

[0040] like Figure 3As shown, the first comparator EA1 includes the sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15, the sixteenth resistor R16, the seventeenth resistor R17 and the eighteenth resistor R18, the source of the eighth NMOS transistor NM8 is the ground terminal of the first comparator EA1, the gate of the eighth NMOS transistor NM8 is the tail current source bias terminal of the first comparator EA1, one end of the seventeenth resistor R17 and one end of the eighteenth resistor R18 are connected, and the connection end is the power supply terminal of the first comparator EA1, the gate of the sixth NMOS transistor NM6 is the negative input terminal of the first comparator EA1, the gate of the seventh NMOS transistor NM7 is the positive input terminal of the first comparator EA1, the drain of the sixth NMOS transistor NM6 and one end of the fifteenth resistor R15 are connected, the drain of the seventh NMOS transistor NM7 and one end of the sixteenth resistor R16 are connected, the other end of the fifteenth resistor R15 and the other end of the seventeenth resistor R17 are connected, and the connection end is the positive output terminal of the first comparator EA1, the other end of the sixteenth resistor R16 and the other end of the eighteenth resistor R18 are connected, and the connection end is the negative output terminal of the first comparator EA1, the source of the sixth NMOS transistor NM6 and one end of the thirteenth resistor R13 are connected, the source of the seventh NMOS transistor NM7 and one end of the fourteenth resistor R14 are connected, the other end of the thirteenth resistor R13, the other end of the fourteenth resistor R14 and the drain of the eighth NMOS transistor NM8 are connected.

[0041] The principle of the full differential peak detection AGC circuit is as follows: when the signal is poured from the VGA, the initial potential of the peak detection output is VDD, the VGA gain is maximum, the VGA amplifies the input signal to , the peak detection circuit detects a large amplitude signal, the peak detection output starts to discharge the capacitor, and finally stabilizes at a certain value, at this time, the gain of the VGA is also adjusted to a smaller level, and the whole loop enters the attenuation state, after a period of stabilization, the output amplitude is stabilized at a certain value; no matter whether the input signal amplitude increases or decreases, the loop will pass through the above process to stabilize the overall output amplitude of the AGC at a certain value.

[0042] On the feedback path, the second buffer amplifier AMP2 extracts the positive and negative two-way signals from the VGA output, and outputs the negative and positive two-way signals through amplification; the output signal is rectified through the first diode D1 and the second diode D2, and the peak of the positive half cycle is cut off; in the negative output signal negative half cycle, the first NMOS tube NM1 discharges the eleventh capacitor C11, and the potential of the first end of the eleventh capacitor C11 begins to drop; in the full differential peak detection circuit, since the positive and negative signals are 180 degrees apart, when the negative output signal enters the positive half cycle, the positive output signal just enters the negative half cycle, and the second NMOS tube NM2 discharges the eleventh capacitor C11, and the potential of the first end of the eleventh capacitor C11 continues to drop; when the positive output signal enters the positive half cycle, the negative output signal will continue to discharge the eleventh capacitor C11 until the potential of the first end of the eleventh capacitor C11 drops to zero, and the potential of the first end of the eleventh capacitor C11 stops dropping.

[0043] The application has the advantages that the full differential peak detection circuit has strong anti-interference ability, greatly improves the reliability, precision and speed of the circuit, and the full differential peak detection circuit composed of the second buffer amplifier AMP2, the first diode D1, the second diode D2, the first NMOS tube NM1, the second NMOS tube NM2 and the eleventh capacitor C11 is more continuous during capacitor discharge, improves the adjustment speed and precision of the overall loop; the differential structure has good anti-interference ability, and even if one signal is missing, the function can be realized, which improves the reliability of the overall loop.

[0044] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the foregoing embodiments of the present application have been described in detail, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A fully differential peak detect AGC circuit, characterized by, The all-differential peak detection AGC circuit comprises a multi-stage variable gain amplifier, a buffer amplifier group, a first comparator EA1, an all-differential peak detection unit and an external port; the external port comprises a power supply end VDD, a ground end GND, a negative signal input end INN, a positive signal input end INP, a positive signal output end VON, a negative signal output end VOP, a plurality of bias ports and a reference voltage end VREF; The negative signal input end INN and the positive signal input end INP are electrically connected to the input end of the multi-stage variable gain amplifier through a resistance-capacitance network. The output end of the multi-stage variable gain amplifier is electrically connected to the input end of the buffer amplifier group through a resistance-capacitance network, and the amplified signal is transmitted to the buffer amplifier group. The buffer amplifier group has two outputs, one of which is the positive signal output end VON and the negative signal output end VOP of the all-differential peak detection AGC circuit, and the other of which is electrically connected to the input end of the all-differential peak detection unit to provide a signal for peak detection. The output end of the all-differential peak detection unit is electrically connected to the negative input end of the first comparator EA1, the positive input end of the first comparator EA1 is electrically connected to the reference voltage end VREF, and the output end of the first comparator EA1 is electrically connected to each gain control end of the multi-stage variable gain amplifier, forming a negative feedback control loop. The bias ports are used for electrically connecting the bias ends of the multi-stage variable gain amplifier, the buffer amplifier group, the all-differential peak detection unit and the first comparator EA1, and are used for providing working bias. The power supply end VDD of the AGC circuit is electrically connected to the power supply ends of the multi-stage variable gain amplifier, the buffer amplifier group, the first comparator EA1 and the all-differential peak detection unit, and the ground end GND of the AGC circuit is electrically connected to the ground ends of the power supply ends of the multi-stage variable gain amplifier, the buffer amplifier group, the first comparator EA1 and the all-differential peak detection unit. The buffer amplifier group comprises a second buffer amplifier AMP2. The all-differential peak detection unit comprises a first NMOS tube NM1, a second NMOS tube NM2, a first diode D1, a second diode D2, an eleventh capacitor C11 and a first PMOS tube PM1. The positive end of the first diode D1 is connected to the negative output end of the second buffer amplifier AMP2, the positive end of the second diode D2 is connected to the positive output end of the second buffer amplifier AMP2, and the negative ends of the first diode D1 and the second diode D2 are commonly connected to the bias port NIB0. The source end of the first NMOS tube NM1 is connected to the negative output end of the second buffer amplifier AMP2, the source end of the second NMOS tube NM2 is connected to the positive output end of the second buffer amplifier AMP2, and the gate ends of the first NMOS tube NM1 and the second NMOS tube NM2 are commonly connected to the bias port VB1. The drain end of the first NMOS tube NM1, the drain end of the second NMOS tube NM2, one end of the eleventh capacitor C11 and the drain end of the first PMOS tube PM1 are commonly connected to the negative input end of the first comparator EA1. The other end of the eleventh capacitor C11 is connected to the ground end GND, the source end of the first PMOS transistor PM1 is connected to the power supply end VDD, and the tail current source bias end of the first comparator EA1 is connected to the bias port VB2.

2. The fully differential peak detect AGC circuit of claim 1, wherein, The multi-stage variable gain amplifier comprises a first variable gain amplifier VGA1, a second variable gain amplifier VGA2, a third variable gain amplifier VGA3 and a fourth variable gain amplifier VGA4 connected in cascade; and the resistance-capacitance network comprises a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a tenth resistor R10. The negative signal input end INN is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is connected to one end of the first resistor R1 and the negative input end of the first variable gain amplifier VGA1, and the other end of the first resistor R1 is connected to the port NVB0; the positive signal input end INP is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is connected to one end of the second resistor R2 and the positive input end of the first variable gain amplifier VGA1, and the other end of the second resistor R2 is connected to the port NVB0. The positive output end of the first variable gain amplifier VGA1 is connected to one end of the third capacitor C3, the other end of the third capacitor C3 is connected to one end of the third resistor R3 and the negative input end of the second variable gain amplifier VGA2, and the other end of the third resistor R3 is connected to the port NVB1; the negative output end of the first variable gain amplifier VGA1 is connected to one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is connected to one end of the fourth resistor R4 and the positive input end of the second variable gain amplifier VGA2, and the other end of the fourth resistor R4 is connected to the port NVB1. The positive output end of the second variable gain amplifier VGA2 is connected to one end of the fifth capacitor C5, the other end of the fifth capacitor C5 is connected to one end of the fifth resistor R5 and the negative input end of the third variable gain amplifier VGA3, and the other end of the fifth resistor R5 is connected to the port NVB2. The negative output end of the second variable gain amplifier VGA2 is connected to one end of the sixth capacitor C6, the other end of the sixth capacitor C6 is connected to one end of the sixth resistor R6 and the positive input end of the third variable gain amplifier VGA3, and the other end of the sixth resistor R6 is connected to the port NVB2. The positive output end of the third variable gain amplifier VGA3 is connected to one end of the seventh capacitor C7, the other end of the seventh capacitor C7 is connected to one end of the seventh resistor R7 and the negative input end of the fourth variable gain amplifier VGA4, and the other end of the seventh resistor R7 is connected to the port NVB3. The negative output end of the third variable gain amplifier VGA3 is connected with one end of the eighth capacitor C8, the other end of the eighth capacitor C8 is connected with one end of the eighth resistor R8 and the positive input end of the fourth variable gain amplifier VGA4 respectively, and the other end of the eighth resistor R8 is connected with the port NVB3; The positive output end of the fourth variable gain amplifier VGA4 is connected with one end of the ninth capacitor C9, the other end of the ninth capacitor C9 is connected with one end of the ninth resistor R9 and the negative input end of the buffer amplifier group respectively, and the other end of the ninth resistor R9 is connected with the port NVB4; The negative output end of the fourth variable gain amplifier VGA4 is connected with one end of the tenth capacitor C10, the other end of the tenth capacitor C10 is connected with one end of the tenth resistor R10 and the negative input end of the buffer amplifier group respectively, and the other end of the tenth resistor R10 is connected with the port NVB4.

3. The fully differential peak detect AGC circuit of claim 2, wherein, The buffer amplifier group comprises a first buffer amplifier AMP1 and a second buffer amplifier AMP2; The positive input ends of the first buffer amplifier AMP1 and the second buffer amplifier AMP2 are commonly connected with the connection point of the other end of the tenth capacitor C10 and one end of the tenth resistor R10, and the negative input ends of the first buffer amplifier AMP1 and the second buffer amplifier AMP2 are commonly connected with the connection point of the other end of the ninth capacitor C9 and one end of the ninth resistor R9; The positive output end of the first buffer amplifier AMP1 is the positive signal output end VON of the AGC circuit, and the negative output end of the first buffer amplifier AMP1 is the negative signal output end VOP of the AGC circuit. The tail current source bias ends of the first buffer amplifier AMP1 and the second buffer amplifier AMP2 are commonly connected with the bias port VB3, the power supply ends of the first buffer amplifier AMP1 and the second buffer amplifier AMP2 are both connected with the power supply end VDD, and the grounding ends of the first buffer amplifier AMP1 and the second buffer amplifier AMP2 are both connected with the grounding end GND.

4. The fully differential peak detect AGC circuit of claim 2, wherein, The gain control ends of the first variable gain amplifier VGA1, the second variable gain amplifier VGA2, the third variable gain amplifier VGA3 and the fourth variable gain amplifier VGA4 are electrically connected with the output end of the first comparator EA1, so as to realize synchronous regulation of the gain.

Images