High-frequency narrow pulse sampling hold circuit

Abstract

The invention relates to the technical field of signal processing circuits, in particular to a high-frequency narrow pulse sampling hold circuit. The circuit is characterized in that the circuit comprises a peak detection unit and a control unit U1, the input end VIN of the peak detection unit is used for receiving an input signal to be detected, the output end OUT of the peak detection unit is connected with the in-phase input end of a comparator U2, and the inverted input end of the comparator U2 is used for receiving a reference signal V1; the level of the reference signal V1 is lower than that of noise in the input signal; the output end of the comparator U2 is connected with the control unit U1, and the comparator U2 is used for outputting a sampling signal V2 to the control unit U1; the peak detection unit is grounded through the switch unit, and the control unit U1 is adaptively connected with the switch unit and used for controlling the switch unit to be switched on or switched off. The circuit structure is low in cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal processing circuit, in particular to a high-frequency narrow pulse sampling and holding circuit. BACKGROUND

[0002] In the signal processing circuit, in order to sample narrow pulse, the prior art uses a high sampling rate ADC circuit, the higher the sampling rate, the larger the data quantity, the stronger the system data processing capacity, however, such system needs larger memory, faster CPU, and higher cost. SUMMARY

[0003] The technical problem to be solved by the present application is to provide a high-frequency narrow pulse sampling and holding circuit, which has low cost.

[0004] To solve the above problems, the following technical solutions are provided:

[0005] The high-frequency narrow pulse sampling and holding circuit has the characteristics that it comprises a peak detection unit and a control unit U1, the input end VIN of the peak detection unit is used for receiving an input signal to be detected, the output end OUT of the peak detection unit is connected with the non-inverting input end of a comparator U2, the inverting input end of the comparator U2 is used for receiving a reference signal V1, the level of the reference signal V1 is lower than the level of noise in the input signal; the output end of the comparator U2 is connected with the control unit U1, and is used for outputting a sampling signal V2 to the control unit U1; the peak detection unit is connected with the ground through a switching unit, and the control unit U1 is adaptively connected with the switching unit, and is used for controlling the switching unit to be turned on or turned off.

[0006] The peak detection unit comprises a diode D1 and a capacitor C1, the anode end of the diode D1 is the input end VIN of the peak detection unit, and the cathode end of the diode D1 is the output end OUT of the peak detection unit; the cathode end of the diode D1 is connected with one end of the capacitor C1, and the other end of the capacitor C1 is connected with the ground.

[0007] The switching unit comprises an NMOS tube Q1, the drain of the NMOS tube Q1 is connected with the input end VIN of the peak detection unit, the gate of the NMOS tube Q1 is connected with one end of a resistor R1 and one end of a resistor R2 respectively, the other end of the resistor R1 is connected with the control unit U1, the control unit U1 sends a control signal to the NMOS tube Q1 through the resistor R1, so as to control the NMOS tube Q1 to be turned on or turned off; the other end of the resistor R2 and the source of the NMOS tube Q1 are connected with the ground.

[0008] The power supply VCC is connected to one fixed terminal of the potentiometer W1, the other fixed terminal of the potentiometer W1 is grounded, the movable terminal of the potentiometer W1 is connected to the non-inverting input terminal of the comparator U2, and the power supply VCC forms the reference signal V1 through the potentiometer W1.

[0009] The output terminal of the comparator U2 is connected to one terminal of the resistor R3, and the other terminal of the resistor R3 is connected to the power supply VCC.

[0010] The above scheme has the following advantages:

[0011] The high-frequency narrow pulse sampling and holding circuit of the present application comprises a peak detection unit and a control unit U1, the output terminal of the peak detection unit is connected to the non-inverting input terminal of the comparator U2, the inverting input terminal of the comparator U2 is used to receive the reference signal V1, the level of the reference signal V1 is lower than that of the noise in the input signal, the output terminal of the comparator U2 is connected to the control unit U1, the peak detection unit is grounded through a switch unit, and the control unit U1 is connected to the switch unit. In use, the input terminal VIN of the peak detection unit inputs an input signal containing noise and unipolar pulse, only the input signal greater than the peak voltage of the peak detection unit can reach the output terminal OUT of the peak detection unit under the action of the peak detection unit. Since the level of the reference signal V1 is lower than that of the noise in the input signal, the non-inverting input terminal of the comparator U2 has no voltage, i.e. the voltage of the non-inverting input terminal of the comparator U2 is lower than the reference signal V1 of the inverting input terminal, and the output terminal of the comparator U2 is at low level. When the VIN has a pulse signal, the voltage of the non-inverting input terminal of the comparator U2 is higher than the reference signal V1 of the inverting input terminal, the output terminal of the comparator U2 is at high level, the control unit U1 controls the switch unit to be turned on, so that the energy of the peak detection unit is released, and the next sampling is waited. The sampling and holding circuit does not need to set a large memory, and the control unit U1 with high sampling rate is also not needed, thereby greatly saving the cost of the whole circuit. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 Fig. 1 is a circuit structure diagram of the high-frequency narrow pulse sampling and holding circuit of the present application;

[0013] Figure 2 Fig. 2 is a working waveform diagram of the high-frequency narrow pulse sampling and holding circuit of the present application. DETAILED DESCRIPTION

[0014] The present application will be further described in detail below in combination with the drawings and examples.

[0015] As Figure 1As shown in the figure, the high-frequency narrow pulse sampling and holding circuit of the present application comprises a peak detection unit 101 and a control unit U1. The input end VIN of the peak detection unit 101 is used to receive an input signal to be detected. The output end OUT of the peak detection unit 101 is connected to the non-inverting input end of a comparator U2. The inverting input end of the comparator U2 is used to receive a reference signal V1, the level of which is lower than the level of the noise in the input signal. The output end of the comparator U2 is connected to the control unit U1, which is used to output a sampling signal V2 to the control unit U1. The peak detection unit 101 is connected to the ground through a switch unit 102. The control unit U1 is connected to the switch unit 102 in a matching manner, which is used to control the switch unit 102 to be turned on or turned off. Specifically, the input end VIN of the peak detection unit 101 inputs an input signal containing noise and unipolar pulses. Under the action of the peak detection unit 101, only the input signal greater than the peak voltage of the peak detection unit 101 can reach the output end OUT of the peak detection unit 101. Since the level of the reference signal V1 is lower than the level of the noise in the input signal, when there is no unipolar pulse, the non-inverting input end of the comparator U2 has no voltage, i.e., the voltage of the non-inverting input end of the comparator U2 is lower than the reference signal V1 of the inverting input end. The output end of the comparator U2 is at a low level. When there is a pulse signal at the VIN, the voltage of the non-inverting input end of the comparator U2 is higher than the reference signal V1 of the inverting input end. The output end of the comparator U2 is at a high level, and the control unit U1 completes sampling. The control unit U1 controls the switch unit 102 to be turned on, so that the peak detection unit 101 releases energy, and waits for the next sampling. In the embodiment, the control unit U1 adopts a general ADC chip, and the specific model can be selected by the demand of the person skilled in the art. It belongs to the prior art, and will not be described here.

[0016] As shown in the figure, Figure 1 In the embodiment, the peak detection unit 101 comprises a diode D1 and a capacitor C1. The anode end of the diode D1 is the input end VIN of the peak detection unit 101, and the cathode end of the diode D1 is the output end OUT of the peak detection unit 101. The cathode end of the diode D1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the ground.

[0017] As shown in the figure, Figure 1 In the embodiment, the switch unit 102 comprises an NMOS tube Q1. The drain of the NMOS tube Q1 is connected to the input end VIN of the peak detection unit 101. The gate of the NMOS tube Q1 is connected to one end of a resistor R1 and one end of a resistor R2, respectively. The other end of the resistor R1 is connected to the control unit U1. The control unit U1 sends a control signal PP to the NMOS tube Q1 through the resistor R1, which controls the NMOS tube Q1 to be turned on or turned off. The other end of the resistor R2 and the source of the NMOS tube Q1 are connected to the ground.

[0018] As shown in the figure, Figure 1As shown, in this embodiment, the power supply VCC is connected to a fixed end of the potentiometer W1, the other fixed end of the potentiometer W1 is grounded, the active end of the potentiometer W1 is connected to the inverting input end of the comparator U2, and the power supply VCC forms a reference signal V1 through the potentiometer W1.

[0019] like Figure 1 As shown, in this embodiment, the output end of the comparator U2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the power supply VCC.

[0020] like Figure 1 As shown, during operation, the input signal contains noise and unipolar pulses. After passing through the detection diode D1, the maximum amplitude voltage of the signal is maintained on the holding capacitor C1. The diode D1 and capacitor C1 form a peak detection circuit. Only the input signal that is higher than the voltage of capacitor C1 plus the forward voltage of diode D1 can pass through diode D1 and be superimposed on capacitor C1. Adjust the potentiometer W1 so that the reference signal V1 is slightly lower than the input signal noise level. The noise just cannot cross diode D1 and be injected into capacitor C1. That is, when there is no valid pulse signal, D1 is cut off and the voltage on C1 is equal to 0V. At this time, the voltage at the positive input terminal of comparator U2 is lower than the voltage at the negative input terminal V1, and the output V2 is a low level of 0V.

[0021] When VIN has a pulse signal, D1 is turned on. Since the forward resistance of D1 is very small, C1 charges quickly to reach the pulse peak, that is, the rising slope of the C1 pulse front and the VIN pulse front is almost the same. When the amplitude exceeds V1, V2 outputs a high level. V2 is the input end of the microcontroller U1 and is set to trigger the interrupt on the rising edge of the pulse. The output end PP of the microcontroller is used to drive the NMOS tube Q1. Normally, PP is low and Q1 is in the cut-off state. The peak detection circuit is equivalent to D1 and C1. When the rising edge of V2 triggers the U1 interrupt, U1 delays appropriately according to the ADC sampling cycle to ensure that the ADC can sample the VIN pulse peak at least once, and then drives PP high to turn on Q1, quickly releasing the peak voltage of C1, and immediately pulling down PP to cut off Q1, restoring the normal peak detection circuit of D1 and C1, waiting for the next pulse. The working waveform is as follows Figure 2 shown.

Claims

1. A high frequency narrow pulse sample-and-hold circuit, characterized by, The peak detection unit and the control unit U1, the input terminal VIN of the peak detection unit is used for receiving the input signal to be detected, the output terminal OUT of the peak detection unit is connected with the non-inverting input terminal of the comparator U2, the inverting input terminal of the comparator U2 is used for receiving the reference signal V1, the level of the reference signal V1 is lower than the level of the noise in the input signal; the output terminal of the comparator U2 is connected with the control unit U1, and is used for outputting the sampling signal V2 to the control unit U1; the peak detection unit is connected with the ground through the switch unit, and the control unit U1 is adaptively connected with the switch unit, and is used for controlling the switch unit to be turned on or turned off.

2. The high frequency narrow pulse sample-and-hold circuit of claim 1, wherein, The peak detection unit comprises a diode D1 and a capacitor C1, the anode of the diode D1 is the input terminal VIN of the peak detection unit, and the cathode of the diode D1 is the output terminal OUT of the peak detection unit; the cathode of the diode D1 is connected with one end of the capacitor C1, and the other end of the capacitor C1 is grounded.

3. The high frequency narrow pulse sample-and-hold circuit of claim 2, wherein, The switch unit comprises an NMOS tube Q1, the drain of the NMOS tube Q1 is connected with the input terminal VIN of the peak detection unit, the gate of the NMOS tube Q1 is connected with one end of a resistor R1 and one end of a resistor R2 respectively, the other end of the resistor R1 is connected with the control unit U1, and the control unit U1 sends a control signal to the NMOS tube Q1 through the resistor R1, so as to control the NMOS tube Q1 to be turned on or turned off; the other end of the resistor R2 and the source of the NMOS tube Q1 are grounded.

4. The high frequency narrow pulse sample-and-hold circuit of claim 1, wherein, The power supply VCC is connected with one fixed end of a potentiometer W1, the other fixed end of the potentiometer W1 is grounded, the movable end of the potentiometer W1 is connected with the inverting input terminal of the comparator U2, and the power supply VCC forms the reference signal V1 through the potentiometer W1.

5. The high frequency narrow pulse sample-and-hold circuit of claim 1, wherein, The output terminal of the comparator U2 is connected with one end of a resistor R3, and the other end of the resistor R3 is connected with the power supply VCC.

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