Semiconductor memory device

Abstract

A semiconductor memory device includes: a substrate; a plurality of lower electrodes on the substrate; and a support connecting the plurality of lower electrodes to each other, in which the support includes a plurality of support holes adjacent to some of the plurality of lower electrodes, the plurality of lower electrodes including a plurality of first lower electrodes adjacent to the plurality of support holes and a plurality of second lower electrodes spaced apart from the plurality of support holes, four adjacent first lower electrodes of the plurality of first lower electrodes are adjacent to one of the plurality of support holes, and the plurality of support holes are equally spaced in a first direction and a second direction intersecting the first direction.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a semiconductor memory device. BACKGROUND

[0002] Semiconductor devices are core components of electronic devices for controlling or amplifying electrical signals, and various types of semiconductor devices can be manufactured. For example, memory devices can be mainly used to store and retrieve data, and non-memory devices can be used to control or amplify electrical signals. Semiconductor devices are core components of electronic devices and play an important role in various fields including computers, communication devices, consumer electronics, etc.

[0003] As the electronic industry develops, the performance and functional requirements of electronic devices are also increasingly high. Accordingly, semiconductor devices can be required to have high performance characteristics, and the integration of semiconductor devices is continuously increasing to meet these requirements. For example, a technology capable of increasing the integration of dynamic random access memory (DRAM) devices and forming a capacitor having excellent electrical characteristics can be required. SUMMARY

[0004] To solve one or more problems (for example, the problems described above and / or other problems not explicitly described herein), the disclosure provides a semiconductor memory device having improved electrical characteristics and reliability.

[0005] According to some embodiments of the disclosure, a semiconductor memory device includes a substrate, a plurality of lower electrodes on the substrate, and a support connecting the plurality of lower electrodes to each other, wherein the support includes a plurality of support holes adjacent to some of the plurality of lower electrodes, the plurality of lower electrodes includes a plurality of first lower electrodes adjacent to the plurality of support holes and a plurality of second lower electrodes spaced apart from the plurality of support holes, four adjacent first lower electrodes of the plurality of first lower electrodes are adjacent to one support hole of the plurality of support holes, and the plurality of support holes are equally spaced apart in a first direction and a second direction intersecting the first direction.

[0006] According to some embodiments of the present disclosure, a semiconductor memory device includes a substrate, a plurality of lower electrodes on the substrate, and a support connecting the plurality of lower electrodes to each other, wherein the support includes a plurality of support holes adjacent to some of the plurality of lower electrodes, the plurality of lower electrodes include a plurality of first lower electrodes adjacent to the plurality of support holes and a plurality of second lower electrodes spaced apart from the plurality of support holes, the plurality of support holes are aligned in a first direction and spaced apart from each other by a first distance, the plurality of support holes are aligned in a second direction perpendicular to the first direction and spaced apart from each other by a second distance different from the first distance, and a number of the second lower electrodes between a first pair of adjacent support holes among the plurality of support holes in the first direction is greater than a number of the second lower electrodes between a second pair of adjacent support holes among the plurality of support holes in the second direction.

[0007] According to some embodiments of the present disclosure, a semiconductor memory device includes a substrate including a transistor, a capacitor structure on the substrate and electrically connected to the transistor, the capacitor structure including a plurality of lower electrodes electrically connected to the transistor, an upper electrode on the plurality of lower electrodes, and a dielectric film between the plurality of lower electrodes and the upper electrode, and a support connecting the plurality of lower electrodes to each other, wherein the support includes a plurality of support holes adjacent to some of the plurality of lower electrodes, the plurality of lower electrodes include a plurality of first lower electrodes adjacent to the plurality of support holes and a plurality of second lower electrodes spaced apart from the plurality of support holes, four adjacent first lower electrodes among the plurality of first lower electrodes are adjacent to one support hole among the plurality of support holes, and a ratio of a number of the first lower electrodes to a number of the second lower electrodes is 1:1.

[0008] According to some embodiments of the present disclosure, the first lower electrodes adjacent to the support holes and the second lower electrodes spaced apart from the support holes are symmetrically arranged, so that the reliability of the semiconductor memory device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become clearer from the following detailed description of example embodiments thereof, taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a plan view for explaining a semiconductor memory device according to some embodiments of the present disclosure;

[0011] Figure 2 is a cross-sectional view taken along line A-A of Figure 1 ;

[0012] Figure 3 is a plan view for explaining a semiconductor memory device according to some embodiments of the present disclosure;

[0013] Figures 4 to 7is a diagram for illustrating a semiconductor storage device according to some embodiments of the present disclosure;

[0014] Figure 8 is a plan view for illustrating a semiconductor storage device according to some embodiments of the present disclosure;

[0015] Figure 9 is a plan view for illustrating a semiconductor storage device according to some embodiments of the present disclosure;

[0016] Figure 10 is a diagram for illustrating a semiconductor storage device according to some embodiments of the present disclosure;

[0017] Figure 11 is a diagram for illustrating a semiconductor storage device according to some embodiments of the present disclosure;

[0018] Figure 12 is a diagram for illustrating a semiconductor storage device according to some embodiments of the present disclosure;

[0019] Figure 13 and Figure 14 is a diagram for illustrating a semiconductor storage device according to some embodiments of the present disclosure;

[0020] Figure 15 and Figure 16 is a diagram for illustrating a semiconductor storage device according to some embodiments of the present disclosure;

[0021] Figures 17 to 25 is a diagram showing an intermediate stage for illustrating a method of manufacturing a semiconductor storage device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0022] A semiconductor storage device according to some embodiments of the present disclosure will be described with reference to Figures 1 to 2

[0023] Figure 1 is a plan view for illustrating a semiconductor storage device according to some embodiments of the present disclosure. Figure 2 is a cross-sectional view taken along the line A-A of Figure 1 For ease of description, Figure 1 in the middle is omitted except for the first support 150 and the lower electrode 130.

[0024] With reference to Figure 1 and Figure 2 , a semiconductor storage device according to some embodiments of the present disclosure can include a substrate 100, an interlayer insulating film 105, a contact plug 110, a landing pad 120, a first support 150, a second support 152, and a capacitor structure C_ST.

[0025] ​The substrate 100 can be, for example, a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In other examples, the substrate 100 can include silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimony, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimony, but is not limited thereto.

[0026] A semiconductor memory device according to some embodiments can include a transistor in the substrate 100. The semiconductor memory device can be an assembly of a memory device including at least one transistor and at least one data storage structure. The semiconductor memory device can be a DRAM or a ferroelectric memory (FeRAM).

[0027] An interlayer insulating film 105 can be disposed on the substrate 100. A landing pad 120 can be disposed on top of the interlayer insulating film 105. A contact plug 110 can be disposed in the interlayer insulating film 105. The contact plug 110 can be connected to the landing pad 120. For example, the contact plug 110 can electrically connect a transistor disposed in the substrate 100 to the landing pad 120.

[0028] For example, the interlayer insulating film 105 can include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon oxynitride (SiOCN), and combinations thereof. For example, the contact plug 110 can include at least one of a doped impurity semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal. For example, the landing pad 120 can include at least one of a doped impurity semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal. In some examples, the landing pad 120 can include tungsten (W).

[0029] An etch stop film 125 can be disposed on the interlayer insulating film 105. The etch stop film 125 can be disposed on the landing pad 120. The etch stop film 125 can be absent from at least a portion of the landing pad 120 (e.g., can be exposed). For example, the etch stop film 125 can include an opening that exposes at least a portion of the landing pad 120.

[0030] For example, the etch stop film 125 can include at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon boron nitride (SiBN), silicon carbon oxide (SiCO), silicon oxynitride (SiON), silicon oxide (SiO), and silicon carbon oxynitride (SiOCN). In the present disclosure, a compound such as silicon carbon oxide (SiCO) includes silicon (Si), carbon (C), and oxygen (O), but does not imply a ratio between silicon (Si), carbon (C), and oxygen (O).

[0031] A capacitor structure C_ST can be provided on the substrate 100. The capacitor structure C_ST can store a signal received from a transistor in the substrate 100. The capacitor structure C_ST can function as a data storage element electrically connected to the transistor. For example, the capacitor structure C_ST can store an electric charge under the control of the transistor.

[0032] The capacitor structure C_ST can include a lower electrode 130, a dielectric film 160, a conductive film 170, and an upper electrode 180.

[0033] A plurality of lower electrodes 130 can be provided on the substrate 100. Each lower electrode 130 can be provided on a landing pad 120. The landing pad 120 can be provided between the substrate 100 and the lower electrode 130. The lower electrode 130 can be electrically connected to the landing pad 120. A portion of the lower electrode 130 can be provided in the etching stop film 125. For example, the lower electrode 130 can extend through the etching stop film 125 and be connected to the landing pad 120.

[0034] The lower electrodes 130 can be arranged in an array, such as a hexagonal honeycomb structure. For example, the lower electrodes 130 can be provided at each vertex of a hexagon and at the center, and the hexagonal structure in which the lower electrodes are arranged can be repeated. Specifically, the lower electrodes 130 can be aligned at a distance from each other in a first direction D1 and a second direction D2. The lower electrodes 130 can be arranged at equal intervals in the first direction D1. The lower electrodes 130 can be arranged in a staggered manner in the second direction D2. The lower electrodes 130 can be linearly arranged along a third direction D3 and a fourth direction D4.

[0035] The first direction D1 and the second direction D2 can be perpendicular to each other. The third direction D3 can intersect the first direction D1 and the second direction D2. The fourth direction D4 can intersect the first direction D1 and the second direction D2. Each of the first direction, the second direction, the third direction, and the fourth direction D1, D2, D3, and D4 can intersect each other. In some examples, the angle formed by the third direction D3 and the fourth direction D4 and the angle formed by the first direction D1 and the third direction D3 can be 60 degrees, respectively. However, the present disclosure is not limited thereto.

[0036] In some examples, the lower electrode 130 can have a vertical rectangular (e.g., columnar) shape. The lower electrode 130 can extend in a fifth direction D5. The fifth direction D5 can be a thickness direction of the substrate 100. In other words, the fifth direction D5 can be a direction perpendicular to an upper surface of the landing pad 120. The fifth direction D5 can be perpendicular to each of the first direction, the second direction, the third direction, and the fourth direction D1, D2, D3, and D4.

[0037] For example, the lower electrode 130 can include at least one of an electrically conductive metal material (cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), etc.), a metal nitride (titanium nitride (TiN), silicon titanium nitride (TiSiN), aluminum titanium nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), etc.), a noble metal material (platinum (Pt), ruthenium (Ru), iridium (Ir), etc.), an electrically conductive oxide film (PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba, Sr) RuO3), CRO (CaRuO3), LSCo, etc.), and a metal silicide film. However, the present disclosure is not limited thereto.

[0038] The first support 150 and the second support 152 can be disposed in the capacitor structure C_ST. However, it should be understood that this is merely an example. In some examples, only one of the first support 150 and the second support 152 can be disposed in the capacitor structure C_ST, or one or more additional supports can be disposed in addition to the first support 150 and the second support 152.

[0039] The first support 150 and the second support 152 can be disposed between the plurality of lower electrodes 130. The first support 150 and the second support 152 can be disposed between adjacent lower electrodes 130. The first support 150 and the second support 152 can be in contact with the lower electrodes 130. The first support 150 and the second support 152 can connect and support the adjacent lower electrodes 130.

[0040] The first support 150 and the second support 152 can be spaced apart from each other in the fifth direction D5. The first support 150 can be disposed on the second support 152. For example, the first support 150 can be disposed to be spaced farther apart from the substrate 100 than the second support 152 in the fifth direction D5. The dielectric film 160, the conductive film 170, and the upper electrode 180 can be disposed between the first support 150 and the second support 152. The first support 150 and the second support 152 can overlap each other in the fifth direction D5.

[0041] An upper surface of the first support 150 can be coplanar with an upper surface of the lower electrode 130. However, it should be understood that this is merely an example. In some examples, the upper surface of the lower electrode 130 can be lower or higher than the upper surface of the first support 150.

[0042] The second support 152 can be disposed on the etching stop film 125. The second support 152 can be spaced apart from the etching stop film 125 in the fifth direction D5. The dielectric film 160, the conductive film 170, and the upper electrode 180 can be disposed between the second support 152 and the etching stop film 125.

[0043] In some examples, the thickness of the first support 150 and the thickness of the second support 152 can be different from each other. The thickness of the first support 150 and the thickness of the second support 152 can refer to the thickness in the fifth direction D5. For example, the thickness of the first support 150 can be greater than the thickness of the second support 152. However, the present disclosure is not limited thereto. Unlike the illustration, the thickness of the first support 150 can be equal to or less than the thickness of the second support 152.

[0044] In some examples, the distance between the first support 150 and the second support 152 with respect to the fifth direction D5 can be less than the distance between the second support 152 and the etching stop film 125. However, the present disclosure is not limited thereto. Unlike the illustration, the distance between the first support 150 and the second support 152 can be equal to or greater than the distance between the second support 152 and the etching stop film 125.

[0045] For example, each of the first support 150 and the second support 152 can include at least one of silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), and tantalum oxide (TaO). In some examples, the first support 150 and the second support 152 can include the same material, but the present disclosure is not limited thereto. For example, the first support 150 and the second support 152 can include different materials from each other.

[0046] The first support 150 can include a support hole 150_H (e.g., adjacent) overlapping / exposed to a portion of the lower electrode 130. Figure 1 As used herein with respect to the support hole 150_H and the one or more lower electrodes 130, the term "adjacent" means that there is no other lower electrode 130 between the support hole 150_H and the lower electrode 130. Further, the adjacent lower electrode 130 can be on the periphery of the support hole 150_H, as Figure 1 The second support 152 can include a support hole overlapping / exposed to a portion of the lower electrode 130. The support hole of the second support 152 can be aligned with the support hole 150_H of the first support 150 in the fifth direction D5. The description of the arrangement of the support hole of the second support 152 can be substantially the same as that of the support hole 150_H of the first support 150. For example, except that the support hole of the second support 152 is spaced apart in the fifth direction D5, the arrangement of the support hole of the second support 152 can be the same as that of the support hole 150_H of the first support 150. Hereinafter, the support hole 150_H of the first support 150 will be mainly described. Figure 1

[0047] ​The first support 150 can include a plurality of support holes 150_H. For example, the term “support” as used herein can refer to a structure including Figure 1 the structure of the support hole 150_H shown in FIG. 1B (e.g., the first support 150 shown in FIG. 1A). Thus, the structure referred to by the term “support” can also include a plurality of segments / portions of the first support 150, for example, in the direction D1 (which is a cross-sectional view of the segments / portions spaced apart from each other in the direction D1). The support hole 150_H can overlap / expose at least a portion of the lower electrode 130. For example, the support hole 150_H can overlap / expose a portion of a side surface (i.e., a sidewall) of the lower electrode 130. The support hole 150_H can be adjacent to (e.g., can overlap / expose) some (but not all) of the plurality of lower electrodes 130. One support hole 150_H can overlap / expose four lower electrodes 130. For example, one support hole 150_H can overlap / expose four adjacent lower electrodes 130. As an example, the four adjacent lower electrodes 130 can all be adjacent to one support hole 150_H (e.g., on a perimeter of one support hole 150_H). Figure 1 Figure 2 The support hole 150_H can be aligned spaced apart from each other in the first direction D1. The support hole 150_H can be aligned spaced apart from each other in the second direction D2. A distance between adjacent support holes 150_H in the first direction D1 can be greater than a distance between adjacent support holes 150_H in the second direction D2.

[0048] The support hole 150_H can be aligned spaced apart from each other in the sixth direction D6. The support hole 150_H can be aligned spaced apart from each other in the seventh direction D7. A distance between adjacent support holes 150_H in the sixth direction D6 can be the same as a distance between adjacent support holes 150_H in the seventh direction D7. In other words, the support holes 150_H can be equally spaced in each of the sixth direction D6 and the seventh direction D7. A distance between adjacent support holes 150_H in the sixth direction D6 can be less than a distance between adjacent support holes 150_H in the second direction D2.

[0049] The sixth direction D6 can be a direction between the first direction D1 and the third direction D3. The seventh direction D7 can intersect the sixth direction D6. In some examples, an angle formed between the sixth direction D6 and the seventh direction D7 can be greater than 90 degrees. However, the present disclosure is not limited thereto. For example, the angle formed between the sixth direction D6 and the seventh direction D7 can be 90 degrees or less.

[0050] The sixth direction D6 can be a direction between the first direction D1 and the third direction D3. The seventh direction D7 can intersect the sixth direction D6. In some examples, an angle formed between the sixth direction D6 and the seventh direction D7 can be greater than 90 degrees. However, the present disclosure is not limited thereto. For example, the angle formed between the sixth direction D6 and the seventh direction D7 can be 90 degrees or less.

[0051] ​The support holes 150_H can be symmetrically arranged. For example, the support holes 150_H can be symmetrically arranged about a virtual line extending in the first direction D1, and can be symmetrically arranged about a virtual line extending in the second direction D2. In some examples, the support holes 150_H can be symmetrically arranged about a virtual line extending in the sixth direction D6, and can be symmetrically arranged about a virtual line extending in the seventh direction D7. The support holes 150_H can be arranged in a checkerboard structure or a grid structure in which a unit grid is a rhombus. In some examples, the support holes 150_H can be arranged in a checkerboard structure rotated by a certain angle.

[0052] The lower electrode 130 can include a first lower electrode 132 overlapping / exposed to the support hole 150_H (e.g., adjacent to the support hole 150_H so as to be on a periphery of the support hole 150_H) and a second lower electrode 134 not overlapping / exposed to the support hole 150_H (e.g., spaced apart from a periphery of the support hole 150_H). The first lower electrode 132 can be defined as the lower electrode 130 at least partially overlapping / exposed to the support hole 150_H, and the second lower electrode 134 can be defined as the lower electrode 130 surrounded by the first support 150 from a two-dimensional perspective.

[0053] The first lower electrode 132 can include first to fourth sub lower electrodes 132_1, 132_2, 132_3, and 132_4. The first to fourth sub lower electrodes 132_1, 132_2, 132_3, and 132_4 can refer to the first lower electrode 132 overlapping / exposed to one support hole 150_H among the plurality of first lower electrodes 132. The first to fourth sub lower electrodes 132_1, 132_2, 132_3, and 132_4 can be the lower electrodes 130 adjacent to each other.

[0054] The first sub lower electrode 132_1 and the second sub lower electrode 132_2 can be spaced apart from each other by a first distance W1 in the first direction D1. The third sub lower electrode 132_3 can be spaced apart from the fourth sub lower electrode 132_4 by a second distance W2 in the second direction D2. The first distance W1 can be smaller than the second distance W2. The distance between the lower electrodes 130 can be a distance measured based on the center of the lower electrode 130. For ease of description, based on the center of the support hole 150_H, the first sub lower electrode 132_1 can refer to the first lower electrode 132 disposed on the right side, the second sub lower electrode 132_2 can refer to the first lower electrode 132 disposed on the left side, the third sub lower electrode 132_3 can refer to the first lower electrode 132 disposed on the upper side, and the fourth sub lower electrode 132_4 can refer to the first lower electrode 132 disposed on the lower side.

[0055] The support hole 150_H can be surrounded by the second lower electrode 134 in a plan view. In other words, the first to fourth sub lower electrodes 132_1, 132_2, 132_3, and 132_4 can be surrounded by the second lower electrode 134.

[0056] The at least one second lower electrode 134 can be disposed between adjacent support holes 150_H. In other words, the at least one second lower electrode 134 can be disposed between one group of the first to fourth sub lower electrodes 132_1, 132_2, 132_3, and 132_4 and another group of the first to fourth sub lower electrodes 132_1, 132_2, 132_3, and 132_4.

[0057] The first lower electrode 132 and the second lower electrode 134 can be disposed between adjacent support holes 150_H in the first direction D1. For example, two first lower electrodes 132 and six second lower electrodes 134 can be disposed between adjacent support holes 150_H in the first direction D1. Specifically, one first lower electrode 132 and two second lower electrodes 134 can be disposed between adjacent third sub lower electrodes 132_3 in the first direction D1. Two second lower electrodes 134 can be disposed between a first sub lower electrode 132_1 overlapping / exposed to one support hole 150_H and a second sub lower electrode 132_2 overlapping / exposed to another support hole 150_H adjacent in the first direction. One first lower electrode 132 and two second lower electrodes 134 can be disposed between fourth sub lower electrodes 132_4 adjacent to each other in the first direction D1.

[0058] The second lower electrode 134 can be disposed between adjacent support holes 150_H in the second direction D2, and the first lower electrode 132 can not be disposed therebetween. Specifically, two second lower electrodes 134 can be disposed between a third sub lower electrode 132_3 overlapping / exposed to one support hole 150_H and a fourth sub lower electrode 132_4 overlapping / exposed to another support hole 150_H adjacent in the second direction D2, and no first lower electrode 132 can be disposed therebetween.

[0059] The at least one second lower electrode 134 can be disposed between adjacent support holes 150_H in the sixth direction D6. The at least one second lower electrode 134 can be disposed between adjacent support holes 150_H in the seventh direction D7. For example, a virtual line connecting the centers of each support hole 150_H can extend in the sixth direction D6 and the seventh direction D7. The centers of the support holes 150_H and the second lower electrodes 134 can be alternately disposed on the virtual line.

[0060] The plurality of lower electrodes 130 can be aligned at regular intervals in the first direction D1. The lower electrodes 130 can be arranged such that the first lower electrodes 132 and the second lower electrodes 134 can be arranged in one-to-one alternation or two-by-two alternation in the first direction D1. For example, based on the third sub-lower electrode 132_3 or the fourth sub-lower electrode 132_4 overlapping / exposed to one support hole 150_H, the second lower electrodes 134 and the first lower electrodes 132 can be arranged in one-to-one alternation in the first direction D1. Also, based on the first sub-lower electrode 132_1 overlapping / exposed to one support hole 150_H, the second lower electrodes 134 and the first lower electrodes 132 can be arranged in two-by-two alternation in the first direction D1.

[0061] The plurality of lower electrodes 130 can be aligned at regular intervals in the third direction D3 and the fourth direction D4. The lower electrodes can be alternately arranged such that the number of the first lower electrodes 132 and the number of the second lower electrodes 134 can be arranged in the order of 2, 1, 2, and 3 in the third direction D3. For example, based on the first sub-lower electrode 132_1 overlapping / exposed to one support hole 150_H, the number of the second lower electrodes 134 and the number of the first lower electrodes 132 can be alternately arranged in the order of 1, 2, 3, and 2 in the third direction D3. Also, based on the third sub-lower electrode 132_3 overlapping / exposed to one support hole 150_H, the number of the second lower electrodes 134 and the number of the first lower electrodes 132 can be alternately arranged in the order of 3, 2, 1, and 2 in the third direction D3 and the fourth direction D4.

[0062] In some examples, the first lower electrode 130 overlapping / exposed to the support hole 150_H can not have a constant area. For example, an area / region R1 of the first sub-lower electrode 132_1 overlapping / exposed to the support hole 150_H can be different from an area / region R2 of the third sub-lower electrode 132_3 overlapping / exposed to the support hole 150_H. The area / region R1 of the first sub-lower electrode 132_1 overlapping / exposed to the support hole 150_H can be greater than the area / region R2 of the third sub-lower electrode 132_3 overlapping / exposed to the support hole 150_H. As an example, a larger portion of the first sub-lower electrode 132_1 (e.g., a portion of a periphery (e.g., circumference) of the first sub-lower electrode 132_1) can be located in the support hole 150_H compared to the third sub-lower electrode 132_3. Accordingly, the first sub-lower electrode 132_1 and the third sub-lower electrode 132_3 can have portions of different sizes in the support hole 150_H. However, the disclosure is not limited thereto. The area / region R1 of the first sub-lower electrode 132_1 and the area / region R2 of the third sub-lower electrode 132_3 can be areas / regions of sidewalls of each of the first sub-lower electrode 132_1 and the third sub-lower electrode 132_3.

[0063] In some examples, an area / region R1 of the first sub lower electrode 132_1 overlapping / exposed to the support hole 150_H can be the same as an area / region of the second sub lower electrode 132_2 overlapping / exposed to the support hole 150_H. An area / region R2 of the third sub lower electrode 132_3 overlapping / exposed to the support hole 150_H can be the same as an area / region of the fourth sub lower electrode 132_4 overlapping / exposed to the support hole 150_H. However, the disclosure is not limited thereto.

[0064] A sidewall of the support hole 150_H can have a convex shape. The sidewall of the support hole 150_H can refer to a portion connected between the first lower electrodes 132. Also, the sidewall of the support hole 150_H can refer to based on an interface of the support hole 150_H with the support 150, and can be a term corresponding to a sidewall of the support 150. For example, the sidewall of the support hole 150_H connecting the first sub lower electrode 132_1 and the third sub lower electrode 132_3 can have a convex shape. In other words, the sidewall of the support 150 connecting the first sub lower electrode 132_1 and the third sub lower electrode 132_3 can have a concave shape.

[0065] The plurality of support holes 150_H can be repeatedly arranged. For example, Figure 1 The illustrated cell region Q1 can be repeatedly arranged in the first direction D1 and the second direction D2. The cell region Q1 can be defined as a region including a repeated arrangement of the first lower electrode 132 and the second lower electrode 134.

[0066] In the semiconductor memory device according to some embodiments, the ratio of the number of the first lower electrodes 132 to the number of the second lower electrodes 134 can be 1:1. In other words, the number of the first lower electrodes 132 and the number of the second lower electrodes 134 can be the same as each other. In the disclosure, comparing the number of the first lower electrodes 132 to the number of the second lower electrodes 134 can refer to comparing them on the cell region Q1. For example, in the cell region Q1, the number of the first lower electrodes 132 can be 8, and the number of the second lower electrodes 134 can also be 8.

[0067] As described above, the plurality of support holes 150_H can be repeatedly arranged. Accordingly, the plurality of first lower electrodes 132 and the plurality of second lower electrodes 134 can be repeatedly arranged according to certain rules. The plurality of first lower electrodes 132 and the plurality of second lower electrodes 134 can be symmetrically arranged. The positions of the first lower electrodes 132 and the positions of the second lower electrodes 134 can be set uniformly as a whole. In other words, the first lower electrodes 132 or the second lower electrodes 134 can not be densely arranged on a certain region or a certain line. Accordingly, it is possible to uniformly maintain the performance of the capacitor structure C_ST, and to improve the reliability of the semiconductor memory device.

[0068] Return Reference Figure 2 , a dielectric film 160 may be disposed on the lower electrode 130, the first support member 150, and the second support member 152. The dielectric film 160 may be disposed on portions of the lower electrode 130 that are exposed to the first support member 150 and the second support member 152 (e.g., not overlapping in direction D1). The dielectric film 160 may extend along the contour of the lower electrode 130. For example, the dielectric film 160 may extend along the side surface of the lower electrode 130 that overlaps / is exposed to the support member hole 150_H. The dielectric film 160 may be disposed on both the upper and lower surfaces of the first support member 150 and the upper and lower surfaces of the second support member 152.

[0069] For example, dielectric film 160 may include a high dielectric constant material, including silicon oxide, silicon nitride, silicon oxynitride, and metal. Although dielectric film 160 is shown as a single layer, this is for ease of description only and the present disclosure is not limited thereto. Unlike the illustration, dielectric film 160 may include multiple films.

[0070] The conductive film 170 may be disposed on the dielectric film 160. The conductive film 170 may extend along the outline of the dielectric film 160. The conductive film 170 may cover the dielectric film 160. The dielectric film 160 may be disposed between the lower electrode 130 and the conductive film 170.

[0071] For example, the conductive film 170 may include at least one of a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, tungsten nitride, etc.), a metal (e.g., ruthenium, iridium, titanium, tantalum, etc.), and a conductive metal oxide (e.g., iridium oxide or niobium oxide, etc.), but the present disclosure is not limited thereto.

[0072] The upper electrode 180 may be disposed on the conductive film 170. The upper electrode 180 may be located in (e.g., may fill) the empty space between the lower electrodes 130. The upper electrode 180 may be electrically connected to the conductive film 170. For example, the upper electrode 180 may include at least one of an elemental semiconductor material film and a compound semiconductor material film. The upper electrode 180 may include doped n-type impurities or p-type impurities.

[0073] Figure 3 is a plan view for illustrating a semiconductor memory device according to some embodiments of the present disclosure. For reference, Figure 3 yes Figure 1 For the sake of convenience, the following description will be mainly about Figure 1 and Figure 2 The differences in the configuration described in .

[0074] refer to Figures 1 to 3According to some embodiments of the disclosure, in the semiconductor memory device, each of the plurality of first lower electrodes 132 can be bent in a predetermined direction. For example, an upper portion 132_UP of the first lower electrode 132 can be bent in a predetermined direction. Unlike the upper portion 132_UP, a lower portion 132_BP of the first lower electrode 132 can not be bent and can be spaced apart from an adjacent lower electrode 130 by a predetermined distance.

[0075] In detail, each of the first, second, third, and fourth sub lower electrodes 132_1, 132_2, 132_3, and 132_4 can be bent (e.g., inclined) in a direction away from the center of the support hole 150_H. Unlike the first, second, third, and fourth sub lower electrodes 132_1, 132_2, 132_3, and 132_4, the fifth and sixth sub lower electrodes 134_1 and 134_2 can not be bent. Figure 1 In contrast, the first sub lower electrode 132_1 can be bent to the right, the second sub lower electrode 132_2 can be bent to the left, the third sub lower electrode 132_3 can be bent to the upper side, and the fourth sub lower electrode 132_4 can be bent to the lower side.

[0076] The second lower electrode 134 can include a fifth sub lower electrode 134_1 and a sixth sub lower electrode 134_2. The fifth sub lower electrode 134_1 can be a lower electrode 130 adjacent to the first sub lower electrode 132_1 in the first direction D1, and the sixth sub lower electrode 134_2 can be a lower electrode 130 adjacent to the fifth sub lower electrode 134_1 in the first direction D1.

[0077] The first sub lower electrode 132_1 is bent to the right, and accordingly, the distance between the first sub lower electrode 132_1 and the adjacent second lower electrode 134 can decrease. For example, based on the first direction D1, a distance W3 from the first sub lower electrode 132_1 to the fifth sub lower electrode 134_1 can be smaller than a distance W4 from the fifth sub lower electrode 134_1 to the sixth sub lower electrode 134_2. The distance between the lower electrodes 130 can be the shortest distance between the lower electrodes 130.

[0078] Figures 4 to 7 FIG. 1 is a diagram for explaining a semiconductor memory device according to some embodiments of the disclosure. For ease of description, differences from the configuration described in FIGS. 1A to 1C will be mainly described. For reference, Figure 1 and Figure 2 Figure 5 is an enlarged view of a region Q2 of Figure 4 Figure 6 is a cross-sectional view taken along line A-A of Figure 4 Figure 7 is a cross-sectional view taken along line B-B of Figure 4

[0079] Reference is made to Figure 4 and Figure 5 ​​​​In the semiconductor storage device according to some embodiments, the area / region R3 of the upper surface of the first sub lower electrode 132_1 can be different from the area / region R4 of the upper surface of the third sub lower electrode 132_3. For example, the area / region R3 of the upper surface of the first sub lower electrode 132_1 can be smaller than the area / region R4 of the upper surface of the third sub lower electrode.

[0080] At least two of the areas / regions of the first to fourth sub lower electrodes 132_1, 132_2, 132_3, and 132_4 that overlap / expose the support hole 150_H can be different from each other. The area / region of the first sub lower electrode 132_1 that overlaps / exposes the support hole 150_H can be larger than the area / region of the third sub lower electrode 132_3 that overlaps / exposes the support hole 150_H. The area / region of the first sub lower electrode 132_1 that overlaps / exposes the support hole 150_H can be the same as the area / region of the second sub lower electrode 132_2 that overlaps / exposes the support hole 150_H. The area / region of the third sub lower electrode 132_3 that overlaps / exposes the support hole 150_H can be the same as the area / region of the fourth sub lower electrode 132_4 that overlaps / exposes the support hole 150_H. However, the present disclosure is not limited thereto. For example, the area / region of the first sub lower electrode 132_1 that overlaps / exposes the support hole 150_H can be different from the area / region of the second sub lower electrode 132_2 that overlaps / exposes the support hole 150_H, and the area / region of the third sub lower electrode 132_3 that overlaps / exposes the support hole 150_H can be different from the area / region of the fourth sub lower electrode 132_4 that overlaps / exposes the support hole 150_H.

[0081] Reference Figure 6 and Figure 7 In the semiconductor storage device according to some embodiments, each of the first to fourth sub lower electrodes 132_1, 132_2, 132_3, and 132_4 can include a chamfered portion on the upper side.

[0082] The chamfered portion of the first sub lower electrode 132_1 can include a first side surface 132_1S. The first side surface 132_1S can have a first slope A1 with respect to an extension line perpendicular to the upper surface of the landing pad 120. The chamfered portion of the third sub lower electrode 132_3 can include a second side surface 132_3S. The second side surface 132_2S can have a second slope A2 with respect to an extension line perpendicular to the upper surface of the landing pad 120. The first slope A1 can be greater than the second slope A2.

[0083] The semiconductor storage device according to some embodiments can further include a first through-pattern 150_P and a second through-pattern 152_P. Each of the first through-pattern 150_P and the second through-pattern 152_P can be disposed on / in the support hole 150_H. The first through-pattern 150_P can be defined as a region in which the support hole 150_H overlaps the first support 150 in the first direction D1. The second through-pattern 152_P can be defined as a region in which the support hole 150_H overlaps the second support 152 in the first direction D1.

[0084] A width of the first through-pattern 150_P in the first direction D1 can be less than a width of the first through-pattern 150_P in the second direction D2. The widths of the first through-pattern 150_P in the first direction D1 and the second direction D2 can increase as a distance from the substrate 100 increases. The width of the first through-pattern 150_P in the first direction D1 can be greater than a width of the second through-pattern 152_P in the first direction D1. The width of the first through-pattern 150_P in the second direction D2 can be greater than a width of the second through-pattern 152_P in the second direction D2.

[0085] Figure 8 FIG. 1 is a plan view for explaining a semiconductor storage device according to some embodiments of the disclosure. For convenience of description, differences from the configuration described in FIGS. 1A and 1B will be mainly described. Figure 1 and Figure 2 FIG. 1B.

[0086] Referring to Figure 8 In the semiconductor storage device according to some embodiments, the support hole 150_H can be disposed on / in the first rectangular pattern HS_1. The first rectangular pattern HS_1 can have a virtual shape formed by extending a sidewall of the support hole 150_H. The sidewall of the support hole 150_H can refer to a portion connected between the first lower electrodes 132. Also, the sidewall of the support hole 150_H can refer to an interface of the support hole 150_H with the support 150, and can be a term corresponding to a sidewall of the support 150. For example, the sidewall of the support hole 150_H can refer to a portion connecting the first sub-lower electrode 132_1 and the third sub-lower electrode 132_3. The sidewall of the support hole 150_H can have a straight line shape from a two-dimensional perspective.

[0087] The vertices of the first rectangular pattern HS_1 can be disposed on the first to fourth sub lower electrodes 132_1, 132_2, 132_3, and 132_4, respectively. The first rectangular pattern HS_1 can have a diamond shape. In some examples, each vertex of the first rectangular pattern HS_1 can be disposed at the center of each of the first to fourth sub lower electrodes 132_1, 132_2, 132_3, and 132_4. However, the disclosure is not limited thereto.

[0088] In some examples, a portion of the sidewall of the support hole 150_H can be parallel to an imaginary straight line extending in the third direction D3. Another portion of the support hole 150_H can be parallel to an imaginary straight line extending in the fourth direction D4. However, the disclosure is not limited thereto.

[0089] Figure 9 is a plan view for explaining a semiconductor memory device according to some embodiments of the disclosure. For convenience of description, a configuration different from that described in Figure 1 and Figure 2 will be mainly described.

[0090] Referring to Figure 9 , according to some embodiments, the support hole 150_H can be disposed on / in the second rectangular pattern HS_2 in the semiconductor memory device. The second rectangular pattern HS_2 can have a virtual shape formed by extending the sidewall of the support hole 150_H. The sidewall of the support hole 150_H can refer to a portion connected between the first lower electrodes 132. Also, the sidewall of the support hole 150_H can refer to an interface based on the support hole 150_H and the support 150, and can be a term corresponding to the sidewall of the support 150. For example, the sidewall of the support hole 150_H can refer to a portion connecting the first sub lower electrode 132_1 and the third sub lower electrode 132_3. The sidewall of the support hole 150_H can have a straight line shape from a two-dimensional perspective.

[0091] Each vertex of the second rectangular pattern HS_2 can be disposed on the third sub lower electrode 132_3 and the fourth sub lower electrode 132_4, respectively. For example, two vertices of the second rectangular pattern HS_2 can be disposed on the sidewall of the third sub lower electrode 132_3. The other two vertices of the second rectangular pattern HS_2 can be disposed on the sidewall of the fourth sub lower electrode 132_4. The second rectangular pattern HS_2 can have a rectangular shape having a longer side in the second direction D2.

[0092] In some examples, a portion of the sidewall of the support hole 150_H can be parallel to an imaginary straight line extending in the first direction D1. Another portion of the support hole 150_H can be parallel to an imaginary straight line extending in the second direction D2. However, the disclosure is not limited thereto.

[0093] Figure 10 is a diagram for explaining a semiconductor storage device according to some embodiments of the disclosure. For reference, Figure 10 may correspond to a cross-sectional view taken along a line A-A of Figure 1 For convenience of description, differences from the configurations described in Figure 1 and Figure 2 will be mainly described.

[0094] Referring to Figure 10 , a semiconductor storage device according to some embodiments can include a first support 150 and a second support 152.

[0095] The first support 150 and the second support 152 can be disposed between a plurality of lower electrodes 130. The first support 150 and the second support 152 can be disposed between adjacent lower electrodes 130. The first support 150 and the second support 152 can connect and support the adjacent lower electrodes 130.

[0096] The first support 150 can have a first thickness in a fifth direction D5. The second support 152 can have a second thickness in the fifth direction D5. The first thickness and the second thickness can be the same as each other.

[0097] In some examples, based on the fifth direction D5, a distance between the first support 150 and the second support 152 can be the same as a distance between the second support 152 and the etching stop film 125. However, the disclosure is not limited thereto.

[0098] Figure 11 is a diagram for explaining a semiconductor storage device according to some embodiments of the disclosure. Figure 12 is a diagram for explaining a semiconductor storage device according to some embodiments of the disclosure. For reference, Figure 11 and Figure 12 may correspond to a cross-sectional view taken along a line A-A of Figure 1 For convenience of description, differences from the configurations described in Figure 1 and Figure 2 will be mainly described.

[0099] Referring to Figure 11 and Figure 12 , a semiconductor storage device according to some embodiments can further include a third support 154.

[0100] The first to third support members 150, 152, and 154 may be disposed between the plurality of lower electrodes 130. The first to third support members 150, 152, and 154 may be disposed between adjacent lower electrodes 130. The first to third support members 150, 152, and 154 may connect and support adjacent lower electrodes 130.

[0101] First to third supporters 150, 152, and 154 may be sequentially disposed on etch stop film 125. For example, first supporter 150 may be disposed highest relative to the upper surface of landing pad 120, and second and third supporters 152 and 154 may be sequentially disposed.

[0102] The first support member 150 may be disposed on the second support member 152. The first support member 150 may be spaced apart from the second support member 152 in the fifth direction D5. The second support member 152 may be disposed on the third support member 154. The second support member 152 may be spaced apart from the third support member 154 in the fifth direction D5. The third support member 154 may be spaced apart from the etching stopper film 125 in the fifth direction D5.

[0103] like Figure 11 As shown, in some examples, the thickness of the first support member 150 may be greater than the thickness of the second support member 152, and the thickness of the second support member 152 may be greater than the thickness of the third support member 154. The thickness may refer to the thickness in the fifth direction D5. However, the present disclosure is not limited thereto.

[0104] like Figure 12 As shown, in some examples, the thickness of the first support member 150 may be the same as the thickness of the second support member 152. The thickness of the first support member 150 and the second support member 152 may be greater than the thickness of the third support member 154. However, the present disclosure is not limited thereto. Although not shown, the thicknesses of the first to third support members 150, 152, and 154 may be the same as each other.

[0105] The dielectric film 160 , the conductive film 170 , and the upper electrode 180 may be respectively disposed between the first support 150 and the second support 152 , between the second support 152 and the third support 154 , and between the third support 154 and the etch stop film 125 .

[0106] In some examples, the first support 150 and the second support 152 may be spaced apart from each other by the same distance as the second support 152 and the third support 154 are spaced apart from each other.

[0107] In some examples, the distance between the first support 150 and the second support 152 can be different from the distance between the second support 152 and the third support 154. For example, the distance between the first support 150 and the second support 152 can be smaller than the distance between the second support 152 and the third support 154. The distance between the second support 152 and the third support 154 can be smaller than the distance between the third support 154 and the etching stop film 125. However, the present disclosure is not limited thereto.

[0108] Figure 13 and Figure 14 is a diagram for explaining a semiconductor memory device according to some embodiments of the present disclosure. As a reference, Figure 13 is a schematic layout diagram for explaining a semiconductor memory device according to some embodiments. Figure 14 is a cross-sectional view taken along line C-C of Figure 13 .

[0109] Referring to Figure 13 and Figure 14 , a semiconductor memory device according to some embodiments can include a plurality of active regions ACT. The active regions ACT can be defined by device isolation films 305 formed in a substrate 300. The active regions ACT can have a bar shape. The plurality of active regions ACT can be spaced apart from each other. The device isolation films 305 can have a shallow trench isolation (STI) structure having excellent device isolation characteristics.

[0110] For example, each of the plurality of device isolation films 305 can include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, but is not limited thereto. Although it is shown that each of the device isolation films 305 is formed of one insulating film, this is only for convenience of description, and the present disclosure is not limited thereto.

[0111] A word line WL can pass through the active regions ACT. The word line WL can extend in a first direction D1. A plurality of word lines WL can be spaced apart from each other in a second direction D2. The plurality of word lines WL can be disposed to be equally spaced apart. The width of the word line WL or the spacing between the word lines WL can be determined according to a design rule.

[0112] In some examples, the word line WL can be disposed on a gate trench and the device isolation film 305 formed in the substrate 300. The word line WL can include a gate insulating film, a gate electrode, and a gate capping pattern.

[0113] The gate electrode can include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, and a conductive metal oxide.

[0114] A plurality of bit lines BL extending in a second direction D2 orthogonal to the word line WL can be provided on the word line WL. The plurality of bit lines BL can extend in parallel to each other. The bit lines BL can be provided at equal intervals. The width of the bit lines BL or the interval between the bit lines BL can be determined according to design rules.

[0115] The bit line BL can include first to third unit conductive films 322, 324, and 326. The first to third unit conductive films 322, 324, and 326 can be sequentially stacked on the substrate 300 and the device isolation film 305. Figure 14 It is illustrated that the bit line BL is a three-layer film, but the present disclosure is not limited thereto.

[0116] Each of the first to third unit conductive films 322, 324, and 326 can include at least one of a doped impurity semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal alloy.

[0117] A bit line capping film 330 can be provided on the bit line BL. The bit line capping film 330 can extend along the upper surface of the third unit conductive film 326. For example, the bit line capping film 330 can include at least one of a silicon nitride film, silicon oxynitride, silicon carbonitride, and silicon oxycarbonitride. The bit line capping film 330 is illustrated as a single film, but the present disclosure is not limited thereto.

[0118] A direct contact DC can be formed between the bit line BL and the substrate 100. The direct contact DC can electrically connect the bit line BL and the substrate 100. The bit line BL can be formed on the direct contact DC. For example, the direct contact DC can be formed at a point where the bit line BL intersects with a middle portion of the active region ACT having an elongated island shape.

[0119] For example, the direct contact DC can include at least one of a doped impurity semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal.

[0120] In a region overlapping with the upper surface of the direct contact DC, the bit line BL can include the second unit conductive film 324 and the third unit conductive film 326. In a region not overlapping with the upper surface of the direct contact DC, the bit line BL can include the first to third unit conductive films 322, 324, and 326.

[0121] A unit insulating film 310 can be formed on the substrate 300 and the device isolation film 305. Specifically, the unit insulating film 310 can be formed on the device isolation film 305 and on a portion of the substrate 300 on which the direct contact DC is not formed. The unit insulating film 310 can be formed between the substrate 300 and the bit line BL and between the device isolation film 305 and the bit line BL.

[0122] The cell line spacer SP can be disposed on the bit line BL and the sidewall of the bit line cap film 330. The cell line spacer SP can be formed on the substrate 300 and the device isolation film 305 at the portion of the bit line BL where the direct contact DC is formed. The cell line spacer SP can be disposed on the sidewall of the bit line BL, the bit line cap film 330, and the direct contact DC.

[0123] However, the cell line spacer SP can be disposed on the cell insulating film 310 in other portions of the bit line BL where the direct contact DC is not formed. The cell line spacer SP can be disposed on the sidewall of the bit line BL and the bit line cap film 330.

[0124] The cell line spacer SP can be a single layer film, but as illustrated, the cell line spacer SP can be a multi-layer film including first to fourth cell line spacers 342, 344, 346, and 348. For example, the first to fourth cell line spacers 342, 344, 346, and 348 can include one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiON), a silicon carbon oxynitride film (SiOCN), an air gap, and a combination thereof, but are not limited thereto.

[0125] The buried contact BC can be disposed between adjacent bit lines BL in the first direction D1. The buried contact BC can be connected to the active region ACT. The buried contact BC can connect the active region ACT and the capacitor structure C_ST. Such an arrangement structure can make the contact area between the buried contact BC and the active region ACT small. Accordingly, the landing pad LP can be disposed to expand the contact area with the active region ACT and also expand the contact area with the capacitor structure C_ST.

[0126] For example, the buried contact BC can include at least one of a doped impurity semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal.

[0127] The landing pad LP can be formed on the buried contact BC. The landing pad LP can be electrically connected to the buried contact BC. The landing pad LP can be disposed between the active region ACT and the buried contact BC. The landing pad LP can be disposed between the buried contact BC and the lower electrode 130. By expanding the contact area via the landing pad LP, the contact resistance between the active region ACT and the lower electrode 130 can be reduced.

[0128] For example, the landing pad LP can include at least one of a doped impurity semiconductor material, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, and a metal alloy.

[0129] A pad isolation insulating film 360 can be disposed between the landing pads LP. The pad isolation insulating film 360 can electrically separate the plurality of landing pads LP from each other. For example, the pad isolation insulating film 360 can include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon oxycarbonitride film, and a silicon carbonitride film.

[0130] An etching stop film 125 can be disposed on an upper surface of the landing pads LP and an upper surface of the pad isolation insulating film 360. For example, the etching stop film 125 can include at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon oxynitride (SiON), and silicon boron nitride (SiBN).

[0131] A capacitor structure C_ST can be disposed on the landing pads LP. The capacitor structure C_ST can be connected to the landing pads LP. That is, the capacitor structure C_ST can be electrically connected to the buried contacts BC.

[0132] The capacitor structure C_ST can include lower electrodes 130, a dielectric film 160, a conductive film 170, and upper electrodes 180. First supports 150 and second supports 152 can be disposed between the lower electrodes 130. Descriptions of the capacitor structure C_ST, the first supports 150, and the second supports 152 can be the same as described above with reference to FIGS. 1A to 1C. Figures 1 to 12

[0133] Figure 15 and Figure 16 are diagrams for illustrating a semiconductor memory device according to some embodiments of the disclosure. As a reference, Figure 16 is a cross-sectional view taken along a line D-D of Figure 15 .

[0134] Referring to Figure 15 and Figure 16 , a semiconductor memory device according to some embodiments can include a substrate 400, a lower insulating film 410, bit lines BL, word lines WL, a gate insulating film 430, a channel layer 450, landing pads LP, and a capacitor structure C_ST. The semiconductor memory device according to some embodiments can be a memory device including a vertical channel transistor VCT. The vertical channel transistor can refer to a structure in which a channel length of the channel layer 450 extends in a fifth direction D5 perpendicular to the substrate 400.

[0135] The lower insulating film 410 can be disposed on the substrate 400. A plurality of bit lines BL can be disposed on the lower insulating film 410. The plurality of bit lines BL can extend in a first direction D1. The plurality of bit lines BL can be spaced apart from each other in a second direction D2.

[0136] ​The plurality of bit lines BL can include a doped semiconductor material, a metal, a metal alloy, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, the plurality of bit lines BL can be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO, RuO, or a combination thereof, but is not limited thereto. The plurality of bit lines BL can include a single layer or multiple layers of the above-described materials. In example aspects, the plurality of bit lines BL can include graphene, carbon nanotubes, or a combination thereof.

[0137] A mold etch stop film 415 can be disposed on the bit line BL. A mold pattern 420 can be disposed on the mold etch stop film 415. The mold etch stop film 415 and the mold pattern 420 can extend in the second direction D2. A plurality of mold patterns 420 can be spaced apart from each other in the first direction D1.

[0138] A channel layer 450 can be disposed on the bit line BL. The channel layer 450 can be disposed between the mold patterns 420. The channel layer 450 can include a horizontal portion in contact with the bit line BL and a vertical portion extending from the horizontal portion in a fifth direction D5. The vertical portion can include a first vertical portion disposed at one end of the horizontal portion and a second vertical portion disposed at the other end (e.g., opposite end) of the horizontal portion. The first vertical portion and the second vertical portion can be spaced apart from each other in the first direction D1. In some examples, the horizontal portion of the channel layer can be separated, unlike the illustration.

[0139] The channel layer 450 can include an oxide semiconductor. For example, the oxide semiconductor can include InGaZnO, InGaSiO, InSnZnO, InZnO, ZnO, ZnSnO, ZnON, ZrZnSnO, SnO, HfInZnO, GaZnSnO, AlZnSnO, YbGaZnO, InGaO, or a combination thereof. The channel layer 450 can include a single layer or multiple layers of the oxide semiconductor. Further, the channel layer 450 can be, for example, polycrystalline or amorphous, but is not limited thereto. In some examples, the channel layer 450 can include graphene, carbon nanotubes, or a combination thereof.

[0140] A gate insulating film 430 can be disposed on the channel layer 450. The gate insulating film 430 can be disposed between the channel layer 450 and the word line WL. The channel layer 450 and the word line WL can be spaced apart from each other by the gate insulating film 430.

[0141] The gate insulating film 430 can include a silicon oxide film, a silicon oxynitride film, a high dielectric constant insulating film having a higher dielectric constant than the silicon oxide film, or a combination thereof.

[0142] A word line WL can be provided on the gate insulating film 430. The word line WL can extend in the second direction D2. The word line WL can extend in the fifth direction D5 along the vertical portion of the channel layer 450.

[0143] In the direction D5, the height of the upper surface of the word line WL can be higher than the height of the upper surface of the channel layer 450. Specifically, the distance to the upper surface of the word line WL can be greater than the distance to the upper surface of the vertical portion of the channel layer 450 with respect to the upper surface of the bit line BL. However, the present disclosure is not limited thereto. For example, the upper surface of the word line WL can be provided on the same plane as the upper surface of the channel layer 450, or below the upper surface of the channel layer 450.

[0144] The word line WL can include an electrically conductive material. For example, the word line WL can include at least one of doped polysilicon, an electrically conductive metal nitride, an electrically conductive metal nitride silicon, a metal carbonitride, an electrically conductive metal silicide, an electrically conductive metal oxide, a two-dimensional material, a metal, and a metal alloy.

[0145] A gate isolation pattern 470 can be provided between the word lines WL. The word lines WL can be spaced apart from each other by the gate isolation pattern 470. For example, the word line WL provided on the first vertical portion and the word line WL provided on the second vertical portion can be spaced apart from each other in the first direction D1 by the gate isolation pattern 470. The gate isolation pattern 470 can include an insulating material.

[0146] A landing pad LP can be provided on the molding pattern 420 and the gate isolation pattern 470. The landing pad LP can include a protruding portion protruding toward the channel layer 450. The protruding portion of the landing pad LP can be in contact with the vertical portion of the channel layer 450. The landing pad LP can be electrically connected to the channel layer 450.

[0147] The landing pad LP can include an electrically conductive material. The landing pad LP can include at least one of doped polysilicon, an electrically conductive metal nitride, an electrically conductive metal nitride silicon, a metal carbonitride, an electrically conductive metal silicide, an electrically conductive metal oxide, a two-dimensional material, a metal, and a metal alloy.

[0148] A capacitor structure C_ST can be provided on the landing pad LP. The capacitor structure C_ST can be connected to the landing pad LP. That is, the channel layer 450 and the capacitor structure C_ST can be electrically connected to each other by the landing pad LP.

[0149] The capacitor structure C_ST can include the lower electrode 130, the dielectric film 160, the conductive film 170, and the upper electrode 180. The first support 150 and the second support 152 can be provided between the lower electrodes 130. The description of the capacitor structure C_ST, the first support 150, and the second support 152 can be the same as described above with reference to Figures 1 to 12 .

[0150] Figures 17 to 25 are plan views showing intermediate stages for explaining a method of manufacturing a semiconductor storage device according to some embodiments of the present disclosure. As a reference, Figure 17 and Figure 20 are plan views showing intermediate stages for explaining a method of manufacturing a semiconductor storage device according to some embodiments of the present disclosure. As a reference, Figure 18 and Figure 19 are cross-sectional views taken along line A-A of Figure 17 , and Figures 21 to 25 is a cross-sectional view taken along line A-A of Figure 20 .

[0151] With reference to Figure 17 and Figure 18 , the contact plug 110, the landing pad 120, and the interlayer insulating film 105 can be formed on the substrate 100. The etching stop film 125, the second sacrificial film SC_2, the second support 152, the first sacrificial film SC_1, and the first support 150 can be sequentially stacked on the interlayer insulating film 105 and the landing pad 120. The first sacrificial film SC_1 and the second sacrificial film SC_2 can include the same or similar material. For example, the first sacrificial film SC_1 and the second sacrificial film SC_2 can include silicon oxide.

[0152] The lower electrode hole 130_H, which extends through the etching stop film 125, the second sacrificial film SC_2, the second support 152, the first sacrificial film SC_1, and the first support 150, can be formed. The lower electrode hole 130_H can expose a portion (e.g., a portion of an upper surface) of the landing pad 120. The lower electrode hole 130_H can extend in the fifth direction D5. Figure 18 It is shown that the width of the lower electrode hole 130_H is constant, but the present disclosure is not limited thereto. For example, the width of the lower electrode hole 130_H can narrow as approaching the landing pad 120. In this case, the lower electrode hole 130_H can have a tapered shape.

[0153] With reference to Figure 18 and Figure 19 , the lower electrode 130 can be formed on the landing pad 120. The lower electrode 130 can fill the lower electrode hole 130_H. The lower electrode 130 can be formed by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or plasma-enhanced ALD.

[0154] With referenceFigure 20 and Figure 21 The mask pattern MP can be formed on the lower electrode 130 and the first support 150. The mask pattern MP can include the openings OP. For example, the mask pattern MP can include at least one of a spin-on hard mask (SOH) or an amorphous carbon layer / film (ACL).

[0155] The openings OP can expose a portion (e.g., a portion of an upper surface) of the lower electrode 130 and the first support 150. The number of the lower electrode 130 exposed by one opening OP can be four.

[0156] The arrangement of the openings OP can correspond to the arrangement of the support holes 150_H described above with reference to Figure 1 For example, the openings OP can be spaced apart from each other at regular intervals in the first direction D1. The openings OP can be spaced apart from each other at regular intervals in the second direction D2. The distance by which the openings OP are spaced apart from each other in the first direction D1 can be greater than the distance by which the openings OP are spaced apart from each other in the second direction D2. The openings OP can be spaced apart from each other at equal intervals in the sixth direction D6 and the seventh direction D7.

[0157] As illustrated, the openings OP can be spaced apart from each other at a first pitch P1 in the sixth direction D6. The openings OP can be spaced apart from each other at a second pitch P2 in the seventh direction D7. The first pitch P1 and the second pitch P2 can be the same as each other. The first pitch P1 and the second pitch P2 can be distances measured with respect to the centers of the openings OP.

[0158] In some examples, the first pitch P1 and the second pitch P2 can be 7.8F. However, the disclosure is not limited thereto. The first pitch P1 and the second pitch P2 can be less than 7.8F. F can refer to a minimum lithography feature size.

[0159] As the degree of integration of semiconductor memory devices is getting higher, the lithography feature size is getting smaller. Accordingly, there is a case where an extreme ultraviolet lithography (EUV) apparatus is needed to implement a smaller lithography feature size. According to the method of manufacturing a semiconductor memory device according to some embodiments of the disclosure, the distance between the openings OP can be 7.8F. Accordingly, according to some embodiments, it is possible to form the openings OP of the mask pattern MP using an ArF immersion apparatus instead of an EUV apparatus. The ArF immersion apparatus can have a longer wavelength than the EUV apparatus, but is low in cost, and accordingly, it is possible to reduce the manufacturing cost of the semiconductor memory device.

[0160] Referring to Figure 22 The first support 150 exposed by the mask pattern MP can be removed, and the first sacrificial film SC_1 can be removed.

[0161] Specifically, the first supports 150 exposed by the mask pattern MP among the plurality of first supports 150 can be removed by an etching process. For example, the etching process can be a dry etching process. In the etching process, the lower electrode 130 having etching selectivity with respect to the first supports 150 can not be removed. The first supports 150 can be removed, and the first sacrificial film SC_1 can be exposed.

[0162] The first sacrificial film SC_1 can be removed by an etching process, and a support hole 150_H can be formed. For example, the first sacrificial film SC_1 can be removed by a wet etching process. The support hole 150_H can expose a portion (e.g., a side surface) of the lower electrode 130 and a portion (e.g., an upper surface) of the second support 152.

[0163] Referring to Figure 23 The second supports 152 exposed by the support hole 150_H among the plurality of second supports 152 can be removed by an etching process. For example, the etching process can be a dry etching process. In the etching process, the lower electrode 130 having etching selectivity with respect to the second supports 152 can not be removed. The second supports 152 can be removed, and the second sacrificial film SC_2 can be exposed.

[0164] The second sacrificial film SC_2 can be removed by an etching process, and the support hole 150_H can extend in a fifth direction D5. For example, the second sacrificial film SC_2 can be removed by a wet etching process. A bottom surface of the support hole 150_H can expose the etching stop film 125.

[0165] Referring to Figure 24 The mask pattern MP can be removed, and a dielectric film 160 can be formed on the lower electrode 130, the first supports 150, and the second supports 152.

[0166] Specifically, the mask pattern MP can be removed, and an upper surface of the lower electrode 130 and an upper surface of the first supports 150 can be exposed. The lower electrode 130 can include a first lower electrode 132 and a second lower electrode 134. The first lower electrode 132 can refer to the lower electrode 130 among the plurality of lower electrodes 130 adjacent (e.g., on a periphery of, exposed by) the support hole 150_H, and the second lower electrode 134 can refer to the lower electrode 130 among the plurality of lower electrodes 130 spaced apart (e.g., not exposed by) from the support hole 150_H.

[0167] The dielectric film 160 can be formed along the upper surface and the side surface of the first lower electrode 132 and the upper surface of the first support 150. In addition, the dielectric film 160 can be formed on the lower surface of the first support 150, the upper surface of the second support 152, and the lower electrode 130 exposed between the first support 150 and the second support 152. The dielectric film 160 can be formed on the lower surface of the second support 152, the upper surface of the etching stop film 125, and the lower electrode 130 exposed between the second support 152 and the etching stop film 125.

[0168] For example, the dielectric film 160 can be formed using a method such as chemical vapor deposition (CVD), atomic layer deposition (ALD), PEALD.

[0169] Referring to FIG. 1B, Figure 25 The conductive film 170 can be formed on the dielectric film 160. The conductive film 170 can be formed along the profile of the dielectric film 160. For example, the conductive film 170 can be formed along the profile of the dielectric film 160 disposed on the lower electrode 130, the first support 150, the second support 152, and the etching stop film 125.

[0170] The conductive film 170 can be formed using a method such as chemical vapor deposition (CVD), atomic layer deposition (ALD), PEALD.

[0171] Referring to FIG. 1B, Figure 2 The upper electrode 180 can be formed on the conductive film 170 and can form a capacitor structure C_ST.

[0172] Although the present disclosure has been described above with respect to the embodiments of the present disclosure, the present disclosure is not limited thereto. Various modifications and variations can be made to the present disclosure by those skilled in the art in the scope of the present disclosure defined by the appended claims (and their equivalents).

Claims

1. A semiconductor memory device, comprising: a substrate; a plurality of lower electrodes on the substrate; and a support connecting the plurality of lower electrodes to each other, wherein the support includes a plurality of support holes adjacent to some of the plurality of lower electrodes, wherein the plurality of lower electrodes includes a plurality of first lower electrodes adjacent to the plurality of support holes and a plurality of second lower electrodes spaced apart from the plurality of support holes, wherein four adjacent first lower electrodes of the plurality of first lower electrodes are adjacent to one support hole of the plurality of support holes, and wherein the plurality of support holes are equally spaced in a first direction and a second direction intersecting the first direction. Each of the plurality of support holes is surrounded by the plurality of second lower electrodes.

2. The semiconductor memory device according to claim 1, wherein, A ratio of a number of the plurality of first lower electrodes to a number of the plurality of second lower electrodes is 1:

1.

3. The semiconductor memory device according to claim 1, wherein, 4. The semiconductor memory device of claim 1, the four adjacent first lower electrodes respectively include a first sub lower electrode, a second sub lower electrode, a third sub lower electrode, and a fourth sub lower electrode, the first sub lower electrode, the second sub lower electrode, the third sub lower electrode, and the fourth sub lower electrode are located on a periphery of the one support hole of the plurality of support holes, wherein wherein the first sub lower electrode is spaced apart from the second sub lower electrode by a first distance in a third direction, wherein the third sub lower electrode is spaced apart from the fourth sub lower electrode by a second distance in a fourth direction perpendicular to the third direction, wherein the first direction, the second direction, the third direction, and the fourth direction intersect each other, and wherein the first distance is smaller than the second distance. a size of a portion of the first sub lower electrode in the one support hole of the plurality of support holes is different from a size of a portion of the third sub lower electrode in the one support hole of the plurality of support holes.

5. The semiconductor memory device according to claim 4, wherein, the size of the portion of the first sub lower electrode is greater than the size of the portion of the third sub lower electrode.

6. The semiconductor memory device according to claim 5, wherein, 7. The semiconductor memory device of claim 4, the plurality of second lower electrodes include a fifth sub lower electrode adjacent to the first sub lower electrode in the third direction and a sixth sub lower electrode adjacent to the fifth sub lower electrode in the third direction, and wherein wherein a distance from the first sub lower electrode to the fifth sub lower electrode is smaller than a distance from the fifth sub lower electrode to the sixth sub lower electrode. a landing between the substrate and a lower electrode of the plurality of lower electrodes and electrically connected to the lower electrode, 8. The semiconductor memory device of claim 4, further comprising: wherein the first sub lower electrode includes a first side surface adjacent to the one support hole of the plurality of support holes, wherein the third sub lower electrode includes a second side surface adjacent to the one support hole of the plurality of support holes, and a slope of the first side surface is greater than a slope of the second side surface with respect to a prolongation line perpendicular to an upper surface of the landing. at least three second lower electrodes of the plurality of second lower electrodes are between two adjacent support holes of the plurality of support holes in the third direction.

9. The semiconductor memory device according to claim 4, wherein, ​ 10. The semiconductor memory device according to claim 4, wherein, Two of the plurality of second lower electrodes are between two adjacent support holes in the fourth direction among the plurality of support holes.

11. The semiconductor memory device according to claim 1, wherein At least one of the plurality of second lower electrodes is between two adjacent support holes among the plurality of support holes, and wherein the two adjacent support holes are adjacent in the first direction.

12. The semiconductor memory device according to claim 1, further comprising: a landing pad between the substrate and a lower electrode among the plurality of lower electrodes, and electrically connected to the lower electrode; an upper electrode on the lower electrode; and a dielectric film between the lower electrode and the upper electrode.

13. A semiconductor memory device, comprising: a substrate; a plurality of lower electrodes on the substrate; and a support connecting the plurality of lower electrodes to each other, wherein the support includes a plurality of support holes adjacent to some of the plurality of lower electrodes, wherein the plurality of lower electrodes includes a plurality of first lower electrodes adjacent to the plurality of support holes and a plurality of second lower electrodes spaced apart from the plurality of support holes, wherein the plurality of support holes are aligned in a first direction and spaced apart from each other by a first distance, wherein the plurality of support holes are aligned in a second direction perpendicular to the first direction and spaced apart from each other by a second distance different from the first distance, and wherein a number of second lower electrodes between a first pair of adjacent support holes in the first direction among the plurality of support holes is greater than a number of second lower electrodes between a second pair of adjacent support holes in the second direction among the plurality of support holes. Each of the plurality of support holes has four of the plurality of lower electrodes on a periphery thereof.

14. The semiconductor memory device according to claim 13, wherein, The first distance is greater than the second distance.

15. The semiconductor memory device according to claim 13, wherein, A ratio of the number of the first lower electrodes to the number of the second lower electrodes is 1:

1.

16. The semiconductor memory device according to claim 13, wherein, A first lower electrode adjacent to one of the plurality of support holes among the plurality of first lower electrodes is surrounded by the plurality of second lower electrodes.

17. The semiconductor memory device of claim 13, wherein, 18. The semiconductor memory device according to claim 13, the plurality of support holes are spaced apart from each other in a third direction and a fourth direction intersecting the third direction, wherein, wherein the third direction intersects the first direction and the second direction, and wherein a number of second lower electrodes between a third pair of adjacent support holes in the third direction among the plurality of support holes is equal to a number of second lower electrodes between a fourth pair of adjacent support holes in the fourth direction among the plurality of support holes.

19. The semiconductor memory device according to claim 13, the plurality of lower electrodes are equally spaced in the first direction, and wherein, wherein the plurality of first lower electrodes and the plurality of second lower electrodes are arranged alternately one by one or two by two in the first direction.

20. A semiconductor memory device, comprising: a substrate including a transistor; ​ a capacitor structure on the substrate and electrically connected to the transistor, the capacitor structure including a plurality of lower electrodes electrically connected to the transistor, an upper electrode on the plurality of lower electrodes, and a dielectric film between the plurality of lower electrodes and the upper electrode; and a support connecting the plurality of lower electrodes to each other, wherein the support includes a plurality of support holes adjacent to some of the plurality of lower electrodes, wherein the plurality of lower electrodes includes a plurality of first lower electrodes adjacent to the plurality of support holes and a plurality of second lower electrodes spaced apart from the plurality of support holes, wherein four adjacent first lower electrodes of the plurality of first lower electrodes are adjacent to one support hole of the plurality of support holes, and wherein a ratio of a number of the first lower electrodes to a number of the second lower electrodes is 1:1.

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