Semiconductor device with insulation structure

Abstract

A semiconductor device includes: a bit line structure; a back gate electrode and a word line on the bit line structure; an active pattern between the back gate electrode and the word line on the bit line structure, the active pattern extending in a vertical direction; a back gate dielectric layer between the back gate electrode and the active pattern, the back gate dielectric layer on a side surface and a lower surface of the back gate electrode; and a first insulating structure between the back gate dielectric layer and the bit line structure. The first insulating structure includes a first stop in contact with the back gate dielectric layer and the bit line structure. The back gate dielectric layer is spaced apart from the bit line structure in the vertical direction by a first stop.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0053810, filed April 23, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The present inventive concept generally relates to a semiconductor device having an insulating structure. BACKGROUND

[0004] As the demand for implementation of high performance, high speed, and / or multifunctionalization of semiconductor devices increases, the degree of integration of semiconductor devices has been increasing. In manufacturing semiconductor devices having fine patterns corresponding to the trend of high integration of semiconductor devices, it is necessary to implement patterns having a fine width or a fine separation distance. SUMMARY

[0005] An aspect of the present inventive concept provides a semiconductor device having an insulating structure including a stopper.

[0006] According to an aspect of the present inventive concept, there is provided a semiconductor device including: a bit line structure; a back gate electrode and a word line on the bit line structure; an active pattern between the back gate electrode and the word line on the bit line structure, the active pattern extending in a vertical direction; a back gate dielectric layer between the back gate electrode and the active pattern, the back gate dielectric layer covering (i.e., on) side surfaces and a lower surface of the back gate electrode;

[0007] and a first insulating structure between the back gate dielectric layer and the bit line structure. The first insulating structure can include a first stopper in contact with the back gate dielectric layer and the bit line structure. The back gate dielectric layer can be spaced apart from the bit line structure in the vertical direction.

[0008] According to another aspect of the inventive concepts, a semiconductor device is provided that includes a bit line structure; a back gate electrode and a word line on the bit line structure; an active pattern between the back gate electrode and the word line on the bit line structure, the active pattern extending in a vertical direction; a back gate dielectric layer between the back gate electrode and the active pattern, the back gate dielectric layer covering side surfaces and a lower surface of the back gate electrode; a gate dielectric layer between the word line and the active pattern, the gate dielectric layer covering side surfaces and a lower surface of the word line; a first insulating structure between the back gate dielectric layer and the bit line structure; and a second insulating structure between the gate dielectric layer and the bit line structure. The active pattern can include a first portion and a second portion on the first portion. The first portion of the active pattern can be in contact with the first insulating structure and the second insulating structure. The second portion of the active pattern can be in contact with the back gate dielectric layer and the gate dielectric layer.

[0009] According to another aspect of the inventive concepts, a semiconductor device is provided that includes a bit line structure; a back gate electrode and a word line on the bit line structure; an active pattern between the back gate electrode and the word line on the bit line structure, the active pattern extending in a vertical direction; a contact structure on the active pattern; an information storage structure on the contact structure; a back gate dielectric layer between the back gate electrode and the active pattern, the back gate dielectric layer covering side surfaces and a lower surface of the back gate electrode, the back gate dielectric layer being in contact with side surfaces of the active pattern; a gate dielectric layer between the word line and the active pattern, the gate dielectric layer covering side surfaces and a lower surface of the word line, the gate dielectric layer being in contact with side surfaces of the active pattern; a first insulating structure in contact with the lower surface of the back gate dielectric layer and an upper surface of the bit line structure; and

[0010] a second insulating structure in contact with the lower surface of the gate dielectric layer and the upper surface of the bit line structure. The first insulating structure can include a first stopper in contact with the back gate dielectric layer and the bit line structure. The back gate dielectric layer can be spaced apart from the bit line structure in the vertical direction. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other aspects, features, and advantages of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals (when used) designate corresponding elements throughout the several views and wherein:

[0012] Figure 1 is a schematic plan view of a semiconductor device according to an example embodiment;

[0013] Figure 2 is Figure 1 is a schematic vertical cross-sectional view of the semiconductor device shown in

[0014] Figure 3 is Figure 2 a partial enlarged view of the semiconductor device shown in

[0015] Figures 4 to 9 is a schematic vertical cross-sectional view of a semiconductor device according to an example embodiment;

[0016] Figure 10 is a flowchart of a method for manufacturing a semiconductor device according to an example embodiment;

[0017] Figures 11 to 25 is a schematic vertical cross-sectional view of a sequential intermediate process in a method of manufacturing a semiconductor device according to an example embodiment;

[0018] Figure 26 is a flowchart of a method of manufacturing a semiconductor device according to an example embodiment;

[0019] Figures 27 to 32 is a schematic vertical cross-sectional view of a sequential intermediate process in a method of manufacturing a semiconductor device according to an example embodiment;

[0020] Figure 33 is a flowchart of a method of manufacturing a semiconductor device according to an example embodiment; and

[0021] Figures 34 to 38 is a schematic vertical cross-sectional view of a sequential intermediate process in a method of manufacturing a semiconductor device according to an example embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, preferred example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0023] Figure 1 is a schematic plan view of a semiconductor device according to an example embodiment. Figure 2 is Figure 1 is a schematic vertical cross-sectional view taken along line I-I’ of the semiconductor device shown in Figure 3 is Figure 2 is a partial enlarged view of the semiconductor device shown in

[0024] Referring to Figures 1 to 3 , a semiconductor device 100 according to an example embodiment of the inventive concept can include a lower insulating layer 101, a bit line structure 110, a back gate electrode 122, a first insulating structure 130, a second insulating structure 135, an active pattern 140, a word line 152, a contact structure 160, and an information storage structure 170.

[0025] The semiconductor device 100 can include a vertical channel transistor including the active pattern 140, the bit line structure 110 electrically connected to the active pattern 140, and the word line 152 disposed on at least one side surface of the active pattern 140. The term "vertical" is intended to refer to an extension or orientation in a direction perpendicular to an upper surface of the lower insulating layer 101 (or other substrate), which is the Z-direction.

[0026] The semiconductor device 100 can be applied to a cell array of, for example, a dynamic random access memory (DRAM), but the inventive concept is not limited thereto.

[0027] The lower insulating layer 101 can include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (SiON), or silicon carbonitride (SiCN).

[0028] The bit line structure 110 can extend on the lower insulating layer 101 in an X-direction parallel to the upper surface of the lower insulating layer 101. In an example embodiment, the bit line structure 110 can be buried in the lower insulating layer 101. The bit line structure 110 can be electrically connected to the active pattern 140. The term "connected" (or similar terms such as "contacted") as can be used herein is intended to refer to a physical and / or electrical connection between two or more elements, and can include other intervening elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. A plurality of bit line structures 110 can be provided, and the plurality of bit line structures 110 can be spaced apart from each other in a Y-direction, and can extend parallel to each other, the Y-direction being parallel to the upper surface of the lower insulating layer 101 and intersecting the X-direction.

[0029] The bit line structure 110 can include doped polysilicon, a metal, a conductive metal nitride, a metal semiconductor compound, a conductive metal oxide, graphene, a carbon nanotube, or a combination thereof. For example, at least one of the bit line structures 110 can be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO xThe bit line structure 110 can include a first conductive pattern 110a, a second conductive pattern 110b, and a third conductive pattern 110c stacked in a vertical direction on the lower insulating layer 101 in sequence, in an example embodiment. The first conductive pattern 110a can include, for example, a metal material such as titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al), the second conductive pattern 110b can include, for example, a metal nitride material such as titanium nitride (TiN) or a metal silicide material such as titanium silicide (TiSi), and the third conductive pattern 110c can include a semiconductor material such as polysilicon. The third conductive pattern 110c can be a layer doped with an impurity. However, according to an example embodiment, the materials of the layers of the bit line structure 110, the number of layers, and the cross-sectional thickness of each of the layers included in the bit line structure 110 can vary in various ways.

[0030] The semiconductor device 100 can further include a back gate dielectric layer 120 and a back gate capping layer 124.

[0031] The back gate electrode 122 can intersect the bit line structure 110. For example, the back gate electrode 122 can extend in the Y direction and can be spaced apart from each other in the X direction.

[0032] The back gate electrode 122 can serve to remove electric charges trapped in the active pattern 140. The active pattern 140 can be a floating body, and the back gate electrode 122 can be a structure for compensating for the floating active pattern 140 to prevent or minimize degradation in performance of the semiconductor device 100 caused by a floating body effect of the active pattern 140.

[0033] The back gate electrode 122 can include doped polysilicon, a metal, a conductive metal nitride, a metal semiconductor compound, a conductive metal oxide, graphene, a carbon nanotube, or a combination thereof. For example, the back gate electrode 122 can be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x x , graphene, a carbon nanotube, or a combination thereof, but the inventive concept is not limited thereto. The back gate electrode 122 can be formed of a single layer or multiple layers formed of the above-described materials.

[0034] ​The back gate dielectric layer 120 can cover side surfaces and a lower surface of the back gate electrode 122 and can extend in the Y direction. The term "cover" (or similar terms) as can be used herein is intended to broadly refer to an element, structure, or layer that is on or over another element, structure, or layer, either directly on or over the other element, structure, or layer or with one or more other intervening elements, structures, or layers between them. The back gate dielectric layer 120 can have a U-shape in a cross-sectional view. For example, the back gate dielectric layer 120 can include a horizontal portion 120a covering a lower surface of the back gate electrode 122, the horizontal portion 120a extending in a horizontal direction, and a vertical portion 120b extending upward (in the Z direction) from an upper surface of the horizontal portion 120a. The vertical portion 120b can cover the side surfaces of the back gate electrode 122, respectively.

[0035] An upper surface of the vertical portion 120b of the back gate dielectric layer 120 can be located at a higher level than a level of an upper surface of the back gate electrode 122, and a lower surface of the horizontal portion 120a of the back gate dielectric layer 120 can be located at a lower level than a level of a lower surface of the back gate electrode 122. The upper surface of the vertical portion 120b of the back gate dielectric layer 120 can be coplanar with an upper surface of the active pattern 140 with respect to an upper surface of the lower insulating layer 101 as a reference layer. The back gate dielectric layer 120 can not be in contact with the bit line structure 110 and can be spaced apart from the bit line structure 110. For example, the first insulating structure 130 can be disposed between the bit line structure 110 and the back gate dielectric layer 120. Each of the back gate dielectric layers 120 can include at least one of silicon oxide and high-k dielectric.

[0036] A back gate capping layer 124 can be disposed on the back gate electrode 122. An upper surface of the back gate capping layer 124 can be coplanar with an upper surface of the back gate dielectric layer 120 with respect to an upper surface of the lower insulating layer 101. The back gate dielectric layer 120 can cover side surfaces of the back gate capping layer 124.

[0037] The back gate capping layer 124 can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low-k dielectric, or a combination thereof.

[0038] The first insulating structure 130 can be disposed between the bit line structure 110 and the back gate dielectric layer 120. Lower and upper surfaces of the first insulating structure 130 can be in contact with an upper surface of the third conductive pattern 110c of the bit line structure 110 and a lower surface of the back gate dielectric layer 120, respectively. The first insulating structure 130 can also be disposed between the active patterns 140 adjacent to each other in the X direction. Side surfaces of the first insulating structure 130 can be in contact with the active patterns 140. In an example embodiment, the lower surface of the first insulating structure 130 can be located at a level higher than a level of the lower surface of the active pattern 140.

[0039] In an example embodiment, the first insulating structure 130 can include a first spacer L1 and a first stopper S1. The first spacer L1 can be disposed on opposite side surfaces of the first stopper S1. For example, the first spacer L1 can cover the side surfaces of the first stopper S1 and the side surfaces of the active pattern 140, respectively. The first spacer L1 and the first stopper S1 can be in contact with the horizontal portion 120a of the back gate dielectric layer 120. Upper and lower surfaces of the first spacer L1 can be coplanar with upper and lower surfaces of the first stopper S1, but the inventive concept is not limited thereto. In an example embodiment, the lower surfaces of the first spacer L1 and the first stopper S1 can be disposed at a level higher than a level of the lower surface of the active pattern 140 with respect to an upper surface of the lower insulating layer 101 as a reference layer.

[0040] The first spacer L1 can include at least one of silicon oxide, silicon oxynitride, and silicon oxycarbide. The first stopper S1 can include silicon oxide.

[0041] The active pattern 140 can be disposed on the bit line structure 110 and can extend in a vertical direction (Z direction). In a plan view, the active pattern 140 can be disposed on opposite side surfaces of the back gate electrode 122. The active patterns 140 can be spaced apart from each other in the X and Y directions. An upper surface of the active pattern 140 can be coplanar with an upper surface of the back gate capping layer 124. A lower surface of the active pattern 140 can be in contact with the third conductive pattern 110c and can be located at a level lower than a level of a lower surface of the back gate dielectric layer 120.

[0042] Each of the active patterns 140 can include a first source / drain region in contact with the bit line structure 110 and a second source / drain region connected to the contact structure 160. In an example embodiment, the first and second source / drain regions can have an N-type conductivity type.

[0043] In example embodiments, the active pattern 140 can include a single-crystal semiconductor material. The single-crystal semiconductor material can include a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor, for example, the single-crystal semiconductor includes at least one of silicon, silicon carbide, germanium, and silicon germanium.

[0044] However, according to example embodiments, the active pattern 140 can include at least one of a polycrystalline semiconductor material layer, an oxide semiconductor material layer such as indium gallium zinc oxide (IGZO), and a two-dimensional material layer such as MoS2.

[0045] The oxide semiconductor layer can be indium gallium zinc oxide (IGZO). However, example embodiments are not limited thereto. For example, the oxide semiconductor layer can include at least one of indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAGO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), ZnO, indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and indium gallium silicon oxide (InGaSiO).

[0046] The two-dimensional material layer can include at least one of a transition metal dichalcogenide (TMD) material layer, a black phosphorus material layer, and a hexagonal boron nitride (hBN) material layer, which can have semiconductor properties. For example, the 2D material layer can include at least one of BiOSe, CrI3, WSe2, MoS2, TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P(black), InSe, h-BN, GaSe, GaN, SrTiO, MXene, and Janus 2D material, which can form a 2D material.

[0047] The word lines 152 can be disposed on the bit line structure 110 and can be disposed on opposite side surfaces of the back gate electrode 122. The word lines 152 can extend in the Y direction and can be spaced apart from each other in the X direction. In a plan view, the word lines 152 can surround at least a portion of the active pattern 140, and the active pattern 140 can be disposed between the back gate dielectric layer 120 and the word lines 152. The term “surround” (or similar terms) as can be used herein is intended to broadly refer to an element, structure, or layer that extends around, or encloses, encircles, or surrounds another element, structure, or layer on all sides, but there can also be breaks or gaps. Thus, for example, a layer of material with voids or gaps therein can still “surround” another layer it encircles.

[0048] The word lines 152 can include doped polysilicon, metal, conductive metal nitride, metal semiconductor compound, conductive metal oxide, graphene, carbon nanotube, or a combination thereof. For example, the word lines 152 can be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x x , graphene, carbon nanotube, or a combination thereof, but the inventive concepts are not limited thereto. The word lines 152 can be formed of a single layer or multiple layers formed of one or more of the above-described materials.

[0049] The semiconductor device 100 can further include a gate dielectric layer 150 and a gate capping layer 154. In a plan view, the gate dielectric layer 150 can be disposed between the word lines 152 and the active pattern 140 and can have a U-shape in a cross-sectional view. For example, the gate dielectric layer 150 can include a horizontal portion 150a covering a lower surface of the word line 152, the horizontal portion 150a extending in a horizontal direction, and a vertical portion 150b extending upward from an upper surface of the horizontal portion 150a. The vertical portion 150b can cover side surfaces of the word line 152, respectively.

[0050] ​An upper surface of the vertical portion 150b of the gate dielectric layer 150 can be located at a level higher than a level of an upper surface of the word line 152, and a lower surface of the horizontal portion 150a of the gate dielectric layer 150 can be located at a level lower than a level of a lower surface of the word line 152. The upper surface of the vertical portion 150b of the gate dielectric layer 150 can be coplanar with an upper surface of the active pattern 140. The gate dielectric layer 150 can not be in contact with the bit line structure 110, and can be spaced apart from the bit line structure 110. For example, the second insulating structure 135 can be disposed between the bit line structure 110 and the gate dielectric layer 150.

[0051] In an example, each of the gate dielectric layers 150 can be a tunnel dielectric layer that does not include an information storage layer. For example, each of the gate dielectric layers 150 can include at least one of silicon oxide and a high-k dielectric. The high-k dielectric can include a metal oxide or a metal nitride oxide. For example, the high-k dielectric can be formed of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but the inventive concept is not limited thereto. Each of the gate dielectric layers 150 can be formed of a single layer or multiple layers formed of the above-described materials.

[0052] In another example, each of the gate dielectric layers 150 can include an information storage layer and a dielectric layer. For example, each of the gate dielectric layers 150 can have a polarization property according to an electric field, and can include a ferroelectric layer that can have a residual polarization caused by a dipole even in the absence of an external electric field. Such a polarization state in the ferroelectric layer can be used to record data. Accordingly, each of the gate dielectric layers 150 can include a ferroelectric layer that can be referred to as an information storage layer. The ferroelectric layer that can be an information storage layer can include a Hf-based compound, a Zr-based compound, and / or a Hf-Zr-based compound. For example, the Hf-based compound can be a HfO-based ferroelectric material, the Zr-based compound can include a ZrO-based ferroelectric material, and the Hf-Zr-based compound can include a hafnium zirconium oxide (HZO)-based ferroelectric material. The ferroelectric layer that can be an information storage layer can include a ferroelectric material doped with an impurity (e.g., at least one of C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and Sr). For example, the ferroelectric layer that can be an information storage layer can be a material obtained by doping at least one of HfO2, ZrO2, and HfZrO with at least one of C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and Sr.

[0053] In the gate dielectric layer 150, the information storage layer is not limited to the above-described material types, and can include a material capable of storing information.

[0054] The gate capping layer 154 can extend in the Y direction between the adjacent word lines 152 and can be spaced apart from each other in the X direction. The gate capping layer 154 can be disposed on the word lines 152 and can extend to the spaces between the word lines 152. For example, the gate capping layer 154 can cover the side surfaces and the upper surfaces of the word lines 152. The gate capping layer 154 can also be in contact with the upper surfaces of the horizontal portions 150a of the gate dielectric layer 150.

[0055] The gate capping layer 154 can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-k dielectric, or a combination thereof. The gate capping layer 154 can include a single layer or multiple layers.

[0056] The second insulating structure 135 can be disposed between the bit line structure 110 and the gate dielectric layer 150. The lower and upper surfaces of the second insulating structure 135 can be in contact with the upper surface of the third conductive pattern 110c of the bit line structure 110 and the lower surface of the gate dielectric layer 150, respectively. The second insulating structure 135 can also be disposed between the active patterns 140 adjacent to each other in the X direction. The side surfaces of the second insulating structure 135 can be in contact with the active patterns 140. In an example embodiment, the lower surface of the second insulating structure 135 can be located at a level higher than that of the lower surface of the active pattern 140.

[0057] In an example embodiment, the second insulating structure 135 can include a second liner L2 and a second stopper S2. The second liner L2 can be disposed on the opposite side surfaces of the second stopper S2. For example, the second liner L2 can cover the side surfaces of the second stopper S2 and the side surfaces of the active pattern 140, respectively. The second liner L2 and the second stopper S2 can be in contact with the horizontal portions 150a of the gate dielectric layer 150. The upper and lower surfaces of the second liner L2 can be coplanar with the upper and lower surfaces of the second stopper S2, respectively, but the inventive concept is not limited thereto. In an example embodiment, the lower surfaces of the second liner L2 and the second stopper S2 can be disposed at a level higher than that of the lower surface of the active pattern 140. It is shown that the upper and lower surfaces of the second insulating structure 135 are located at the same levels as those of the upper and lower surfaces of the first insulating structure 130, but the present invention is not limited thereto. In some example embodiments, the upper surface of the second insulating structure 135 can be disposed at a level different from that of the upper surface of the first insulating structure 130, or the lower surface of the second insulating structure 135 can be disposed at a level different from that of the lower surface of the first insulating structure 130, with respect to the upper surface of the lower insulating layer 101.

[0058] The second liner L2 can include at least one of silicon oxide, silicon oxynitride, and silicon oxycarbide. The second stopper S2 can include silicon oxide.

[0059] In an example embodiment, the active pattern 140 can include a first portion 140a and a second portion 140b on the first portion 140a. The first portion 140a can be disposed between the first insulating structure 130 and the second insulating structure 135, and side surfaces of the first portion 140a can be in contact with the first insulating structure 130 and the second insulating structure 135. For example, a first side surface of the first portion 140a can be in contact with a first liner L1 of the first insulating structure 130, and a second side surface of the first portion 140a opposite the first side surface can be in contact with a second liner L2 of the second insulating structure 135.

[0060] The second portion 140b of the active pattern 140 can be disposed between the back gate dielectric layer 120 and the gate dielectric layer 150, and side surfaces of the second portion 140b can be in contact with the back gate dielectric layer 120 and the gate dielectric layer 150. In an example embodiment, when lower surfaces of the first insulating structure 130 and the second insulating structure 135 are disposed at a level higher than a level of a lower surface of the active pattern 140, the active pattern 140 can further include a third portion 140c disposed below the first portion 140a with respect to an upper surface of the lower insulating layer 101. Side surfaces and a lower surface of the third portion 140c can be in contact with the third conductive pattern 110c of the bit line structure 110.

[0061] The contact structure 160 can be disposed on the active pattern 140 and can be electrically connected to the active pattern 140. The contact structure 160 can electrically connect the active pattern 140 and the information storage structure 170 to each other. A lower surface of the contact structure 160 can be in contact with the back gate dielectric layer 120, the active pattern 140, and the gate dielectric layer 150.

[0062] The contact structure 160 can include a conductive material, for example, doped single crystalline silicon, doped polycrystalline silicon, metal, conductive metal nitride, metal semiconductor compound, conductive metal oxide, conductive graphene, carbon nanotube, or a combination thereof. In an example embodiment, the contact structure 160 can include first to fourth contact layers 160a, 160b, 160c, and 160d stacked in a vertical direction in sequence. For example, the first contact layer 160a can include undoped polycrystalline silicon, the second contact layer 160b can include doped polycrystalline silicon, the third contact layer 160c can include silicide material, and the fourth contact layer 160d can include metal. However, according to an example embodiment, the number of layers of the contact structure 160 and the type of material of the layers can vary in various ways.

[0063] The semiconductor device 100 can also include insulating patterns 165 disposed between the contact structures 160. Each of the insulating patterns 165 can vertically extend in contact with the insulating structures 160 or the back gate capping layer 124. The insulating patterns 165 can spatially separate the contact structures 160 from each other and can electrically insulate the contact structures 160 from each other.

[0064] The information storage structure 170 can include a first electrode 172 electrically connected to the contact structure 160, a second electrode 176 covering the first electrode 172, and a dielectric layer 174 between the first electrode 172 and the second electrode 176.

[0065] In an example embodiment, the information storage structure 170 can be a capacitor storing information in a DRAM. For example, the dielectric layer 174 of the information storage structure 170 can be a capacitor dielectric layer of a DRAM, and the dielectric layer 174 can include a high-k dielectric, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0066] According to an example embodiment, the information storage structure 170 can be a structure storing DRAM and other memory information. For example, the dielectric layer 174 of the information storage structure 170 can be a capacitor dielectric layer of a ferroelectric random access memory (FeRAM). In this case, the dielectric layer 174 can be a ferroelectric layer capable of recording data using a polarization state. In another embodiment, the dielectric layer 174 can also include a lower dielectric layer including at least one of silicon oxide and a high-k dielectric, and a ferroelectric layer disposed on the lower dielectric layer.

[0067] Figures 4 to 9 is a schematic vertical cross-sectional view of a semiconductor device according to an example embodiment.

[0068] Figures 4 to 9 may correspond to a partial enlarged view of the semiconductor device 100 shown in Figure 3

[0069] Referring to Figure 4 , the semiconductor device 200 can include a first insulating structure 130 disposed between the back gate dielectric layer 120 and the bit line structure 110, and a second insulating structure 235 disposed between the gate dielectric layer 150 and the bit line structure 110. In an example embodiment, the second insulating structure 235 can include a second stopper S2, a second liner L2, and a third liner L3. The third liner L3 can be disposed between the second stopper S2 and the second liner L2, and can be in contact with the gate dielectric layer 150 and the bit line structure 110. The third liner L3 can include a material different from that of the second liner L2. For example, the second liner L2 can include at least one of silicon oxide, silicon oxynitride, and silicon oxycarbide. The third liner L3 can include silicon nitride.​

[0070] Referring to Figure 5 , the semiconductor device 300 can include the first insulating structure 130 disposed between the back gate dielectric layer 120 and the bit line structure 110, and the second insulating structure 235 disposed between the gate dielectric layer 350 and the bit line structure 110. In an example embodiment, an upper end of the second stopper S2 of the second insulating structure 235 can be disposed at a higher level than upper ends of the second and third spacers L2 and L3 with respect to an upper surface of the bit line structure 110 as a reference layer. The horizontal portion 150a of the gate dielectric layer 350 can include a recess such that the upper end of the second stopper S2 protrudes upward in a vertical direction toward the recess of the horizontal portion 150a of the gate dielectric layer 350.

[0071] Referring to Figure 6 , the semiconductor device 400 can include the first insulating structure 130 disposed between the back gate dielectric layer 120 and the bit line structure 110, and the second insulating structure 235 disposed between the gate dielectric layer 450 and the bit line structure 110. In an example embodiment, a top of the second stopper S2 of the second insulating structure 235 can be disposed at a lower level than tops of the second and third spacers L2 and L3 with respect to an upper surface of the bit line structure 110. The horizontal portion 150a of the gate dielectric layer 450 can include a protrusion portion protruding vertically downward toward the second stopper S2.

[0072] Figures 4 to 6 Example embodiments of the semiconductor device 100 can also be applied to example embodiments of the semiconductor device 200 described below. Figures 7 to 9

[0073] Referring to Figure 7 , the semiconductor device 500 can include the first insulating structure 130 disposed between the back gate dielectric layer 120 and the bit line structure 110, and the second insulating structure 535 disposed between the gate dielectric layer 150 and the bit line structure 110. In an example embodiment, unlike example embodiments of the semiconductor device 200, Figure 3 , a second spacer L2 can be omitted from the second insulating structure 535. For example, the second insulating structure 535 can include the second stopper S2, and the second stopper S2 can be in contact with a side surface of the active pattern 140.

[0074] ​The active pattern 140 can include a first portion 140a, a second portion 140b on the first portion 140a, and a third portion 140c below the first portion 140a. In an example embodiment, the first portion 140a of the active pattern 140 can include a first side surface facing the first insulating structure 130, and a second side surface opposite the first side surface, the second side surface facing the second insulating structure 535. The first side surface of the first portion 140a can be in contact with the first liner L1, and the second side surface of the first portion 140a can be in contact with the second stopper S2.

[0075] Referring to Figure 8 , the semiconductor device 600 can include a first insulating structure 630 disposed between the back gate dielectric layer 120 and the bit line structure 110, and a second insulating structure 135 disposed between the gate dielectric layer 150 and the bit line structure 110. In an example embodiment, unlike the example embodiment of Figure 3 , the first liner L1 can be omitted from the first insulating structure 630. For example, the first insulating structure 630 can include the first stopper S1, and the first stopper S1 can be in contact with a side surface of the active pattern 140.

[0076] The active pattern 140 can include a first portion 140a, a second portion 140b, and a third portion 140c. In an example embodiment, the first portion 140a of the active pattern 140 can include a first side surface and a second side surface facing the first insulating structure 630 and the second insulating structure 135, respectively. The first side surface of the first portion 140a can be in contact with the first stopper S1, and the second side surface of the first portion 140a can be in contact with the second liner L2.

[0077] Referring to Figure 9 , the semiconductor device 700 can include a first insulating structure 730 disposed between the back gate dielectric layer 120 and the bit line structure 110, and a second insulating structure 735 disposed between the gate dielectric layer 150 and the bit line structure 110. In an example embodiment, unlike the example embodiment of Figure 3 , the first liner L1 can be omitted from the first insulating structure 730, and the second liner L2 can be omitted from the second insulating structure 735. For example, the first insulating structure 730 can include the first stopper S1, and the first stopper S1 can be in contact with a side surface of the active pattern 140. The second insulating structure 735 can include the second stopper S2, and the second stopper S2 can be in contact with a side surface of the active pattern 140.

[0078] The active pattern 140 can include a first portion 140a, a second portion 140b, and a third portion 140c. In an example embodiment, the first portion 140a of the active pattern 140 can include first and second side surfaces facing the first and second insulating structures 730 and 735, respectively. The first side surface of the first portion 140a can be in contact with the first stopper S1, and the second side surface of the first portion 140a can be in contact with the second stopper S2.

[0079] Figure 10 is a flowchart of a method for manufacturing a semiconductor device according to an example embodiment.

[0080] Referring to Figure 10 A method of manufacturing a semiconductor device according to an example embodiment can include forming a back gate trench in a substrate (S100), forming a first stopper in the back gate trench (S110), forming a back gate electrode on the first stopper (S120), forming a word line trench in the substrate (S130), forming a second stopper in the word line trench (S140), forming a word line on the second stopper (S150), forming a contact structure and an information storage structure on the word line (S160), removing the substrate (S170), performing an etching process to expose an active pattern (S180), and forming a bit line structure on the active pattern (S190). The term "expose" (or "exposed" or similar terms) can be used herein to describe a relationship between elements and / or to describe a relationship with reference to intermediate processes in manufacturing an integrated circuit device, but it can not be required that a particular element be exposed in the completed device. Likewise, the term "not expose" can be used to describe a relationship between elements and / or to describe a relationship with reference to intermediate processes in manufacturing an integrated circuit device, but it can not be required that a particular element not be exposed in the completed device.

[0081] In an example embodiment, the method can further include, after forming the back gate trench in the substrate (S100) and before forming the first stopper in the back gate trench (S110), forming a first liner on an inner wall of the back gate trench (S102); and forming a first lower trench in the substrate (S104). In an example embodiment, the method can further include, after forming the word line trench in the substrate (S130) and before forming the second stopper in the word line trench (S140), forming a second liner on an inner wall of the word line trench (S132); and forming a second lower trench in the substrate (S134).

[0082] Figures 11 to 25 is a schematic vertical cross-sectional view of a sequence of intermediate processes in a method of manufacturing a semiconductor device according to an example embodiment.

[0083] Referring to Figure 11A first mask layer M1 and a second mask layer M2 can be formed on the substrate 10. The substrate 10 can include single-crystal silicon. In an example embodiment, the substrate 10 can be a bulk silicon substrate. The first mask layer M1 and the second mask layer M2 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the first mask layer M1 can include silicon nitride, and the second mask layer M2 can include silicon oxide.

[0084] Referring to Figure 12 A back gate trench T1a can be formed in the substrate 10 by anisotropically etching the substrate 10 (S100). The back gate trench T1a can vertically pass through the first mask layer M1 and the second mask layer M2, and can expose the substrate 10. The back gate trench T1a can extend in the Y direction, and can be spaced apart from each other in the X direction.

[0085] Referring to Figure 13 A first liner L1 can be formed on inner walls of the back gate trench T1a (S102), and a first lower trench T1b can be formed in the substrate 10 (S104). First, the first liner L1 can be conformally formed along the inner walls of the back gate trench T1a. The first liner L1 can cover the inner walls of the back gate trench T1a, a side surface of the first mask layer M1, and a side surface and an upper surface of the second mask layer M2.

[0086] The substrate 10 can be exposed in the back gate trench T1a by anisotropically etching the first liner L1. The exposed substrate 10 can be etched to form the first lower trench T1b. The exposed substrate 10 can be etched by a wet etching to form the first lower trench T1b. In a cross-sectional view, the first lower trench T1b can have a circular or elliptical shape. The first lower trench T1b can be formed under the back gate trench T1a, and can be connected to the back gate trench T1a. The first lower trench T1b can extend in the Y direction along the back gate trench T1a. When the first lower trench T1b is formed, a portion of the substrate 10 covered by the first liner L1 can not be etched.

[0087] Referring to Figure 14, a first stopper S1 may be formed in the back gate trench T1a (S110). The first stopper S1 may fill the lower portion of the back gate trench T1a. As may be used herein, the term "fill" (or similar terms) is intended to broadly refer to completely filling a defined space (e.g., the lower portion of the back gate trench T1a) or partially filling the defined space; that is, the defined space does not need to be completely filled, but may, for example, be partially filled or have gaps or other spaces throughout the space. In example embodiments, the first stopper S1 may also fill the first lower trench T1b. The first stopper S1 may extend in the Y direction along the back gate trench T1a and the first lower trench T1b. In example embodiments, a stopper material layer may be formed to fill the back gate trench T1a and the first lower trench T1b and cover the second mask layer M2, and the stopper material layer may then be etched back to form the first stopper S1. In example embodiments, the first stopper S1 may be formed by stacking a stopper material layer from a lower surface of the first lower trench T1b without performing an etch-back process.

[0088] After forming the first stopper S1, the first liner L1 may be etched back to expose the substrate 10 through the back gate trench T1a. The upper surface of the etched-back first liner L1 and the upper surface of the first stopper S1 are shown to be coplanar with each other, but the present inventive concept is not limited thereto. In some example embodiments, the upper surface of the first liner L1 and the upper surface of the first stopper S1 may be disposed at different levels. The second mask layer M2 may be removed.

[0089] Reference Figure 15 A back gate electrode 122 may be formed on the first stopper S1 (S120). First, a dielectric material layer 120p may be conformally formed in the upper portion of the back gate trench T1a above the lower portion. The dielectric material layer 120p may cover the inner wall of the back gate trench T1a, the upper surface of the first liner L1, and the upper surface of the first stopper S1.

[0090] After forming a conductive material on the dielectric material layer 120p, the conductive material may be etched back to form a back-gate electrode 122. An insulating material may be formed on the back-gate electrode 122 to fill the inner wall of the dielectric material layer 120p and cover the first mask layer M1, and then the insulating material may be etched back to form an initial capping layer 124p. In example embodiments, the back-gate electrode 122 may include a metal nitride such as TiN or polysilicon.

[0091] Reference Figure 16The upper surface of the substrate 10 can be exposed by removing the first mask layer M1. For example, the first mask layer M1 can be selectively removed using a wet etching process. The sacrificial material layer SL can be conformally formed to cover the upper surface of the substrate 10, the side surface of the dielectric material layer 120p, and the upper surface of the initial cap layer 124p. The sacrificial material layer SL can include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0092] Referring to Figure 17 The word line trench T2a can be formed in the substrate 10 (S130). The word line trench T2a can be formed by anisotropically etching the sacrificial material layer SL and the substrate 10. The sacrificial material layer SL can be etched to form a sacrificial spacer SP on the side surface of the dielectric material layer 120p. The word line trench T2a can expose the substrate 10. The back gate trench T1a can extend in the Y direction and can be spaced apart from each other in the X direction.

[0093] The initial active pattern 140p can be formed using an anisotropic etching process. The initial active pattern 140p can extend in a vertical direction and can be defined by the back gate trench T1a and the word line trench T2a. For example, the back gate trench T1a and the word line trench T2a can define the side surface of the initial active pattern 140p. The upper surface of the initial active pattern 140p can be covered with the sacrificial spacer SP.

[0094] Referring to Figure 18 The second liner L2 can be formed on the inner wall of the word line trench T2a (S132). The second liner L2 can be conformally formed along the word line trench T2a, the sacrificial spacer SP, the dielectric material layer 120p, and the initial cap layer 124p.

[0095] Referring to Figure 19 The second lower trench T2b can be formed in the substrate 10 (S134). The substrate 10 can be exposed in the word line trench T2a by anisotropically etching the second liner L2. The exposed substrate 10 can be etched to form the second lower trench T2b. The exposed substrate 10 can be etched by a wet etching to form the second lower trench T2b. In a cross-sectional view, the second lower trench T2b can have a circular or elliptical shape and can expose a portion of the first stopper S1. The second lower trench T2b can be formed below the word line trench T2a and can be connected to the word line trench T2a. The second lower trench T2b can extend in the Y direction along the word line trench T2a. When the second lower trench T2b is formed, the initial active pattern 140p covered by the second liner L2 can not be etched.

[0096] Referring to Figure 20A second stopper S2 can be formed in the word line trench T2a (S140). The second stopper S2 can fill a lower portion of the word line trench T2a. In an example embodiment, the second stopper S2 can also fill the second lower trench T2b. The second stopper S2 can extend in the Y direction along the word line trench T2a and the second lower trench T2b. In an example embodiment, a stopper material layer can be formed to fill the word line trench T2a and the second lower trench T2b and cover the sacrificial spacer SP, the dielectric material layer 120p, and the initial cap layer 124p, and then the stopper material layer can be etched back to form the second stopper S2. In an example embodiment, the second stopper S2 can be formed by stacking the stopper material layer from a lower surface of the second lower trench T2b without performing an etch back process.

[0097] The portion of the first stopper S1 filling the first lower trench T1b can be alternately arranged with the portion of the second stopper S2 filling the second lower trench T2b in the X direction. In an example embodiment, the second stopper S2 can include the same material as the material of the first stopper S1. In an example embodiment, the second stopper S2 can include a different material from the material of the first stopper S1.

[0098] After the second stopper S2 is formed, the second liner L2 can be etched back to expose the initial active pattern 140p through the word line trench T2a, as shown in Figure 21 The upper surface of the etched-back second liner L2 and the upper surface of the second stopper S2 can be coplanar with each other, as shown in Figure 21 However, the inventive concept is not limited thereto. In some example embodiments, the upper surface of the second liner L2 and the upper surface of the second stopper S2 can be arranged at different levels.

[0099] The initial active pattern 140p can be spaced apart from the substrate 10. For example, the first stopper S1 and the second stopper S2 can be arranged between the initial active pattern 140p and the substrate 10, and a lower surface of the initial active pattern 140p can be joined to the first stopper S1 and the second stopper S2.

[0100] Referring to Figure 21 A word line 152 can be formed on the second stopper S2 (S150). First, a gate dielectric layer 150 can be conformally formed in an upper portion of the word line trench T2a (see Figure 20 ) located above the lower portion. The gate dielectric layer 150 can cover an inner wall of the word line trench T2a, an upper surface of the second liner L2, and an upper surface of the second stopper S2.

[0101] After forming a conductive material on the gate dielectric layer 150, word lines 152 may be formed by etching back the conductive material. An insulating material may be formed on the word lines 152 to fill the inner wall of the gate dielectric layer 150 and cover the dielectric material layer 120p and the initial capping layer 124p, and then the insulating material may be etched back to form the gate capping layer 154. In an example embodiment, the word lines 152 may be formed by forming a first insulating material on the conductive material and etching the conductive material and the first insulating material simultaneously. The gate capping layer 154 may be formed by depositing a second insulating material on the first insulating material.

[0102] After forming the gate capping layer 154, the sacrificial spacers SP may be removed. Portions of the dielectric material layer 120p and the preliminary capping layer 124p located on the preliminary active pattern 140p may be removed to form the back-gate dielectric layer 120 and the back-gate capping layer 124. The upper surfaces of the back-gate dielectric layer 120 and the back-gate capping layer 124 may be coplanar with the upper surfaces of the preliminary active pattern 140p and the gate capping layer 154 (i.e., located at the same vertical level as the upper surfaces of the preliminary active pattern 140p and the gate capping layer 154 relative to the lower surface of the substrate 10).

[0103] In example embodiments, the preliminary active patterns 140p may be patterned in the X direction before forming the word lines 152. Figure 1 As shown in FIG, the patterned preliminary active patterns 140 p may be spaced apart from each other in the X and Y directions.

[0104] Reference Figure 22 , a contact structure 160 and an information storage structure 170 may be formed on the word line 152 (S160). The contact structure 160 may be formed by stacking contact material layers and then patterning the contact material layers. The contact structure 160 may include a first contact layer 160a, a second contact layer 160b, a third contact layer 160c, and a fourth contact layer 160d sequentially stacked in a vertical direction. The contact structure 160 may be electrically connected to the initial active pattern 140p.

[0105] Insulation patterns 165 may be formed between the patterned contact structures 160. The insulation patterns 165 may electrically separate the contact structures 160 from each other.

[0106] An information storage structure 170 including a first electrode 172, a dielectric layer 174, and a second electrode 176 may be formed on the contact structure 160. The first electrode 172 may make contact with the fourth contact layer 160d of the contact structure 160.

[0107] Reference Figure 23 , which can make Figure 22The resulting structure is inverted so that the information storage structure 170 is located under the substrate 10, and a planarization process can be used to remove the substrate 10 (S170). For example, a chemical mechanical polishing (CMP) process can be used to remove the substrate 10. The first stopper S1 and the second stopper S2 can be used as CMP stoppers in the CMP process.

[0108] When the first stopper S1 and the second stopper S2 are not present, the metal material of the back gate electrode 122 and the word line 152 can be polished at the same time as the insulating material such as the back gate dielectric layer 120, the gate dielectric layer 150, and the gate capping layer 154. In this case, a dent or an erosion can occur on the surface being polished. However, according to example embodiments of the inventive concept, the CMP process can be performed in a state in which the first stopper S1 and the second stopper S2 (CMP stoppers) are provided, thereby preventing the dent or the erosion. Accordingly, defects in the semiconductor device can be reduced. In addition, as Figure 11 As shown in FIG. 1, the substrate 10 can be a bulk silicon substrate. Rather than a silicon-on-insulator (SOI) substrate, the cost required to manufacture the semiconductor device is reduced as compared to the case in which the SOI substrate is used.

[0109] Referring to FIG. 1, Figure 24 An etching process can be performed to expose the active pattern 140 (S180). The etching process can include at least one of an anisotropic etching process, an isotropic etching process, and a CMP process. The initial active pattern 140p can be etched using the etching process to form the active pattern 140, and an upper surface of the active pattern 140 can be exposed.

[0110] The first pad L1, the first stopper S1, the second pad L2, and the second stopper S2 can be partially etched using the etching process, and upper surfaces of the first pad L1, the first stopper S1, the second pad L2, and the second stopper S2 can be coplanar with the upper surface of the active pattern 140. The etched first pad L1 and the first stopper S1 can form the first insulating structure 130, and the etched second pad L2 and the second stopper S2 can form the second insulating structure 135.

[0111] Referring to FIG. 1, Figure 25 A bit line structure 110 can be formed on the active pattern 140 (S190) to manufacture the semiconductor device 100. The bit line structure 110 can include a third conductive pattern 110c, a second conductive pattern 110b, and a first conductive pattern 110a sequentially stacked on the active pattern 140.

[0112] In example embodiments, a cleaning process may be performed before forming the bit line structure 110. The cleaning process may remove an oxide film formed on the active pattern 140. The first pad L1, the first stopper S1, the second pad L2, and the second stopper S2 may be partially etched using the cleaning process, and side surfaces of the active pattern 140 may be exposed.

[0113] In example embodiments, a process of forming a peripheral circuit structure on the lower insulating layer 101 may also be performed. The peripheral circuit structure may include peripheral circuit devices, at least one of which may be electrically connected to the bit line structure 110, and at least one of which may be electrically connected to the information storage structure 170.

[0114] In an example embodiment, Figure 10 In the method for manufacturing a semiconductor device shown in , forming the first liner L1 on the inner wall of the back gate trench T1a (S102) and forming the first lower trench T1b in the substrate 10 (S104) can be omitted. In this case, as shown in FIG. Figure 8 As shown in , the first insulating structure 630 may not include the first liner L1 , and the first stopper S1 may be in contact with the active pattern 140 .

[0115] In an example embodiment, Figure 10 In the method for manufacturing a semiconductor device shown in , forming the second liner L2 on the inner wall of the word line trench T2a (S132) and forming the second lower trench T2b in the substrate 10 (S134) can be omitted. In this case, as Figure 7 As shown in , the second insulating structure 535 may not include the second liner L2 , and the second stopper S2 may be in contact with the active pattern 140 .

[0116] Figure 26 is a flowchart of a method of manufacturing a semiconductor device according to example embodiments.

[0117] Reference Figure 26 , and reference Figure 10 Compared to the method of manufacturing a semiconductor device described above, the method of manufacturing a semiconductor device according to example embodiments may further include: after forming a second liner L2 on an inner wall of the word line trench T2a (S132) and before forming a second lower trench T2b in the substrate 10 (S134), forming a third liner L3 on the second liner L2 (S133).

[0118] Figures 27 to 32 are schematic vertical cross-sectional views of sequential intermediate processes in a method of fabricating a semiconductor device according to example embodiments. Figures 27 to 32 It shows Figure 26 Schematic diagram of a method of manufacturing a semiconductor device shown in .

[0119] Referring to Figure 27 After the process of forming the second liner L2 is performed, a third liner L3 can be formed on the second liner L2. The third liner L3 can be disposed conformally along a surface of the second liner L2. The third liner L3 can include a material different from a material of the second liner L2. Figure 18 Referring to

[0120] The second lower trench T2b can be formed in the substrate 10 (S134). The substrate 10 can be exposed in the word line trench T2a by anisotropically etching the second liner L2 and the third liner L3. The exposed substrate 10 can be etched to form the second lower trench T2b. The second lower trench T2b can be formed by wet etching the exposed substrate 10. When the second lower trench T2b is formed, the initial active pattern 140p covered by the second liner L2 can not be etched. Figure 28 Referring to

[0121] The second stopper S2 can be formed in the word line trench T2a (S140). The second stopper S2 can fill a lower portion of the word line trench T2a and the second lower trench T2b. In an example embodiment, a stopper material layer can be formed to fill the word line trench T2a and the second lower trench T2b and cover the sacrificial spacer SP, the dielectric material layer 120p, and the initial cap layer 124p, and then the stopper material layer can be etched back to form the second stopper S2. When the stopper material layer is etched back, the third liner L3 can protect the second liner L2 and the initial active pattern 140p from being etched. Figure 29 Referring to

[0122] After the second stopper S2 is formed, the second liner L2 and the third liner L3 can be etched back to expose the initial active pattern 140p through the word line trench T2a. First, the third liner L3 can be etched back using a wet etching process, and the second liner L2 can be exposed. Then, the second liner L2 can be etched back using a wet etching process, and the initial active pattern 140p can be exposed. Figure 30 It is shown that the upper surface of the etched-back second liner L2 and the upper surface of the etched-back third liner L3 are coplanar with the upper surface of the second stopper S2, but the present disclosure is not limited thereto. As

[0123] As shown in FIGS. 1A and 1B, the upper surface of the second liner L2, the upper surface of the third liner L3, and the upper surface of the second stopper S2 can be disposed at different levels with respect to the upper surface of the substrate 10. Figure 5 Figure 6 Referring to

[0124] Referring to Figure 31 ​A word line 152 can be formed on the second stopper S2 (S150). In addition, a gate dielectric layer 150 and a gate capping layer 154 can be formed.

[0125] Referring to Figure 32 , the process of operations S120, S130, and S140 described with reference to Figures 22 to 25 , the process of operations S160 to S190 described with reference to Figure 4 , the process of operations S200 to S210 described with reference to Figure 32 , and the process of operations S220 to S230 described with reference to

[0126] Figure 33 is a flowchart of a method of manufacturing a semiconductor device according to an example embodiment.

[0127] Referring to Figure 33 , the process of operations S120, S130, and S140 described with reference to Figure 10 , the process of operations S200 to S210 described with reference to , and the process of operations S220 to S230 described with reference to

[0128] Figures 34 to 38 is a schematic vertical sectional view of a sequence intermediate process in the method of manufacturing a semiconductor device according to an example embodiment. Specifically, Figures 34 to 38 depicts an intermediate process in the method of manufacturing a semiconductor device shown in the flowchart of Figure 33

[0129] Referring to Figure 34 , a back gate trench T1a can be formed in the substrate 10 by anisotropically etching the substrate 10 (S100), and a first stopper S1 can be formed in the back gate trench T1a (S110). The first stopper S1 can fill a lower portion of the back gate trench T1a. Unlike Figure 14 , a first lower trench T1b can not be formed below the back gate trench T1a.

[0130] Referring to Figure 35 , the process of operations S120, S130, and S140 described with reference to Figures 15 to 17 , Figure 19 , and Figure 20 , the process of operations S200 to S210 described with reference to Figure 20Differently, the second lower trench T2b can not be formed under the word line trench T2a. The initial active pattern 140p can be disposed on the substrate 10 and can be spaced apart from each other in the X direction.

[0131] Referring to Figure 36 , the reference Figure 21 and Figure 22 described operations S150 and S160 of the process. The word line 152 can be formed on the second stopper S2, and the contact structure 160 and the information storage structure 170 can be formed on the word line 152.

[0132] Referring to Figure 37 , the resulting structure of Figure 36 is inverted so that the information storage structure 170 is located under the substrate 10, and the substrate 10 can be removed using a planarization process (S170). For example, the substrate 10 can be removed using a CMP process. The first stopper S1 and the second stopper S2 can be used as a CMP stopper in the CMP process.

[0133] Referring to Figure 38 , an etching process can be performed to expose the active pattern 140 (S180), and a bit line structure 110 can be formed on the active pattern 140 (S190) to manufacture the semiconductor device 700. Figure 9 may correspond to the partial enlarged view of Figure 38 .

[0134] According to example embodiments of the inventive concept, the first stopper and the second stopper can be disposed under the back gate electrode and the word line, thereby preventing dishing or erosion during the CMP process. In addition, in the method of manufacturing a semiconductor device according to the present disclosure, an SOI substrate can not be used, thereby reducing the cost required to manufacture the semiconductor device.

[0135] Although example embodiments have been shown and described above, it will be clear to those skilled in the art that modifications and changes can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device comprising: a bit line structure; a back gate electrode and a word line over the bit line structure; an active pattern between the back gate electrode and the word line over the bit line structure, the active pattern extending in a vertical direction perpendicular to a lower surface of the semiconductor device; a back gate dielectric layer between the back gate electrode and the active pattern, the back gate dielectric layer being on a side surface and a lower surface of the back gate electrode; and a first insulating structure between the back gate dielectric layer and the bit line structure, wherein the first insulating structure includes a first stopper in contact with the back gate dielectric layer and the bit line structure, and the back gate dielectric layer is spaced apart from the bit line structure in the vertical direction by the first stopper.

2. The semiconductor device according to claim 1, wherein the first insulating structure further includes a first liner between the first stopper and the active pattern, and the first liner is in contact with a side surface of the active pattern. the first stopper is in contact with a side surface of the active pattern.

3. The semiconductor device according to claim 1, wherein the back gate dielectric layer includes a horizontal portion on the lower surface of the back gate electrode and a vertical portion extending upward from the horizontal portion, the vertical portion being on the side surface of the back gate electrode.

4. The semiconductor device according to claim 1, wherein the horizontal portion of the back gate dielectric layer is in contact with an upper surface of the first insulating structure.

5. The semiconductor device according to claim 4, wherein the back gate dielectric layer has a U-shape in a cross-sectional view.

6. The semiconductor device according to claim 1, wherein 7. The semiconductor device according to claim 1, further comprising: a gate dielectric layer between the word line and the active pattern, the gate dielectric layer being on a side surface and a lower surface of the word line, and a second insulating structure between the gate dielectric layer and the bit line structure, the second insulating structure including a second stopper. the gate dielectric layer is spaced apart from the bit line structure in the vertical direction.

8. The semiconductor device according to claim 7, wherein 9. The semiconductor device according to claim 7, wherein the second insulating structure further includes a second liner between the second stopper and the active pattern, and the second liner is in contact with a side surface of the active pattern. the second insulating structure further includes a third liner between the second liner and the second stopper.

10. The semiconductor device according to claim 9, wherein the third liner includes a material different from a material of the second liner.

11. The semiconductor device according to claim 10, wherein 12. The semiconductor device according to claim 9, wherein the gate dielectric layer includes a horizontal portion on a lower surface of the word line, and the horizontal portion of the gate dielectric layer includes a protruding portion extending toward the second liner in the vertical direction.

13. The semiconductor device according to claim 7, wherein the gate dielectric layer includes a horizontal portion on a lower surface of the word line, and the horizontal portion of the gate dielectric layer includes a protruding portion extending toward the second stopper in the vertical direction. the second stopper is in contact with a side surface of the active pattern.

14. The semiconductor device according to claim 7, wherein 15. A semiconductor device comprising: a bit line structure; a back gate electrode and a word line over the bit line structure; ​ an active pattern located between the back gate electrode and the word line on the bit line structure, the active pattern extending in a vertical direction perpendicular to a lower surface of the semiconductor device; a back-gate dielectric layer, located between the back-gate electrode and the active pattern, the back-gate dielectric layer being located on the side surface and the lower surface of the back-gate electrode; a gate dielectric layer located between the word line and the active pattern, the gate dielectric layer being located on side surfaces and a lower surface of the word line; a first insulating structure located between the back gate dielectric layer and the bit line structure; as well as a second insulating structure located between the gate dielectric layer and the bit line structure, The active pattern includes a first portion and a second portion on the first portion. A first portion of the active pattern contacts the first insulating structure and the second insulating structure, and A second portion of the active pattern contacts the back gate dielectric layer and the gate dielectric layer.

16. The semiconductor device according to claim 15, wherein The active pattern further includes a third portion located below the second portion, and A lower surface and a side surface of the third portion of the active pattern contact the bit line structure.

17. The semiconductor device according to claim 15, wherein The first insulating structure includes a first stopper and a first liner on opposite sides of the first stopper, and A second portion of the active pattern contacts one of the first pads.

18. The semiconductor device according to claim 15, wherein The second insulating structure includes a second stopper and a second liner on an opposite side of the second stopper, and The second portion of the active pattern contacts one of the second pads.

19. The semiconductor device according to claim 18, wherein The second insulating structure further includes a third gasket located between the second stopper and the second gasket, and The second liner includes a material different from a material of the third liner.

20. A semiconductor device comprising: bit line structure; a back gate electrode and a word line on the bit line structure; an active pattern located between the back gate electrode and the word line on the bit line structure, the active pattern extending in a vertical direction perpendicular to a lower surface of the semiconductor device; a contact structure located on the active pattern; an information storage structure located on the contact structure; a back-gate dielectric layer, located between the back-gate electrode and the active pattern, the back-gate dielectric layer being located on the side surface and the lower surface of the back-gate electrode, and the back-gate dielectric layer being in contact with the side surface of the active pattern; a gate dielectric layer located between the word line and the active pattern, the gate dielectric layer being located on side surfaces and a lower surface of the word line, and the gate dielectric layer being in contact with side surfaces of the active pattern; a first insulating structure in contact with a lower surface of the back gate dielectric layer and an upper surface of the bit line structure; as well as a second insulating structure in contact with a lower surface of the gate dielectric layer and an upper surface of the bit line structure, The first insulating structure includes a first stopper in contact with the back gate dielectric layer and the bit line structure, and The back gate dielectric layer is spaced apart from the bit line structure in the vertical direction by the first stopper.

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