Flash memory device and preparation method thereof

Abstract

The invention provides a flash memory device and a preparation method thereof, and belongs to the field of semiconductors, and the preparation method of the flash memory device comprises the steps: providing a substrate which comprises an active region; forming a tunneling oxide layer on the active region; forming a plurality of pseudo grid bars which are arranged at intervals in the word line direction and extend in the bit line direction on the tunneling oxide layer; filling an isolation layer between the adjacent pseudo grid bars; etching and thinning the pseudo grid bars to form floating grid bars; etching the floating gate bars, and forming a plurality of floating gate blocks which are arranged at intervals along the bit line direction; depositing an inter-active dielectric layer and a gate material layer in sequence; and planarizing the gate material layer and staying on the inter-gate dielectric layer at the top of the isolation layer, and forming a control gate above the floating gate block. According to the invention, electric leakage between the storage units can be avoided, and the active region is not damaged, so that the flash memory performance is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a flash memory device and a method for manufacturing the same. BACKGROUND

[0002] Flash memory, also known as flash, is a mainstream non-volatile memory, which has the advantages of high integration, fast storage speed, easy erasing and rewriting, and is widely used in microcomputers, automation control and other fields. Flash memory is particularly suitable for portable devices and has become one of the mainstreams in the industry.

[0003] At present, due to the defects in the preparation process, when etching is insufficient, a leakage path may be formed between each flash memory storage unit; when etching is excessive, the active area on both sides of the ONO (a composite layer composed of a silicon dioxide layer, a silicon nitride layer and a silicon dioxide layer) bottom corner may be damaged, thereby affecting the reliability of the flash memory. SUMMARY

[0004] The present application provides a flash memory device and a method for manufacturing the same, which can avoid the leakage problem between the storage units and will not damage the active area, thereby improving the performance of the flash memory.

[0005] According to an aspect of the present application, a method for manufacturing a flash memory device is provided, comprising: providing a substrate, the substrate comprising an active area; forming a tunneling oxide layer on the active area; forming a plurality of pseudo-gate strips arranged in the direction of word lines and extending in the direction of bit lines on the tunneling oxide layer; filling an isolation layer between adjacent pseudo-gate strips; etching and thinning the pseudo-gate strips to form floating gate strips; etching the floating gate strips to form a plurality of floating gate blocks arranged in the direction of bit lines; sequentially depositing an interlayer dielectric layer and a gate material layer; planarizing the gate material layer and stopping on the gate interlayer dielectric layer on top of the isolation layer to form a control gate above the floating gate blocks.

[0006] Optionally, the step of forming a plurality of pseudo-gate strips arranged in the direction of word lines and extending in the direction of bit lines on the tunneling oxide layer comprises: depositing a gate material layer on the tunneling oxide layer; etching and removing part of the gate material layer to form a plurality of pseudo-gate strips on the tunneling oxide layer.

[0007] Optionally, the step of filling an isolation layer between adjacent pseudo-gate strips comprises: The isolation material layer is formed on the sidewall of the dummy gate by a sidewall deposition process. The isolation layer is formed by filling an insulating material layer between the adjacent dummy gates and planarizing the insulating material layer.

[0008] Optionally, the isolation material layer is formed on the sidewall of the dummy gate by a sidewall deposition process, including: The isolation material layer is formed on the sidewall of the dummy gate by a sidewall deposition process. The isolation material layer is formed on the sidewall of the dummy gate by a sidewall deposition process.

[0009] Optionally, the insulating material layer filled between the adjacent dummy gates is an interlayer dielectric layer formed by high-density plasma chemical vapor deposition or low-pressure chemical vapor deposition.

[0010] Optionally, the dummy gate is thinned by etching to form a floating gate, including: The dummy gate is etched by a selective etching process to remove the upper part of the dummy gate and retain the gate material layer of the lower part of the dummy gate, which is the floating gate; the height of the isolation layer is higher than the height of the floating gate.

[0011] Optionally, the interlayer dielectric layer and the gate material layer are sequentially deposited, including: The interlayer dielectric layer is formed on the floating gate by a deposition process, so that the interlayer dielectric layer covers the floating gate and the isolation layer and the sidewall of the isolation layer. The gate material layer is formed on the interlayer dielectric layer by a deposition process.

[0012] Optionally, the material of the dummy gate is polysilicon; the interlayer dielectric layer is a composite layer composed of a silicon dioxide layer, a silicon nitride layer and a silicon dioxide layer; and the material of the isolation layer is silicon dioxide.

[0013] Optionally, the thickness of the dummy gate is 1000-6000 angstroms; and the thickness of the floating gate is 1 / 5-1 / 2 of the thickness of the dummy gate.

[0014] According to another aspect of the present application, there is provided a flash memory device, including: The flash memory device is prepared by the preparation method of any embodiment of the present application.

[0015] The application fills the isolation layer between the adjacent pseudo gate strips, removes the upper part of the pseudo gate strips to form a plurality of floating gate strips, etches each floating gate strip to form a plurality of spaced floating gate blocks along the bit line direction, sequentially forms the inter-electrode dielectric layer and the gate material layer on the device, so that the inter-electrode dielectric layer covers the plurality of floating gate blocks and the isolation layer, and the gate material layer covers the inter-electrode dielectric layer; the gate material layer on the isolation layer is removed to form the control gate. The unexpected technical effect of the application is that the isolation layer is filled between the pseudo gate strips, so that the polysilicon in the trench between the storage units does not need to be etched again in the subsequent process, and the polysilicon residue in the trench is avoided; and by defining the pseudo gate strips in advance, then filling the isolation layer between the adjacent pseudo gate strips, sequentially forming the inter-electrode dielectric layer and the gate material layer on the device, and finally removing the gate material layer on the isolation layer to form the control gate, in the process of removing the isolation layer, at most the inter-electrode dielectric layer on the isolation layer is removed, and the active region is not damaged.

[0016] It should be understood that the description in this section is not intended to identify key or critical features of embodiments of the application or to limit the scope of the application. Other features of the application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0018] Figure 1 It is a partial top view of a flash memory device; Figure 2 It is a partial top view of a flash memory device; Figure 1 After the ONO layer is deposited in the flash memory preparation process shown in the figure, the isolation layer is etched along the direction of the bit line to form a plurality of floating gate blocks. Figure 1 It is a partial cross-sectional view of the device with A1-A2 as the cross-sectional line in the figure. Figure 3 It is a partial top view of a flash memory device; Figure 1 After the control gate is deposited in the flash memory preparation process shown in the figure, the isolation layer is etched along the direction of the bit line to form a plurality of floating gate blocks. Figure 1 It is a partial cross-sectional view of the device with A1-A2 as the cross-sectional line in the figure. Figure 4 It is a partial top view of a flash memory device; Figure 1 After the flash memory unit is formed in the flash memory preparation process shown in the figure, the isolation layer is etched along the direction of the bit line to form a plurality of floating gate blocks. Figure 1 It is a partial cross-sectional view of the device with A1-A2 as the cross-sectional line in the figure. Figure 5 It is a partial top view of a flash memory device; Figure 1 After the flash memory unit is formed in the flash memory preparation process shown in the figure, the isolation layer is etched along the direction of the bit line to form a plurality of floating gate blocks. Figure 1A cross-sectional view of a part of the device with B1-B2 as the cross-sectional line; Figure 6 A circuit schematic diagram of the flash memory is shown in FIG. 1; Figure 1 Figure 7 A flow chart of a method for manufacturing a flash memory device is provided in Embodiment One of the present application; Figure 8 A cross-sectional view of a part of the device with A1-A2 as the cross-sectional line after forming a photoresist pattern on the gate material layer in Embodiment of the present application; Figure 9 A cross-sectional view of a part of the device with B1-B2 as the cross-sectional line after forming a photoresist pattern on the gate material layer in Embodiment of the present application; Figure 10 A cross-sectional view of a part of the device with A1-A2 as the cross-sectional line after etching the gate material layer in Embodiment of the present application; Figure 11 A cross-sectional view of a part of the device with A1-A2 as the cross-sectional line after depositing a side wall on the pseudo gate strip in Embodiment of the present application; Figure 12 A cross-sectional view of a part of the device with A1-A2 as the cross-sectional line after etching the side wall of the pseudo gate strip in Embodiment of the present application; Figure 13 A cross-sectional view of a part of the device with A1-A2 as the cross-sectional line after filling the trench between the pseudo gate strips with an insulating material layer in Embodiment of the present application; Figure 14 A cross-sectional view of a part of the device with A1-A2 as the cross-sectional line after chemical mechanical polishing of the excess insulating material layer in Embodiment of the present application; Figure 15 A partial top view of the device after chemical mechanical polishing of the excess insulating material layer in Embodiment of the present application; Figure 16 A cross-sectional view of a part of the device with A1-A2 as the cross-sectional line after removing the upper part of the pseudo gate strip in Embodiment of the present application; Figure 17 A cross-sectional view of a part of the device with B1-B2 as the cross-sectional line after removing the upper part of the pseudo gate strip in Embodiment of the present application; Figure 18 A cross-sectional view of a part of the device with B1-B2 as the cross-sectional line after forming a photoresist pattern on the floating gate strip in Embodiment of the present application; Figure 19 A cross-sectional view of a part of the device with B1-B2 as the cross-sectional line after etching the floating gate strip in Embodiment of the present application; Figure 20 A cross-sectional view of a part of the device with B1-B2 as the cross-sectional line after sequentially forming an inter-electrode dielectric layer and a gate material layer on the floating gate block in Embodiment of the present application; Figure 21 ​Fig. 2 is a cross-sectional view of the flash memory device according to an embodiment of the present application, taken along the section line A1-A2 in Fig. 1. Figure 22 Fig. 3 is a cross-sectional view of the flash memory device according to an embodiment of the present application, taken along the section line A1-A2 in Fig. 1.

[0019] Reference Signs List: 100 - substrate; 110 - isolation structure; 200 - flash memory cell; 210a - floating gate layer; 210 - floating gate block; 220 - inter-electrode dielectric layer; 230 - gate material layer; 240 - control gate; 21 - dummy gate strip; 20 - floating gate strip; 300 - tunnel oxide layer; 400 - polysilicon residue; 500 - damage region; 600 - photoresist; 710 - isolation material layer; 720 - insulating material layer; 800 - isolation layer. DETAILED DESCRIPTION

[0020] In order to make the personnel in the art better understand the present application scheme, the following will be combined with the drawings in the embodiments of the present application, the technical scheme in the embodiments of the present application is described clearly and completely, obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without making creative labor should belong to the scope of the present application.

[0021] It should be noted that the specification and claims of the present application and the above-mentioned drawings of the term "first", "second" and so on are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0022] Figure 1 Fig. 1 is a partial plan view of a flash memory device according to an embodiment of the present application. Figure 1 , Figure 1Six flash memory cells 200 are shown in the figure. The six flash memory cells 200 are arranged in an array along the X direction and the Y direction (the X direction and the Y direction are perpendicular to each other. Generally, the X direction can be considered as the word line direction and the Y direction can be considered as the bit line direction. In the subsequent embodiments, the X direction is the word line direction and the Y direction is the bit line direction). The substrate 100 is divided into several active areas (Active Area, AA) by the trench isolation structure 110. Figure 1 The long dashed boxes extending along the Y direction represent leakage paths that may exist between the flash memory cells 200 .

[0023] Figures 2-4 This is a partial cross-sectional diagram of a flash memory device during its preparation process, with the word line direction A1-A2 as the cross-sectional line. Figure 5 : is a partial cross-sectional diagram with the bit line direction B1-B2 as the cross-sectional line. Figures 2-3 As shown, in the prior art, when preparing a flash memory device, a floating gate layer 210a is first formed on the tunneling oxide layer 300, and then an ONO layer 220 (oxide-nitride-oxide stacked layer) is formed on the floating gate layer 210a; then a gate material layer 230 is formed on the ONO layer 220. In order to form the flash memory cells 200 arranged at intervals, the stacked structure consisting of the floating gate layer 210a, the ONO layer 220 and the gate material layer 230 needs to be etched, and after etching, the following is formed. Figures 4-5 In the flash memory cell 200 shown, the gate structure of the flash memory cell 200 includes a floating gate layer 210 a , an ONO layer 220 , and a control gate 240 .

[0024] Figure 4 During the etching process, due to insufficient etching, polysilicon residue 400 may be present at the bottom of the trench between adjacent flash memory cells 200 in the word line direction, thereby forming a leakage path (such as Figure 6 (shown as dashed line in ). Figure 5 When over-etching occurs, the tunneling oxide layer 300 between the flash memory cells 200 in the bit line direction may be over-etched, thereby damaging the active area below the tunneling oxide layer 300 to form a damaged area 500, which will affect the accuracy of the stored information and reduce the reliability of the flash memory.

[0025] Based on this, the present invention provides a flash memory device and a method for manufacturing the same. The method comprises: providing a substrate including an active area; forming a tunneling oxide layer on the active area; forming a plurality of dummy gate strips spaced apart in the word line direction and extending in the bit line direction on the tunneling oxide layer; filling an isolation layer between adjacent dummy gate strips; etching and thinning the dummy gate strips to form floating gate strips; etching the floating gate strips to form a plurality of floating gate blocks spaced apart in the bit line direction; sequentially depositing an inter-active dielectric layer and a gate material layer; flattening the gate material layer and resting it on the inter-gate dielectric layer on top of the isolation layer, and forming a control gate above the floating gate block. The present invention can prevent leakage between memory cells without damaging the active area, thereby improving flash memory performance.

[0026] Figure 7 A flowchart of a method for preparing a flash memory device is provided for the first embodiment of the present invention. Figure 7 As shown, the method includes: Step S1, providing a substrate, wherein the substrate includes an active area; Step S2, forming a tunneling oxide layer on the active area; Step S3, forming a plurality of dummy gate strips on the tunnel oxide layer, which are arranged in a word line direction at intervals and extend in a bit line direction; Step S4, filling an isolation layer between adjacent dummy gate strips; Step S5: etching and thinning the dummy gate strips to form floating gate strips; Step S6: etching the floating gate strips to form a plurality of floating gate blocks arranged at intervals along the bit line direction; Step S7: depositing an interlayer dielectric layer and a gate material layer in sequence; Step S8: planarize the gate material layer and allow it to remain on the inter-gate dielectric layer on top of the isolation layer, and form a control gate above the floating gate block.

[0027] Figures 8-22 Schematic diagram of the steps of preparing a flash memory device, wherein: Figure 8 、 Figures 10-14 、 Figure 15 、 Figures 21-22 is a cross-sectional schematic diagram with the word line direction A1-A2 as the section line; Figure 9 , Figures 17-20 It is a cross-sectional schematic diagram with the bit line direction B1 - B2 as the section line. like Figure 8 As shown, the substrate 100 provided in step S1 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon-on-insulator substrate, but is not limited thereto. The substrate 100 includes several active regions separated by isolation structures 110 .

[0028] The tunneling oxide layer 300 is formed on the active region in step S2. The tunneling oxide layer 300 is usually made of silicon dioxide, and can also be made of a laminated structure of silicon dioxide and a material with high dielectric constant.

[0029] As shown in a cross-sectional view with A1-A2 as the cross-sectional line, Figure 10 As shown in a cross-sectional view with A1-A2 as the cross-sectional line, step S3 forms a plurality of pseudo gate strips 21 on the tunneling oxide layer 300, which are arranged in the word line direction and extend in the bit line direction. In this embodiment, the height of the pseudo gate strips 21 can be set to 1000-6000 angstroms; the height of the floating gate strips 20 can be set to 1 / 5-1 / 2 of the thickness of the pseudo gate strips 21. This is only an exemplary description, and other heights can also be set in practice. In addition, the floating gate strips 20 can be obtained by etching the material on the upper part of the pseudo gate strips 21. The setting of the pseudo gate strips 21 can define the position of the control gate in advance.

[0030] Specifically, the preparation method of the plurality of pseudo gate strips 21 on the tunneling oxide layer 300 can refer to the preparation method of the plurality of pseudo gate strips 21 on the tunneling oxide layer 300 in the preparation method of the control gate of the memory cell of the memory device in the prior art, Figures 8-10 Figure 8 and Figure 10 As shown in a cross-sectional view with A1-A2 as the cross-sectional line, Figure 9 As shown in a cross-sectional view with B1-B2 as the cross-sectional line. As shown in Figure 8 and Figure 10 first, a gate material layer 230 is formed on the tunneling oxide layer 300 by using a deposition process, then photoresist 600 is coated on the gate material layer 230, a photoresist pattern is formed after exposure and development, and then the gate material not covered by the photoresist is etched to form a plurality of pseudo gate strips 21, and a groove is formed between adjacent pseudo gate strips 21. As can be seen Figure 8 In the cross-sectional view with A1-A2 as the cross-sectional line, the photoresist pattern is arranged in an interval pattern, and Figure 9 In the cross-sectional view with B1-B2 as the cross-sectional line, the photoresist pattern completely covers the gate material layer 230, that is, the photoresist pattern formed after exposure and development only exists in part of the area on the gate material layer 230, and after etching the gate material layer 230, a plurality of pseudo gate strips 21 along the Y direction are generated.

[0031] As shown in Figure 14 Step S4 fills an isolation layer 800 between adjacent pseudo gate strips 21, and the isolation layer 800 is made of an insulating material such as silicon dioxide to avoid forming a leakage path between adjacent pseudo gate strips. There are many methods for filling the isolation layer 800, and one preferred method in this embodiment is as follows: The method for filling the isolation layer 800 between adjacent pseudo gate strips 21 is as follows Figures 11-14 ​As shown: First, an isolation material layer is formed on the sidewall of the dummy gate strip 21 by a sidewall deposition process as a sidewall, and an insulating material layer 720 is filled between adjacent dummy gate strips 21 and planarized to obtain an isolation layer 800.

[0032] The process of forming the sidewalls includes forming an isolation material layer 710 on the dummy gate strips 21 and on the inner walls of the trenches between adjacent dummy gate strips 21. For example, a layer of isolation material can be uniformly deposited on the dummy gate strips 21 and in the trenches between adjacent dummy gate strips 21 by using techniques such as chemical vapor deposition (CVD) and atomic layer deposition (ALD). Figure 11 The isolation material layer 710 shown in FIG. The isolation material layer 710 can be silicon dioxide, silicon nitride or other specific compounds. Then, a selective etching process is used to remove the isolation material layer 710 on the dummy gate 21 and the isolation material layer 710 on the bottom wall of the trench, leaving only the isolation material layer 710 on the side wall of the dummy gate 21 as the side wall. The schematic diagram after etching is as shown in FIG. Figure 12 As shown, compared to Figure 11 , Figure 12 The isolation material layer 710 on the dummy gate 21 and the isolation material layer 710 on the bottom wall of the trench are both removed. In this embodiment, a highly selective plasma etching technique can be used to etch the isolation material layer 710 on the dummy gate 21 and the isolation material layer 710 on the bottom wall of the trench by controlling parameters such as the type, flow rate, power, and pressure of the etching gas.

[0033] like Figure 13 As shown, a deposition process can be used to fill the trenches between adjacent dummy gate strips 21 with an insulating material layer 720, so that the insulating material layer 720 extends onto the dummy gate strips 21 and covers the dummy gate strips 21. In this embodiment, high-density plasma chemical vapor deposition or low-pressure chemical vapor deposition can be used to fill the trenches between adjacent dummy gate strips 21 with an insulating material (such as an interlayer dielectric film made of silicon dioxide), that is, an insulating material layer 720, and the insulating material layer 720 can extend above the dummy gate strips 21, so that the insulating material layer 720 covers the dummy gate strips 21. The insulating material layer 720 is generally a silicon dioxide film, but can also be other insulating materials.

[0034] It should be noted that when shallow trench isolation structures need to be filled or a lower temperature deposition process is required, high-density plasma chemical vapor deposition of silicon dioxide can be used; for non-filling or high-temperature insensitive process nodes, low-pressure chemical vapor deposition can be used to deposit silicon dioxide as an insulating layer.

[0035] like Figure 14As shown, in order to expose the dummy gate strip 21, a chemical mechanical polishing process (CMP) can be used to remove the insulating material layer 720 above the dummy gate strip 21. At the same time, the excess insulating material layer 720 above the trench can also be removed, thereby flattening the plane where the upper surface of the dummy gate strip 21 is located. In this embodiment, the isolation material layer 710 on the trench sidewall and the insulating material layer 720 in the trench together constitute an isolation layer 800.

[0036] Figure 15 This is a partial top view of the excess insulating material layer after chemical mechanical polishing in this embodiment; the cross-sectional schematic diagram with A1-A2 as the section line can be referred to Figure 14 . Figure 15 The structure includes dummy gate lines 21 and isolation layers 800 between adjacent dummy gate lines 21 .

[0037] like Figure 16 and Figure 17 As shown, in step S5, the gate material layer on top of the plurality of dummy gate strips 21 is removed to form a plurality of floating gate strips 20. In this embodiment, the position of the control gate is defined in advance through the dummy gate process; by forming dummy gate strips 21 with a height higher than the floating gate strips 20 and forming an isolation layer 800 between the dummy gate strips 21 before preparing the control gate, the position and size of the final control gate can be precisely defined and controlled. Figure 16 and Figure 17 The dummy gate material can be removed by etching the material layer above the dummy gate strip 21. It can be seen that after removing the material layer above the dummy gate strip 21, the height of the gate changes from d1 to d2. For example, the height d1 of the gate material layer can be set to 1000-6000 angstroms, and d2 can be set to 1 / 5-1 / 2 of the thickness of the dummy gate strip 21. The desired height can also be set as needed, and this embodiment is not limited thereto. In a preferred embodiment, the height d1 of the gate material layer can be set to 3000 angstroms, and d2 can be set to 1000 angstroms.

[0038] like Figures 18-19 As stated, Figures 18-19 In step S6, a photoresist 600 may be coated on the floating gate strip 20, and a photoresist pattern may be formed after exposure, development and patterning. Figure 18 As shown, the cross section of the photoresist pattern formed along the X direction is a spaced pattern; an etching process is used to remove the area of ​​each floating gate strip 20 not covered by the photoresist 600, and a pattern is formed along the bit line direction as shown in FIG. Figure 19 After etching is completed, the floating gate blocks 210 arranged at intervals are formed into a plurality of floating gate blocks 210 arranged in an array.

[0039] like Figures 20-21 As shown, Figure 20 It is a cross-sectional diagram with B1-B2 as the section line.Figure 21 A1-A2 as the cross-sectional line. In step S7, a deposition process can be used to form the inter-electrode dielectric layer 220 on the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, on the isolation layer 800 and the sidewall of the isolation layer 800. It can be understood that the inter-electrode dielectric layer 220 completely covers the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, and the isolation layer 800. Figure 16 A1-A2 as the cross-sectional line. In step S7, a deposition process can be used to form the inter-electrode dielectric layer 220 on the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, on the isolation layer 800 and the sidewall of the isolation layer 800. It can be understood that the inter-electrode dielectric layer 220 completely covers the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, and the isolation layer 800. Figure 18 A1-A2 as the cross-sectional line. In step S7, a deposition process can be used to form the inter-electrode dielectric layer 220 on the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, on the isolation layer 800 and the sidewall of the isolation layer 800. It can be understood that the inter-electrode dielectric layer 220 completely covers the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, and the isolation layer 800. A1-A2 as the cross-sectional line. In step S7, a deposition process can be used to form the inter-electrode dielectric layer 220 on the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, on the isolation layer 800 and the sidewall of the isolation layer 800. It can be understood that the inter-electrode dielectric layer 220 completely covers the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, and the isolation layer 800.

[0040] A1-A2 as the cross-sectional line. In step S7, a deposition process can be used to form the inter-electrode dielectric layer 220 on the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, on the isolation layer 800 and the sidewall of the isolation layer 800. It can be understood that the inter-electrode dielectric layer 220 completely covers the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, and the isolation layer 800. Figures 20-21 A1-A2 as the cross-sectional line. In step S7, a deposition process can be used to form the inter-electrode dielectric layer 220 on the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, on the isolation layer 800 and the sidewall of the isolation layer 800. It can be understood that the inter-electrode dielectric layer 220 completely covers the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, and the isolation layer 800. A1-A2 as the cross-sectional line. In step S7, a deposition process can be used to form the inter-electrode dielectric layer 220 on the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, on the isolation layer 800 and the sidewall of the isolation layer 800. It can be understood that the inter-electrode dielectric layer 220 completely covers the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, and the isolation layer 800.

[0041] A1-A2 as the cross-sectional line. In step S7, a deposition process can be used to form the inter-electrode dielectric layer 220 on the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, on the isolation layer 800 and the sidewall of the isolation layer 800. It can be understood that the inter-electrode dielectric layer 220 completely covers the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, and the isolation layer 800. Figure 22 A1-A2 as the cross-sectional line. In step S7, a deposition process can be used to form the inter-electrode dielectric layer 220 on the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, on the isolation layer 800 and the sidewall of the isolation layer 800. It can be understood that the inter-electrode dielectric layer 220 completely covers the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, and the isolation layer 800. Figure 22 A1-A2 as the cross-sectional line. In step S7, a deposition process can be used to form the inter-electrode dielectric layer 220 on the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, on the isolation layer 800 and the sidewall of the isolation layer 800. It can be understood that the inter-electrode dielectric layer 220 completely covers the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, and the isolation layer 800. A1-A2 as the cross-sectional line. In step S7, a deposition process can be used to form the inter-electrode dielectric layer 220 on the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, on the isolation layer 800 and the sidewall of the isolation layer 800. It can be understood that the inter-electrode dielectric layer 220 completely covers the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, and the isolation layer 800.

[0042] A1-A2 as the cross-sectional line. In step S7, a deposition process can be used to form the inter-electrode dielectric layer 220 on the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, on the isolation layer 800 and the sidewall of the isolation layer 800. It can be understood that the inter-electrode dielectric layer 220 completely covers the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, and the isolation layer 800. A1-A2 as the cross-sectional line. In step S7, a deposition process can be used to form the inter-electrode dielectric layer 220 on the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, on the isolation layer 800 and the sidewall of the isolation layer 800. It can be understood that the inter-electrode dielectric layer 220 completely covers the floating gate block 210, the sidewall of the floating gate block 210, the bottom wall of the trench between adjacent floating gate blocks 210, and the isolation layer 800.

[0043] The application also provides a flash memory device, comprising: The flash memory device prepared by the preparation method of the flash memory device according to any one of the embodiments of the application.

[0044] The above detailed description does not constitute a limitation on the protection scope of the application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent replacement and improvement made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A method of fabricating a flash memory device, comprising: The method comprises the following steps: providing a substrate comprising an active region; forming a tunneling oxide layer on the active region; forming a plurality of dummy gate strips arranged in a direction perpendicular to the word line direction and extending in the word line direction on the tunneling oxide layer; filling an isolation layer between adjacent dummy gate strips; etching and thinning the dummy gate strips to form floating gate strips; etching the floating gate strips to form a plurality of floating gate blocks arranged in the word line direction; sequentially depositing an inter-electrode dielectric layer and a gate material layer; planarizing the gate material layer and stopping on the gate inter-electrode dielectric layer on the top of the isolation layer to form a control gate above the floating gate blocks.

2. The method of claim 1, wherein the method further comprises: The step of forming a plurality of dummy gate strips arranged in a direction perpendicular to the word line direction and extending in the word line direction on the tunneling oxide layer comprises: depositing a gate material layer on the tunneling oxide layer; etching and removing part of the gate material layer to form a plurality of dummy gate strips arranged in a direction perpendicular to the word line direction and extending in the word line direction on the tunneling oxide layer.

3. The method of claim 1, wherein the method further comprises: The step of filling an isolation layer between adjacent dummy gate strips comprises: forming an isolation material layer as a side wall on the sidewall of the dummy gate strip by a side wall deposition process; filling an insulating material layer between adjacent dummy gate strips and planarizing to obtain the isolation layer.

4. The method of claim 3, wherein the method further comprises: The step of forming an isolation material layer as a side wall on the sidewall of the dummy gate strip by a side wall deposition process comprises: forming an isolation material layer on the dummy gate strip and the inner wall of the trench between adjacent dummy gate strips; removing the isolation material layer on the top of the dummy gate strip and the isolation material layer on the bottom wall of the trench by a selective etching process to form a side wall.

5. The method of claim 3, wherein the method further comprises: The insulating material layer filled between adjacent dummy gate strips is an interlayer dielectric layer deposited by high-density plasma chemical vapor deposition or low-pressure chemical vapor deposition.

6. The method of claim 1, wherein the method further comprises: The step of etching and thinning the dummy gate strips to form floating gate strips comprises: etching the dummy gate strips by a selective etching process to remove the upper part of the plurality of dummy gate strips and retain the gate material layer of the lower part of the dummy gate strips, the gate material layer of the lower part of the dummy gate strips being the floating gate strips; the height of the isolation layer being higher than the height of the floating gate strips.

7. The method of claim 1, wherein the method further comprises: The step of sequentially depositing an inter-electrode dielectric layer and a gate material layer comprises: forming the inter-electrode dielectric layer on the floating gate strips by a deposition process, so that the inter-electrode dielectric layer covers the floating gate blocks, the isolation layer and the sidewall of the isolation layer; forming the gate material layer on the inter-electrode dielectric layer by a deposition process.

8. The method of claim 1, wherein the method further comprises: The material of the dummy gate strips is polysilicon; the inter-electrode dielectric layer is a composite layer composed of a silicon dioxide layer, a silicon nitride layer and a silicon dioxide layer; and the material of the isolation layer is silicon dioxide.

9. The method of claim 1, wherein The thickness of the dummy gate strips is 1000-6000 angstroms; and the thickness of the floating gate strips is 1 / 5-1 / 2 of the thickness of the dummy gate strips.

10. A flash memory device, comprising: The flash memory device is prepared by the method of any one of claims 1-9.

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