Flash memory devices and their fabrication methods

Abstract

This invention provides a flash memory device and its fabrication method, belonging to the semiconductor field. The fabrication method of the flash memory device includes: providing a substrate, the substrate including an active region; forming a tunneling oxide layer on the active region; forming multiple dummy gate strips spaced apart in the word line direction and extending along the bit line direction on the tunneling oxide layer; filling an isolation layer between adjacent dummy gate strips; etching and thinning the dummy gate strips to form floating gate strips; etching the floating gate strips to form multiple floating gate blocks spaced apart along the bit line direction; sequentially depositing an inter-gate dielectric layer and a gate material layer; planarizing the gate material layer and placing it on the inter-gate dielectric layer on top of the isolation layer; and forming a control gate above the floating gate blocks. This invention can avoid leakage between memory cells and does not damage the active region, thereby improving flash memory performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a flash memory device and its fabrication method. Background Technology

[0002] Flash memory, also known as flash storage, is the mainstream non-volatile memory. It has advantages such as high integration, fast storage speed, and easy erasure and rewriting. Therefore, it has been widely used in many fields such as microcomputers and automation control. Flash memory is particularly suitable for use in portable devices and has become one of the mainstream research areas in the industry.

[0003] Currently, due to defects in the manufacturing process, insufficient etching may cause leakage paths between flash memory cells; excessive etching may damage the active areas on both sides of the bottom corner of the ONO (a composite layer composed of silicon dioxide, silicon nitride and silicon dioxide), thereby affecting the reliability of the flash memory. Summary of the Invention

[0004] This invention provides a flash memory device and its fabrication method, which avoids leakage problems between memory cells and does not damage the active area, thereby improving flash memory performance.

[0005] According to one aspect of the present invention, a method for fabricating a flash memory device is provided, comprising:

[0006] A substrate is provided, the substrate including an active region;

[0007] A tunneling oxide layer is formed on the active region;

[0008] Multiple pseudo-gate strips are formed on the tunneling oxide layer, spaced apart in the word line direction and extending along the bit line direction;

[0009] An isolation layer is filled between adjacent pseudo-grid strips;

[0010] The pseudo-grid strips are etched and thinned to form floating grid strips;

[0011] The floating gate strips are etched to form multiple spaced floating gate blocks along the bit line direction;

[0012] The interphase dielectric layer and the gate material layer are deposited sequentially;

[0013] The gate material layer is planarized and placed on the inter-gate dielectric layer on top of the isolation layer, forming a control gate above the floating gate block.

[0014] Optionally, forming multiple pseudo-gate strips spaced apart in the word line direction and extending along the bit line direction on the tunneling oxide layer includes:

[0015] A gate material layer is deposited on the tunneling oxide layer;

[0016] Etching removes a portion of the gate material layer to form multiple pseudo gate bars on the tunneling oxide layer.

[0017] Optionally, filling the spacer layer between adjacent pseudo-gate strips includes:

[0018] A sidewall deposition process is used to form an isolation material layer on the sidewall of the pseudo-grid as a sidewall;

[0019] The isolation layer is obtained by filling the space between adjacent pseudo-grid strips with an insulating material layer and planarizing it.

[0020] Optionally, a sidewall deposition process is used to form an insulating material layer on the sidewall of the dummy grid as a sidewall, including:

[0021] An insulating material layer is formed on the dummy grid strips and on the inner walls of the grooves between adjacent dummy grid strips;

[0022] The isolation material layer on the top of the dummy grid and the isolation material layer on the bottom wall of the trench are removed by selective etching process to form a sidewall.

[0023] Optionally, the insulating material layer filling between adjacent pseudo-grid strips is an interlayer dielectric layer formed by high-density plasma chemical vapor deposition or low-pressure chemical vapor deposition.

[0024] Optionally, the etching and thinning of the dummy gate strip to form a floating gate strip includes:

[0025] The dummy gate strips are etched using a selective etching process to remove the upper parts of multiple dummy gate strips, while retaining the gate material layer at the lower part of the dummy gate strips. The gate material layer at the lower part of the dummy gate strips is the floating gate strip. The height of the isolation layer is higher than the height of the floating gate strip.

[0026] Optionally, the sequential deposition of the interphase dielectric layer and the gate material layer includes:

[0027] The interelectrode dielectric layer is formed on the floating grid bar using a deposition process, such that the interelectrode dielectric layer covers the floating grid block, the isolation layer, and the sidewall of the isolation layer;

[0028] The gate material layer is formed on the inter-electrode dielectric layer using a deposition process.

[0029] Optionally, the pseudo-gate strip is made of polycrystalline silicon; the inter-electrode dielectric layer is a composite layer composed of silicon dioxide, silicon nitride, and silicon dioxide stacked together; and the isolation layer is made of silicon dioxide.

[0030] Optionally, the thickness of the dummy grid strip is 1000-6000 angstroms; the thickness of the floating grid strip is 1 / 5-1 / 2 of the thickness of the dummy grid strip.

[0031] According to another aspect of the present invention, a flash memory device is provided, comprising:

[0032] The flash memory device is prepared using the fabrication method of any embodiment of the present invention.

[0033] This invention involves filling an isolation layer between adjacent dummy gate strips; removing the upper part of the dummy gate strips to form multiple floating gate strips; etching each floating gate strip to form multiple spaced floating gate blocks along the bit line direction; sequentially forming an inter-electrode dielectric layer and a gate material layer on the device, such that the inter-electrode dielectric layer covers the multiple floating gate blocks and the isolation layer, and the gate material layer covers the inter-electrode dielectric layer; removing the gate material layer on the isolation layer to form a control gate. An unexpected technical advantage of this invention is that filling the dummy gate strips with an isolation layer eliminates the need for subsequent etching of the polysilicon in the trenches between memory cells, avoiding polysilicon residue in the trenches; furthermore, by pre-defining the dummy gate strips, filling the isolation layer between adjacent dummy gate strips, sequentially forming the inter-electrode dielectric layer and the gate material layer on the device, and finally removing the gate material layer on the isolation layer to form a control gate, the process of removing the isolation layer at most removes the inter-electrode dielectric layer on the isolation layer without damaging the active region.

[0034] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A partial top view of a flash memory device;

[0037] Figure 2 for Figure 1 After depositing the ONO layer during the flash memory fabrication process shown, along Figure 1 A cross-sectional schematic diagram of some components with section lines A1-A2 as the cross-section line;

[0038] Figure 3 for Figure 1 The flash memory fabrication process shown depicts the deposition of a control gate, followed by... Figure 1 A cross-sectional schematic diagram of some components with section lines A1-A2 as the cross-section line;

[0039] Figure 4 for Figure 1The flash memory fabrication process shown depicts a type of process after the formation of flash memory cells. Figure 1 A cross-sectional schematic diagram of some components with section lines A1-A2 as the cross-section line;

[0040] Figure 5 for Figure 1 The flash memory fabrication process shown is another process following the formation of flash memory cells. Figure 1 A cross-sectional schematic diagram of some components with B1-B2 as the section line;

[0041] Figure 6 for Figure 1 The circuit diagram of the flash memory is shown below;

[0042] Figure 7 The flowchart illustrates a method for fabricating a flash memory device according to Embodiment 1 of the present invention.

[0043] Figure 8 This is a cross-sectional view with A1-A2 as the section line after a photoresist pattern is formed on the gate material layer in an embodiment of the present invention.

[0044] Figure 9 This is a cross-sectional view of the pattern formed on the gate material layer after photoresist is formed in an embodiment of the present invention, with B1-B2 as the cross-section line.

[0045] Figure 10 This is a cross-sectional view of the gate material layer after etching, with A1-A2 as the cross-sectional line in an embodiment of the present invention.

[0046] Figure 11 This is a cross-sectional view of the pseudo-grid strips after sidewall deposition in an embodiment of the present invention, with A1-A2 as the section line;

[0047] Figure 12 This is a cross-sectional view of the pseudo grid strip after sidewall etching in an embodiment of the present invention, with A1-A2 as the section line;

[0048] Figure 13 This is a cross-sectional view with A1-A2 as the section line after the grooves between the pseudo grid bars are filled with an insulating material layer in an embodiment of the present invention.

[0049] Figure 14 This is a cross-sectional view with A1-A2 as the section line after the excess insulating material layer has been chemically and mechanically polished in an embodiment of the present invention.

[0050] Figure 15 This is a partial top view of the excess insulating material layer after chemical mechanical polishing in an embodiment of the present invention;

[0051] Figure 16 This is a cross-sectional view of the embodiment of the present invention after removing the upper part of the pseudo grid strips, with A1-A2 as the section line;

[0052] Figure 17 This is a cross-sectional view of the embodiment of the present invention after removing the upper part of the pseudo grid strip, with B1-B2 as the section line;

[0053] Figure 18 This is a cross-sectional view with B1-B2 as the section line after the photoresist pattern is formed on the floating grid strip in an embodiment of the present invention.

[0054] Figure 19 This is a cross-sectional view of the floating grid strip after etching, with B1-B2 as the section line, according to an embodiment of the present invention.

[0055] Figure 20 This is a cross-sectional view of an embodiment of the present invention, showing the inter-electrode dielectric layer and the gate material layer sequentially formed on the floating gate block, with B1-B2 as the cross-section line.

[0056] Figure 21 This is a cross-sectional view of an embodiment of the present invention, showing the inter-electrode dielectric layer and gate material layer sequentially formed on the floating gate block and the isolation layer, with A1-A2 as the cross-section line.

[0057] Figure 22 This is a cross-sectional view with A1-A2 as the section line after the final flash memory device is obtained in the embodiment of the present invention.

[0058] Explanation of reference numerals in the attached figures:

[0059] 100-Substrate; 110-Isolation structure; 200-Flash memory cell; 210a-Floating gate layer; 210-Floating gate block; 220-Inter-electrode dielectric layer; 230-Gate material layer; 240-Control gate; 21-Dummy gate bar; 20-Floating gate bar; 300-Tunneling oxide layer; 400-Polysilicon residue; 500-Damaged region; 600-Photoresist; 710-Isolation material layer; 720-Insulating material layer; 800-Isolation layer. Detailed Implementation

[0060] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0061] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0062] Figure 1 For a partial top view of a flash memory device, please refer to [reference needed]. Figure 1 , Figure 1 The diagram illustrates six flash memory cells 200, which are arranged in an array along the X and Y directions (the X and Y directions are perpendicular; generally, the X direction can be considered the word line direction and the Y direction the bit line direction. In subsequent embodiments, the X direction is always the word line direction and the Y direction is always the bit line direction). The substrate 100 is divided into several active areas (AA) by trench isolation structures 110. Figure 1 The long dashed frame extending along the Y direction represents the possible leakage paths between several flash memory cells 200.

[0063] Figures 2-4 This is a partial cross-sectional schematic diagram of a flash memory device during its fabrication process, using the word line direction A1-A2 as the cross-sectional line. Figure 5 This is a partial cross-sectional diagram with the section line B1-B2 as the section line. For example... Figures 2-3 As shown, in the prior art, when fabricating a flash memory device, a floating gate layer 210a is first formed on the tunneling oxide layer 300, and then an ONO layer 220 (oxide-nitride-oxide stacked layer) is formed on the floating gate layer 210a; subsequently, a gate material layer 230 is formed on the ONO layer 220. To form spaced flash memory cells 200, the stacked structure consisting of the floating gate layer 210a, the ONO layer 220, and the gate material layer 230 needs to be etched. After etching, a structure is formed as shown... Figures 4-5 The flash memory cell 200 shown has a gate structure including a floating gate layer 210a, an ONO layer 220, and a control gate 240.

[0064] Figure 4 During the etching process, insufficient etching may result in polysilicon residue 400 at the bottom of the trench between adjacent flash memory cells 200 in the word line direction, thus creating a leakage path between the flash memory cells 200 (e.g., Figure 6(The dashed line shown). Figure 5 However, when over-etching occurs, the tunnel oxide layer 300 between the flash memory cells 200 in the bit line direction may be over-etched, thereby damaging the active area below the tunnel oxide layer 300 and forming a damaged area 500, which will affect the accuracy of stored information and reduce the reliability of flash memory.

[0065] Based on this, the present invention provides a flash memory device and a method for fabricating the same. The method for fabricating the flash memory device includes: providing a substrate, the substrate including an active region; forming a tunneling oxide layer on the active region; forming multiple dummy gate strips spaced apart in the word line direction and extending along the bit line direction on the tunneling oxide layer; filling an isolation layer between adjacent dummy gate strips; etching and thinning the dummy gate strips to form floating gate strips; etching the floating gate strips to form multiple floating gate blocks spaced apart along the bit line direction; sequentially depositing an inter-gate dielectric layer and a gate material layer; planarizing the gate material layer and placing it on the inter-gate dielectric layer on top of the isolation layer; and forming a control gate above the floating gate blocks. The present invention can avoid leakage between memory cells and does not damage the active region, thereby improving flash memory performance.

[0066] Figure 7 This is a flowchart illustrating a method for fabricating a flash memory device according to Embodiment 1 of the present invention. Figure 7 As shown, the method includes:

[0067] Step S1: Provide a substrate, the substrate including an active region;

[0068] Step S2: Form a tunneling oxide layer on the active region;

[0069] Step S3: Form multiple pseudo gate strips that are spaced apart in the word line direction and extend along the bit line direction on the tunneling oxide layer;

[0070] Step S4: Fill the gaps between adjacent pseudo-grid strips with an isolation layer;

[0071] Step S5: Etch and thin the dummy grid to form a floating grid;

[0072] Step S6: Etch the floating gate strips to form multiple spaced floating gate blocks along the bit line direction;

[0073] Step S7: Sequentially deposit the interphase dielectric layer and the gate material layer;

[0074] Step S8: Planarize the gate material layer and place it on the inter-gate dielectric layer on top of the isolation layer to form a control gate above the floating gate block.

[0075] Figures 8-22 This is a schematic diagram illustrating the steps involved in the fabrication of a flash memory device. Figure 8 , Figures 10-14 , Figure 15 , Figures 21-22 This is a cross-sectional diagram with the text line direction A1-A2 as the section line; Figure 9 , Figures 17-20 This is a schematic cross-sectional view with the section line B1-B2 as the section line.

[0076] like Figure 8 As shown, the substrate 100 provided in step S1 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, or a fully depleted silicon-on-insulator substrate, but is not limited thereto. The substrate 100 includes several active regions separated by the isolation structure 110.

[0077] In step S2, a tunneling oxide layer 300 is formed on the active region. The tunneling oxide layer 300 is usually made of silicon dioxide, but it can also be a stacked structure composed of silicon dioxide and a material with a high dielectric constant.

[0078] like Figure 10 As shown in the cross-sectional diagram with A1-A2 as the cross-section line, step S3 forms multiple pseudo-gate strips 21 spaced apart in the word line direction and extending along the bit line direction on the tunneling oxide layer 300. In this embodiment, the height of the pseudo-gate strips 21 can be set to 1000-6000 angstroms; the height of the floating gate strip 20 can be set to 1 / 5-1 / 2 of the thickness of the pseudo-gate strip 21. This embodiment is only for illustrative purposes, and other heights can also be set in practice. In addition, the floating gate strip 20 can be obtained by etching the material on the upper part of the pseudo-gate strips 21. The position of the control gate can be defined in advance when setting the pseudo-gate strips 21.

[0079] Specifically, the preparation method for forming multiple pseudo-gate strips 21 on the tunneling oxide layer 300 can be referred to Figures 8-10 , Figure 8 and Figure 10 This is a schematic diagram of a cross-section with section line A1-A2. Figure 9 This is a schematic cross-sectional view with section lines B1-B2. (Example) Figure 8 and Figure 10 As shown, firstly, a deposition process is used to form a gate material layer 230 on the tunneling oxide layer 300. Then, photoresist 600 is coated onto the gate material layer 230. After exposure, development, and patterning, a photoresist pattern is formed. Next, etching is used to remove the gate material not covered by the photoresist. After etching, multiple dummy gate strips 21 are formed, and trenches are formed between adjacent dummy gate strips 21. It can be seen that... Figure 8 In the cross-sectional diagram with section line A1-A2, the photoresist pattern is arranged in an alternating pattern, while Figure 9 In the cross-sectional diagram with B1-B2 as the cross-section line, the photoresist pattern completely covers the gate material layer 230. That is, the photoresist pattern formed after exposure, development and patterning only exists in a part of the gate material layer 230. After etching the gate material layer 230, multiple pseudo gate strips 21 along the Y direction can be generated.

[0080] like Figure 14 As shown, in step S4, an isolation layer 800 is filled between adjacent dummy gate strips 21. The isolation layer 800 is made of an insulating material, such as silicon dioxide, to prevent leakage paths from forming between adjacent dummy gate strips. There are various methods for filling the isolation layer 800; a preferred method in this embodiment is as follows:

[0081] The method of filling the isolation layer 800 between adjacent pseudo-gate strips 21 is as follows: Figures 11-14 As shown: First, an isolation material layer is formed on the sidewall of the pseudo grid 21 as a sidewall using a sidewall deposition process. An insulating material layer 720 is filled between adjacent pseudo grids 21 and planarized to obtain an isolation layer 800.

[0082] The process of forming the sidewalls includes forming an isolation material layer 710 on the dummy bars 21 and on the inner walls of the trenches between adjacent dummy bars 21. For example, an isolation material layer can be uniformly deposited on the dummy bars 21 and in the trenches between adjacent dummy bars 21 using techniques such as chemical vapor deposition (CVD) and atomic layer deposition (ALD) to form a layer of isolation material. Figure 11 The isolation material layer 710 is shown in the diagram. The isolation material layer 710 can be silicon dioxide, silicon nitride, or other specific compounds. Then, a selective etching process is used to remove the isolation material layer 710 on the dummy gate 21 and the isolation material layer 710 on the bottom wall of the trench, leaving only the isolation material layer 710 on the sidewalls of the dummy gate 21 as sidewalls. A schematic diagram after etching is shown in the diagram. Figure 12 As shown, compared to Figure 11 , Figure 12 The isolation material layer 710 on the dummy gate 21 and the isolation material layer 710 on the bottom wall of the trench are both removed. In this embodiment, highly selective plasma etching and other techniques can be used to etch the isolation material layer 710 on the dummy gate 21 and the isolation material layer 710 on the bottom wall of the trench by controlling parameters such as the type, flow rate, power, and pressure of the etching gas.

[0083] like Figure 13 As shown, an insulating material layer 720 can be filled into the trenches between adjacent dummy gate strips 21 using a deposition process, such that the insulating material layer 720 extends onto and covers the dummy gate strips 21. In this embodiment, high-density plasma chemical vapor deposition or low-pressure chemical vapor deposition can be used to fill the trenches between adjacent dummy gate strips 21 with an insulating material (such as an interlayer dielectric film made of silicon dioxide), i.e., an insulating material layer 720, and the insulating material layer 720 can extend above the dummy gate strips 21, so that the insulating material layer 720 covers the dummy gate strips 21. The insulating material layer 720 is generally a silicon dioxide film, but can also be other insulating materials.

[0084] It should be noted that for deposition processes that require filling shallow trench isolation structures or require lower temperatures, high-density plasma chemical vapor deposition of silicon dioxide can be used; while for non-filled or high-temperature insensitive process nodes, low-pressure chemical vapor deposition can be used to deposit silicon dioxide as an insulating layer.

[0085] like Figure 14 As shown, to expose the dummy grid 21, a chemical mechanical polishing (CMP) process can be used to remove the insulating material layer 720 above the dummy grid 21. This also removes excess insulating material layer 720 above the trench, thus flattening the plane containing the upper surface of the dummy grid 21. In this embodiment, the insulating material layer 710 on the trench sidewall and the insulating material layer 720 in the trench together constitute the insulating layer 800.

[0086] Figure 15 This is a partial top view of the excess insulating material layer after chemical mechanical polishing in this embodiment; A1-A2 are cross-sectional schematic diagrams of the cross-section lines, which can be referenced. Figure 14 . Figure 15 It includes pseudo grid strips 21 and isolation layers 800 between adjacent pseudo grid strips 21.

[0087] like Figure 16 and Figure 17 As shown, in step S5, the gate material layer on top of multiple dummy gate strips 21 is removed to form multiple floating gate strips 20. In this embodiment, the position of the control gate is defined in advance by using a dummy gate process; the control gate is fabricated by forming dummy gate strips 21 with a height higher than the floating gate strips 20 and forming an isolation layer 800 between the dummy gate strips 21, thereby enabling precise definition and control of the position and size of the final control gate. Figure 16 and Figure 17 The dummy gate material can be removed by etching the material layer on top of the dummy gate 21. It can be seen that after removing the material layer on top of the dummy gate 21, the gate height changes from d1 to d2. For example, the height d1 of the gate material layer can be set to 1000-6000 angstroms, and d2 can be 1 / 5-1 / 2 of the thickness of the dummy gate 21. The desired height can also be set as needed; this embodiment does not impose any limitations. In a preferred embodiment, the height d1 of the gate material layer can be set to 3000 angstroms, and d2 to 1000 angstroms.

[0088] like Figures 18-19 As described above, Figures 18-19 This is a cross-sectional view with B1-B2 as the section line. In step S6, photoresist 600 can be coated on the floating grid strip 20, and after exposure, development, and patterning, a photoresist pattern is formed, such as... Figure 18As shown, the resulting photoresist pattern has an intermittent arrangement in cross-section along the X direction; an etching process is used to remove the areas of each floating gate strip 20 not covered by the photoresist 600, forming a pattern along the bit line direction as shown. Figure 19 The multiple floating gate blocks 210 arranged at intervals shown can be etched to generate multiple floating gate blocks 210 arranged in an array after the etching is completed.

[0089] like Figures 20-21 As shown, Figure 20 This is a schematic diagram of a cross-section with section lines B1-B2. Figure 21 This is a cross-sectional view with section line A1-A2. In step S7, a deposition process can be used to form an interpolar dielectric layer 220 on top of the floating gate block 210, on the sidewalls of the floating gate block 210, on the bottom wall of the trench between adjacent floating gate blocks 210, on top of the isolation layer 800, and on the sidewalls of the isolation layer 800. This can be understood as the interpolar dielectric layer 220 completely covering... Figure 16 as well as Figure 18 The device shown. In this embodiment, the inter-electrode dielectric layer 220 is made of an insulating material, which can generally be a composite layer (ONO layer) composed of silicon dioxide, silicon nitride and silicon dioxide stacked together, which plays the role of storing charge and isolating and protecting.

[0090] Furthermore, such as Figures 20-21 As shown, in step S7, a deposition process can be used to form a gate material layer 230 covering the inter-electrode dielectric layer 220. Both the gate material layer 230 and the floating gate block 210 are made of polysilicon.

[0091] like Figure 22 As shown, in step S8, a chemical mechanical polishing (CMP) process can be used to remove the gate material layer 230 on the isolation layer 800, exposing the inter-electrode dielectric layer 220 on the isolation layer 800. Simultaneously, excess gate material layer 230 can be removed, making the plane containing the exposed inter-electrode dielectric layer 220 on the isolation layer 800 planar. Through the above steps, the gate structure of the flash memory cell 200, composed of the control gate 240, the inter-electrode dielectric layer 220, and the floating gate block 210, can be obtained. Figure 22 In this configuration, adjacent flash memory cells 200 are separated by an isolation layer 800. Because there is an isolation layer 800 between adjacent flash memory cells 200, no further etching is required, thus avoiding polysilicon residue and damage to the active area.

[0092] The technical solution of this invention involves filling an isolation layer between adjacent dummy gate strips; removing the upper part of the dummy gate strips to form multiple floating gate strips; etching each floating gate strip to form multiple spaced floating gate blocks; sequentially forming an inter-electrode dielectric layer and a gate material layer on the device, such that the inter-electrode dielectric layer covers multiple floating gate blocks and the isolation layer, and the gate material layer covers the inter-electrode dielectric layer; removing the gate material layer on the isolation layer to form a control gate. The unexpected technical effect of this invention is that filling the dummy gate strips with an isolation layer eliminates the need for subsequent etching of the polysilicon in the trenches between memory cells, avoiding polysilicon residue in the trenches; furthermore, by pre-defining the dummy gate strips, filling the isolation layer between adjacent dummy gate strips, sequentially forming the inter-electrode dielectric layer and the gate material layer on the device, and finally removing the gate material layer on the isolation layer to form a control gate, the process of removing the isolation layer at most removes the inter-electrode dielectric layer on the isolation layer without damaging the active region.

[0093] The present invention also provides a flash memory device, comprising:

[0094] The flash memory device is prepared using the fabrication method of any embodiment of the present invention.

[0095] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for fabricating a flash memory device, characterized in that, include: A substrate is provided, the substrate including an active region; A tunneling oxide layer is formed on the active region; Multiple pseudo-gate strips are formed on the tunneling oxide layer, spaced apart in the word line direction and extending along the bit line direction; An isolation layer is filled between adjacent pseudo-grid strips; The pseudo-grid strips are etched and thinned to form floating grid strips; The floating gate strips are etched to form multiple spaced floating gate blocks along the bit line direction; The interphase dielectric layer and the gate material layer are deposited sequentially; The gate material layer is planarized and placed on the inter-gate dielectric layer on top of the isolation layer, forming a control gate above the floating gate block.

2. The method for fabricating a flash memory device according to claim 1, characterized in that, The formation of multiple pseudo gate strips spaced apart in the word line direction and extending along the bit line direction on the tunneling oxide layer includes: A gate material layer is deposited on the tunneling oxide layer; Etching removes a portion of the gate material layer to form multiple pseudo gate bars spaced apart in the word line direction and extending along the bit line direction on the tunneling oxide layer.

3. The method for fabricating a flash memory device according to claim 1, characterized in that, The step of filling the gaps between adjacent pseudo-gate strips includes: A sidewall deposition process is used to form an isolation material layer on the sidewall of the pseudo-grid as a sidewall; The isolation layer is obtained by filling the space between adjacent pseudo-grid strips with an insulating material layer and planarizing it.

4. The method for fabricating a flash memory device according to claim 3, characterized in that, A sidewall deposition process is used to form an insulating material layer on the sidewall of the dummy grid as a sidewall, including: An insulating material layer is formed on the dummy grid strips and on the inner walls of the grooves between adjacent dummy grid strips; The isolation material layer on the top of the dummy grid and the isolation material layer on the bottom wall of the trench are removed by selective etching process to form a sidewall.

5. The method for fabricating a flash memory device according to claim 3, characterized in that, The insulating material layer filling between adjacent pseudo-grids is an interlayer dielectric layer formed by high-density plasma chemical vapor deposition or low-pressure chemical vapor deposition.

6. The method for fabricating a flash memory device according to claim 1, characterized in that, The process of etching and thinning the dummy grid to form a floating grid includes: The dummy gate strips are etched using a selective etching process to remove the upper parts of multiple dummy gate strips, while retaining the gate material layer at the lower part of the dummy gate strips. The gate material layer at the lower part of the dummy gate strips is the floating gate strip. The height of the isolation layer is higher than the height of the floating gate strip.

7. The method for fabricating a flash memory device according to claim 1, characterized in that, The sequential deposition of the intermediate dielectric layer and the gate material layer includes: The interelectrode dielectric layer is formed on the floating grid bar using a deposition process, such that the interelectrode dielectric layer covers the floating grid block, the isolation layer, and the sidewall of the isolation layer; The gate material layer is formed on the inter-electrode dielectric layer using a deposition process.

8. The method for fabricating a flash memory device according to claim 1, characterized in that, The pseudo-gate strip is made of polycrystalline silicon; the inter-electrode dielectric layer is a composite layer composed of silicon dioxide, silicon nitride, and silicon dioxide stacked together; and the isolation layer is made of silicon dioxide.

9. The method for fabricating a flash memory device according to claim 1, characterized in that, The thickness of the pseudo grid strip is 1000-6000 angstroms; the thickness of the floating grid strip is 1 / 5-1 / 2 of that of the pseudo grid strip.

10. A flash memory device, characterized in that, It is prepared by the method of any one of claims 1-9 for the fabrication of a flash memory device.

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