Memory device, method of manufacturing memory device, and method of operating memory device

Abstract

The invention relates to a memory device, a method of manufacturing the memory device, and a method of operating the memory device. The memory device includes a channel layer, a barrier layer surrounding the channel layer, a plurality of charge well layers spaced apart from each other and arranged along a surface of the barrier layer, a plurality of tunnel insulating layers, each of the plurality of tunnel insulating layers contacting a different one of the plurality of charge well layers, and a plurality of gate lines, each of the plurality of gate lines contacts a different one of the plurality of tunnel insulating layers, and each of the plurality of tunnel insulating layers is positioned between a different one of the plurality of charge well layers and a different one of the plurality of gate lines.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0053526, filed on April 22, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] The present disclosure relates to a memory device, a method of manufacturing the memory device, and a method of operating the memory device, including but not limited to a memory device having a three-dimensional structure, a method of manufacturing the memory device, and a method of operating the memory device. BACKGROUND

[0004] A memory device includes an array of memory cells in which data is stored, and a peripheral circuit configured to perform a program, read, or erase operation of the array of memory cells.

[0005] The array of memory cells includes memory blocks, and the memory blocks can be formed in a two-dimensional structure or a three-dimensional structure.

[0006] The memory blocks formed in the two-dimensional structure can include memory cells arranged along a substrate. The memory blocks formed in the three-dimensional structure can include memory cells stacked in a vertical direction on a substrate. The memory cells of the memory blocks formed in the three-dimensional structure can be programmed according to a method of trapping electric charges in a charge trap layer. SUMMARY

[0007] According to one embodiment of the present disclosure, a memory device includes a channel layer, a blocking layer surrounding the channel layer, a plurality of charge trap layers spaced apart from each other and arranged along a surface of the blocking layer, a plurality of tunnel insulating layers, and a plurality of gate lines, each tunnel insulating layer of the plurality of tunnel insulating layers contacting a different charge trap layer of the plurality of charge trap layers, each gate line of the plurality of gate lines contacting a different tunnel insulating layer of the plurality of tunnel insulating layers, and each tunnel insulating layer of the plurality of tunnel insulating layers being positioned between a different charge trap layer of the plurality of charge trap layers and a different gate line of the plurality of gate lines.

[0008] According to one embodiment of the disclosure, a method of manufacturing a memory device includes alternately stacking a plurality of first material layers and a plurality of second material layers, forming openings in the first material layers and the second material layers to expose regions of the first material layers and the second material layers, forming recesses between the plurality of first material layers and the plurality of second material layers by removing portions of the second material layers exposed through the openings, forming a tunnel insulating layer in contact with one of the second material layers and a charge trap layer in contact with the tunnel insulating layer in each of the recesses, forming a barrier layer along a surface of the charge trap layer and the plurality of first material layers exposed through the openings, and forming a channel layer along a surface of the barrier layer.

[0009] According to one embodiment of the disclosure, a method of operating a memory device includes applying a program voltage at a negative voltage level to a selected word line among a plurality of word lines connected to a memory block, applying a pass voltage at a positive voltage level to unselected word lines among the plurality of word lines, applying a program enable voltage to a selected bit line among a plurality of bit lines connected to the memory block, and applying a program inhibit voltage to unselected bit lines among the plurality of bit lines.

[0010] According to one embodiment of the disclosure, a method of operating a memory device includes applying an erase voltage at a positive voltage level to a plurality of word lines connected to a memory block, and applying a bit line voltage to a plurality of bit lines connected to the memory block.

[0011] According to one embodiment of the disclosure, a memory device includes a barrier layer surrounding a channel layer, a plurality of charge trap layers spaced apart and arranged along a surface of the barrier layer, each of the plurality of charge trap layers including a protrusion extending toward the barrier layer, a plurality of tunnel insulating layers each contacting a different one of the plurality of charge trap layers, and a plurality of gate lines each contacting a different one of the plurality of tunnel insulating layers. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a diagram illustrating a memory device according to an embodiment of the disclosure;

[0013] Figure 2 is a diagram illustrating a memory cell array according to an embodiment of the disclosure;

[0014] Figure 3 is a circuit diagram illustrating a memory block according to an embodiment of the disclosure;

[0015] Figure 4A and Figure 4B is a diagram illustrating a view of a first structure of a memory device according to an embodiment of the disclosure;

[0016] Figures 5A-5HFIG. 1 is a diagram illustrating a view of a first structure of a memory device formed using a first method of fabricating the first structure;

[0017] Figures 6A-6J FIG. 2 is a diagram illustrating a view of the first structure of the memory device formed using a second method of fabricating the first structure;

[0018] Figure 7 FIG. 3 is a diagram illustrating a second structure of a memory device according to an embodiment of the disclosure;

[0019] Figures 8A-8I FIG. 4 is a diagram illustrating a view of the second structure of the memory device formed using a first method of fabricating the second structure;

[0020] Figures 9A-9K FIG. 5 is a diagram illustrating a view of the second structure of the memory device formed using a second method of fabricating the second structure;

[0021] Figure 10A and Figure 10B FIG. 6 is a diagram illustrating a view of a memory block and a portion of the first structure during a program operation of a program method according to an embodiment of the disclosure;

[0022] Figure 11A and Figure 11B FIG. 7 is a diagram illustrating a view of the memory block and the portion of the first structure during an erase operation of an erase method according to an embodiment of the disclosure;

[0023] Figure 12A and Figure 12B FIG. 8 is a diagram illustrating a read method according to an embodiment of the disclosure;

[0024] Figure 13 FIG. 9 is a diagram illustrating a solid state drive (SSD) system including the memory device of the disclosure; and

[0025] Figure 14 FIG. 10 is a diagram illustrating a memory card system including the memory device of the disclosure. DETAILED DESCRIPTION

[0026] Embodiments of the disclosure are described in detail with reference to the accompanying drawings. The detailed description of the embodiments of the disclosure is provided as examples in order to describe the concepts disclosed in the present application. The examples or embodiments according to the concepts can be implemented in various forms, and the scope of the disclosure is not limited to the examples or embodiments described in the specification.

[0027] The terms "first" and "second" and the like are used to distinguish between various elements and are not intended to signify size, order, priority, number, or importance. For example, a first element can be termed a second element, and a second element can be termed a first element in another example. When an element is identified as "connected" to another element, it can be directly connected to the other element or connected through intervening elements between the two elements. When two elements are identified as "directly connected," one element is directly connected to the other element without intervening elements between the two elements.

[0028] Terms such as "vertical," "top," "bottom," "upper," "side," "upper," "lower," "higher," "column," "row," "horizontal," and other terms that imply relative spatial relationships or orientations are used for the purpose of convenience in describing or referencing the drawings only and do not constitute other limitations.

[0029] In a three-dimensional memory device, a charge-trap layer can extend in a vertical direction. Since different memory cells trap charges in different regions of the charge-trap layer extending in the vertical direction, interference between consecutive memory cells in the vertical direction can increase, and thus the retention characteristics of the threshold voltages of the programmed memory cells to be maintained can deteriorate. One embodiment of the present disclosure provides a memory device and a manufacturing method thereof in which the retention characteristics of memory cells can be improved.

[0030] Figure 1 is a diagram illustrating a memory device.

[0031] Reference Figure 1 The memory device 100 includes a memory cell array 110 and a peripheral circuit 180.

[0032] The memory cell array 110 includes first to j-th memory blocks BLK1 to BLKj, where j is a positive integer. Each of the memory blocks BLK1 to BLKj includes memory cells capable of storing data. Drain select lines DSL, word lines WL, source select lines SSL, and source lines SL are connected to each of the memory blocks BLK1 to BLKj, and bit lines BL are commonly connected to the memory blocks BLK1 to BLKj. The memory blocks BLK1 to BLKj can correspond to memory blocks shown in Figure 4A The memory blocks BLK1 to BLKj correspond to memory blocks shown in Figure 7 .

[0033] The memory blocks BLK1 to BLKj can be formed in a two-dimensional structure or a three-dimensional structure. A memory block having a two-dimensional structure can include memory cells arranged in parallel on a substrate. A memory block having a three-dimensional structure can include memory cells stacked in a vertical direction on a substrate. As an embodiment of the present disclosure, a memory block formed in a three-dimensional structure is disclosed.

[0034] A memory cell stores one bit or multiple bits of data according to a programming method. For example, a method of storing one bit of data in one memory cell is referred to as a single-layer cell method, and a method of storing two bits of data in one memory cell is referred to as a multi-layer cell method. A method of storing three bits of data in one memory cell is referred to as a triple-layer cell method, and a method of storing four bits of data in one memory cell is referred to as a quad-layer cell method. Five bits or more of data can be stored in one memory cell.

[0035] The peripheral circuit 180 is configured to perform a programming operation (including storing data in the memory cell array 110), a read operation (including outputting data stored in the memory cell array 110), and an erase operation (including erasing data stored in the memory cell array 110). For example, the peripheral circuit 180 includes the voltage generator 120, the row decoder 130, the page buffer set 140, the column decoder 150, the input / output circuit 160, and the control circuit 170.

[0036] The voltage generator 120 generates various operation voltages Vop used during the programming operation, the read operation, and the erase operation in response to the operation code OPCD. For example, the voltage generator 120 is configured to generate a program voltage, a turn-on voltage, a turn-off voltage, a verify voltage, a read voltage, a pass voltage, and an erase voltage in response to the operation code OPCD. Each of the operation voltages Vop generated by the voltage generator 120 can have various voltage levels. The operation voltages Vop generated by the voltage generator 120 are applied to the drain select lines DSL, the word lines WL, the source select lines SSL, and the source lines SL of the memory block selected through the row decoder 130.

[0037] A program voltage includes a voltage applied to a selected word line among the word lines WL during a program operation, and is used to increase a threshold voltage of a memory cell connected to the selected word line. A pass voltage is applied to a drain select line DSL or a source select line SSL, and is used to turn on a drain select transistor or a source select transistor. An off voltage is applied to the drain select line DSL or the source select line SSL, and is used to turn off the drain select transistor and the source select transistor. A verify voltage is used during a verify operation to determine whether the threshold voltage of a selected memory cell is increased to a target level. The verify voltage is set to various levels according to the target level, and is applied to the selected word line. A read voltage is applied to the selected word line during a read operation of the selected memory cell. For example, the read voltage is set to various levels according to a program method of the selected memory cell. A pass-through voltage includes a voltage applied to an unselected word line among the word lines WL during a program or read operation, and is used to turn on a memory cell connected to the unselected word line. An erase voltage is used to erase memory cells included in a selected memory block during an erase operation, and is applied to the word lines WL.

[0038] The row decoder 130 is configured to transfer the operation voltage Vop to the drain select lines DSL, the word lines WL, the source select lines SSL, and the source lines SL connected to a selected memory block according to the row address RADD. For example, the row decoder 130 is connected to the voltage generator 120 through a global line, and is connected to the memory blocks BLK1 to BLKj through the drain select lines DSL, the word lines WL, the source select lines SSL, and the source lines SL. In one embodiment, the source lines SSL are not connected to the row decoder 130, and are connected to a separate source line driver (not shown).

[0039] The page buffer set 140 includes page buffers PB1 to PBn (not shown) connected to the memory blocks BLK1 to BLKj. Each of the page buffers is connected to the memory blocks BLK1 to BLKj through a bit line BL. During a read operation, the page buffers sense a current or a voltage of the bit line varying according to a threshold voltage of a selected memory cell in response to a page buffer control signal PBSIG, and temporarily store the sensed data.

[0040] The column decoder 150 is configured to cause data to be transferred between the page buffer set 140 and the input / output circuit 160 in response to a column address CADD. For example, the column decoder 150 is connected to the page buffer set 140 through a column line CL, and transfers an enable signal through the column line CL. The page buffers included in the page buffer set 140 receive or output data through a data line DL in response to the enable signal.

[0041] The input / output circuit 160 is configured to receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 transmits the command CMD and the address ADD received from an external controller to the control circuit 170 through the input / output line I / O, and transmits data received from the external controller to the page buffer group 140 through the input / output line I / O. Alternatively, the input / output circuit 160 outputs data received from the page buffer group 140 to the external controller through the input / output line I / O.

[0042] The control circuit 170 outputs an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to the command CMD and the address ADD. For example, when the command CMD input to the control circuit 170 is a command corresponding to a program operation, the control circuit 170 controls a device included in the peripheral circuit 180 to perform a program operation of a memory block selected by the address ADD. When the command CMD input to the control circuit 170 is a command corresponding to a read operation, the control circuit 170 controls a device included in the peripheral circuit 180 to perform a read operation of a memory block selected by the address, and outputs the data read. When the command CMD input to the control circuit 170 is a command corresponding to an erase operation, the control circuit 170 controls a device included in the peripheral circuit 180 to perform an erase operation of a selected memory block.

[0043] Figure 2 is a diagram illustrating a memory cell array.

[0044] Reference Figure 2 The memory cell array 110 includes a first memory block BLK1 to a j-th memory block BLKj. Each of the memory blocks BLK1 to BLKj can be configured using the same structure.

[0045] The memory blocks BLK1 to BLKj are spaced apart from each other along the Y direction. For example, the memory blocks BLK1 to BLKj are separated from each other by a slit SLT. Each of the slits SLT extends along the X direction and is arranged along the Y direction.

[0046] Figure 3 is a circuit diagram illustrating a memory block.

[0047] Since the memory blocks BLK1 to BLKj illustrated in Figure 2 The j-th memory block BLKj among the memory blocks BLK1 to BLKj is illustrated in Figure 3

[0048] Reference Figure 3 ​The jth memory block BLKj includes strings ST connected between the first bit line BL1 to the nth bit line BLn and the source line SL, where n is a positive integer. Because the bit lines BL1 to BLn extend along the Y direction and are arranged to be spaced apart from each other along the X direction, the strings ST extending in the Z direction are arranged to be spaced apart from each other along the X direction and the Y direction. Figure 3 The strings ST arranged along the X direction are shown in FIG. 1.

[0049] When one of the strings ST connected to the nth bit line BLn is described as an example, the string ST includes a source select transistor SST, first to ith memory cells MC1 to MCi, and a drain select transistor DST, where i is a positive integer. Because Figure 2 The jth memory block BLKj shown in FIG. 1 is a diagram illustrating a connection configuration of a memory block, and thus the number of the source select transistors SST, the memory cells MC1 to MCi, and the drain select transistors DST included in the string ST can vary depending on the memory device.

[0050] The gates of the source select transistors SST included in different strings ST are connected to a source select line SSL, the gates of the memory cells MC1 to MCi are connected to first to ith word lines WL1 to WLi, and the gates of the drain select transistors DST are connected to a drain select line DSL.

[0051] Among the memory cells MC1 to MCi, the memory cells formed on the same layer or level are connected to the same word line. For example, the first memory cells MC1 included in different strings ST are commonly connected to the first word line WL1, and the ith memory cells included in different strings ST are commonly connected to the ith word line WLi. A group of memory cells included in different strings ST and connected to the same word line is referred to as a page PG. A program operation and a read operation can be performed in units of the page PG, and an erase operation can be performed in units of the memory block.

[0052] Figure 4A and Figure 4B is a diagram illustrating a view of a first structure of a memory device according to an embodiment of the disclosure.

[0053] Referring to Figure 4A and Figure 4B , a portion of a memory block included in a memory device is shown. The memory block includes first material layers M1 stacked in alternation with second material layers M2, cell plugs CPL passing through the material layers M1 and M2, and a tunnel insulating layer (tunnel isolation layer) TX and a charge trap layer CT positioned between the second material layers M2 and the cell plugs CPL.

[0054] The first material layer M1 can be formed to include an insulating material such as an oxide layer. For example, the first material layer M1 can be a silicon oxide material. The second material layer M2 can be formed to include a conductive material that functions as a gate line GL such as a drain select line, a word line, or a source select line. The second material layer M2 can be formed to include a metal such as tungsten (W), molybdenum (Mo), cobalt (Co), and nickel (Ni), or a semiconductor material such as silicon (Si) or polysilicon (Poly-Si).

[0055] The cell plug CPL includes a barrier layer BX, a channel layer CH, and a core pillar CP that extends in the Z direction and is formed in a cylindrical shape.

[0056] The barrier layer BX includes a first barrier layer B1, a second barrier layer B2, and a third barrier layer B3. Among the barrier layers B1 to B3, the first barrier layer B1 is positioned radially outermost, and the second barrier layer B2 and the third barrier layer B3 are sequentially positioned radially inward from the first barrier layer B1 toward the channel layer CH. The third barrier layer B3 can be formed in a cylindrical shape. The second barrier layer B2 surrounds the third barrier layer B3. The first barrier layer B1 surrounds the second barrier layer B2. The first barrier layer B1 and the third barrier layer B3 can be formed to include an oxide material, and the second barrier layer B2 can be formed to include a nitride material. Alternatively, the first barrier layer B1 and the third barrier layer B3 can be formed to include a high dielectric material (high-K), and the second barrier layer B2 can be formed to include a low dielectric material (low-K). The channel layer CH surrounds the core pillar CP, and can be formed to include polysilicon. The core pillar CP can be formed in a cylindrical shape, and can be formed to include an insulating material or a conductive material.

[0057] The tunnel insulating layer TX and the charge trap layer CT are positioned between the first material layers M1 in the X direction. The tunnel insulating layer TX is positioned between the second material layer M2 and the charge trap layer CT, and can be formed to include an insulating material. The tunnel insulating layer TX can be formed to include a silicon oxide material. The charge trap layer CT is positioned between the tunnel insulating layer TX and the cell plug CPL, and can be formed to include a material that traps electrons. For example, the charge trap layer CT can be formed to include a nitride material. The charge trap layer CT can be formed to include at least one of silicon nitride SiN and silicon oxynitride SiON.

[0058] The cell plug CPL can have a first width W1 or diameter regardless of the position. The width W1 or diameter of the inner wall of the first material layer M1 surrounding the cell plug CPL is the same as the width W1 or diameter of the inner wall of the charge trap layer CT. Since the charge trap layer CT and the tunnel insulating layer TX surround the surface of the cell plug CPL, the width or diameter of the wall surrounding the outer surface of the tunnel insulating layer TX has a second width W2 or diameter that is greater than the first width W1 or diameter. When the structure surrounded by the second material layer M2 is a memory cell, the memory cell has the second width W2.

[0059] The charge trap layer CT included in the memory cell traps electrons during a program operation and discharges or releases the electrons during an erase operation. In one embodiment, since the tunnel insulating layer TX is positioned between the gate line GL and the charge trap layer CT, and the blocking layer BX is positioned between the charge trap layer CT and the channel layer CH, during the program operation, the electrons of the gate line GL pass through the tunnel insulating layer TX and are trapped in the charge trap layer CT. As described above, the program voltage applied to the selected word line is a negative voltage lower than 0 V, so that the electrons move from the gate line GL to the charge trap layer CT during the program operation. The erase voltage applied to the word line is a positive voltage higher than 0 V, so that the electrons can move from the charge trap layer CT to the gate line GL during the erase operation. Since the electrons are trapped in the charge trap layer CT of the programmed memory cell, the read voltage applied to the selected word line is a positive voltage higher than 0 V during the read operation.

[0060] According to the first structure of the present disclosure, since the first material layer M1 formed to include an insulating material is positioned between the charge trap layers CT stacked in the Z direction, interference between the memory cells closest to each other in the Z direction can be reduced. Also, since the charge trap layers CT adjacent to each other in the Z direction are separated from each other, each of the charge trap layers CT is in a floating state. As a result, when the electrons are trapped in the charge trap layer CT, the electrons trapped in the charge trap layer CT are maintained until the erase operation is performed, and the data retention characteristics of the memory device can be improved.

[0061] A method of manufacturing a memory device is described in detail.

[0062] Figures 5A-5H FIG. 1 is a view illustrating a first structure of a memory device formed using a first method of manufacturing the first structure.

[0063] Reference Figure 5AOn a lower structure (not shown), first material layers M1 and second material layers M2 are alternately stacked in the Z direction. The lower structure can be a substrate or a peripheral circuit, and can include various other structures. The first material layers M1 are formed to include an insulating material such as an oxide layer. For example, the first material layers M1 can be a silicon oxide material. The second material layers M2 are formed to include a conductive material that serves as a gate line GL such as a drain select line, a word line, and a source select line. For example, the second material layers M2 can be formed to include a metal material such as tungsten (W), molybdenum (Mo), cobalt (Co), and nickel (Ni), or a semiconductor material such as silicon (Si) or polysilicon (Poly-Si). Each of the first material layers M1 is formed to have a first thickness T1, and each of the second material layers M2 is formed to have a second thickness T2. The second thickness T2 can be equal to or smaller than the first thickness T1.

[0064] Referring to Figure 5B An etching process is performed to form openings PR through the material layers M1 and M2. The openings PR can have a circular or elliptical shape in the XY plane.

[0065] To form the openings PR in a direction perpendicular to the material layers M1 and M2, the etching process is performed using, for example, a dry etching method. For example, an anisotropic dry etching process can be performed. The openings PR are formed to have a first width W1 or diameter. For example, the spaces between the first material layers M1 are the openings PR at the first width W1 or diameter, and the openings PR are formed such that the spaces between the second material layers M2 have the first width W1. When the openings PR are formed, the surfaces of each of the material layers M1 and M2 are exposed through the openings PR.

[0066] Referring to Figure 5C An etching process is performed to remove a portion of the second material layers M2 exposed through the openings PR. To selectively remove the portion of the second material layers M2, an etchant having a higher selectivity to the second material layers M2 than to the first material layers M1 is used. The region in which the portion of the second material layers M2 is removed is referred to as a first recess 1RC. For example, the second material layers M2 are removed by a first distance D1. As a result, the width W3 or diameter / distance between the second material layers M2 in which the first recess 1RC is formed is greater than the first width W1 or diameter. The third width W3 is (2xD1)+W1. The third width W3 can be equal to or smaller than the second width W2 of the second material layers M2. Figure 4A

[0067] Referring to Figure 5D ​, a tunnel insulating layer TX is selectively formed on the surface of the second material layer M2 exposed by the first recess 1RC. The tunnel insulating layer TX can be formed using an oxidation process. For example, the second material layer M2 is oxidized by an oxidation process to form a film having a surface 1Sm on the second material layer M2, and an oxide layer is formed on the surface 1Sm of the film of the second material layer M2. The tunnel insulating layer TX is formed in the first recess 1RC and on the film formed by oxidizing a portion of the second material layer M2. As shown in FIG. Figure 5C The third width W3 is equal to or less than Figure 4A The second width W2.

[0068] refer to Figure 5E , the charge trap layer CT is formed on Figure 5D The charge trap layer CT may be formed to include polysilicon in the remaining space of the first recess 1RC in which the tunnel insulating layer TX is formed. For example, after the polysilicon for the charge trap layer CT is formed within the opening PR to fill the first recess 1RC, the polysilicon may be formed on the surface of the first material layer M1. An etching process may be performed to remove the polysilicon formed on the surface of the first material layer M1, while the polysilicon filling the first recess 1RC remains. Because the charge trap layer CT is formed in the region where the second material layer M2 is positioned, each of the charge trap layers CT is formed to have a second thickness T2.

[0069] refer to Figure 5F , a barrier layer BX is formed along the surfaces of the charge trap layer CT and the first material layer M1 exposed in the opening PR. The barrier layer BX includes barrier layers B1 to B3. For example, the first barrier layer B1 is formed along the surfaces of the first material layer M1 and the charge trap layer CT exposed by the opening PR. The second barrier layer B2 is formed along the surface of the first barrier layer B1 exposed by the opening PR. The third barrier layer B3 is formed along the surface of the second barrier layer B2 exposed by the opening PR. Each of the barrier layers B1, B2, and B3 is formed to have the same thickness in the X direction. When the opening PR is formed in a circular or elliptical shape in the XY plane, the barrier layer BX is formed in a cylindrical shape.

[0070] refer to Figure 5G A channel layer CH is formed along the innermost surface of the barrier layer BX exposed through the opening PR. For example, the channel layer CH is formed along the surface of the third barrier layer B3. Because the barrier layer BX is formed in a cylindrical shape, the channel layer CH is formed in a cylindrical shape. The channel layer CH may be formed to include polysilicon.

[0071] refer to Figure 5HThe core pillar CP is formed in a region surrounded by the channel layer CH. The core pillar CP can include an insulating material or a conductive material, and is filled into the region surrounded by the channel layer CH. Thus, a cell plug CPL including the barrier layer BX, the channel layer CH, and the core pillar CP is formed.

[0072] Figures 6A-6J is a diagram illustrating a view of a first structure of a memory device formed using a second method of manufacturing the first structure.

[0073] During the second method of manufacturing the first structure, a third material layer M3 of a material different from the second material layer M2 is formed instead of Figure 5A the second material layer M2. The second material layer M2 is filled into a region in which the third material layer M3 is removed in a subsequent process. The second method of manufacturing the first structure is described in detail.

[0074] Referring to Figure 6A , the first material layer M1 and the third material layer M3 are alternately stacked along the Z direction on a lower structure (not shown). The lower structure can be a substrate or a peripheral circuit, and can include various structures. The first material layer M1 can be formed to include an insulating material such as an oxide layer. For example, the first material layer M1 can be a silicon oxide material. The third material layer M3 can be formed to include a material having an etching selectivity different from that of the first material layer M1 used as a sacrificial layer. The third material layer M3 can be formed to include a nitride material. The third material layer M3 can be formed to include a silicon nitride material. Each of the first material layers M1 is formed to have a first thickness T1, and each of the third material layers M3 is formed to have a second thickness T2. The second thickness T2 is equal to or smaller than the first thickness T1.

[0075] Referring to Figure 6B , an etching process is performed to form openings PR through the material layers M1 and M3. The openings PR can have a circular or elliptical shape in the XY plane.

[0076] To form the openings PR in a direction perpendicular to the material layers M1 and M3, the etching process is performed using, for example, a dry etching method. For example, an anisotropic dry etching process can be performed. The openings PR are formed to have a first width W1 or diameter. For example, the spaces between the first material layers M1 are the openings PR at the first width W1 or diameter, and the openings PR are formed such that the spaces between the third material layers M3 have the first width W1. When the openings PR are formed, the surface of each of the material layers M1 and M3 is exposed through the openings PR.

[0077] Referring to Figure 6C, an etching process is performed to remove a portion of the third material layer M3 exposed through the opening PR. To selectively remove the portion of the third material layer M3, an etchant having a higher selectivity to the third material layer M3 than to the first material layer M1 is used. The area in which the portion of the third material layer M3 is removed is referred to as a first recess 1RC. For example, the third material layer M3 is removed by a first distance D1. As a result, the width W3 or diameter / distance between the third material layer M3 in which the first recess 1RC is formed is greater than the first width W1 or diameter. The third width W3 can be equal to or less than Figure 4A the second width W2.

[0078] Referring to Figure 6D , a tunnel insulating layer TX is selectively formed on the surface of the third material layer M3 exposed through the first recess 1RC. The tunnel insulating layer TX can be formed using an oxidation process. The tunnel insulating layer TX is formed within the first recess 1RC from a portion of the third material layer M3 by the oxidation process. As described with reference to Figure 6C , the third width W3 is equal to or less than Figure 4A the second width W2.

[0079] Referring to Figure 6E , a charge trap layer CT is formed in the remaining space of the first recess 1RC in which the tunnel insulating layer TX is formed. Figure 6D The charge trap layer CT can be formed to include polysilicon. For example, after the polysilicon for the charge trap layer CT is formed within the opening PR to fill the first recess 1RC, the polysilicon can be formed on the surface of the first material layer M1. An etching process can be performed to remove the polysilicon formed on the surface of the first material layer M1, while the polysilicon filled in the first recess 1RC remains. Since the charge trap layer CT is formed in the area in which the third material layer M3 is positioned, each of the charge trap layers CT has a second thickness T2.

[0080] Referring to Figure 6F , a blocking layer BX is formed along the surfaces of the charge trap layer CT and the first material layer M1 exposed in the opening PR. The blocking layer BX includes blocking layers B1 to B3. For example, a first blocking layer B1 is formed along the surfaces of the first material layer M1 and the charge trap layer CT exposed through the opening PR. A second blocking layer B2 is formed along the surface of the first blocking layer B1 exposed through the opening PR. A third blocking layer B3 is formed along the surface of the second blocking layer B2 exposed through the opening PR. When the opening PR is formed in a circular or elliptical shape in the XY plane, the blocking layer BX is formed in a cylindrical shape.

[0081] Referring to Figure 6GA channel layer CH is formed along the surface of the barrier layer BX exposed by the opening PR. For example, the channel layer CH is formed along the surface of the third barrier layer B3 of the barrier layer BX. Because the barrier layer BX is formed in a cylindrical shape, the channel layer CH is formed in a cylindrical shape. The channel layer CH may be formed to include polysilicon.

[0082] refer to Figure 6H , a core column CP is formed in a region surrounded by the channel layer CH. The core column CP may include an insulating material or a conductive material and is filled into the region surrounded by the channel layer CH. Thus, a cell plug CPL including the barrier layer BX, the channel layer CH, and the core column CP is formed.

[0083] refer to Figure 6I ,like Figure 2 As shown, a trench is formed in the slit region SLT that divides the memory block, and an etching process is performed to remove the third material layer M3 exposed by the trench. The region where the third material layer M3 is removed is referred to as a second recess 2RC. The region of the first material layer M1 and the region of the tunnel insulation layer TX are exposed through the second recess 2RC.

[0084] refer to Figure 6J , the second material layer M2 is formed on Figure 6I For example, the second material layer M2 is formed by referring to Figure 6I and Figure 2 The depicted slit region SLT fills the second recess 2RC.

[0085] Figure 7 is a diagram illustrating a second structure of a memory device according to an embodiment of the present disclosure.

[0086] refer to Figure 7 In the second structure of the present disclosure, the charge trap layer CT includes a protrusion PT. The protrusion PT includes a surface 2Sm that protrudes or extends from the charge trap layer CT in a direction toward the central axis AX of the cell plug CPL. The surface 2Sm of the protrusion PT may be a convex curved surface. The width of the surface 2Sm of the charge trap layer CT between the closest points at the same level in the Z direction through the cell plug CPL is a fourth width W4 or diameter that is narrower than the first width W1 or diameter.

[0087] Since they are formed on the protrusion PT, a portion of the barrier layer BX and a portion of the channel layer CH also have a convex shape. For example, since the first barrier layer B1 is first formed among the barrier layers B1 to B3 included in the barrier layer BX, a portion of the first barrier layer B1 formed along the surfaces of the charge trap layer CT and the first material layer M1 has a convex shape due to the protrusion PT.

[0088] The outer surface of the channel layer CH is uneven and includes a concave portion due to being formed on the third barrier layer B3 having an uneven surface. The interface or boundary between the channel layer CH and the core column CP is convex in the area corresponding to the protrusion PT. The channel layer CH is thicker than the third barrier layer B3, and the inner surface of the channel layer CH is flat and formed as a substantially straight line in the Z direction.

[0089] When the charge trap layer CT includes the protrusion PT, electrons are more stably trapped during a program operation due to an increase in the volume of the charge trap layer CT. Figure 7 In the example, the ratio of the area of ​​the charge trap layer CT in contact with the barrier layer BX to the area of ​​the barrier layer BX in contact with the channel layer CH is Figure 4A In the example of FIG, the coupling ratio between the charge trap layer CT and the channel layer CH can be improved.

[0090] In addition to reference Figure 7 The charge trap layer CT, the protrusion PT and the barrier layer BX described above are the same as those in reference Figure 4A The parts described are similar.

[0091] Figures 8A-8I is a diagram illustrating a second structural view of a memory device formed using the first method of manufacturing the second structure.

[0092] refer to Figure 8A , first material layers M1 and second material layers M2 are alternately stacked along the Z direction on a lower structure (not shown). The lower structure can be a substrate or a peripheral circuit, and can include various other structures. The first material layer M1 is formed to include an insulating material such as an oxide layer. For example, the first material layer M1 can be a silicon oxide material. The second material layer M2 is formed to include a conductive material, which serves as a gate line GL, such as a drain select line, a word line, or a source select line. The second material layer M2 can be formed to include a metal such as tungsten (W), molybdenum (Mo), cobalt (Co), and nickel (Ni), or a semiconductor material such as silicon (Si) or polycrystalline silicon (Poly-Si). Each first material layer M1 in the first material layer M1 is formed to have a first thickness T1, and each second material layer M2 in the second material layer M2 is formed to have a second thickness T2. The second thickness T2 can be equal to or less than the first thickness T1.

[0093] refer to Figure 8B , an etching process is performed to form an opening PR passing through the material layers M1 and M2. The opening PR may have a circular or elliptical shape in the XY plane.

[0094] To form the openings PR in a direction perpendicular to the material layers M1 and M2, an etching process is performed, for example, using a dry etching method. For example, an anisotropic dry etching process can be performed. The openings PR are formed to have a first width W1 or diameter. For example, the spaces between the first material layers M1 are the openings PR in the first width W1 or diameter, and the openings PR are formed so that the spaces between the second material layers M2 have the first width W1. When the openings PR are formed, the surfaces of each of the material layers M1 and M2 are exposed through the openings PR.

[0095] Referring to Figure 8C , an etching process is performed to remove a portion of the second material layers M2 exposed through the openings PR. To selectively remove the portion of the second material layers M2, an etchant having a higher selectivity to the second material layers M2 than to the first material layers M1 is used. The region in which the portion of the second material layers M2 is removed is referred to as a first recess 1RC. For example, the second material layers M2 are removed by a first distance D1. As a result, the width W3 or diameter / distance between the second material layers M2 in which the first recess 1RC is formed is greater than the first width W1 or diameter. The third width W3 is (2xD1)+W1. The third width W3 can be equal to or less than Figure 4A the second width W2.

[0096] Referring to Figure 8D , a tunnel insulating layer TX is selectively formed on the surfaces of the second material layers M2 exposed through the first recess 1RC. The tunnel insulating layer TX can be formed using an oxidation process.

[0097] Referring to Figure 8E , a charge trap layer CT is formed in the remaining spaces of the first recess 1RC in which the tunnel insulating layer TX is formed. Figure 8D The charge trap layer CT can be formed to include polysilicon. For example, after the polysilicon for the charge trap layer CT is formed within the openings PR to fill the first recess 1RC, the polysilicon can be formed on the surfaces of the first material layers M1. An etching process can be performed to remove the polysilicon formed on the surfaces of the first material layers M1, while the polysilicon filled in the first recess 1RC remains. Because the charge trap layer CT is formed in the regions in which the second material layers M2 are positioned, each of the charge trap layers CT is formed in the second thickness T2.

[0098] Referring to Figure 8FThe protrusions PT are selectively formed on the surface of the charge trap layer CT exposed through the openings PR. For example, the protrusions PT can be formed using an in-situ method after the charge trap layer CT is formed. The protrusions PT can be formed using a method of growing the protrusions PT from the respective charge trap layers CT. Since the area at the center of the protrusions PT in the Z direction is larger than the area at the top edge and the bottom edge of the protrusions PT of the charge trap layer CT exposed through the openings PR, the protrusions PT grow faster at the center of the charge trap layer CT. Accordingly, the protrusions PT are formed to have a curved surface. Since the protrusions PT extend in the direction of the central axis AX of the openings PR, the width between the protrusions PR positioned on the same layer in the Z direction is a fourth width W4 narrower than the first width W1.

[0099] Referring to Figure 8G A barrier layer BX is formed along the surfaces of the protrusions PT and the first material layer M1 exposed in the openings PR. The barrier layer BX includes barrier layers B1 to B3. For example, a first barrier layer B1 is formed along the surfaces of the first material layer M1 and the protrusions PT exposed through the openings PR. A second barrier layer B2 is formed along the surfaces of the first barrier layer B1 exposed through the openings PR. A third barrier layer B3 is formed along the surfaces of the second barrier layer B2 exposed through the openings PR. Each of the barrier layers B1, B2, and B3 can be formed in the X direction with the same thickness. Since the barrier layers B1 to B3 are formed along the surfaces of the protrusions PT and the first material layer M1, the barrier layers B1 to B3 formed on the protrusions PT have a convex curved surface. The barrier layer BX can be formed to have a cylindrical shape with a non-flat side surface.

[0100] Referring to Figure 8H A channel layer CH is formed along the innermost surface of the barrier layer BX exposed through the openings PR. For example, the channel layer CH is formed along the surface of the third barrier layer B3. Since the barrier layer BX is formed in a cylindrical shape, the channel layer CH is also formed in a cylindrical shape. In this example, the innermost surface of the channel layer CH is cylindrical and straight in the Z direction, and the outermost surface of the channel layer CH is non-flat and follows the contour of the third barrier layer B3, including flat portions alternating with concave portions that cooperate with convex portions of the third barrier layer B3. The channel layer CH can be formed to include polysilicon. The channel layer CH between the protrusions PT is formed to be thicker than each of the barrier layers B1 to B3 in the X direction.

[0101] Referring to Figure 8I A core pillar CP is formed in the region surrounded by the channel layer CH. The core pillar CP can include an insulating material or a conductive material and is filled into the region surrounded by the channel layer CH. Accordingly, a cell plug CPL including the barrier layer BX, the channel layer CH, and the core pillar CP is formed.

[0102] Figures 9A-9K is a view illustrating a second structure of a memory device formed using a second method of manufacturing the second structure.

[0103] During the second method of manufacturing the second structure, a third material layer M3 of a material different from the second material layer M2 is formed instead of Figure 8A the second material layer M2. The second material layer M2 is filled into an area in which the third material layer M3 is removed in a subsequent process. The second method of manufacturing the second structure is described in detail.

[0104] Referring to Figure 9A , first material layers M1 and third material layers M3 are alternately stacked along a Z direction on a lower structure (not shown). The lower structure can be a substrate or a peripheral circuit, and can include various structures. The first material layers M1 can be formed to include an insulating material such as an oxide layer. For example, the first material layers M1 can be a silicon oxide material. The third material layers M3 can be formed to include a material having an etching selectivity different from that of the first material layers M1 used as a sacrificial layer. The third material layers M3 can be formed to include a nitride material. The third material layers M3 can be formed to include a silicon nitride material. Each of the first material layers M1 is formed to have a first thickness T1, and each of the third material layers M3 is formed to have a second thickness T2. The second thickness T2 is equal to or smaller than the first thickness T1.

[0105] Referring to Figure 9B , an etching process is performed to form openings PR through the material layers M1 and M3. The openings PR can have a circular or elliptical shape in an XY plane.

[0106] To form the openings PR in a direction perpendicular to the material layers M1 and M3, the etching process is performed using, for example, a dry etching method. For example, an anisotropic dry etching process can be performed. The openings PR are formed to have a first width W1 or diameter. For example, spaces between the first material layers M1 are the openings PR at the first width W1 or diameter, and the openings PR are formed such that spaces between the third material layers M3 have the first width W1. When the openings PR are formed, surfaces of each of the material layers M1 and M3 are exposed through the openings PR.

[0107] Referring to Figure 9C , an etching process is performed to remove a portion of the third material layer M3 exposed through the openings PR. To selectively remove the portion of the third material layer M3, an etchant having a selectivity higher to the third material layer M3 than to the first material layer M1 is used. An area in which the portion of the third material layer M3 is removed is referred to as a first recess 1RC. For example, the third material layer M3 is removed by a first distance D1.

[0108] Referring to Figure 9D , a tunnel insulating layer TX is selectively formed on a surface of the third material layer M3 exposed through the first recess 1RC. The tunnel insulating layer TX can be formed using an oxidation process. The tunnel insulating layer TX is formed within the first recess 1RC from a portion of the third material layer M3 by the oxidation process.

[0109] Referring to Figure 9E , a charge trap layer CT is formed in Figure 9D a remaining space of the first recess 1RC in which the tunnel insulating layer TX is formed. The charge trap layer CT can be formed to include polysilicon. For example, after the polysilicon for the charge trap layer CT is formed within the opening PR to fill the first recess 1RC, the polysilicon can be formed on a surface of the first material layer M1. An etching process can be performed to remove the polysilicon formed on the surface of the first material layer M1, while the polysilicon filled in the first recess 1RC remains. Since the charge trap layer CT is formed in an area in which the third material layer M3 is positioned, each of the charge trap layers CT has a second thickness T2.

[0110] Referring to Figure 9F , a protrusion PT is selectively formed on a surface of the charge trap layer CT exposed through the opening PR. For example, the protrusion PT can be formed using an in-situ method after the charge trap layer CT is formed. The protrusion PT can be formed using a method of growing the protrusion PT from the corresponding charge trap layer CT. Since an area at a center of the protrusion PT in the Z direction is greater than areas at a top edge and a bottom edge of the charge trap layer CT exposed through the opening PR, the protrusion PT grows faster at the center of the charge trap layer CT. Accordingly, the protrusion PT is formed to have a curved surface. Since the protrusion PT extends in a direction of the central axis AX of the opening PR, a width between the protrusions PR positioned on the same layer in the Z direction is a fourth width W4 narrower than the first width W1.

[0111] Referring to Figure 9G , a barrier layer BX is formed along surfaces of the protrusion PT and the first material layer M1 exposed in the opening PR. The barrier layer BX includes first to third barrier layers B1 to B3. For example, the first barrier layer B1 is formed along surfaces of the first material layer M1 and the protrusion PT exposed through the opening PR. The second barrier layer B2 is formed along a surface of the first barrier layer B1 exposed through the opening PR. The third barrier layer B3 is formed along a surface of the second barrier layer B2 exposed through the opening PR. Since the barrier layers B1 to B3 are formed along the surfaces of the protrusion PT and the first material layer M1, the barrier layers B1 to B3 formed on the protrusion PT have a convex curved surface. The barrier layer BX can be formed to have a cylindrical shape with an uneven side surface.

[0112] Referring to Figure 9H, a channel layer CH is formed along the innermost surface of the barrier layer BX exposed by the opening PR. For example, the channel layer CH is formed along the surface of the third barrier layer B3. Because the barrier layer BX is formed into a cylindrical shape, the channel layer CH is also formed into a cylindrical shape. In this example, the innermost surface of the channel layer CH is cylindrical and straight in the Z direction, while the outermost surface of the channel layer CH is uneven and follows the contour of the third barrier layer B3, including flat portions alternating with concave portions that cooperate with the convex portions of the third barrier layer B3. The channel layer CH can be formed to include polycrystalline silicon. The channel layer CH between the protrusions PT is formed to be thicker than each of the barrier layers B1 to B3 in the X direction.

[0113] refer to Figure 91 The core column CP is formed in the region surrounded by the channel layer CH. The core column CP may include an insulating material or a conductive material and is filled into the region surrounded by the channel layer CH. Thus, a cell plug CPL including the barrier layer BX, the channel layer CH, and the core column CP is formed.

[0114] refer to Figure 9J ,like Figure 2 As shown, a trench is formed in the slit region SLT that divides the memory block, and an etching process is performed to remove the third material layer M3 exposed by the trench. The region where the third material layer M3 is removed is referred to as a second recess 2RC. The region of the first material layer M1 and the region of the tunnel insulation layer TX are exposed through the second recess 2RC.

[0115] refer to Figure 9K , forming a second material layer M2 on Figure 9J For example, the second material layer M2 is formed by referring to Figure 9J and Figure 2 The depicted slit region SLT fills the second recess 2RC.

[0116] Figure 10A and Figure 10B is a diagram illustrating a view of a memory block and a portion of a first structure during a program operation of a program method according to an embodiment of the present disclosure.

[0117] refer to Figure 10AThe programming operation of the memory block is performed in units of pages. For example, the programming operation is performed in units of pages connected to the selected word line Sel WL. During the programming operation of the memory block, a program enable voltage Val is applied to the selected bit line Sel BL, and a program inhibit voltage Vin is applied to the unselected bit line Unsel BL. According to one embodiment, the program enable voltage Val is 0 V or a negative voltage (-) lower than 0 V, and the program inhibit voltage Vin is a positive voltage (+) higher than 0 V. A source voltage Vsl is applied to the source line SL. The source voltage Vsl is at a ground voltage or a negative voltage. A turn-on voltage Von is applied to the drain select line DSL and the source select line SSL. The turn-on voltage Von is a positive voltage (+) higher than 0 V. A program voltage Vpgm is applied to the selected word line Sel WL, and a pass voltage Vpass is applied to the unselected word line Unsel WL. According to one embodiment, the program voltage Vpgm is a negative voltage (-) lower than 0 V, and the pass voltage Vpass is a positive voltage (+) higher than 0 V.

[0118] As described above, the program voltage Vpgm applied to the selected word line Sel WL is set to a negative voltage (-), as described with reference to Figure 10B .

[0119] Referring to Figure 10B , Figure 4A a part of the first structure shown is shown as an example, although the same programming operation can be performed in the second structure shown. Figure 7

[0120] According to one embodiment, since the tunnel insulating layer TX is positioned between the charge trap layer CT and the word lines Sel WL and Unsel WL, and the blocking layer BX is positioned between the charge trap layer CT and the channel layer CH, electrons ("e") tunnel between the charge trap layer CT and the word lines Sel WL and Unself WL. When the program enable voltage Val at a negative voltage (-) level is applied to the selected bit line Sel BL, the potential of the channel layer CH is lowered. When the program voltage Vpgm at a negative voltage (-) level is applied to the selected word line Sel WL, the electrons e included in the selected word line Sel WL tunnel through the tunnel insulating layer TX and move into the charge trap layer CT. The negative voltage (-) level of the program voltage Vpgm can vary. Since the blocking layer BX blocks the electrons e in the charge trap layer CT closest to the selected word line Sel WL from moving into the channel layer CH, the electrons e are trapped in the charge trap layer CT. Since the successive charge trap layers CT in the Z direction are spaced apart from each other, the electrons e trapped in the charge trap layer are maintained in the charge trap layer T.

[0121] ​Because a pass voltage Vpass at a positive voltage (+) level is applied to the unselected word line Unsel_WL, electrons do not flow into the charge trap layer CT closest to the unselected word line Unsel_WL.

[0122] Figure 11A and Figure 11B is a diagram illustrating a view of a portion of a memory block and a first structure during an erase operation of an erase method according to an embodiment of the disclosure.

[0123] Referring to Figure 11A , an erase operation of a memory block is performed in units of memory blocks. During the erase operation of the memory block, a bit line voltage Vbl at a positive voltage (+) level or a negative voltage (-) level is applied to the bit line BL. A source voltage Vsl is applied to the source line SL. The source voltage Vsl is a ground voltage, a negative voltage, or a positive voltage. An on voltage Von is applied to the drain select line DSL and the source select line SSL. The on voltage Von is a positive voltage (+) higher than 0V. An erase voltage Ver is applied to the word line WL. According to one embodiment, the erase voltage Vers is a positive voltage (-) higher than 0V. The positive voltage (+) level of the erase voltage Vers can vary.

[0124] As described above, the erase voltage Vers applied to the word line WL is at a positive voltage (+), as described with reference to Figure 11B .

[0125] Referring to Figure 11B , as described with reference to Figure 10B , because the electrons e are trapped in the charge trap layer CT of the programmed memory cell, during the erase operation, the electrons e trapped in the charge trap layer CT can leak or pass into the word line WL through the tunnel insulating layer TX. To move the electrons e from the charge trap layer CT into the word line WL, the erase voltage Vers at a positive voltage (+) level is applied to the word line WL, and the bit line voltage Vbl at a positive voltage (+) level or a negative voltage (-) level is applied to the channel layer CH.

[0126] Figure 12A and Figure 12B is a diagram illustrating a view of a portion of a memory block and a first structure during a read operation of a read method according to an embodiment of the disclosure.

[0127] Referring to Figure 12A, a read operation of the memory block is performed in units of pages. For example, a read operation is performed in units of pages connected to a selected word line Sel_WL. During a read operation of the memory block, a precharge voltage Vpre at a positive voltage (+) level is applied to the bit line BL. A source voltage Vsl is applied to the source line SL. The source voltage Vsl is at a ground voltage or a negative voltage. An on voltage Von is applied to the drain select line DSL and the source select line SSL. The on voltage Von is set to a positive voltage (+) higher than 0 V. A program voltage Vpgm is applied to the selected word line Sel_WL, and a pass voltage Vpass is applied to the unselected word line Unsel_WL. According to one embodiment, a read voltage Vrd is at a positive voltage (+) higher than 0 V, and a pass voltage Vpass is at a positive voltage (+) higher than 0 V. The read voltage Vrd can vary depending on logical page data.

[0128] Referring to Figure 12B Since the electron e is trapped in the charge trap layer CT of the programmed memory cell MCp, the threshold voltage of the programmed memory cell MCp is higher than the threshold voltage of the erased memory cell MCe. To determine the state of the memory cell, a precharge voltage Vpre at a positive voltage (+) level is applied to the bit line BL, and the potential of the channel layer CH is increased. A read voltage Vrd is applied to the selected word line Sel_WL, and a pass voltage Vpass is applied to the unselected word line Unsel_WL. The pass voltage Vpass is a voltage for forming a channel in the channel layer CH, and the read voltage Vrd is a voltage for determining the threshold voltage of the memory cell connected to the selected word line Sel_WL. For example, among the memory cells connected to the selected word line Sel_WL, no channel is formed in the memory cell whose threshold voltage is higher than the read voltage Vrd, and a channel is formed in the memory cell whose threshold voltage is lower than the read voltage Vrd. As a result, by sensing a voltage change at the bit line BL, data of the memory cell can be read.

[0129] Figure 13 is a diagram illustrating a solid state drive (SSD) system including a memory device of the disclosure.

[0130] Referring to Figure 13 , the SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 can exchange signals with the host 4100 through a signal connector 4001, and receive power through a power connector 4002. The SSD 4200 includes a controller 4210, memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0131] According to an embodiment of the disclosure, each of the memory devices 4221 to 422n is similar to the memory device 1000 described with reference to FIG. 1.Figure 1 、 Figure 4A and / or Figure 7 The memory device 100 described is configured.

[0132] The controller 4210 controls the plurality of memory devices 4221 through 422n in response to signals received from the host 4100. For example, the signals are based on signals of an interface between the host 4100 and the SSD 4200. The signals can be configured according to at least one of interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Express PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wireless Network (Wi-Fi), Bluetooth, NVMe, etc.

[0133] The auxiliary power supply 4230 is connected to the host 4100 through the power supply connector 4002. The auxiliary power supply 4230 receives a power supply voltage from the host 4100 and can be charged. When the power supply from the host 4100 is unreliable or of poor quality, the auxiliary power supply 4230 provides a power supply voltage to the SSD 4200. For example, the auxiliary power supply 4230 can be positioned in the SSD 4200 or can be located outside the SSD 4200. For example, the auxiliary power supply 4230 can be located on a main board and can provide auxiliary power to the SSD 4200.

[0134] The buffer memory 4240 is a buffer memory of the SSD 4200. For example, the buffer memory 4240 temporarily stores data received from the host 4100 or data received from the memory devices 4221 through 422n, or temporarily stores metadata (e.g., a mapping table) of the memory devices 4221 through 422n. The buffer memory 4240 can include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, etc. or a non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc.

[0135] Figure 14 is a diagram illustrating a memory card system including a memory device of the disclosure.

[0136] Referring to Figure 14 The memory system 70000 can be implemented as a memory card or a smart card. The memory system 70000 includes the memory device 1100, the controller 1200, and a card interface 7100.

[0137] The memory device 1100 may be similar to Figure 1 、 Figure 4A and / or Figure 7 The memory device 100 is configured as shown.

[0138] The controller 1200 controls data exchange between the memory device 1100 and the card interface 7100. According to one embodiment, the card interface 7100 may be a secure digital (SD) card interface, a multimedia card (MMC) interface, or the like.

[0139] The card interface 7100 interfaces the host 60000 and the controller 1200 for data exchange according to the protocol of the host 60000. According to one embodiment, the card interface 7100 may support a universal serial bus (USB) protocol, an inter-chip (IC) USB protocol, etc. The card interface 7100 includes, for example, hardware capable of supporting the protocol used by the host 60000, software installed in the hardware, and / or a signal transmission method.

[0140] When the memory system 70000 is connected to the host interface 6200 of the host 60000, such as a PC, tablet PC, digital camera, digital audio player, mobile phone, console video game hardware, or digital set-top box, the interface 6200 communicates data with the memory device 1100 through the card interface 7100 and the controller 1200 under the control of the microprocessor (μP) 6100.

[0141] Although detailed embodiments of the present disclosure are described in this disclosure, it will be understood by those skilled in the art that various modifications, additions, and substitutions related to these embodiments are possible without departing from the scope and technical concepts of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments. All changes within the meaning and equivalent range of the claims are included within their scope.

Claims

1. A memory device, comprising: a channel layer; a blocking layer surrounding the channel layer; a plurality of charge well layers spaced apart from one another and arranged along the blocking layer; a plurality of tunnel insulating layers, each of the plurality of tunnel insulating layers contacting a different charge well layer of the plurality of charge well layers; and a plurality of gate lines, each of the plurality of gate lines contacting a different tunnel insulating layer of the plurality of tunnel insulating layers; wherein each of the plurality of tunnel insulating layers is positioned between a different charge well layer of the plurality of charge well layers and a different gate line of the plurality of gate lines.

2. The memory device of claim 1, wherein the channel layer extends in a direction perpendicular to a substrate.

3. The memory device of claim 1, wherein the blocking layer surrounds the channel layer.

4. The memory device of claim 1, wherein the blocking layer comprises: a first blocking layer contacting the plurality of charge well layers; a second blocking layer contacting the first blocking layer; and a third blocking layer positioned between the second blocking layer and the channel layer.

5. The memory device of claim 4, wherein the first blocking layer and the third blocking layer are formed to comprise an oxide material, and the second blocking layer is formed to comprise a nitride material.

6. The memory device of claim 4, wherein the first blocking layer and the third blocking layer are formed to comprise a high-K material, and the second blocking layer is formed to comprise a low-K material.

7. The memory device of claim 1, wherein the charge well layers are formed to comprise a nitride material.

8. The memory device of claim 1, wherein the charge well layers are formed to comprise at least one of silicon nitride (SiN) and silicon oxynitride (SiON).

9. The memory device of claim 1, further comprising an insulating material positioned along a surface of the blocking layer and between successive charge well layers of the plurality of charge well layers.

10. The memory device of claim 1, wherein each of the plurality of charge well layers comprises a protrusion extending toward the blocking layer.

11. The memory device of claim 10, wherein the protrusion and the plurality of charge well layers are formed to comprise a same material.

12. The memory device of claim 10, wherein an interface of the protrusion contacting the blocking layer is a curved surface.

13. A memory device, comprising: a blocking layer surrounding a channel layer; a plurality of charge well layers spaced apart and arranged along a surface of the blocking layer, each of the plurality of charge well layers comprising a protrusion extending toward the blocking layer; a plurality of tunnel insulating layers, each of the plurality of tunnel insulating layers contacting a different charge well layer of the plurality of charge well layers; and a plurality of gate lines, each of the plurality of gate lines contacting a different tunnel insulating layer of the plurality of tunnel insulating layers.

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