Ferroelectric semiconductor junction field effect transistor, preparation method and application

Abstract

The application discloses a ferroelectric semiconductor junction field effect transistor, a preparation method and application, the transistor can utilize physical characteristics of itself to realize simultaneously optical sensor, storage, synapse, logic in a single device, and the structure comprises source and drain, control gate, channel layer, ferroelectric gate layer, oxide layer and substrate from top to bottom.The channel layer adopts two-dimensional transition metal sulfide semiconductor material, the ferroelectric gate layer adopts two-dimensional ferroelectric semiconductor material, the source and the drain are respectively located at two layers of two-dimensional semiconductor channel, and the control gate is just above the ferroelectric gate layer.The preparation method and application of the ferroelectric semiconductor junction field effect transistor provided by the application can integrate optical signal sensing, data storage, synapse calculation and self-switching logic function in a single transistor, break through the functional division limitation of traditional devices, provide a new path for high-density integrated reconfigurable electronic devices, and effectively balance structural complexity and function density.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of new semiconductor devices, in particular to a ferroelectric semiconductor junction field effect transistor, a preparation method and application. BACKGROUND

[0002] Inspired by the working principle of human brain, neuromorphic computing technology has made important breakthroughs in recent years and has become one of the effective alternatives to make up for the shortcomings of traditional digital computing in power and delay. Neuromorphic hardware, such as field effect transistors, ferroelectric transistors and resistive random access memories, provides a platform for developing diversified neuromorphic architectures to achieve efficient computing and storage operations. In order to build an intelligent computing system that can perform multiple tasks, it is crucial to design homogeneous devices with reconfigurable functions to improve the integration level of modules.

[0003] Two-dimensional materials have atomic thickness and adjustable electrical properties, and can realize reconfigurable switching of multiple functions through material stacking, quickly respond to multi-channel signals, and meet the requirements of neuromorphic chips for low power consumption, compactness and high functional density. At present, the research on reconfigurable devices based on two-dimensional materials involves single-gate transistors (such as ferroelectric transistors, ionic transistors, gradient-doped transistors), multi-gate adjustment, semi-floating gate and other complex structures. Although these two-dimensional reconfigurable devices have made progress in integrating multiple functions to achieve neural network applications, there are still the following problems to be solved:

[0004] (1) Contradiction between functional density and structural complexity. Integrating multiple functions through multi-layer material or gate dielectric stacking will significantly affect the performance of the device due to interface effects and process, leading to unstable performance and complex preparation process, thereby limiting the improvement of functional density.

[0005] (2) Difficulty in integrating reconfigurable logic and synaptic function in a single device. Logic function requires clear 0 / 1 digital state switching, and the voltage of 0 / 1 state needs to be stable in the corresponding state; while synaptic function requires triggering multiple intermediate states by applying a pulse voltage, and the state can be temporarily retained after removing the voltage to support subsequent computing operations. The working mechanisms of the two are significantly different, and it is difficult to seamlessly integrate them in the same device.

[0006] (3) Complexity of function switching method. Devices integrating multiple functions usually require complex switching methods, such as ultraviolet or visible light irradiation, which limits the practical application of the device. SUMMARY

[0007] The present application aims to overcome the shortcomings of the prior art and provides a ferroelectric semiconductor junction field effect transistor, a preparation method and application.

[0008] The application aims to realize the above-mentioned purpose by the following technical scheme: a ferroelectric semiconductor junction field effect transistor, comprising a source electrode, a drain electrode, a control gate, a channel layer, a ferroelectric gate layer, an insulating isolation layer and a substrate.

[0009] The insulating isolation layer is covered on the surface of the substrate, the ferroelectric gate layer is arranged above the insulating isolation layer, and the channel layer and the ferroelectric gate layer are stacked to form a longitudinal heterojunction structure.

[0010] The control gate is arranged at one end of the ferroelectric gate layer and used for applying a gate voltage to regulate the polarization state of the ferroelectric layer, and the source electrode and the drain electrode are arranged at two ends of the channel layer respectively to form a path for carrier injection and collection.

[0011] Further, the channel layer adopts a two-dimensional transition metal sulfide semiconductor material, specifically one of WSe2, MoTe2, WS2 and ReS2, and the thickness is 3-10 nm.

[0012] Further, the ferroelectric gate layer adopts a two-dimensional ferroelectric semiconductor material, specifically one of In2Se3, InSe and SnSe, and the thickness is 40-80 nm.

[0013] Further, the source electrode, the drain electrode and the control gate are all metal Au electrodes, and the thickness is 40-80 nm.

[0014] The insulating isolation layer is an oxide layer, which is a SiO2 layer with a thickness of 50 nm, and the substrate is a highly doped p-type or n-type silicon substrate.

[0015] According to another aspect of the specification, the application further provides a method for preparing the transistor, comprising:

[0016] Step one: substrate cleaning: a p-type silicon (Si) substrate with a 50 nm thick silicon dioxide (SiO2) layer on the surface and a resistivity of 0.001-0.005 Ω·cm is prepared, the substrate surface is cleaned to remove impurities, and the adhesion of subsequent material transfer is ensured.

[0017] Step two: ferroelectric gate layer and channel layer material selection: a tape-assisted mechanical exfoliation method is used to exfoliate In2Se3 and MoTe2 from the bulk crystal of two-dimensional ferroelectric n-type semiconductor In2Se3 and two-dimensional p-type semiconductor MoTe2 to a polydimethylsiloxane substrate (PMDS). The long strip-shaped flakes with a thickness, size and shape meeting the requirements are selected by an optical microscope, wherein the width is 3-10 μm, the length is 15-30 μm, the thickness of the selected In2Se3 is 40-80 nm, and the thickness of the selected MoTe2 is 3-10 nm.

[0018] Step three: ferroelectric gate layer transfer: In2Se3 flakes are preferentially transferred to the surface of the p-type Si / SiO2 substrate by the transfer platform. The peeled In2Se3 flakes are smoothly transferred to the central region of the substrate by the PDMS, and the flakes are tightly attached to the substrate.

[0019] Step four: channel layer transfer: MoTe2 material is accurately transferred to the surface of the ferroelectric gate layer In2Se3 by PDMS, and the two long strip-shaped materials are stacked in a cross shape, forming a channel layer / ferroelectric gate layer heterojunction.

[0020] Step five: electrode preparation: long strip-shaped electrode patterns are patterned at both ends of the channel layer and one end of the ferroelectric gate layer by photolithography, and then metal gold electrodes are prepared by thermal evaporation and metal stripping process, forming source, drain and control gate. According to another aspect of the specification, the application also provides an application of the ferroelectric semiconductor junction field effect transistor as a light sensor, a memory, a heterosynaptic device and a self-switching logic.

[0021] Further, the application of the ferroelectric semiconductor junction field effect transistor as a light sensor specifically includes: in a completely dark environment, a scanning bias of -1 V to 1 V is applied between the source or drain and the control gate, and the heterojunction dark state current is collected; a light spot illuminator is introduced to the active area of the device, and the photocurrent signal under different light intensities is measured synchronously by adjusting the light intensity.

[0022] Further, the application of the ferroelectric semiconductor junction field effect transistor as a memory specifically includes: by applying a programming electric pulse of ±20 V to the substrate for 5 s, the polarization direction of the ferroelectric gate layer is switched; a read voltage is applied between the source and the drain, and data storage is realized according to the high and low resistance states of the channel layer current, wherein high current corresponds to low resistance state "1", and low current corresponds to high resistance state "0".

[0023] Further, the application of the ferroelectric semiconductor junction field effect transistor in a heterosynaptic device specifically includes:

[0024] The source and the drain are used as post-synaptic current reading ends, and the substrate is used as a weight modulation end; before testing, the ferroelectric gate layer is initialized to a polarization upward state, and under a fixed source-drain bias, a sequence of -10~10 V electric pulses is applied to the substrate.

[0025] Negative electric pulses induce enhancement of post-synaptic current, and positive electric pulses cause inhibition of post-synaptic current.

[0026] By adjusting the pulse parameters, the channel layer realizes continuous modulation of multiple conductance states, simulating the short-term / long-term memory conversion function of biological synapses.

[0027] Further, the application of the ferroelectric semiconductor junction field effect transistor to realize self-switching logic specifically includes:

[0028] First, the polarization direction of the ferroelectric gate layer is preprogrammed by applying a ±20 V, 5 s electric pulse to the substrate; the substrate gate voltage is taken as the INA port, the control gate voltage is taken as the INB port, and the current of the channel layer is taken as the output:

[0029] When the polarization direction is upward, only input "00" corresponds to low current output "0", realizing "or non" logic;

[0030] When the polarization direction is downward, only input "11" corresponds to high current output "1", realizing "and non" logic.

[0031] The beneficial effects of the present application: a compact new device structure is constructed by coupling mechanism of two-dimensional material heterojunction and ferroelectric semiconductor, avoiding the interface effect and process complexity caused by multi-layer material or gate dielectric stacking, significantly improving the stability of device performance and simplifying the preparation process, laying the foundation for high functional density integration;

[0032] By utilizing the synergistic effect of the unique ferroelectric polarization storage characteristics and semiconductor transport characteristics of ferroelectric semiconductor materials, the 0 / 1 digital state stable switching required for logic operation and the pulse triggered multiple intermediate state temporary storage function required for synapse simulation are realized in a single device, breaking through the functional integration bottleneck caused by the difference in working mechanism of traditional devices;

[0033] Based on the reconfigurable function switching mode of electrical regulation, without relying on external stimulation conditions such as ultraviolet light, the device can realize convenient switching of logic, storage, synapse, light detection and other functions by applying different forms of voltage signals, and can realize the junction field effect transistor transport characteristics of no hysteresis and steep sub-threshold swing, significantly improving the flexibility and applicability of the device in practical application;

[0034] The device structure has low power consumption characteristics and multi-functional integration capability, which can meet the demand of neuromorphic computing system for high integration, low energy consumption intelligent hardware, and provide core device support for the development of next generation reconfigurable intelligent computing chip. BRIEF DESCRIPTION OF DRAWINGS

[0035] Fig. 1 is a structural schematic diagram of a two-dimensional ferroelectric semiconductor junction field effect transistor (FeJFET);

[0036] Fig. 2 is an optical microscope diagram of a FeJFET prepared by In2Se3 / MoTe2 material;

[0037] Fig. 3 is a transfer and output electrical characteristic curve of the FeJFET;

[0038] Figure 4 shows the photoresponse electrical curves of FeJFET as a photodetector under different optical power densities under 808 nm laser, and the electrical curves of different laser wavelengths under the same optical power density.

[0039] Figure 5 shows the memory resistance state retention characteristic curve and fatigue resistance test curve in the FeJFET memory function application;

[0040] Figure 6 shows the characteristic curves of FeJFET synaptic function as a function of the number of electrical pulses and the long-term enhancement-long-term suppression characteristic curves.

[0041] Figure 7 is a schematic diagram of the input and output terminals of a device using the FeJFET self-switching logic function.

[0042] Figure 8 shows the characteristic curves of the "OR NOT" and "NAND NOT" logic functions implemented in the FeJFET self-switching logic function application. Detailed Implementation

[0043] The following are specific embodiments of the present invention, further illustrating the invention. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms fall within the scope defined by the appended claims.

[0044] Example 1

[0045] like Figure 1 As shown in the figure, an embodiment of the present invention provides a ferroelectric semiconductor junction field-effect transistor (FeJFET), the core structure of which includes: source and drain 1, control gate 2, channel layer 3, ferroelectric gate layer 4, oxide layer 5, and substrate 6. The spatial arrangement and functional division of each structural layer are clearly defined: the oxide layer 5 completely covers the surface of the substrate 6, serving as an insulating isolation layer; the ferroelectric gate layer 4 is stacked on top of the oxide layer 5, constituting the ferroelectric control core of the device; the channel layer 3 and the ferroelectric gate layer 4 are further stacked to form a vertical heterojunction structure, wherein the channel layer 3 serves as a carrier transport channel, and the ferroelectric gate layer 4 serves as a polarization control unit; the control gate 2 is only disposed at one end of the ferroelectric gate layer 4, used to apply a gate voltage to control the polarization state of the ferroelectric layer; the source and drain 1 are symmetrically disposed at both ends of the channel layer 3, forming a pathway for carrier injection and collection. The significant advantage of this structural design is that it can integrate optical signal sensing, data storage, synaptic computation, and self-switching logic functions into a single transistor, achieving multi-functional integration characteristics.

[0046] From the material selection, the channel layer 3 adopts a two-dimensional transition metal sulfide semiconductor material, which can be selected from WSe2, MoTe2, WS2, ReS2, and the thickness is controlled in the range of 3 to 10 nm, which can ensure the quantum confinement effect of the two-dimensional material and maintain good carrier mobility;

[0047] The ferroelectric gate layer 4 adopts a two-dimensional ferroelectric semiconductor material, which can be selected from In2Se3, InSe, SnSe, and the thickness is 40 to 80 nm, which can ensure stable ferroelectric polarization characteristics and facilitate voltage regulation;

[0048] The source and drain 1 and the control gate 2 both adopt a metal Au electrode with a thickness of 40 to 80 nm, which has good ohmic contact between the Au electrode and the two-dimensional material, and can reduce the contact resistance;

[0049] The oxide layer 5 is a SiO2 layer with a thickness of 50 nm, which is used as an insulating medium to effectively isolate the substrate and the upper layer structure;

[0050] The substrate 6 is a highly doped p-type or n-type silicon substrate, which provides structural support and can also be used as a back gate electrode to assist in regulating the channel.

[0051] The core innovation of the present application lies in the unique device structure and regulation mechanism. Unlike the existing technology, which sets the source and drain on two different materials, the source and drain 1 of the present application are located on the same material channel layer 3, and the two-dimensional ferroelectric semiconductor material such as In2Se3 is used as the ferroelectric gate layer 4 to bear the voltage applied by the control gate 2. This design fundamentally changes the regulation mechanism of the device. By switching the polarization direction of the ferroelectric gate layer 4, the carrier depletion and accumulation state of the channel layer 3 can be dynamically regulated, rather than the traditional heterojunction conduction and shutdown. Further, combined with the voltage regulation of the ferroelectric gate 2 and the synergistic effect of the substrate 6 back gate, the FeJFET can realize more diversified function regulation modes, laying a structural foundation for multi-functional integrated applications.

[0052] Example 2

[0053] The preparation method of the ferroelectric semiconductor junction field effect transistor in this embodiment includes the following steps:

[0054] The mechanical exfoliation method assisted by adhesive tape is used to mechanically exfoliate from the bulk crystal of two-dimensional ferroelectric n-type semiconductor In2Se3 and two-dimensional p-type semiconductor MoTe2 to a polydimethylsiloxane substrate, and through optical microscopy, long strip-shaped flakes with thickness, size and shape meeting the requirements are screened out, wherein the width is 3-10 μm, the length is 15-30 μm, the thickness of the selected In2Se3 is 40-80 nm, and the thickness of the selected MoTe2 is 3-10 nm. A p-type silicon (Si) substrate with a 50 nm thick silicon dioxide (SiO2) layer and a resistivity of 0.001-0.005 Ω·cm is prepared, the surface of the substrate is cleaned to remove impurities, and the adhesion in the subsequent material transfer process is ensured. Through the transfer platform, the In2Se3 flakes are preferentially transferred to the surface of the p-type Si / SiO2 substrate. By using the precise positioning function of the transfer platform, the exfoliated In2Se3 flakes are smoothly transferred to the central area of the substrate through the PDMS, ensuring that the flakes are tightly attached to the substrate. The MoTe2 material is precisely transferred to the surface of the ferroelectric gate layer In2Se3 through the PDMS, and the two long strip-shaped materials are stacked in a cross shape, forming a channel layer / ferroelectric gate layer heterojunction; a direct writing lithography system is used to define the electrode pattern on the surface of the double-layer heterostructure, and a 50 nm thick gold (Au) electrode is deposited by thermal evaporation method. The specific steps include: forming a mask in the target area using photoresist, etching the electrode pattern by direct writing lithography technology; after removing the photoresist in the unprotected area, evaporating gold material in a vacuum environment to deposit Au in the patterned area, forming an electrode structure with uniform thickness. Figure 1 The structure diagram of the prepared ferroelectric semiconductor junction field effect transistor is shown in Figure 2 .

[0055] Based on the above electrical characteristics test of the ferroelectric semiconductor junction field effect transistor.

[0056] When a voltage of-1~1 V is applied to the In2Se3 ferroelectric gate layer 4 to regulate the channel current, the device shows p-channel transfer characteristics, as shown in Figure 3 (a), where the abscissa is the voltage V fg applied to the ferroelectric gate layer 4, ranging from-1.0 to 0.5 V; the ordinate is the logarithmic drain current I ds . Under different drain biases V ds (-1 V, -0.5 V, -0.1 V, corresponding to blue, light blue and orange curves), when V cg increases negatively (enhances hole attraction), I ds significantly increases, and the on / off current ratio is more than 10 4 ; the light-colored curve I gs in the figure is the drain current of the FeJFET, which is as low as 10 -11A, fully embodies excellent leakage suppression performance. The MoTe2 material thickness is most suitable when being 3-10 nm, if the thickness is less than 3 nm, the carrier concentration is low, and it is difficult to form ohmic contact between the metal of the source and the drain and the channel; if the thickness is greater than 10 nm, the carrier concentration is too high, and the material gradually changes from p-type to bipolar type or even to partial n-type, at this time, it is difficult to form a good pn junction between MoTe2 and In2Se3 to constitute a junction field effect transistor. The thickness of In2Se3 material needs to be controlled in the range of 40-80 nm, if the thickness is less than 40 nm, the insufficient carrier concentration will increase the ferroelectric gate voltage, resulting in the increase of the device opening voltage; if the thickness is greater than 80 nm, the too high carrier concentration will weaken the distinction between high and low resistance states, and cannot guarantee the synergistic effect of ferroelectricity and semiconductor characteristics. It is worth noting that the p-type transistor has a much higher difficulty in electrode contact interface preparation than the n-type device due to the hole transport characteristics, and the present application successfully constructs a p-type junction field effect transistor, which highlights the innovative advantages of the structure design.

[0057] As shown in (b) of FIG. 1, Figure 3 The horizontal coordinate V ds ranges from-1.0 to 0 V, and the vertical coordinate I ds is in units of μA, the negative current conforms to the p-channel hole transport, in the output characteristic test, different V fg , the low V ds region current changes linearly with the bias voltage, showing ohmic contact characteristics, and the high V ds region shows the saturation behavior of the junction field effect transistor; in the double scanning test, the device has a steep subthreshold swing and negligible hysteresis, which is different from the traditional MOSFET. The junction field effect transistor has no gate dielectric layer, the gate and the channel are directly coupled, and the gate-channel capacitance tends to be infinite in theory, which is the core structural advantage of the steeper subthreshold swing. At the same time, V cg In the process of scanning from-1 to 1 V, In2Se3 does not occur ferroelectric polarization reversal within the ferroelectric coercive field voltage range (-3.5 V~3 V), the device is mainly based on semiconductor carrier modulation rather than ferroelectric reversal mechanism, which further guarantees the stability and controllability of the electrical characteristics, and highlights the potential of FeJFET in low-power and high on-off ratio application scenarios.

[0058] Embodiment 3

[0059] The application method of the photodetector based on the above-mentioned ferroelectric semiconductor junction field effect transistor in this embodiment.

[0060] During the test, first, in a full dark and constant temperature environment, a scanning voltage of-1 V to 1 V is applied between the source (or drain) and the control gate 2 of the In2Se3 / MoTe2 ferroelectric semiconductor junction field effect transistor, and the dark state current-voltage (I-V) characteristic curve (correspondingFigure 4 (a), the horizontal coordinate is the voltage V between the source-drain and the control gate 2 PN , covering the reverse bias, zero bias and forward bias interval, the vertical coordinate is the heterojunction current I on a logarithmic scale PN to expand the current dynamic observation range). In the dark state, the electric field in the reverse bias region suppresses the thermal excitation of carriers, and the current is as low as 10 -12 order of magnitude, the curve is flat; in the forward bias region, carriers are injected with an exponential electric field, and the curve rises steeply. The light response test maintains the same voltage scanning conditions, and uses an 808 nm laser (photon energy 1.53 eV, higher than the In2Se3 band gap 1.35 eV and the MoTe2 multilayer band gap 1 eV, which can efficiently excite photo-generated carriers) to adjust the light intensity (3.1~4970 mW / cm², corresponding to the curve from blue to red in turn). Under reverse bias, the strong electric field quickly separates the photo-generated electron-hole pairs, and the current linearly climbs with the light intensity; near zero bias, the diffusion of photo-generated carriers dominates the transport, and the light current gradually overtakes the dark state; in the forward bias region, the electric field assists the injection of carriers, and the curve slope is steeper under high power. What is particularly key is that the intersection of the curves corresponding to different light powers and the horizontal coordinate (voltage axis) (i.e. the open circuit voltage when the current is zero) gradually shifts to the positive direction as the light power increases, indicating that the stronger the light power, the greater the open circuit voltage, directly confirming that the photovoltaic effect is enhanced with the increase of light intensity. At the same time, the photoelectric current gain in the full voltage interval is more significant as the light intensity increases, further verifying the light intensity response law of the device.

[0061] As shown in (b) of FIG. 17, Figure 4 , the horizontal coordinate is time, recording the timing of 375 nm (ultraviolet band), 532 nm (visible band), 808 nm (near-infrared band), and 1064 nm (near-infrared band) pulsed light; the vertical coordinate is the photocurrent I ph , the test fixed the drain bias voltage at 1 V, and the light power of each wavelength was 500 mW / cm². In the 375 nm band, the device has a clear light response, with a photocurrent of about 3 nA; in the 532 nm band, the matching degree of photon energy and heterojunction band gap is improved, and the light absorption efficiency is enhanced, with a current jump to 10 nA; in the 808 nm band, the photon energy matches the In2Se3 band gap, and the light absorption and carrier transport are optimal, with a response of 22 nA; in the 1064 nm band, the photon energy is lower than the In2Se3 band gap, and the light absorption is mainly performed by MoTe2, and the device also has a clear response in the infrared band.

[0062] Based on the bandgap matching of In2Se3 and MoTe2, the device achieves an effective response in the spectral range of 400~1200 nm (corresponding to photon energies of 1.03~3.1 eV). Combined with the photocurrent gain characteristics under ferroelectric modulation, the enhanced photovoltaic effect and self-powered capability, it is clear that this FeJFET can be used as a broadband photodetector to achieve efficient detection and sensitive response of optical signals in the ultraviolet, visible and near-infrared bands.

[0063] Example 4

[0064] This embodiment describes the application method of the memory based on the aforementioned ferroelectric semiconductor junction field-effect transistor.

[0065] The polarization direction of the In2Se3 ferroelectric gate layer 4 was switched by applying an electrical pulse of ±20 V for 5 s to the device through the Si substrate 6. The +20 V induced the In2Se3 ferroelectric gate layer 4 to polarize upwards. up -20 V induced downward polarization P down The carrier density of the MoTe2 channel layer 3 is modulated by polarization charge. down At this time, the positive charge on the In2Se3 surface repels holes in MoTe2, forming a depletion region and a downward-bending energy band, corresponding to a high-resistivity state (low current); P up At this time, the negative charge on the surface attracts holes to accumulate, the depletion region shrinks, corresponding to a low-resistivity state (high current). After programming, a read voltage of -0.1 V is applied between the source and drain, and the drain current I of the MoTe2 channel layer 3 is acquired using a semiconductor parameter analyzer. ds , Figure 5 The vertical axis is I on a logarithmic scale. ds The high and low resistance states stored in the device are determined based on the magnitude of the current. Figure 5 In the diagram, (a) represents time on the x-axis, and P... down (Blue line) corresponds to high current, maintained at 10. -8 A, P up (Orange line) corresponds to low current, maintained at 10. -10 A. These two resistive states can be stably maintained for more than 500 s under a drain-source bias of -0.1 V, verifying the memory resistive state retention behavior of the device; Figure 5 In (b), the horizontal axis represents the number of cycles. After each ±20 V, 100 ms pulse switching polarization is applied, the current is read at -0.1 V. down Always maintain high current, P up It maintains a low current throughout and shows no significant performance degradation after 100 cycles, exhibiting excellent fatigue resistance, thus enabling non-volatile storage functionality.

[0066] Example 5

[0067] This embodiment is based on the application method of the synapse of the ferroelectric semiconductor junction field-effect transistor described above.

[0068] Using source and drain 1 as readout terminals for postsynaptic current and substrate 6 as modulation terminal for synaptic weight, a programmed gate voltage pulse is applied. Before testing, the In2Se3 of ferroelectric gate layer 4 is initialized to polarization-upward P. up In this state, the MoTe2 channel is in a high-resistivity state due to the wide depletion region of the heterojunction, and the channel current (postsynaptic current PSC) measured at the drain is at an initial low level. Figure 6 As shown in (a), the horizontal axis represents time, the vertical axis represents PSC, and the source-drain bias voltage V is constant. ds =-0.1 V, multiple sets of -7 V, 100 ms negative electrical pulse sequences (20-50 pulses, corresponding to blue, light blue, orange, and light orange curves) were applied through substrate 6: As the number of pulses increased (from 20 to 50), the peak value of PSC gradually increased (the peak value exceeded 30 nA at 50 pulses), and the current decay rate slowed down significantly after the pulse ended. This is because each negative pulse pushes In2Se3 from P up Gradually towards polarization downward P down The flipping process causes the depletion region of the heterojunction to shrink continuously, and the channel conductivity to increase continuously, enabling the device to transition from short-term memory (few pulses, fast decay) to long-term memory (many pulses, slow decay), simulating the consolidation process of biological synapses through "repetitive stimulation to strengthen memory".

[0069] Figure 6 As shown in (b), the horizontal axis represents the number of pulses, and the vertical axis represents PSC. For the first 50 pulses (-7 V, 100 ms, marked in orange), PSC increases approximately linearly with the number of pulses (Long-Term Enhancement (LTP), simulating enhanced synaptic weights). After the 50th pulse, a positive pulse (5 V, 100 ms, marked in blue) is applied, and PSC decreases rapidly (Long-Term Suppression (LTD), simulating weakened synaptic weights). The mechanism lies in the fact that the negative pulse drives In₂Se₃ polarization from P... up To P down Gradually flipping, the depletion region width continuously decreases, and the conductance continuously increases; the positive pulse reverses the polarization from P down To P up The polarization of In2Se3 can be continuously adjusted by controlling the polarization and number of voltage pulses, thereby achieving multi-state continuous control of the MoTe2 channel conductance. This perfectly simulates the weighted plasticity of biological synapses (such as LTP enhancing connections during learning and LTD weakening connections during forgetting). At the same time, the control of the number of pulses from short-term to long-term memory states also matches the dynamic learning characteristics of biological synapses, highlighting the biomimetic application potential of this FeJFET in the field of neuromorphic computing.

[0070] Example 6

[0071] This embodiment is based on the application method of the self-switching logic of the ferroelectric semiconductor junction field-effect transistor described above.

[0072] First, the ferroelectric gate layer 4 is pre-programmed to switch its polarization direction to upward or downward by applying an electrical pulse of ±20 V for 5 s on the substrate 6. The gate voltage on the substrate 6 and the control gate 2 voltage on the ferroelectric gate layer 4 are used as the two logic input ports INA and INB (INA is "1" and "0" respectively at 0.5 V / 0 V, and INB is "1" and "0" respectively at 0 V / −3 V). The current in the channel layer 3 is used as the output port. A schematic diagram of the voltage application method is shown in [the diagram]. Figure 7 When the polarization state is upward P up When inputting "00", the output is "0" for low current; otherwise, it is "1" for high current. Figure 8 The "NOR" logic behavior is shown in (a) above. When the polarization state is downward, P... down When inputting "11", only the high current output "1" is displayed; otherwise, the low current output "0" is displayed. Figure 8 The NAND logic behavior is shown in (b) above. The current ratio of the output "0" and "1" in the two logic states is close to 10. 4 This ensures the reliability of logic state discrimination and low-power operation. Furthermore, the small voltages applied to INA and INB are both within the In2Se3 coercive field range, which can avoid polarization reversal and ensure the stability of the in-memory logic function. Thus, the reconfigurable logic functions of "AND" and "OR" can be achieved in a single transistor by switching the polarization direction of the ferroelectric gate layer 4.

[0073] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0074] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. This application is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A ferroelectric semiconductor junction field-effect transistor, characterized in that, include: Source, drain, control gate, channel layer, ferroelectric gate layer, insulating isolation layer and substrate; The insulating isolation layer covers the substrate surface, the ferroelectric gate layer is disposed above the insulating isolation layer, and the channel layer and the ferroelectric gate layer are stacked to form a vertical heterojunction structure; the channel layer is made of a two-dimensional transition metal sulfide semiconductor material, specifically MoTe2. The ferroelectric gate layer is made of a two-dimensional ferroelectric semiconductor material, specifically In2Se3, with a thickness of 40 to 80 nm; the ferroelectric coercive field voltage range of In2Se3 is -3.5 V to 3 V. MoTe2 material was precisely transferred to the surface of the ferroelectric gate layer In2Se3 using PDMS; The control gate is disposed at one end of the ferroelectric gate layer and is used to apply a gate voltage to regulate the polarization state of the ferroelectric layer. The source and drain are respectively disposed at both ends of the channel layer to form a path for carrier injection and collection. The ferroelectric semiconductor junction field-effect transistor is used as a memory, heterosynthetic device, or to implement self-switching logic. In the application of the ferroelectric semiconductor junction field-effect transistor as a memory, the polarization direction of the ferroelectric gate layer is switched by applying a programming electrical pulse of ±20 V for 5 seconds to the substrate. The heterosynaptic device uses the source and drain as readout terminals for postsynaptic current, and the substrate as a modulation terminal for synaptic weight to apply a programmed gate voltage pulse. The ferroelectric semiconductor junction field-effect transistor implements self-switching logic by first applying ±20 V, 5s electrical pulses to the substrate to pre-program the polarization direction of the ferroelectric gate layer; the substrate gate voltage is used as the INA port, the control gate voltage is used as the INB port, and the current of the channel layer is used as the output: INA is 1 and 0 at 0.5 V and 0 V respectively, and INB is 1 and 0 at 0 V and −3 V respectively.

2. The ferroelectric semiconductor junction field-effect transistor according to claim 1, characterized in that, The thickness of the channel layer is 3 to 10 nm.

3. The ferroelectric semiconductor junction field-effect transistor according to claim 1, characterized in that, The source, drain, and control gate are all metal Au electrodes with a thickness of 40 to 80 nm. The insulating isolation layer is an oxide layer, specifically a 50 nm thick SiO2 layer, and the substrate is a highly doped p-type or n-type silicon substrate.

4. The ferroelectric semiconductor junction field-effect transistor according to claim 1, characterized in that, The application of the ferroelectric semiconductor junction field-effect transistor as a memory specifically includes: applying a read voltage between the source and drain, and realizing data storage according to the high and low resistance states of the channel layer current value, wherein high current corresponds to low resistance state "1" and low current corresponds to high resistance state "0".

5. A ferroelectric semiconductor junction field-effect transistor according to claim 1, characterized in that, The specific applications of the self-switching logic implemented by the ferroelectric semiconductor junction field-effect transistor include: When the polarization direction is upward, only inputting "00" corresponds to a low current output of "0", realizing "OR NOT" logic; When the polarization direction is downward, only input "11" corresponds to high current output "1", realizing "NAND" logic.

6. A ferroelectric semiconductor junction field-effect transistor according to claim 1, characterized in that, The specific applications of the ferroelectric semiconductor junction field-effect transistor in heterosynthetic devices include: The source and drain are used as postsynaptic current readout terminals, and the substrate is used as a weighting modulation terminal. Before testing, the ferroelectric gate layer is initialized to the polarization-up state. Under a fixed source-drain bias, a sequence of electrical pulses of -10 to 10 V is applied through the substrate. Negative electrical pulses induce an increase in postsynaptic current, while positive electrical pulses lead to an inhibition of postsynaptic current. By adjusting the pulse parameters, continuous modulation of multiple conductance states can be achieved in the channel layer, simulating the short-term / long-term memory switching function of biological synapses.

7. A method for fabricating the ferroelectric semiconductor junction field-effect transistor according to any one of claims 1-6, characterized in that, include: Step 1: Substrate cleaning: Prepare a p-type silicon substrate with a 50 nm thick silicon dioxide layer on the surface and a resistivity of 0.001-0.005 Ω·cm. Clean the substrate surface to remove impurities and ensure the adhesion of subsequent material transfer. Step 2: Selection of Ferroelectric Gate Layer and Channel Layer Materials: Using a tape-assisted mechanical peeling method, the bulk crystals of two-dimensional ferroelectric n-type semiconductor In2Se3 and two-dimensional p-type semiconductor MoTe2 were peeled down to the polydimethylsiloxane substrate. Long strips with the required thickness, size and shape were selected by optical microscopy for later use. The width was 3-10 μm and the length was 15-30 μm. The selected In2Se3 thickness was 40-80 nm and the MoTe2 thickness was 3-10 nm. Step 3: Ferroelectric gate layer transfer: The In2Se3 sheet is preferentially transferred to the surface of the p-type Si / SiO2 substrate using a transfer platform; the precise positioning function of the transfer platform is used to smoothly transfer the stripped In2Se3 sheet to the central region of the substrate using PDMS, ensuring that the sheet and the substrate are closely adhered. Step 4: Channel layer transfer: MoTe2 material is precisely transferred to the surface of the ferroelectric gate layer In2Se3 using PDMS. The two long strip materials are stacked in a cross shape to form a channel layer / ferroelectric gate layer heterojunction. Step 5: Electrode fabrication: Using photolithography, elongated electrode patterns are patterned at both ends of the channel layer and one end of the ferroelectric gate layer. Then, gold electrodes are fabricated using thermal evaporation and metal lift-off processes to form the source, drain, and control gate.

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