Integrated circuit device

Abstract

An integrated circuit device includes: a substrate including fin-type active regions spaced apart from each other in a first direction and protruding in a second direction, with a separation groove disposed between the fin-type active regions; lamellar partition walls including a lower lamellar partition wall and an upper lamellar partition wall located on the lower lamellar partition wall, the lamellar partition walls extending in a third direction along the partition groove; a sheet barrier pattern on a lower surface and / or at least a portion of a side surface of the upper sheet partition wall; the nanosheet stacking structures are located on the fin-type active region and are spaced apart from each other in the first direction, the lamellar partition walls are located between the nanosheet stacking structures, and each nanosheet stacking structure comprises nanosheets; the gate electrode is located on the fin-type active region and the nanosheet stacking structure; the indented spacer is positioned between the nanosheet and the lamellar partition wall; and a spacer layer between the gate electrode and the sheet partition wall.

Description

TECHNICAL FIELD

[0001] The present inventive concept relates to an integrated circuit device, and more particularly, to an integrated circuit device including a multi-gate metal oxide semiconductor field effect transistor (MOSFET). BACKGROUND

[0002] As the integration of integrated circuit devices has increased, device sizes have decreased to near the minimum state, and scaling of devices has reached near the limit. Therefore, in order to improve the performance of devices, it can be necessary to develop new methods by changing the structure of devices, and thus, integrated circuit devices including transistors having a new structure (e.g., a multi-gate MOSFET) have been proposed. SUMMARY

[0003] The present inventive concept provides an integrated circuit device including a multi-gate metal oxide semiconductor field effect transistor (MOSFET) having improved operating characteristics.

[0004] According to an aspect of the present inventive concept, an integrated circuit device includes: a bulk substrate layer including a pair of fin-type active regions spaced apart from each other in a first direction and protruding in a second direction, wherein a separation groove is provided between the pair of fin-type active regions; a sheet layer separation wall including a lower sheet layer separation wall and an upper sheet layer separation wall on the lower sheet layer separation wall, the sheet layer separation wall extending in a third direction along the separation groove; a sheet layer blocking pattern on at least a portion of a lower surface and / or a side surface of the upper sheet layer separation wall; a pair of nanosheet stack structures on the pair of fin-type active regions and spaced apart from each other in the first direction, wherein the separation groove and the sheet layer separation wall are between the pair of nanosheet stack structures, and each of the pair of nanosheet stack structures includes a plurality of nanosheets; a gate electrode on the pair of fin-type active regions and the pair of nanosheet stack structures and extending in the first direction; a plurality of recessed spacers between the plurality of nanosheets and the sheet layer separation wall; and a plurality of spacer layers between the gate electrode and the sheet layer separation wall, wherein the first direction is parallel to a lower surface of the bulk substrate layer, wherein the second direction is perpendicular to the lower surface of the bulk substrate layer, and wherein the third direction is parallel to a lower surface of the bulk substrate layer and intersects the first direction.

[0005] According to another aspect of the inventive concepts, an integrated circuit device includes: a bulk substrate layer including a pair of fin-type active regions spaced apart from each other in a first direction and protruding in a second direction, with a separation groove provided between the pair of fin-type active regions; a sheet layer separation wall extending in a third direction along the separation groove and including a lower sheet layer separation wall and an upper sheet layer separation wall on the lower sheet layer separation wall, wherein, in the first direction, a width of the lower sheet layer separation wall is greater than a width of the upper sheet layer separation wall; a sheet layer barrier pattern between a lower surface of the upper sheet layer separation wall and an upper surface of the lower sheet layer separation wall; a pair of nanosheet stack structures on the pair of fin-type active regions and spaced apart from each other in the first direction, the separation groove and the sheet layer separation wall being between the pair of nanosheet stack structures, and each of the pair of nanosheet stack structures including a plurality of nanosheets; a pair of source / drain regions on the pair of fin-type active regions and electrically connected to the plurality of nanosheets included in the pair of nanosheet stack structures; a gate electrode on the pair of fin-type active regions and the pair of nanosheet stack structures and extending in the first direction; a plurality of recessed spacers between the plurality of nanosheets and the sheet layer separation wall; and a plurality of spacer layers between the gate electrode and the sheet layer separation wall, wherein the first direction is parallel to a lower surface of the bulk substrate layer, wherein the second direction is perpendicular to the lower surface of the bulk substrate layer, and wherein the third direction is parallel to the lower surface of the bulk substrate layer and intersects the first direction.

[0006] According to another aspect of the inventive concepts, an integrated circuit device includes: a bulk substrate layer including a pair of fin-type active regions spaced apart from each other in a first direction and protruding in a second direction, a separation groove being provided between the pair of fin-type active regions; a sheet layer separation wall including a lower sheet layer separation wall and an upper sheet layer separation wall on the lower sheet layer separation wall, wherein the lower sheet layer separation wall and the upper sheet layer separation wall are spaced apart from each other in the second direction, and the sheet layer separation wall extends in a third direction along the separation groove; a sheet layer barrier pattern on a lower surface and a side surface of the upper sheet layer separation wall and including a material different from a material in the sheet layer separation wall; a pair of nanosheet stack structures on the pair of fin-type active regions and spaced apart from each other in the first direction, the separation groove and the sheet layer separation wall being between the pair of nanosheet stack structures, and each of the pair of nanosheet stack structures including a plurality of nanosheets; source / drain regions on the pair of fin-type active regions and electrically connected to the plurality of nanosheets included in the pair of nanosheet stack structures; a gate electrode on the pair of fin-type active regions and the pair of nanosheet stack structures and extending in the first direction; a gate insulating layer between the gate electrode and the plurality of nanosheets included in the pair of nanosheet stack structures and between the gate electrode and the pair of fin-type active regions; a plurality of recessed spacers between the plurality of nanosheets and the sheet layer separation wall; and a plurality of spacer layers between the gate electrode and the sheet layer separation wall, wherein a thickness of each of the plurality of spacer layers on a side surface of the sheet layer separation wall in the first direction is less than a thickness of each of the plurality of recessed spacers in the first direction, wherein a width of the upper sheet layer separation wall is less than a width of the lower sheet layer separation wall in the first direction, wherein the first direction is parallel to a lower surface of the bulk substrate layer, wherein the second direction is perpendicular to the lower surface of the bulk substrate layer, and wherein the third direction is parallel to the lower surface of the bulk substrate layer and intersects the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0007] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a layout illustrating an integrated circuit device according to some embodiments; FIG. 2A , FIG. 2B , FIG. 2C , FIG. 2D , FIG. 2E ,FIG. 2F FIG. 2G FIG. 2H FIG. 2I FIG. 2J FIG. 2K FIG. 2L FIG. 2M FIG. 2N FIG. 2O FIG. 2P FIG. 2Q FIG. 2R FIG. 2S FIG. 2T FIG. 2U FIG. 3A FIG. 3B FIG. 3C FIG. 4A FIG. 4B FIG. 5A FIG. 5B FIG. 6A FIG. 6B FIG. 7A FIG. 7B FIG. 8A FIG. 8B FIG. 9A FIG. 9B FIG. 10A FIG. 10B FIG. 11A FIG. 11B FIG. 12A FIG. 12B FIG. 13A FIG. 13B FIG. 14A FIG. 14B are vertical cross-sectional views and perspective views for describing a method of manufacturing an integrated circuit device according to some embodiments; FIG. 15A FIG. 15B FIG. 15C FIG. 15D are vertical cross-sectional views showing an integrated circuit device according to some embodiments; FIG. 16A FIG. 16B FIG. 16C FIG. 16D FIG. 16E FIG. 16F FIG. 16G are vertical cross-sectional views for describing a method of manufacturing an integrated circuit device according to some embodiments; FIG. 17 is a vertical cross-sectional view showing an integrated circuit device according to some embodiments; FIG. 18A FIG. 18B FIG. 18C FIG. 18D FIG. 18E FIG. 18F FIG. 18G ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​is a vertical cross-sectional view for describing a method of manufacturing an integrated circuit device according to some embodiments; FIG. 19 is a vertical cross-sectional view showing an integrated circuit device according to some embodiments; FIG. 20A and FIG. 20B and FIG. 21A and FIG. 21B is a vertical cross-sectional view showing an integrated circuit device according to some embodiments; FIG. 22 and FIG. 23 is a vertical cross-sectional view showing an integrated circuit device according to some embodiments. DETAILED DESCRIPTION

[0008] FIG. 1 is a layout showing an integrated circuit device according to some embodiments.

[0009] Referring to FIG. 1 , the integrated circuit device 1 can include a plurality of slice wall spacers SWS extending along a first horizontal direction (e.g., an X direction) (in the first horizontal direction), a plurality of fin-type active regions FA, a plurality of gate electrodes GL extending along a second horizontal direction (e.g., a Y direction) (in the second horizontal direction), and at least one gate cut structure PCT extending along the first horizontal direction (e.g., the X direction) (in the first horizontal direction) and cutting at least some gate electrodes (at least one gate electrode) of the plurality of gate electrodes GL. The first horizontal direction (e.g., the X direction) and the second horizontal direction (e.g., the Y direction) can intersect each other (e.g., can be perpendicular). A plurality of nanosheet stack structures NSS can be located at intersections between the plurality of fin-type active regions FA and the plurality of gate electrodes GL. Each of the plurality of nanosheet stack structures NSS can include a plurality of nanosheets NS stacked to be spaced apart from each other in a vertical direction (e.g., a Z direction) (see FIG. 15A and FIG. 15C). The source / drain regions SD can be located on the fin-type active regions FA between a pair of the nanosheet stack structures NSS adjacent to each other among the plurality of nanosheet stack structures NSS in a first horizontal direction (e.g., an X direction). For example, the plurality of nanosheet stack structures NSS and the plurality of source / drain regions SD can be alternately located on the plurality of fin-type active regions FA along the first horizontal direction (e.g., the X direction). For example, the first horizontal direction and the second horizontal direction can be parallel to an upper surface and / or a lower surface of a bulk substrate layer BSUB (to be described later), and the vertical direction can be perpendicular to the upper surface and / or the lower surface of the bulk substrate layer BSUB. As used herein, the expression “and / or” includes any and all combinations of one or more of the associated listed items. An expression such as “at least one of (a), (b), and (c)” when following a list of elements, modifies the entire list of elements and does not modify the individual elements of the list.

[0010] The plurality of nanosheet stack structures NSS can be arranged in rows and columns along the first horizontal direction (e.g., the X direction) and the second horizontal direction (e.g., the Y direction) (in the first horizontal direction and the second horizontal direction). The plurality of nanosheet stack structures NSS can be adjacent to the plurality of sheet layer separation walls SWS and can be arranged in columns along the first horizontal direction (e.g., the X direction) (in the first horizontal direction). A pair of the nanosheet stack structures NSS corresponding to each other among the plurality of nanosheet stack structures NSS can be spaced apart from each other in the second horizontal direction (e.g., the Y direction) with the sheet layer separation wall SWS located therebetween.

[0011] The integrated circuit device 1 can include a plurality of logic units. Each logic unit can include a plurality of circuit elements such as transistors and registers, and can be configured in various ways. The logic unit can include, for example, an AND, NAND, OR, NOR, exclusive OR (XOR), exclusive NOR (XNOR), inverter (INV), adder (ADD), buffer (BUF), delay (DLY), filter (FIL), multiplexer (MXT / MXIT), OR / AND / INVERTER (OAI), AND / OR (AO), AND / OR / INVERTER (AOI), D flip-flop, reset flip-flop, master-slave flip-flop, and / or latch, and the logic unit can constitute a standard cell that performs a logic function.

[0012] The gate electrodes GL split into two parts by the gate cut structures PCT can be spaced apart from each other in the second horizontal direction (e.g., the Y direction) with the gate cut structures PCT located therebetween.

[0013] FIG. 2A 、 FIG. 2B 、 FIG. 2C 、 FIG. 2D 、 FIG. 2E 、 FIG. 2F 、FIG. 2G , FIG. 2H , FIG. 2I , FIG. 2J , FIG. 2K , FIG. 2L , FIG. 2M , FIG. 2N , FIG. 2O , FIG. 2P , FIG. 2Q , FIG. 2R , FIG. 2S , FIG. 2T and FIG. 2U , FIG. 3A , FIG. 3B and FIG. 3C , FIG. 4A and FIG. 4B , FIG. 5A and FIG. 5B , FIG. 6A and FIG. 6B , FIG. 7A and FIG. 7B , FIG. 8A and FIG. 8B , FIG. 9A and FIG. 9B , FIG. 10A and FIG. 10B , FIG. 11A and FIG. 11B , FIG. 12A and FIG. 12B , FIG. 13A and FIG. 13B and FIG. 14A and FIG. 14B are vertical sectional views and perspective views for describing a method of manufacturing an integrated circuit device according to some embodiments. In detail, FIG. 2A , FIG. 2B , FIG. 2C , FIG. 2D , FIG. 2D , FIG. 2E , FIG. 2D , FIG. 2E , FIG. 2F , FIG. 2F , FIG. 2G , FIG. 2H , FIG. 2I , FIG. 2I , FIG. 2J , FIG. 2J , FIG. 2K , FIG. 2K , FIG. 2L , FIG. 2M and FIG. 2N , FIG. 2N , FIG. 2O , FIG. 2O , FIG. 2P , FIG. 2P and FIG. 2Q are vertical sectional views and perspective views for describing a method of manufacturing an integrated circuit device according to some embodiments. In detail, FIG. 2Qa vertical cross-sectional view taken along line A-A' of FIG. 2R , FIG. 2R , FIG. 2S , FIG. 2S , FIG. 2T , FIG. 2U and FIG. 3A is a vertical cross-sectional view taken along line B-B' of FIG. 3B , FIG. 3C , FIG. 4A , FIG. 4B , FIG. 4A and FIG. 4B is a vertical cross-sectional view taken along line C-C' of FIG. 5A , FIG. 5B , FIG. 5A , FIG. 5B , FIG. 6A , FIG. 6B and FIG. 6A , FIG. 6B , FIG. 7A are perspective views corresponding to FIG. 7B , FIG. 7A , FIG. 7B , FIG. 8A , FIG. 8B , FIG. 9A and FIG. 9B .

[0014] Referring to FIG. 9A , a plurality of sacrificial layers SL and a plurality of nanosheets NS can be alternately stacked on the base substrate layer BSUB layer by layer. Each of the plurality of sacrificial layers SL can be located between the base substrate layer BSUB and a lowermost nanosheet NS among the plurality of nanosheets NS and between two nanosheets NS adjacent to each other in a vertical direction (e.g., Z direction) among the plurality of nanosheets NS. Each of the plurality of nanosheets NS and the plurality of sacrificial layers SL can extend parallel to an upper surface (e.g., top surface) of the base substrate layer BSUB. In some embodiments, the plurality of nanosheets NS can be formed to have substantially the same thickness. Alternatively, in some embodiments, a lowermost nanosheet NS among the plurality of nanosheets NS can be thinner than the other nanosheets NS.

[0015] The bulk substrate layer BSUB can include, for example, a semiconductor material such as silicon (Si) and / or germanium (Ge), or a compound semiconductor material such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and / or indium phosphide (InP). In some embodiments, the bulk substrate layer BSUB can include and / or can be formed of a III-V material and / or a IV material. The III-V material can be a binary, ternary, or quaternary compound semiconductor material including at least one element from group III and at least one element from group V. The bulk substrate layer BSUB can include a conductive region, for example, a well doped with an impurity or a structure doped with an impurity.

[0016] In some embodiments, the plurality of nanosheets NS can include and / or can be formed of a material having the same or similar etching characteristics as a material of the bulk substrate layer BSUB. The plurality of sacrificial layers SL can include and / or can be formed of a material having etching selectivity with respect to a material of the plurality of nanosheets NS. In some embodiments, each of the plurality of nanosheets NS and the bulk substrate layer BSUB can include a semiconductor material such as Si or Ge. In some embodiments, the plurality of sacrificial layers SL can include a compound semiconductor material such as SiGe. In some embodiments, each of the plurality of nanosheets NS, the bulk substrate layer BSUB, and the plurality of sacrificial layers SL can include a compound semiconductor material such as SiGe. A concentration of Ge atoms among Si atoms and Ge atoms included in each of the plurality of nanosheets NS and the bulk substrate layer BSUB can be different from a concentration of Ge atoms among Si atoms and Ge atoms included in each of the plurality of sacrificial layers SL.

[0017] Referring to FIG. 9B A plurality of hard mask patterns HMK can be formed on the stack structure of the plurality of sacrificial layers SL and the plurality of nanosheets NS, the plurality of nanosheets NS and the plurality of sacrificial layers SL can be patterned by using the plurality of hard mask patterns HMK as etching masks, and portions of the bulk substrate layer BSUB exposed between the patterned resulting structures can also be removed to form the plurality of trenches TRE and the separation grooves WTR. In some embodiments, a buffer layer BFL can be formed on the stack structure of the plurality of sacrificial layers SL and the plurality of nanosheets NS, and then the plurality of hard mask patterns HMK can be formed on the buffer layer BFL. The buffer layer BFL, the plurality of nanosheets NS, and the plurality of sacrificial layers SL can be patterned by using the plurality of hard mask patterns HMK as etching masks. In some embodiments, the buffer layer BFL can include and / or can be formed of an oxide.

[0018] A portion of the base substrate layer BSUB protruding from a lower surface (e.g., a bottom surface) of each of the plurality of trenches TRE and the lower separation recess WTR can be referred to as a fin-type active region FA. The lower separation recess WTR can refer to a portion of the lower separation recess WTR located lower in a vertical direction (e.g., a Z direction) than a lowermost one of the plurality of sacrificial layers SL (or a lowermost one of the plurality of nanosheets NS). A vertical height can be a relative position (e.g., a distance) in the vertical direction (e.g., a Z direction) from a lower surface of the base substrate layer BSUB. A distance farther from the lower surface of the base substrate layer BSUB can be a higher vertical height. A distance closer to the base substrate layer BSUB can be a lower vertical height.

[0019] The plurality of hard mask patterns HMK can extend in a first horizontal direction (e.g., an X direction) and can be spaced apart from each other in a second horizontal direction (e.g., a Y direction). The first horizontal direction (e.g., the X direction) and the second horizontal direction (e.g., the Y direction) can be perpendicular to each other. Each of the plurality of hard mask patterns HMK can include, for example, nitride. For example, each of the plurality of hard mask patterns HMK can include silicon nitride (e.g., can be formed of silicon nitride).

[0020] Each of the plurality of trenches TRE and the lower separation recess WTR can extend in a first horizontal direction (e.g., an X direction). In some embodiments, the plurality of trenches TRE and the plurality of lower separation recesses WTR can be alternately arranged along a second horizontal direction (e.g., a Y direction). The plurality of trenches TRE can be formed such that a horizontal width of each of the plurality of trenches TRE in the second horizontal direction (e.g., the Y direction) is greater than a horizontal width of each lower separation recess WTR in the second horizontal direction (e.g., the Y direction). In some embodiments, each of the plurality of trenches TRE and the lower separation recess WTR can extend in a vertical direction (e.g., a Z direction) and can have a tapered shape in which a horizontal width in the second horizontal direction (e.g., the Y direction) increases.

[0021] Reference FIG. 10AA first material layer CDL1 can be formed on (e.g., covering or overlapping) the plurality of hardmask patterns HMK, the plurality of buffer layers BFL, the plurality of nanosheets NS, the plurality of sacrificial layers SL, and the bulk substrate layer BSUB. The first material layer CDL1 can include (e.g., be formed from) an insulating material. For example, the first material layer CDL1 can include (e.g., be formed from) an oxide. In some embodiments, the first material layer CDL1 can conformally cover exposed surfaces of the plurality of hardmask patterns HMK, the plurality of buffer layers BFL, the plurality of nanosheets NS, the plurality of sacrificial layers SL, and the bulk substrate layer BSUB, and can incompletely (partially or completely) fill the plurality of trenches TRE and the separation trenches WTR. The first material layer CDL1 can be in (e.g., partially fill) the plurality of trenches TRE and the separation trenches WTR. For example, the first material layer CDL1 can be formed by using thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), metal-organic ALD (MOALD), and / or metal-organic CVD (MOCVD).

[0022] Referring to FIG. 10B A second material layer CDL2 can be formed on (e.g., covering or overlapping) the first material layer CDL1. The second material layer CDL2 can include (e.g., be formed from) an insulating material. For example, the second material layer CDL2 can include (e.g., be formed from) silicon carbonate (SiOC). In some embodiments, the second material layer CDL2 can conformally cover surfaces of the first material layer CDL1, and can incompletely (partially or completely) fill the plurality of trenches TRE and the separation trenches WTR. The second material layer CDL2 can be in (e.g., partially fill) the plurality of trenches TRE and the separation trenches WTR. For example, the second material layer CDL2 can be formed by using thermal oxidation, ALD, CVD, PVD, MOALD, and / or MOCVD.

[0023] Referring to FIG. 6A and FIG. 6BThe physical properties of the second material layer CDL2 can be changed to form a third material layer CDL3. For example, a thermal treatment can be performed on the second material layer CDL2 to change the physical properties of the second material layer CDL2 to form the third material layer CDL3. The third material layer CDL3 can include (e.g., can be formed of) an insulating material. Although the first material layer CDL1 can be maintained and only the physical properties of the second material layer CDL2 can be changed to form the third material layer CDL3 in FIG. 10A and FIG. 10B , this is for ease of illustration, and the inventive concepts are not limited thereto. Although the physical properties of the second material layer CDL2 are changed to form the third material layer CDL3, the physical properties of the first material layer CDL1 can also be changed such that the first material layer CDL1 has similar characteristics to the characteristics of the third material layer CDL3. For example, some carbon atoms included in the second material layer CDL2 can diffuse into the first material layer CDL1, and both (each) of the first material layer CDL1 and the third material layer CDL3 can include silicon carbonate having a carbon atom content lower than that of the second material layer CDL2.

[0024] Referring to FIG. 11A , a preliminary lower separation layer SWLP can be formed on (e.g., covering or overlapping) the third material layer CDL3 and filling the separation recesses WTR. The preliminary lower separation layer SWLP can completely (entirely or fully) fill the separation recesses WTR, and can partially fill the plurality of trenches TRE. For example, a thickness of the preliminary lower separation layer SWLP can be 1 / 2 (half) or more (greater than half) of a horizontal distance in the second horizontal direction (e.g., Y direction) between adjacent (facing) third material layers CDL3 in the separation recesses WTR. For example, the preliminary lower separation layer SWLP can include (can be formed of) silicon nitride.

[0025] Referring to FIG. 11B and FIG. 11AThe lower sheet layer separation wall SWL can be formed by removing a portion (e.g., an upper portion) of the preliminary lower separation layer SWLP. The lower sheet layer separation wall SWL can be located in (e.g., can partially fill) the separation groove WTR. When the lower sheet layer separation wall SWL is formed, the preliminary lower separation layer SWLP (all portions of) in (filling the plurality of trenches TRE) can be removed. For example, the lower sheet layer separation wall SWL can fill (at least) a lower portion of the separation groove WTR, and can not fill an upper portion of the separation groove WTR. A vertical height at which an upper surface (e.g., an uppermost surface) of the lower sheet layer separation wall SWL is located can be equal to or higher than a horizontal height of a lower surface (e.g., a bottom surface) of an uppermost nanosheet NS among the plurality of nanosheets NS and lower than a vertical height of an upper surface (e.g., a top surface) of the uppermost nanosheet NS. For example, the upper surface of the lower sheet layer separation wall SWL can overlap the uppermost nanosheet NS among the plurality of nanosheets NS in a second horizontal direction (e.g., a Y direction).

[0026] Referring to FIG. 11B A fourth material layer CDL4 can be formed on (e.g., covering or overlapping) an upper surface (e.g., a top surface) of the lower sheet layer separation wall SWL and a surface of the third material layer CDL3. The fourth material layer CDL4 can conformally cover the upper surface (e.g., the top surface) of the lower sheet layer separation wall SWL and the surface of the third material layer CDL3, and can incompletely (partially or completely) fill the plurality of trenches TRE and the separation groove WTR. For example, the fourth material layer CDL4 can be located in (e.g., can partially fill) the plurality of trenches TRE and the separation groove WTR. The fourth material layer CDL4 can include an insulating material (e.g., can be formed of an insulating material). For example, the fourth material layer CDL4 can include silicon carbonate (e.g., can be formed of silicon carbonate). For example, the fourth material layer CDL4 can be formed by using thermal oxidation, ALD, CVD, PVD, MOALD, and / or MOCVD.

[0027] Referring to FIG. 12AA preliminary upper spacer layer SWUP can be formed on (e.g., covering or overlapping) the fourth material layer CDL4 and (at least partially) fill the upper portion of the spacer trench WTR. The preliminary upper spacer layer SWUP can be located in (e.g., can completely (all or fully) fill) the spacer trench WTR and can be located in (e.g., can partially fill) the plurality of trenches TRE. For example, the preliminary upper spacer layer SWUP can include (e.g., can be formed of) silicon nitride.

[0028] Referring to FIG. 12B and FIG. 12A The upper sheet layer spacer wall SWU can be formed by removing a portion (e.g., an upper portion) of the preliminary upper spacer layer SWUP. The upper sheet layer spacer wall SWU can be in (e.g., can fill a portion of) the upper portion of the spacer trench WTR. The upper sheet layer spacer wall SWU can partially fill the upper portion of the spacer trench WTR. At the same time of forming the upper sheet layer spacer wall SWU, the preliminary upper spacer layer SWUP (all portions thereof) located in (filling) the plurality of trenches TRE can be removed. For example, the upper sheet layer spacer wall SWU can not fill the portion of the upper portion of the spacer trench WTR. A vertical height at which an upper surface (e.g., an uppermost surface) of the upper sheet layer spacer wall SWU is located can be higher than a vertical height of an upper surface of an uppermost nanosheet NS among the plurality of nanosheets NS and lower than a vertical height of an upper surface (e.g., a top surface) of the hard mask pattern HMK. For example, the upper surface of the upper sheet layer spacer wall SWU can overlap the hard mask pattern HMK and / or the buffer layer BFL in the second horizontal direction (e.g., the Y direction). In the second horizontal direction (e.g., the Y direction), a horizontal width of the upper sheet layer spacer wall SWU can be less than a horizontal width of the lower sheet layer spacer wall SWL. For example, in the second horizontal direction (e.g., the Y direction), the horizontal width of the upper sheet layer spacer wall SWU can be less than the horizontal width of the lower sheet layer spacer wall SWL by twice a thickness of the fourth material layer CDL4.

[0029] The upper sheet layer spacer wall SWU and the lower sheet layer spacer wall SWL can constitute a sheet layer spacer wall SWS. The upper sheet layer spacer wall SWU and the lower sheet layer spacer wall SWL can be spaced apart from each other in the vertical direction (e.g., the Z direction) (by the fourth material layer CDL4). A portion of the fourth material layer CDL4 can be located between the upper sheet layer spacer wall SWU and the lower sheet layer spacer wall SWL.

[0030] Referring to FIG. 12B and FIG. 13AThe physical properties of the portion of the fourth material layer CDL4 that is exposed to the exterior and the portion of the third material layer CDL3 that is in contact with the portion of the fourth material layer CDL4 can be changed to form a fifth material layer CDL5. The fifth material layer CDL5 can comprise an insulating material (e.g., can be formed from an insulating material).

[0031] The remaining (unchanged) portion of the third material layer CDL3 can remain as the first insulating pattern CDL3P, and the remaining (unchanged) portion of the fourth material layer CDL4 can remain as the sheet layer barrier pattern CDL4P. The first insulating pattern CDL3P can be located between the sheet layer separation wall SWs and the first material layer CDL1, and the sheet layer barrier pattern CDL4P can be located on the side surface and the lower surface (e.g., the bottom surface) of the upper sheet layer separation wall SWU (e.g., can cover or overlap the side surface and the lower surface (e.g., the bottom surface) of the upper sheet layer separation wall SWU). A portion of the sheet layer barrier pattern CDL4P can be located between the upper sheet layer separation wall SWU and the lower sheet layer separation wall SWL.

[0032] Referring to FIG. 1A together with FIG. 1B, FIG. 13B and FIG. 14A The fifth material layer CDL5 and the portion of the first material layer CDL1 that is in contact with the fifth material layer CDL5 can be removed. The (remaining) portion of the first material layer CDL1 can remain as the second insulating pattern CDL1P. For example, the portion of the first material layer CDL1 that is in contact with the first insulating pattern CDL3P can remain as the second insulating pattern CDL1P.

[0033] Referring to FIG. 1A together with FIG. 1B, FIG. 14B A sixth material layer CDL6 can be formed on (e.g., cover or overlap) the exposed surfaces of the base substrate layer BSUB, the plurality of sacrificial layers SL, the plurality of nanosheets NS, the plurality of buffer layers BFL, the plurality of hard mask patterns HMK, the upper sheet layer separation wall SWU, the first insulating pattern CDL3P, the second insulating pattern CDL1P, and the sheet layer barrier pattern CDL4P. The sixth material layer CDL6 can comprise a semiconductor material (e.g., can be formed from a semiconductor material). For example, the sixth material layer CDL6 can comprise silicon (e.g., can be formed from silicon). For example, the sixth material layer CDL6 can be formed by using thermal oxidation, ALD, CVD, PVD, MOALD, and / or MOCVD.

[0034] The sixth material layer CDL6 can include a first layer CDL6A and a second layer CDL6B. The first layer CDL6A can be a portion of the sixth material layer CDL6 on (e.g., covering or overlapping with) a surface of the crystalline material and / or the polycrystalline material, and the second layer CDL6B can be a portion of the sixth material layer CDL6 on (e.g., covering or overlapping with) a surface of the amorphous material. The first layer CDL6A and the second layer CDL6B can have different physical properties. For example, the first layer CDL6A can include (e.g., can be formed of) the crystalline material and / or the polycrystalline material, and the second layer CDL6B can include (e.g., can be formed of) the amorphous material. In some embodiments, the first layer CDL6A can be a portion of the sixth material layer CDL6 on (e.g., covering or overlapping with) a surface of the semiconductor material, and the second layer CDL6B can be a portion of the sixth material layer CDL6 on (e.g., covering or overlapping with) a surface of the insulating material. For example, the first layer CDL6A can be located on (e.g., can conformally cover or can overlap with) the exposed surfaces of the bulk substrate layer BSUB, the plurality of sacrificial layers SL, and the plurality of nanosheets NS, and the second layer CDL6B can be located on (e.g., can cover or can overlap with) the exposed surfaces of the plurality of buffer layers BFL, the plurality of hardmask patterns HMK, the upper sheet layer separation wall SWU, the first insulating pattern CDL3P, the second insulating pattern CDL1P, and the sheet layer blocking pattern CDL4P.

[0035] Reference is made to FIG. 9AA seventh material layer CDL7 can be formed on (e.g., overlying or overlapping) the sixth material layer CDL6. The seventh material layer CDL7 can have a thickness large enough to cover an entire uppermost end of the sixth material layer CDL6. The seventh material layer CDL7 can include (e.g., be formed of) an insulating material. For example, the seventh material layer CDL7 can include (e.g., be formed of) silicon oxide, silicon nitride, silicon oxynitride, and / or a combination thereof.

[0036] Referring collectively to FIG. 9B and FIG. 14A A physical property of a portion of the sixth material layer CDL6 can be changed. For example, a portion of the sixth material layer CDL6 located in the plurality of trenches TRE can be oxidized to form a portion of the seventh material layer CDL7. For example, by changing (e.g., oxidizing) the physical property of the portion of the sixth material layer CDL6 to the physical property of the seventh material layer CDL7, the seventh material layer CDL7 can expand to include the portion of the sixth material layer CDL6. A remaining portion of the sixth material layer CDL6 can remain as the overlying pattern CDL6P. The overlying pattern CDL6P can be located on (e.g., overlying or overlapping) an upper surface (e.g., a top surface) of the hardmask pattern HMK. The overlying pattern CDL6P can be located on (upper and side surfaces of) the hardmask pattern HMK, (an upper surface of) the upper sheet separation wall SWU, (an upper surface of) the first insulating pattern CDL3P, (an upper surface of) the second insulating pattern CDL1P, and (an upper surface of) the sheet blocking pattern CDL4P.

[0037] Referring collectively to FIG. 15A and FIG. 15B The overlying pattern CDL6P (e.g., an upper surface) can be exposed by removing a portion of an upper portion of the seventh material layer CDL7. In some embodiments, an upper surface (e.g., a top surface) of the seventh material layer CDL7 removed of the portion of the upper portion of the seventh material layer CDL7 and an upper surface (e.g., a top surface) of the overlying pattern CDL6P can be located at a same vertical height (can be coplanar with each other).

[0038] Referring collectively to FIG. 15C and FIG. 15D A portion of an upper portion of the seventh material layer CDL7 can be further removed such that the overlying pattern CDL6P can protrude from (e.g., be exposed by) an upper surface (e.g., a top surface) of the seventh material layer CDL7 further removed of the portion of the upper portion.

[0039] Referring collectively to FIG. 15A andFIG. 1 A portion of the cover pattern CDL6P can be removed. In some embodiments, a portion of the cover pattern CDL6P located on (e.g., covering or overlapping) the upper surface (e.g., top surface) of the hard mask pattern HMK and a portion of the cover pattern CDL6P located between the (side surface of the) hard mask pattern HMK and the portion (of the side surface) of the seventh material layer CDL7 located in the separation trench WTR can be removed.

[0040] Referring to FIG. 15B and FIG. 1 The plurality of hard mask patterns HMK can be removed.

[0041] Referring to FIG. 15C and FIG. 1 A portion of the upper portion of the seventh material layer CDL7 can be removed to form a device isolation film STI, the device isolation film STI being a remaining portion of the seventh material layer CDL7. For example, the device isolation film STI can include (e.g., can be formed of) silicon oxide, silicon nitride, and / or silicon oxynitride. The device isolation film STI can have a single-layer structure including one type of insulating film or a multi-layer structure including more than one type of insulating film. For example, the device isolation film STI can include two different types of insulating films. For example, the device isolation film STI can include a silicon oxide film and a silicon nitride film. For example, the device isolation film STI can have a three-layer structure (multi-layer structure) including a silicon oxide film, a silicon nitride film, and a silicon oxide film.

[0042] To form the device isolation film STI, a portion of the first insulating pattern CDL3P, a portion of the second insulating pattern CDL1P, a portion of the cover pattern CDL6P, and the plurality of buffer layers BFL can be simultaneously removed while a portion of the upper portion of the seventh material layer CDL7 is removed. For example, from among the first insulating pattern CDL3P and the second insulating pattern CDL1P, a portion (upper portion) of the first insulating pattern CDL3P located above the upper surface (e.g., top surface) of the uppermost nanosheet NS among the plurality of nanosheets NS and a portion (upper portion) of the second insulating pattern CDL1P located above the upper surface (e.g., top surface) of the uppermost nanosheet NS among the plurality of nanosheets NS and a portion of the cover pattern CDL6P located on (e.g., covering or overlapping) the first insulating pattern CDL3P and the second insulating pattern CDL1P can be removed together with the portion of the upper portion of the seventh material layer CDL7.

[0043] The upper sheet layer spacer wall SWU can be surrounded by the cover pattern CDL6P and the sheet layer barrier pattern CDL4P. For example, the sheet layer barrier pattern CDL4P can be located on the side surfaces and the lower surface of the upper sheet layer spacer wall SWU, and the cover pattern CDL6P can be located on the upper surface of the upper sheet layer spacer wall SWU.

[0044] Referring to FIG. 15D A eighth material layer CDL8 can be formed on (e.g., cover or overlap) surfaces of the device isolation film STI, the plurality of sacrificial layers SL, the plurality of nanosheets NS, the cover pattern CDL6P, and the sheet layer barrier pattern CDL4P. The eighth material layer CDL8 can include (e.g., be formed of) an insulating material. For example, the eighth material layer CDL8 can include (e.g., be formed of) silicon oxide. In some embodiments, the eighth material layer CDL8 can be a dummy gate insulating layer. In some embodiments, a portion of the eighth material layer CDL8 that is on (e.g., covers or overlaps) an upper surface (e.g., top surface) of the device isolation film STI can be part of the device isolation film STI. The eighth material layer CDL8 can be on (e.g., cover or overlap) the first insulating pattern CDL3P and the second insulating pattern CDL1P.

[0045] In some embodiments, a vertical height at which an upper surface (e.g., top surface) of the device isolation film STI is located can be (substantially) the same as a vertical height of an upper surface (e.g., top surface) of the fin-type active region FA. For example, the upper surface of the device isolation film STI can be coplanar with the upper surface of the fin-type active region FA. For example, the fin-type active region FA can be a portion of the bulk substrate layer BSUB that is defined by the device isolation film STI.

[0046] Referring to FIG. 15A , FIG. 15A and FIG. 15BA dummy gate electrode DPC can be formed on (e.g., cover or overlap) the eighth material layer CDL8, and then the dummy gate electrode DPC and the eighth material layer CDL8 can be patterned and separated into a plurality of portions. Next, a gate space GSP can be formed on (e.g., cover or overlap) a side surface of each of the patterned dummy gate electrode DPC and the patterned eighth material layer CDL8. The dummy gate electrode DPC can include (e.g., be formed of) polysilicon, and the gate space GSP can include (e.g., be formed of) silicon nitride.

[0047] With reference to FIG. 15C and FIG. 15D A portion of an upper portion of the dummy gate electrode DPC can be removed to expose a portion of an upper portion of the eighth material layer CDL8. The portion of the upper portion of the dummy gate electrode DPC can be removed such that a portion of the eighth material layer CDL8 that is on (e.g., covers or overlaps) an upper surface (e.g., top surface) of an uppermost nanosheet NS among the plurality of nanosheets NS is not exposed.

[0048] With reference to FIG. 1 and FIG. 15A and FIG. 15B and FIG. 15C The portion of the eighth material layer CDL8 that is exposed by removing the portion of the upper portion of the dummy gate electrode DPC can be removed, and then a portion of the cover pattern CDL6P and a portion of the upper sheet separation wall SWU can be removed.

[0049] With reference to FIG. 15D and FIG. 16A and FIG. 16B and FIG. 16CA portion of the upper layer separation wall SWU and a portion of the dummy gate electrode DPC can be removed. A portion of the eighth material layer CDL8 and the device isolation film STI can be exposed by further removing a portion of the dummy gate electrode DPC. Next, a portion of the upper portion of the sheet layer blocking pattern CDL4P can be removed. A portion of the sheet layer blocking pattern CDL4P that is on (e.g., covers or overlaps) the upper surface (e.g., top surface) of the lower sheet layer separation wall SWL can be left (retained) without being removed. For example, only the portion of the sheet layer blocking pattern CDL4P that is on the upper surface of the lower sheet layer separation wall SWL can be left after the portion of the upper portion of the sheet layer blocking pattern CDL4P is removed. In a cross-sectional view, the removed portion of the upper portion of the sheet layer blocking pattern CDL4P can be a portion of the sheet layer blocking pattern CDL4P that extends in a vertical direction (e.g., Z direction).

[0050] Referring to FIG. 16D and FIG. 16E and FIG. 16F and FIG. 16G A portion of the plurality of nanosheets NS and a portion of the plurality of sacrificial layers SL can be exposed by removing the exposed portion of the eighth material layer CDL8.

[0051] Referring to FIG. 16A and FIG. 16B and FIG. 16C and FIG. 16D The exposed portions of the plurality of nanosheets NS and the plurality of sacrificial layers SL, and a portion of the second insulating pattern CDL1P adjacent to the portions of the plurality of nanosheets NS and the plurality of sacrificial layers SL and a portion of the first insulating pattern CDL3P adjacent to the portions of the plurality of nanosheets NS and the plurality of sacrificial layers SL can be removed. A plurality of source / drain regions SD can be formed on (from) the remaining portions of the plurality of nanosheets NS and the plurality of fin-type active regions FA. Next, a ninth material layer CDL9 can be formed on (conformally covering or overlapping) a surface of the plurality of source / drain regions SD, the device isolation film STI, the sheet layer blocking pattern CDL4P, and the dummy gate electrode DPC. The ninth material layer CDL9 can include (e.g., be formed of) an insulating material. For example, the ninth material layer CDL9 can include silicon nitride (e.g., be formed of silicon nitride).

[0052] Each of the plurality of source / drain regions SD can include an embedded SiGe structure including a plurality of epitaxially grown SiGe layers, an epitaxially grown Si layer, and / or an epitaxially grown SiC layer.

[0053] In some embodiments, some of the plurality of source / drain regions SD (a first group of source / drain regions) and other source / drain regions (a second group of source / drain regions) can include impurities of different conductivity types. In some embodiments, the plurality of nanosheets NS (a first group of nanosheets NS) that contact some of the plurality of source / drain regions SD (a first group of source / drain regions) and the plurality of nanosheets NS (a second group of nanosheets NS) that contact other source / drain regions (a second group of source / drain regions) of the plurality of source / drain regions SD can include impurities of different conductivity types. For example, n-type metal-oxide-semiconductor (NMOS) transistors can be formed in portions of some of the plurality of source / drain regions SD (a first group of source / drain regions), and p-type metal-oxide-semiconductor (PMOS) transistors can be formed in portions of other source / drain regions (a second group of source / drain regions) of the plurality of source / drain regions SD. For example, some of the plurality of source / drain regions SD (a first group of source / drain regions) can include n-type impurities, other source / drain regions (a second group of source / drain regions) of the plurality of source / drain regions SD can include p-type impurities, the plurality of nanosheets NS (a first group of nanosheets NS) that contact some of the plurality of source / drain regions SD (a first group of source / drain regions) can include p-type impurities, and the plurality of nanosheets NS (a second group of nanosheets NS) that contact other source / drain regions (a second group of source / drain regions) of the plurality of source / drain regions SD can include n-type impurities.

[0054] Referring to FIGS. 1-3 together FIG. 16E and FIG. 16F A tenth material layer CDL10 can be formed on (e.g., overlying or overlapping) the ninth material layer CDL9. The tenth material layer CDL10 can be an interlayer dielectric layer ILD. For example, the tenth material layer CDL10 can include silicon oxide and / or an insulating material having a lower dielectric constant than silicon oxide (e.g., can be formed from silicon oxide and / or an insulating material having a lower dielectric constant than silicon oxide). In some embodiments, the interlayer dielectric layer ILD can include a tetraethyl orthosilicate (TEOS) film and / or an ultra-low-k (ULK) film having a dielectric constant K of (approximately) 2.2 to (approximately) 2.4. The ULK film can include a SiOC film and / or a SiCOH film.

[0055] Referring to FIGS. 1-3 together FIG. 16G and FIG. 1and FIG. 2G and FIG. 16A After the tenth material layer CDL10 is formed, the dummy gate electrode DPC can be removed (e.g., in a wet etch process, as shown in FIG. 2G and FIG. 16B the remaining portion of the dummy gate electrode DPC after the process shown in FIG. 7). In some embodiments, the dummy gate electrode DPC can be removed by performing a wet etch. To perform the wet etch, an etchant including, for example, HNO3, diluted hydrofluoric acid (DHF), NH4OH, tetramethylammonium hydroxide (TMAH), KOH, and / or a combination thereof (e.g., formed from, for example, HNO3, diluted hydrofluoric acid (DHF), NH4OH, tetramethylammonium hydroxide (TMAH), KOH, and / or a combination thereof) can be used.

[0056] After the plurality of source / drain regions SD is formed, the plurality of nanosheets NS located on each of the plurality of fin-type active regions FA can be referred to as a nanosheet stack structure NSS. Each of the plurality of nanosheet stack structures NSS can include, but is not limited to, four nanosheets NS positioned sequentially upward to be spaced apart from each other in a vertical direction (e.g., Z direction). For example, each of the plurality of nanosheet stack structures NSS can include three nanosheets NS or five or more nanosheets NS.

[0057] Referring to FIG. 16C and ​ and ​ and ​ A portion of the plurality of sacrificial layers SL and a portion of the plurality of nanosheets NS can be exposed by removing the eighth material layer CDL8 exposed due to the removal of the dummy gate electrode DPC.

[0058] Referring to ​ and ​ and ​ and ​ The plurality of gate spaces GS can be formed between the fin-type active region FA and the lowermost nanosheet NS among the plurality of nanosheets NS and between two nanosheets NS among the plurality of nanosheets NS adjacent to each other in a vertical direction (e.g., Z direction) by removing the plurality of sacrificial layers SL.

[0059] Referring to ​ and ​ and ​ and ​After the plurality of sacrificial layers SL is removed, the second insulating pattern CDL1P and the first insulating pattern CDL3P can be divided into a plurality of portions by removing a portion of the second insulating pattern CDL1P inside each of the plurality of gate spaces GS (e.g., overlapping each of the plurality of gate spaces GS in the second horizontal direction (e.g., Y direction)) and a portion of the first insulating pattern CDL3P inside each of the plurality of gate spaces GS (e.g., overlapping each of the plurality of gate spaces GS in the second horizontal direction (e.g., Y direction)) and a portion of the lower sheet layer separation wall SWL in the plurality of gate spaces GS (e.g., overlapping the plurality of gate spaces GS in the second horizontal direction (e.g., Y direction)). For example, a portion of the second insulating pattern CDL1P exposed by the plurality of gate spaces GS and a portion of the first insulating pattern CDL3P exposed by the plurality of gate spaces GS can be removed to expose a portion of the lower sheet layer separation wall SWL. Each of the plurality of gate spaces GS can extend from an end of the nanosheet NS opposite the sheet layer separation wall SWL to a sidewall of the lower sheet layer separation wall SWL. The first insulating pattern CDL3P and the second insulating pattern CDL1P divided into a plurality of portions can be located (in the second horizontal direction (e.g., Y direction)) between the nanosheet NS and the sheet layer separation wall SWL. The stack structure of the first insulating pattern CDL3P and the second insulating pattern CDL1P located between the nanosheet NS and the sheet layer separation wall SWL can be referred to as (collectively as) an indent spacer IDT. A plurality of indent spacers IDT can be located between the sheet layer separation wall SWL and the plurality of nanosheets NS.

[0060] The lower sheet layer separation wall SWL, the upper sheet layer separation wall SWU, the sheet layer barrier pattern CDL4P, and the plurality of indent spacers IDT can together function as a sheet layer separation wall structure located between a pair of nanosheet stack structures NSS adjacent to each other in the second horizontal direction (e.g., Y direction). The sheet layer separation wall structure can be in an indent shape, with the indent spacers IDT spaced apart from each other along the vertical direction (e.g., Z direction) arranged on each of two sides (e.g., opposite sides) in the second horizontal direction (e.g., Y direction).

[0061] Reference is made together ​ and ​A spacer layer SP can be formed on a surface of the lower-layer separation wall SWL exposed in each of the plurality of gate spaces GS. The spacer layer SP can include (e.g., can be formed of) an insulating material. For example, the spacer layer SP can include (e.g., can be formed of) silicon oxide. The spacer layer SP can also be formed at both ends (e.g., opposite ends) in the first horizontal direction (e.g., the X direction) of each of the plurality of gate spaces GS. For example, the spacer layer SP can be on (e.g., can cover or overlap with) the ninth material layer CDL9 (see FIG. 9A) located at both ends (e.g., opposite ends) in the first horizontal direction (e.g., the X direction) of the plurality of gate spaces GS (e.g., can cover or overlap with). That is, the spacer layer SP can be on (e.g., can cover or overlap with) the surface of the lower-layer separation wall SWL and the surface of the ninth material layer CDL9 in each of the plurality of gate spaces GS (e.g., can cover or overlap with). ​ and ​ ) of the plurality of gate spaces GS. That is, the spacer layer SP can be on (e.g., can cover or overlap with) the surface of the lower-layer separation wall SWL and the surface of the ninth material layer CDL9 in each of the plurality of gate spaces GS (e.g., can cover or overlap with).

[0062] Although the thickness (in the second horizontal direction (e.g., the Y direction)) of the spacer layer SP on the side surface of the lower-layer separation wall SWL and the thickness (in the second horizontal direction (e.g., the Y direction)) of the second insulating pattern CDL1P are the same in ​ , the present application is not limited thereto. For example, the thickness (in the second horizontal direction (e.g., the Y direction)) of the spacer layer SP on the side surface of the lower-layer separation wall SWL can be smaller than the thickness (in the second horizontal direction (e.g., the Y direction)) of the indented spacer IDT.

[0063] ​ 、 ​ 、 ​ and ​ are vertical cross-sectional views illustrating an integrated circuit device according to some embodiments. In detail, ​ is a vertical cross-sectional view taken along line A-A' of ​ . ​ is a vertical cross-sectional view taken along line B-B' of ​ . ​ is a vertical cross-sectional view taken along line C-C' of ​ . ​ is an enlarged view of a portion XVD of ​ .

[0064] Reference is made together with ​ 、 ​ 、 ​ and ​The integrated circuit device 1 can be formed by forming a gate insulating layer Gox (e.g., covering or overlapping the surface exposed after the spacer layer SP is formed) on the surface exposed after the spacer layer SP is formed and forming a gate electrode GL (e.g., covering or overlapping the gate insulating layer Gox) on the gate insulating layer Gox. For example, the plurality of gate insulating layers Gox and the plurality of gate electrodes GL can be formed by using a replacement metal gate (RMG) process.

[0065] The gate insulating layer Gox can include a silicon oxide film, a high-k dielectric film, and / or a combination thereof. In some embodiments, the gate insulating layer Gox can have a stack structure of an interface layer and a high-k dielectric film. The interface layer can include a low dielectric material having a dielectric constant of (approximately) 9 or less (e.g., can be formed of a low dielectric material having a dielectric constant of (approximately) 9 or less). For example, the interface layer can include an oxide, a nitride, and / or an oxynitride (e.g., can be formed of an oxide, a nitride, and / or an oxynitride). The high-k dielectric film can include a metal oxide and / or a metal oxynitride (e.g., can be formed of a metal oxide and / or a metal oxynitride). The high-k dielectric film can include a material having a higher dielectric constant than a silicon oxide film (e.g., can be formed of a material having a higher dielectric constant than a silicon oxide film). For example, the high-k dielectric film can have a dielectric constant of (approximately) 10 to (approximately) 25. The high-k dielectric film can have a thickness of (approximately) 10 A to (approximately) 40 A, but the inventive concept is not limited thereto. In some embodiments, the interface layer can be omitted. For example, the gate insulating layer Gox can include HfO2, Al2O3, HfAlO3, Ta2O3, and / or TiO2 (e.g., can be formed of HfO2, Al2O3, HfAlO3, Ta2O3, and / or TiO2).

[0066] The gate electrode GL can include a metal-containing layer for adjusting a work function and a metal-containing layer for gap filling filling an upper space of the metal-containing layer for adjusting a work function. The metal-containing layer for adjusting a work function can include, for example, Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and / or Pd. In some embodiments, the gate electrode GL can have a structure in which a metal nitride layer, a metal layer, a conductive cap layer, and a gap filling metal film are sequentially stacked. The metal nitride layer and the metal layer can include, for example, Ti, Ta, W, Ru, Nb, Mo, and / or Hf. The gap filling metal film can include, for example, a W film and / or an Al film. In some embodiments, the gate electrode GL can have, but is not limited to, a stack structure of TiAlC / TiN / W, a stack structure of TiN / TaN / TiAlC / TiN / W, or a stack structure of TiN / TaN / TiN / TiAlC / TiN / W.

[0067] Reference is made to ​ , ​ , ​ , ​ and ​ Together, the integrated circuit device 1 can include: a bulk substrate layer BSUB including a plurality of fin-type active regions FA protruding in a vertical direction (e.g., Z-direction); a plurality of nanosheet stack structures NSS each including a plurality of nanosheets NS located on the plurality of fin-type active regions FA; a sheet layer separation wall SWS located on the bulk substrate layer BSUB and extending along a first horizontal direction (e.g., X-direction); and a plurality of gate electrodes GL located on the plurality of nanosheet stack structures NSS and extending along a second horizontal direction (e.g., Y-direction) to intersect the plurality of fin-type active regions FA. In some embodiments, the integrated circuit device 1 can further include at least one gate cut structure PCT extending along the first horizontal direction (e.g., X-direction) and cutting across at least some of the plurality of gate electrodes GL. The gate electrodes GL split into two parts by the gate cut structure PCT can be spaced apart from each other in the second horizontal direction (e.g., Y-direction) with the gate cut structure PCT located therebetween.

[0068] The plurality of nanosheet stack structures NSS can be arranged in rows and columns along (in) the first horizontal direction (e.g., X-direction) and the second horizontal direction (e.g., Y-direction). The plurality of nanosheet stack structures NSS can be adjacent to the plurality of sheet layer separation walls SWS and can be arranged in columns along (in) the first horizontal direction (e.g., X-direction). A pair of (adjacent) nanosheet stack structures NSS corresponding to each other among the plurality of nanosheet stack structures NSS and a pair of (adjacent) source / drain regions SD corresponding to each other among the plurality of source / drain regions SD can be spaced apart from each other in the second horizontal direction (e.g., Y-direction) with (at least a portion of) the sheet layer separation wall SWS located therebetween. The pair of (adjacent) source / drain regions SD can be spaced apart from each other in the second horizontal direction (e.g., Y-direction) with (at least a portion of) the sheet layer separation wall SWS located therebetween and the pair of (adjacent) source / drain regions SD are connected to the pair of (adjacent) nanosheet stack structures NSS spaced apart from each other in the second horizontal direction (e.g., Y-direction) with (at least a portion of) the sheet layer separation wall SWS located therebetween.

[0069] Each of the plurality of nanosheets NS included in each of the plurality of nanosheet stack structures NSS can extend parallel to an upper surface (e.g., a top surface) of the fin active region FA (in the second horizontal direction (e.g., in the Y direction)). The plurality of nanosheets NS can be located on the fin active region FA and can be spaced apart from each other along a vertical direction (e.g., the Z direction). One end (in the second horizontal direction (e.g., the Y direction)) of the plurality of nanosheets NS included in the plurality of nanosheet stack structures NSS can face the plurality of sheet layer separation walls SWS.

[0070] The plurality of gate electrodes GL can be located on an uppermost nanosheet NS among the plurality of nanosheets NS and between the plurality of nanosheets NS. A main gate portion MG of the plurality of gate electrodes GL located on the uppermost nanosheet NS and a sub gate portion SG located between the plurality of nanosheets NS can be connected to each other. A spacer layer SP can be located between the sub gate portion SG and the sheet layer separation wall SWS.

[0071] The plurality of gate insulating layers Gox can be located between the plurality of gate electrodes GL and the plurality of nanosheet stack structures NSS including the plurality of nanosheets NS and between the plurality of gate electrodes GL and the plurality of fin active regions FA. Each of the plurality of source / drain regions SD can be connected to the plurality of nanosheets NS included in each of the plurality of nanosheet stack structures NSS. Each of the plurality of source / drain regions SD can be connected to the other end of the plurality of nanosheets NS included in each of the plurality of nanosheet stack structures NSS.

[0072] The plurality of nanosheet stack structures NSS including the plurality of nanosheets NS, the plurality of gate electrodes GL, and the plurality of source / drain regions SD can constitute a plurality of multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0073] A device isolation film STI can be located in the plurality of trenches TRE. The device isolation film STI can define the plurality of fin active regions FA. A ninth material layer CDL9 and a tenth material layer CDL10 can be located on (e.g., cover or overlap) the device isolation film STI and the plurality of source / drain regions SD.

[0074] A pair of nanosheet stack structures NSS adjacent to each other in a second horizontal direction (e.g., Y direction) can be spaced apart from the sheet layer separation wall SWS (by the indented spacer IDT). In some embodiments, the indented spacer IDT can be located between the sheet layer separation wall SWS and an end of each of the plurality of nanosheets NS included in each of the pair of nanosheet stack structures NSS adjacent to each other in the second horizontal direction (e.g., Y direction), while the sheet layer separation wall SWS is located between the pair of nanosheet stack structures NSS adjacent to each other in the second horizontal direction (e.g., Y direction). The indented spacer IDT can have a stack (stacked in the second horizontal direction (e.g., Y direction)) of a first insulating pattern CDL3P in contact with the sheet layer separation wall SWS and a second insulating pattern CDL1P in contact with (an end of) each of the plurality of nanosheets NS.

[0075] Each of the plurality of sheet layer separation walls SWS can include a lower sheet layer separation wall SWL and an upper sheet layer separation wall SWU located on the lower sheet layer separation wall SWL. A portion of the sheet layer separation wall SWS located between a pair of nanosheet stack structures NSS adjacent to each other along (in) the second horizontal direction (e.g., Y direction) can include a portion of the lower sheet layer separation wall SWL and a portion of the upper sheet layer separation wall SWU. A portion of the sheet layer separation wall SWS located between a pair of source / drain regions SD adjacent to each other along (in) the second horizontal direction (e.g., Y direction) can include a portion of the lower sheet layer separation wall SWL, but can not include a portion of the upper sheet layer separation wall SWU.

[0076] A sheet layer blocking pattern CDL4P can be located between the lower sheet layer separation wall SWL and the upper sheet layer separation wall SWU. The sheet layer blocking pattern CDL4P can be (e.g., can cover or overlap) on a lower surface (e.g., a bottom surface) of the upper sheet layer separation wall SWU and two side surfaces (e.g., opposite side surfaces) in the second horizontal direction (e.g., Y direction) located between a pair of nanosheet stack structures NSS adjacent to each other along (in) the second horizontal direction (e.g., Y direction), and can be (e.g., can cover or overlap) on an upper surface (e.g., a top surface) of (at least) a portion of the lower sheet layer separation wall SWL located between a pair of source / drain regions SD adjacent to each other in the second horizontal direction (e.g., Y direction). A cover pattern CDL6P can be located on (e.g., can cover or overlap) an upper surface (e.g., a top surface) of the upper sheet layer separation wall SWU.

[0077] The plurality of lower-tier separation walls SWL can be spaced apart from each other along (in) the second horizontal direction (e.g., Y-direction), and can each extend in the first horizontal direction (e.g., X-direction). In a plan view, the plurality of upper-tier separation walls SWU can be arranged in a matrix to be spaced apart from each other along (in) the first horizontal direction (e.g., X-direction) and the second horizontal direction (e.g., Y-direction).

[0078] The separation recess WTR can be located between the pair of fin-type active regions FA and the pair of nanosheet stack structures NSS adjacent to each other along (in) the second horizontal direction (e.g., Y-direction). A recess width NSD of the separation recess WTR in the second horizontal direction (e.g., Y-direction) can be greater than a lower width LWW of the lower-tier separation wall SWL in the second horizontal direction (e.g., Y-direction). The recess width NSD can be (approximately) 35 nanometers (nm) or less. The recess width NSD can be a distance between the pair of fin-type active regions FA adjacent to each other along (in) the second horizontal direction (e.g., Y-direction). A height (e.g., trench depth TRD) of the fin-type active region FA can be (approximately) 0.5 nm to (approximately) 100 nm, which is a vertical distance from an upper surface (e.g., top surface) of the fin-type active region FA to a lower surface (e.g., bottom surface) of the device isolation film STI.

[0079] The tier separation wall SWS can extend upward from an interior of the separation recess WTR to a position above an uppermost end of the pair of (adjacent) nanosheet stack structures NSS. A lower portion of the lower-tier separation wall SWL can be located between the pair of fin-type active regions FA adjacent to each other along (in) the second horizontal direction (e.g., Y-direction), and an upper portion of the lower-tier separation wall SWL can be located between the pair of nanosheet stack structures NSS adjacent to each other along (in) the second horizontal direction (e.g., Y-direction).

[0080] A vertical height LWU of the uppermost end of the lower sheet layer spacer wall SWL can be equal to (co-planar with) a vertical height of a lower surface (e.g., a bottom surface) of an uppermost nanosheet NS among the plurality of nanosheets NS included in the nanosheet stack structure NSS, or higher than the vertical height of the lower surface (e.g., a bottom surface) of the uppermost nanosheet NS among the plurality of nanosheets NS included in the nanosheet stack structure NSS. The vertical height LWU of the uppermost end of the lower sheet layer spacer wall SWL can be lower than a vertical height NSU of an upper surface (e.g., a top surface) of the uppermost nanosheet NS by a first depth UWD. For example, the first depth UWD can be (approximately) 1 nm to (approximately) 30 nm. In other embodiments, the vertical height LWU of the uppermost end of the lower sheet layer spacer wall SWL can be equal to (co-planar with) the vertical height NSU of the upper surface (e.g., a top surface) of the uppermost nanosheet NS, or higher than the vertical height NSU of the upper surface (e.g., a top surface) of the uppermost nanosheet NS. For example, the vertical height LWU of the uppermost end of the lower sheet layer spacer wall SWL can be equal to, or higher than (approximately) 5 nm than the vertical height NSU of the upper surface (e.g., a top surface) of the uppermost nanosheet NS.

[0081] An uppermost end of the upper sheet layer spacer wall SWU can protrude from an upper surface (e.g., a top surface) of the uppermost nanosheet NS by an upper protrusion height UWH in a vertical direction (e.g., a Z direction). The upper protrusion height UWH can be (approximately) 1 nm to (approximately) 25 nm. The uppermost end of the upper sheet layer spacer wall SWU and the uppermost end of the sheet layer blocking pattern CDL4P can be at the same vertical height (can be co-planar with each other in a vertical direction (e.g., a Z direction)).

[0082] The lower sheet layer spacer wall SWL can have a lower width LWW (in a second horizontal direction (e.g., a Y direction)), and the upper sheet layer spacer wall SWU can have an upper width UWW (in the second horizontal direction (e.g., a Y direction)). In some embodiments, the lower width LWW can be greater than the upper width UWW. For example, the lower width LWW can be greater than the upper width UWW by a thickness of the sheet layer blocking pattern CDL4P. The lower width LWW can be (approximately) 30 nm or less.

[0083] The vertical height LWU of the uppermost end (upper surface) of the lower-tier separation wall SWL can be lower than the vertical height SDU of the uppermost end (upper surface) of the source / drain region SD by a second depth LWD. For example, the second depth LWD can be (approximately) 1 nm to (approximately) 10 nm. In other embodiments, the vertical height LWU of the uppermost end (upper surface) of the lower-tier separation wall SWL can be equal to or higher than the vertical height SDU of the uppermost end (upper surface) of the source / drain region SD. For example, the vertical height LWU of the uppermost end (upper surface) of the lower-tier separation wall SWL can be equal to the vertical height SDU of the uppermost end (upper surface) of the source / drain region SD, or higher than the vertical height SDU of the uppermost end (upper surface) of the source / drain region SD by (approximately) 30 nm.

[0084] From the side surface of the tier separation wall SWS, the spacer layer SP can have a first thickness SPT (in the second horizontal direction (e.g., Y direction)), and the indented spacer IDT can have a second thickness WND (in the second horizontal direction (e.g., Y direction)). The second thickness WND can be greater than the first thickness SPT. For example, the second thickness WND can be (approximately) 10 nm or less, and the first thickness SPT can be (approximately) 0.5 nm to (approximately) 5 nm.

[0085] In the separation recess WTR, the lower-tier separation wall SWL of the tier separation wall SWS and the fin-type active region FA can be spaced apart from each other by a vertical separation distance LWL in the vertical direction (e.g., Z direction), and can be spaced apart from each other by a horizontal separation distance LWS in the second horizontal direction (e.g., Y direction). For example, each of the vertical separation distance LWL and the horizontal separation distance LWS can be (approximately) 10 nm or less. In some embodiments, each of the vertical separation distance LWL and the horizontal separation distance LWS can be (substantially) the same as the second thickness WND. In the separation recess WTR, the stack structure of the first insulating pattern CDL3P and the second insulating pattern CDL1P can be located between the lower-tier separation wall SWL of the tier separation wall SWS and the fin-type active region FA.

[0086] The portion of the gate electrode GL that fills the gate space GS and faces the tier separation wall SWS (i.e., one end of the sub-gate portion SG) can be closer to the tier separation wall SWS than the one end of the nanosheet NS facing the tier separation wall SWS by a proximity distance GND in the second horizontal direction (e.g., Y direction). The proximity distance GND can be (approximately) 7 nm or less. That is, the one end of the sub-gate portion SG facing the tier separation wall SWS can protrude toward the tier separation wall SWS by the proximity distance GND in the second horizontal direction (e.g., Y direction) than the one end of the nanosheet NS.

[0087] In the integrated circuit device 1 according to the present concept, because the portion of the gate electrode GL that fills the gate space GS and faces the sheet layer separation wall SWS (i.e., one end of the sub-gate portion SG) is closer to the sheet layer separation wall SWS than the one end of the nanosheet NS is in the second horizontal direction (e.g., the Y direction) by the adjacent distance GND, the effective channel width can be increased. Also, in the integrated circuit device 1 according to the present concept, because the sheet layer separation wall SWS and the nanosheet NS that serves as a channel region are spaced apart from each other due to the indented spacers IDT, leakage current due to fixed charges can be reduced (e.g., prevented). Thus, the operating characteristics of the integrated circuit device 1 including transistors having multi-gate MOSFETs can be improved.

[0088] In the integrated circuit device 1 according to the present concept, because the sheet layer separation wall SWS includes the lower sheet layer separation wall SWL and the upper sheet layer separation wall SWU that are formed by separate processes, a joint can be prevented from occurring in the sheet layer separation wall SWS, and contamination and / or damage to the plurality of nanosheets NS can be prevented.

[0089] ​ 、 ​ 、 ​ 、 ​ 、 ​ 、 ​ and ​ are vertical cross-sectional views for describing a method of manufacturing an integrated circuit device according to an embodiment. In detail, ​ 、 ​ 、 ​ 、 ​ 、 ​ 、 ​ and ​ are vertical cross-sectional views taken along the line A-A' of ​

[0090] Together with ​ and ​ , a portion of the third material layer CDL3 and a portion of the first material layer CDL1 can be removed. The remaining portion of the third material layer CDL3 can be left as a first insulating pattern CDL3P, and the remaining portion of the first material layer CDL1 can be left as a second insulating pattern CDL1P. For example, in the separation trench WTR, the portions of the third material layer CDL3 and the first material layer CDL1 that are located between the lower sheet layer separation wall SWL and the stack structure of the plurality of sacrificial layers SL and the plurality of nanosheets NS can be left as the first insulating pattern CDL3P and the second insulating pattern CDL1P, respectively (rather than being removed).

[0091] In some embodiments, instead of ​ ​The stack structure of the buffer layer BFL and the hard mask pattern HMK can form a stack structure of a first buffer layer BFL1, a first hard mask pattern HMK1, a second buffer layer BFL2, and a second hard mask pattern HMK2 on the stack structure of the plurality of sacrificial layers SL and the plurality of nanosheets NS. The first buffer layer BFL1 and the second buffer layer BFL2 can include an oxide (e.g., can be formed of an oxide). In some embodiments, the first buffer layer BFL1 and the second buffer layer BFL2 can include the same material (e.g., can be formed of the same material). The first hard mask pattern HMK1 and the second hard mask pattern HMK2 can include the same material (e.g., can be formed of the same material), but the inventive concept is not limited thereto. For example, one of the first hard mask pattern HMK1 and the second hard mask pattern HMK2 can include a nitride (e.g., can be formed of a nitride), and the other can include an insulating material including carbon (e.g., can be formed of an insulating material including carbon).

[0092] Referring to ​ After the first insulating pattern CDL3P and the second insulating pattern CDL1P are formed, a fourth material layer CDL4 can be formed on (e.g., covering or overlapping with) the exposed surface. The fourth material layer CDL4 can include an insulating material (e.g., can be formed of an insulating material). For example, the fourth material layer CDL4 can include silicon carbonate (e.g., can be formed of silicon carbonate).

[0093] Referring to ​ A preliminary upper separation layer SWUP can be formed on (e.g., covering or overlapping with) the fourth material layer CDL4 and in the upper portion of the separation groove WTR (at least partially filling the upper portion of the separation groove WTR). The preliminary upper separation layer SWUP can completely fill the separation groove WTR, but can only partially fill the plurality of trenches TRE. For example, the preliminary upper separation layer SWUP can include silicon nitride (e.g., can be formed of silicon nitride).

[0094] Referring to FIG. 16C and FIG. 16D The upper sheet layer separation wall SWU can be formed by removing a portion of the preliminary upper separation layer SWUP. The upper sheet layer separation wall SWU can fill a portion of the upper portion of the separation groove WTR. The upper sheet layer separation wall SWU and the lower sheet layer separation wall SWL can constitute a sheet layer separation wall SWS. The upper sheet layer separation wall SWU and the lower sheet layer separation wall SWL can be spaced apart from each other in a vertical direction (e.g., a Z direction) (through the fourth material layer CDL4). A portion of the fourth material layer CDL4 can be located between the upper sheet layer separation wall SWU and the lower sheet layer separation wall SWL.

[0095] Referring toFIG. 16D and FIG. 16E A physical property of the portion of the fourth material layer CDL4 that is exposed to the exterior can be changed to form a changed material layer CDL4C. The remaining (unchanged) portion of the fourth material layer CDL4 can remain as a sheet layer barrier pattern CDL4P. The changed material layer CDL4C can have a lower carbon atom content than the sheet layer barrier pattern CDL4P.

[0096] Referring to FIG. 16E and FIG. 16F The changed material layer CDL4C can be removed. The sheet layer barrier pattern CDL4P can remain (be preserved) without being removed.

[0097] Referring to FIG. 16E , FIG. 16F and FIG. 16G A sixth material layer CDL6 can be formed on (e.g., conformally cover or overlap) a surface exposed after the changed material layer CDL4C is removed. The sixth material layer CDL6 can include a semiconductor material (e.g., can be formed of a semiconductor material). The sixth material layer CDL6 can include a first layer CDL6A and a second layer CDL6B. The first layer CDL6A and the second layer CDL6B can have different physical properties.

[0098] FIG. 17 is a vertical cross-sectional view illustrating an integrated circuit device according to some embodiments. In detail, FIG. 17 is a vertical cross-sectional view taken along line A-A' of FIG. 1 .

[0099] Referring to FIG. 17 After the sixth material layer CDL6 of FIG. 16G is formed, referring to FIG. 2N , FIG. 2O , FIG. 2P , FIG. 2Q , FIG. 2R , FIG. 2S , FIG. 2T , FIG. 2U , FIG. 3A , FIG. 3B , FIG. 3C , FIG. 4A , FIG. 4B , FIG. 5A , FIG. 5B , FIG. 6A , FIG. 6B , FIG. 7A , FIG. 7B , FIG. 8A , FIG. 8B , FIG. 9A , FIG. 9B ,FIG. 10A 、 FIG. 10B 、 FIG. 11A 、 FIG. 11B 、 FIG. 12A 、 FIG. 12B 、 FIG. 13A 、 FIG. 13B 、 FIG. 14A and FIG. 14A form an integrated circuit device 2. A lower slice separation wall SWL of the slice separation wall SWS included in the integrated circuit device 2 can have a lower width LWW (in the second horizontal direction (e.g., Y direction)), and an upper slice separation wall SWU of the slice separation wall SWS can have an upper width UWWa (in the second horizontal direction (e.g., Y direction)). In some embodiments, the upper width UWWa can be greater than the lower width LWW. For example, the upper width UWWa can be greater (approximately) 9 nm or less than the lower width LWW.

[0100] In some embodiments, the indented spacer IDT can not be located between the slice separation wall SWS and the uppermost nanosheet NS among the plurality of nanosheets NS, but can be located between the slice separation wall SWS and the remaining nanosheets NS (lower than the uppermost nanosheet NS among the plurality of nanosheets NS).

[0101] FIG. 14B 、 FIG. 20A 、 FIG. 20B 、 FIG. 21A 、 FIG. 21B 、 FIG. 20A and FIG. 21A are vertical cross-sectional views for describing a method of manufacturing an integrated circuit device according to some embodiments. In detail, FIG. 1 、 FIG. 20B 、 FIG. 20A 、 FIG. 21B 、 FIG. 21A 、 FIG. 20A and FIG. 20B are vertical cross-sectional views taken along the line A-A' of FIG. 21A

[0102] Referring to FIG. 21B and FIG. 22 together, a portion of the third material layer CDL3 and a portion of the first material layer CDL1 can be removed. The (remaining) portion of the third material layer CDL3 can be left as a first insulating pattern CDL3P, and the (remaining) portion of the first material layer CDL1 can be left as a second insulating pattern CDL1P.

[0103] ​After forming the first insulating pattern CDL3P and the second insulating pattern CDL1P, a fourth material layer CDL4 can be formed on the exposed surfaces (e.g., covering the exposed surfaces or overlapping the exposed surfaces). The fourth material layer CDL4 can include (e.g., can be formed of) an insulating material. For example, the fourth material layer CDL4 can include (e.g., can be formed of) silicon carbonate.

[0104] In some embodiments, instead of the stack structure of the buffer layer BFL and the hard mask pattern HMK, FIG. 23 a stack structure of a first buffer layer BFL1, a first hard mask pattern HMK1, a second buffer layer BFL2, and a second hard mask pattern HMK2a can be formed on the stack structure of the plurality of sacrificial layers SL and the plurality of nanosheets NS. In some embodiments, the first buffer layer BFL1 and the second buffer layer BFL2 can include (e.g., can be formed of) the same material. The first hard mask pattern HMK1 and the second hard mask pattern HMK2a can include (e.g., can be formed of) different materials. For example, the first hard mask pattern HMK1 and the second hard mask pattern HMK2a can include (e.g., can be formed of) insulating materials having different carbon atom contents.

[0105] Referring to FIG. 22 and FIG. 1 a portion of the fourth material layer CDL4 on (e.g., covering or overlapping in a vertical direction with) the upper surface (e.g., top surface) of the substrate substrate layer BSUB, the second hard mask pattern HMK2a, the first insulating pattern CDL3P, the second insulating pattern CDL1P, and the lower sheet layer separation wall SWL can be removed. For example, a portion of the fourth material layer CDL4 can be removed by performing an etch-back process.

[0106] Referring to FIG. 22 a preliminary upper separation layer SWUP can be formed on (e.g., covering or overlapping with) the fourth material layer CDL4, the second hard mask pattern HMK2a, and the lower sheet layer separation wall SWL and in an upper portion of the separation groove WTR (at least partially filling the upper portion of the separation groove WTR). The preliminary upper separation layer SWUP can directly contact the upper surface (e.g., top surface) of the lower sheet layer separation wall SWL. The initial upper separation layer SWUP can completely fill the separation groove WTR, but can only partially fill the plurality of trenches TRE. For example, the preliminary upper separation layer SWUP can include (e.g., can be formed of) silicon nitride.

[0107] Referring toFIG. 2T and FIG. 2U An upper sheet layer separation wall SWU can be formed by removing a portion of the preliminary upper separation layer SWUP. The upper sheet layer separation wall SWU can be located in (e.g., can fill) a portion of the upper portion of the separation groove WTR. The upper sheet layer separation wall SWU and the lower sheet layer separation wall SWL can constitute a sheet layer separation wall SWS. A lower surface (e.g., a bottom surface) of the upper sheet layer separation wall SWU and an upper surface (e.g., a top surface) of the lower sheet layer separation wall SWL can contact each other.

[0108] Referring to FIG. 22 and FIG. 23 A physical property of an exposed-to-external portion of the fourth material layer CDL4 can be changed to form a fifth material layer CDL5. A remaining (unchanged) portion of the fourth material layer CDL4 can remain as a sheet layer barrier pattern CDL4P. The sheet layer barrier pattern CDL4P can be located on (e.g., can cover or overlap with) a side surface of the upper sheet layer separation wall SWU. One side surface of a stack structure of the first buffer layer BFL1, the first hard mask pattern HMK1, the second buffer layer BFL2, and the second hard mask pattern HMK2a in the second horizontal direction (e.g., the Y direction) can be covered (or overlapped) by a portion of the fifth material layer CDL5, an upper portion of the other side surface of the stack structure can be covered (or overlapped) by another portion of the fifth material layer CDL5, and a lower portion of the other side surface of the stack structure can be covered (or overlapped) by the sheet layer barrier pattern CDL4P. For example, the stack structure of the first buffer layer BFL1, the first hard mask pattern HMK1, the second buffer layer BFL2, and the second hard mask pattern HMK2a can be located between the fifth material layer CDL5 and the sheet layer barrier pattern CDL4P in the second horizontal direction (e.g., the Y direction).

[0109] Referring to FIG. 15A and FIG. 2H The fifth material layer CDL5 can be removed. The sheet layer barrier pattern CDL4P can remain (be maintained) without being removed.

[0110] Referring to ​ , ​ and ​A sixth material layer CDL6 can be formed on (e.g., conformally covering or overlapping) the surface exposed after removal of the fifth material layer CDL5. The sixth material layer CDL6 can include a semiconductor material (e.g., can be formed of a semiconductor material). The sixth material layer CDL6 can include a first layer CDL6A and a second layer CDL6B. The first layer CDL6A and the second layer CDL6B can have different physical properties.

[0111] ​ is a vertical cross-sectional view illustrating an integrated circuit device according to some embodiments. In detail, ​ is a vertical cross-sectional view taken along ​ line A-A' of

[0112] Referring to ​ , after forming ​ the sixth material layer CDL6 shown, reference can be made to ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ and ​The integrated circuit device 3 is formed. The sheet layer blocking pattern CDL4P included in the integrated circuit device 3 can be a side surface of the upper sheet layer separation wall SWU (e.g., can cover or overlap the side surface of the upper sheet layer separation wall SWU). The sheet layer blocking pattern CDL4P can not be located between the lower sheet layer separation wall SWL and the upper sheet layer separation wall SWU of the sheet layer separation wall SWS included in the integrated circuit device 3. The lower sheet layer separation wall SWL and the upper sheet layer separation wall SWU of the sheet layer separation wall SWS can directly contact each other.

[0113] In some embodiments, the indented spacer IDT can not be located between the sheet layer separation wall SWS and the uppermost nanosheet NS among the plurality of nanosheets NS, but can be located between the sheet layer separation wall SWS and the remaining nanosheets NS (lower than the uppermost nanosheet NS among the plurality of nanosheets NS).

[0114] ​ and ​ and ​ and ​ are vertical cross-sectional views illustrating an integrated circuit device according to some embodiments. In detail, ​ and ​ are vertical cross-sectional views taken along the line A-A' of ​ ​ is an enlarged view illustrating a portion XXB of ​ ​ is an enlarged view illustrating a portion XXIB of ​

[0115] Referring to ​ and ​ together, the gate insulating layer Gox and the gate electrode GL included in the integrated circuit device 4, which are located on the gate insulating layer Gox (e.g., cover or overlap the gate insulating layer Gox), can pass through the sheet layer separation wall SWS to connect a pair of gate spaces GS corresponding to each other in the second horizontal direction (e.g., Y direction). For example, the gate insulating layer Gox and the gate electrode GL can pass through the lower sheet layer separation wall SWL, but can not pass through the upper sheet layer separation wall SWU. For example, a portion of the lower sheet layer separation wall SWL can be separated from each other by the gate insulating layer Gox and the gate electrode GL therebetween (in the vertical direction (e.g., Z direction)).

[0116] ​​​In the integrated circuit device 4 according to the present inventive concept, because the sheet layer separation wall SWS includes the lower sheet layer separation wall SWL and the upper sheet layer separation wall SWU formed through separate processes, the gate insulating layer Gox and the gate electrode GL can pass (only) through the lower sheet layer separation wall SWL. Therefore, the gate electrode GL can function as a shared gate shared by a pair of nanosheet stack structures NSS adjacent to each other in the second horizontal direction (e.g., Y direction).

[0117] Referring to ​ and ​ The gate insulating layer Gox and the gate electrode GL included in the integrated circuit device 5 can pass through the sheet layer separation wall SWS to connect a plurality of gate spaces GS of a pair of nanosheet stack structures NSS adjacent to each other. For example, the gate insulating layer Gox and the gate electrode GL can pass through the lower sheet layer separation wall SWL, but can not pass through the upper sheet layer separation wall SWU. For example, a portion of the lower sheet layer separation wall SWL can be separated from each other by the gate insulating layer Gox and the gate electrode GL therebetween (in the vertical direction (e.g., Z direction) and / or the second horizontal direction (e.g., Y direction)).

[0118] In the second horizontal direction (e.g., Y direction), the lower sheet layer separation wall SWL can not be located between a pair of nanosheet stack structures NSS adjacent to each other, but the lower sheet layer separation wall SWL can be located between a pair of fin-type active regions FA adjacent to each other in the second horizontal direction (e.g., Y direction).

[0119] In the integrated circuit device 5 according to the present inventive concept, because the sheet layer separation wall SWS includes the lower sheet layer separation wall SWL and the upper sheet layer separation wall SWU formed through separate processes, after the plurality of gate spaces GS are formed, the entire portion of the lower sheet layer separation wall SWL located between a pair of nanosheet stack structures NSS adjacent to each other in the second horizontal direction (e.g., Y direction) can be removed, so that the gate insulating layer Gox and the gate electrode GL filling the plurality of gate spaces GS of the pair of nanosheet stack structures NSS adjacent to each other are connected to each other. The gate electrode GL can function as a shared gate shared by a pair of nanosheet stack structures NSS adjacent to each other in the second horizontal direction (e.g., Y direction).

[0120] Therefore, in the integrated circuit device 5 according to the present inventive concept, because a uniform bias can be applied to each of the plurality of nanosheets NS included in each of the pair of nanosheet stack structures NSS, operational reliability can be ensured.

[0121] ​ and ​ are vertical cross-sectional views illustrating an integrated circuit device according to some embodiments. In detail, ​and 23 is a vertical cross-sectional view taken along ​ line A-A' of

[0122] Referring to ​ , the sheet layer barrier pattern CDL4P included in the integrated circuit device 6 can be located on a lower surface (e.g., a bottom surface) of the upper sheet layer separation wall SWU (e.g., cover or overlap the lower surface (e.g., bottom surface) of the upper sheet layer separation wall SWU), but can not be located on at least a portion of a side surface of the upper sheet layer separation wall SWU (e.g., can not cover at least a portion of the side surface of the upper sheet layer separation wall SWU).

[0123] Referring to ​ , ​ and ​ , when the eighth material layer CDL8 is formed after removing the portion of the sheet layer barrier pattern CDL4P that is exposed to the outside, the sheet layer barrier pattern CDL4P can not be located on at least a portion of a side surface of the upper sheet layer separation wall SWU (e.g., can not cover at least a portion of the side surface of the upper sheet layer separation wall SWU).

[0124] In some embodiments, an uppermost end of the sheet layer barrier pattern CDL4P can be located at the same vertical height as (e.g., can be coplanar with) an upper surface (e.g., a top surface) of an uppermost nanosheet NS among the plurality of nanosheets NS. For example, the sheet layer barrier pattern CDL4P can be located on a lower surface (e.g., a bottom surface) of the upper sheet layer separation wall SWU (e.g., can cover or overlap the lower surface (e.g., bottom surface) of the upper sheet layer separation wall SWU), can be located only on a lower portion of a side surface of the upper sheet layer separation wall SWU (e.g., can cover the lower portion of the side surface of the upper sheet layer separation wall SWU), and can not be located on a remaining upper portion of the side surface of the upper sheet layer separation wall SWU (e.g., can not cover the remaining upper portion of the side surface of the upper sheet layer separation wall SWU).

[0125] Referring to ​ , the lower sheet layer separation wall SWL of the sheet layer separation wall SWS included in the integrated circuit device 7 can have a lower width LWW (in the second horizontal direction (e.g., Y direction)), and the upper sheet layer separation wall SWU of the sheet layer separation wall SWS can have an upper width UWWb (in the second horizontal direction (e.g., Y direction)). For example, the lower width LWW can be greater than the upper width UWWb by a thickness of the sheet layer barrier pattern CDL4P. The upper width UWWb of the upper sheet layer separation wall SWU included in the integrated circuit device 7 can be less than the upper width UWW of the upper sheet layer separation wall SWU included in the integrated circuit device 1 of ​ .

[0126] In forming ​ In the process of forming the fourth material layer CDL4, when the fourth material layer CDL4 is formed relatively thick, the upper width UWWb of the upper sheet layer separation wall SWU can be formed relatively narrow.

[0127] While the present concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the scope of the appended claims.

Claims

1. An integrated circuit device comprising: a bulk substrate layer including a pair of fin-type active regions spaced apart from each other in a first direction and protruding in a second direction, with a separation groove provided between the pair of fin-type active regions; a sheet layer separation wall including a lower sheet layer separation wall and an upper sheet layer separation wall on the lower sheet layer separation wall, the sheet layer separation wall extending in a third direction along the separation groove; a sheet layer barrier pattern on at least a portion of a side surface and / or a lower surface of the upper sheet layer separation wall; a pair of nanosheet stack structures on the pair of fin-type active regions and spaced apart from each other in the first direction, the separation groove and the sheet layer separation wall being between the pair of nanosheet stack structures, and each of the pair of nanosheet stack structures including a plurality of nanosheets; a gate electrode on the pair of fin-type active regions and the pair of nanosheet stack structures and extending in the first direction; a plurality of recessed spacers between the plurality of nanosheets and the sheet layer separation wall; and a plurality of spacer layers between the gate electrode and the sheet layer separation wall, wherein the first direction is parallel to a lower surface of the bulk substrate layer, wherein the second direction is perpendicular to the lower surface of the bulk substrate layer, and wherein the third direction is parallel to the lower surface of the bulk substrate layer and intersects the first direction. In the first direction, a width of the upper sheet layer separation wall and a width of the lower sheet layer separation wall are different from each other.

2. The integrated circuit device of claim 1, wherein, In a side surface of the sheet layer separation wall, a thickness of each of the plurality of recessed spacers in the first direction is greater than a thickness of each of the plurality of spacer layers in the first direction.

3. The integrated circuit device of claim 1, wherein, The upper sheet layer separation wall and the lower sheet layer separation wall are spaced apart from each other in the second direction, and 4. The integrated circuit device of claim 1, wherein, wherein the sheet layer barrier pattern is between the lower surface of the upper sheet layer separation wall and an upper surface of the lower sheet layer separation wall. The sheet layer barrier pattern is on at least a lower portion of the side surface of the upper sheet layer separation wall and the lower surface of the upper sheet layer separation wall.

5. The integrated circuit device of claim 4, wherein, In the first direction, an end of the gate electrode facing a side surface of the sheet layer separation wall is closer to the side surface of the sheet layer separation wall than a respective end of each of the plurality of nanosheets facing the side surface of the sheet layer separation wall.

6. The integrated circuit device of claim 1, wherein, The lower surface of the upper sheet layer separation wall and an upper surface of the lower sheet layer separation wall are in contact with each other, and 7. The integrated circuit device of claim 1, wherein, wherein the sheet layer barrier pattern is on the side surface of the upper sheet layer separation wall. Each of the plurality of recessed spacers includes a stack structure including a first insulating pattern on the side surface of the sheet layer separation wall and a second insulating pattern on the first insulating pattern.

8. The integrated circuit device of claim 1, wherein, ​ 9. The integrated circuit device of claim 1, wherein, An uppermost end of the upper sheet layer partition wall protrudes from an upper surface of an uppermost nanosheet among the plurality of nanosheets in the second direction.

10. The integrated circuit device of claim 1, wherein, An uppermost end of the lower sheet layer partition wall is farther from a lower surface of the base substrate layer than a lower surface of an uppermost nanosheet among the plurality of nanosheets in the second direction.

11. The integrated circuit device of claim 1, wherein, The plurality of recessed spacers are located between nanosheets lower than the uppermost nanosheet among the plurality of nanosheets and the sheet layer partition wall.

12. An integrated circuit device, the integrated circuit device comprising: a base substrate layer including a pair of fin-type active regions spaced apart from each other in a first direction and protruding in a second direction, a partitioned recess being provided between the pair of fin-type active regions; a sheet layer partition wall extending in a third direction along the partitioned recess and including a lower sheet layer partition wall and an upper sheet layer partition wall located on the lower sheet layer partition wall, wherein a width of the lower sheet layer partition wall is greater than a width of the upper sheet layer partition wall in the first direction; a sheet layer barrier pattern located between a lower surface of the upper sheet layer partition wall and an upper surface of the lower sheet layer partition wall; a pair of nanosheet stack structures located on the pair of fin-type active regions and spaced apart from each other in the first direction, the partitioned recess and the sheet layer partition wall being located between the pair of nanosheet stack structures, and each of the pair of nanosheet stack structures including a plurality of nanosheets; a pair of source / drain regions located on the pair of fin-type active regions and electrically connected to the plurality of nanosheets included in the pair of nanosheet stack structures; a gate electrode located on the pair of fin-type active regions and the pair of nanosheet stack structures and extending in the first direction; a plurality of recessed spacers located between the plurality of nanosheets and the sheet layer partition wall; and a plurality of spacer layers located between the gate electrode and the sheet layer partition wall, wherein the first direction is parallel to a lower surface of the base substrate layer, wherein the second direction is perpendicular to the lower surface of the base substrate layer, and wherein the third direction is parallel to the lower surface of the base substrate layer and intersects the first direction.

13. The integrated circuit device of claim 12, wherein, the upper sheet layer partition wall and the lower sheet layer partition wall are spaced apart from each other in the second direction, and wherein the sheet layer barrier pattern extends between a lower surface of the upper sheet layer partition wall and the upper surface of the lower sheet layer partition wall onto at least a portion of a side surface of the upper sheet layer partition wall.

14. The integrated circuit device of claim 13, wherein, an uppermost end of the sheet layer barrier pattern and an uppermost end of the upper sheet layer partition wall are coplanar with each other.

15. The integrated circuit device of claim 12, the integrated circuit device further comprising: a gate insulating layer located between the gate electrode and the plurality of nanosheets included in the pair of nanosheet stack structures and between the gate electrode and the pair of fin-type active regions; and a coverage pattern on an upper surface of the upper sheet layer partition wall and between the upper sheet layer partition wall and the gate insulating layer.

16. The integrated circuit device of claim 12, wherein, the pair of nanosheet stack structures are spaced apart from each other in the first direction by the upper sheet layer partition wall, wherein the pair of nanosheet stack structures are spaced apart from each other in the first direction by the lower sheet layer partition wall, and wherein the pair of source / drain regions are spaced apart from each other in the first direction by the lower sheet layer partition wall.

17. The integrated circuit device of claim 16, wherein, an uppermost end of the lower sheet layer partition wall between the pair of source / drain regions is closer to the lower surface of the bulk substrate layer than an uppermost end of each of the pair of source / drain regions.

18. The integrated circuit device of claim 12, wherein, on a side surface of the sheet layer partition wall, a thickness of each of the plurality of indented spacers in the first direction is greater than a thickness of each of the plurality of spacer layers in the first direction, and wherein, in the first direction, an end of the gate electrode facing a side surface of the sheet layer partition wall is closer to the side surface of the sheet layer partition wall than a respective end of each of the plurality of nanosheets facing the side surface of the sheet layer partition wall.

19. An integrated circuit device, the integrated circuit device comprising: a bulk substrate layer comprising a pair of fin-type active regions spaced apart from each other in a first direction and protruding in a second direction, wherein a partitioned recess is provided between the pair of fin-type active regions; a sheet layer partition wall comprising a lower sheet layer partition wall and an upper sheet layer partition wall on the lower sheet layer partition wall, wherein the lower sheet layer partition wall and the upper sheet layer partition wall are spaced apart from each other in the second direction, and the sheet layer partition wall extends in a third direction along the partitioned recess; a sheet layer blocking pattern on a lower surface and a side surface of the upper sheet layer partition wall and comprising a material different from a material in the sheet layer partition wall; a pair of nanosheet stack structures on the pair of fin-type active regions and spaced apart from each other in the first direction, the partitioned recess and the sheet layer partition wall being between the pair of nanosheet stack structures, and each of the pair of nanosheet stack structures comprising a plurality of nanosheets; a source / drain region on the pair of fin-type active regions and electrically connected to the plurality of nanosheets included in the pair of nanosheet stack structures; a gate electrode on the pair of fin-type active regions and the pair of nanosheet stack structures and extending in the first direction; a gate insulating layer between the gate electrode and the plurality of nanosheets included in the pair of nanosheet stack structures and between the gate electrode and the pair of fin-type active regions; a plurality of indented spacers between the plurality of nanosheets and the sheet layer partition wall; and a plurality of spacer layers between the gate electrode and the sheet layer partition walls, wherein each of the plurality of spacer layers has a thickness in the first direction on a side surface of the sheet layer partition walls that is less than a thickness in the first direction of each of the plurality of indented spacers, wherein, in the first direction, a width of the upper sheet layer partition wall is less than a width of the lower sheet layer partition wall, wherein the first direction is parallel to a lower surface of the bulk substrate layer, wherein the second direction is perpendicular to the lower surface of the bulk substrate layer, and wherein the third direction is parallel to the lower surface of the bulk substrate layer and intersects the first direction.

20. The integrated circuit device of claim 19, wherein, an uppermost end of the upper sheet layer partition wall is further from the lower surface of the bulk substrate layer than an upper surface of an uppermost nanosheet among the plurality of nanosheets, wherein an uppermost end of the lower sheet layer partition wall is closer to the lower surface of the bulk substrate layer than the upper surface of the uppermost nanosheet among the plurality of nanosheets, and wherein the uppermost end of the lower sheet layer partition wall is coplanar with or further from the lower surface of the bulk substrate layer than a lower surface of the uppermost nanosheet among the plurality of nanosheets.

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