Semi-insulating gallium arsenide photoconductive switch with nested porous multilayer structure and method

Abstract

The invention discloses a semi-insulating gallium arsenide photoconductive switch with a nested porous multilayer structure. The semi-insulating gallium arsenide photoconductive switch comprises a bottom layer unit and a GaAs layer which are sequentially arranged from bottom to top, the upper surface of the GaAs layer is provided with a combined hole unit; a composite coating layer is laid on the upper surface of the GaAs layer, and the composite coating layer is used for filling the combined hole units; a positive electrode and a negative electrode are embedded in the composite coating layer, and the bottom surfaces of the positive electrode and the negative electrode are in embedded contact with the upper surface of the GaAs layer; the combined hole unit is positioned in a GaAs layer region between the positive electrode and the negative electrode; a cofferdam is arranged on the upper surface of the composite coating layer between the positive electrode and the negative electrode, the projection of the combined hole units on the composite coating layer is in the cofferdam, and the cofferdam is filled with a sealing layer. According to the photoconductive switch, the voltage endurance capability of the switch is improved, and the performance of the switch is improved. The invention also discloses a preparation method of the photoconductive switch.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of high-power ultra-wideband electromagnetic pulse, and particularly relates to a nested multi-hole multi-layer structure semi-insulated gallium arsenide photoconductive switch and a preparation method thereof. BACKGROUND

[0002] High-power ultra-wideband electromagnetic pulse technology has a broad application prospect in the fields of wireless communication, radar, tracking, precise positioning, electromagnetic pulse weapons and the like. One of the core technologies of electromagnetic pulse formation is high-voltage sub-nanosecond switch technology. Compared with pure electrical switch technology, the output electric pulse of a semi-insulated gallium arsenide photoconductive switch (SI-GaAs PCSS) has the characteristics of small time jitter, fast rising front, compact system, high repetition frequency and the like, so that the SI-GaAs PCSS becomes an important technical means in the field. The basic principle of the SI-GaAs PCSS is the picosecond photoconductive effect. When a laser triggers the SI-GaAs PCSS, photo-generated carriers are generated in the semiconductor to make the switch quickly close; with the recombination of the photo-generated carriers, the resistance of the SI-GaAs PCSS is restored, and the switch is turned off, so that an ultrafast electric pulse is output on the load. In particular, in the nonlinear mode of the SI-GaAs PCSS, the required trigger light energy is smaller, and the output electric pulse front is faster, so that the SI-GaAs PCSS has a better application prospect at high voltage.

[0003] In order to improve the power capacity and the amplitude of the output pulse of the SI-GaAs PCSS, it needs to have the ability to withstand high voltage. But when the surface of the gallium arsenide crystal is completely exposed to the electric field, the electric breakdown strength of the two material surfaces is significantly lower than the bulk breakdown field of either material surface, which seriously limits the improvement of the voltage withstand capability of the semi-insulating gallium arsenide photoconductive switch. The intrinsic breakdown field of the gallium arsenide material reaches 250kV / cm, but in the past reports, the semi-insulating gallium arsenide photoconductive switch often occurs surface flashover at about 40kV / cm, which leads to the switch conduction, greatly affecting the service life and performance of the switch. After research, it is found that the initial electrons are emitted to the material surface at the junction of the electrode metal, the semiconductor and the gas, and the initial electrons bombard the surface of the semi-insulating gallium arsenide material, form secondary electron (SE) emission under the action of strong electric field, and the electron emission is multiplied step by step, and finally forms flashover on the surface of the switch. Therefore, the key to improve the voltage withstand capability of the semi-insulating gallium arsenide material is to suppress the occurrence of surface flashover of the semi-insulating gallium arsenide material, and the core of suppressing the occurrence of flashover is to reduce the secondary electron emission coefficient (SEY) under strong field. The present application mainly suppresses the secondary electron emission coefficient of the semi-insulating gallium arsenide material through the surface microstructure, the surface coating and the vacuum cofferdam filling technology, so as to improve the voltage withstand capability. SUMMARY

[0004] The first object of the present application is to provide a semi-insulating gallium arsenide photoconductive switch with a nested porous multilayer structure, which can effectively reduce the secondary electron emission coefficient of the surface of the semi-insulating gallium arsenide material, suppress the occurrence of surface flashover of the switch, improve the voltage withstand capability of the switch, and improve the performance of the switch.

[0005] The second object of the present application is to provide a preparation method of the semi-insulating gallium arsenide photoconductive switch with a nested porous multilayer structure.

[0006] The first technical solution adopted by the present application is a semi-insulating gallium arsenide photoconductive switch with a nested porous multilayer structure, which comprises a bottom layer unit and a GaAs layer arranged in sequence from bottom to top; a combined hole unit is opened on the upper surface of the GaAs layer; a composite coating layer is laid on the upper surface of the GaAs layer, and the composite coating layer is used to fill the combined hole unit; The positive electrode and the negative electrode are embedded in the composite coating layer, and the bottom surfaces of the positive electrode and the negative electrode are in embedded contact with the upper surface of the GaAs layer; The combined hole unit is located in the GaAs layer region between the positive electrode and the negative electrode; a cofferdam is arranged on the upper surface of the composite coating layer between the positive electrode and the negative electrode, the projection of the combined hole unit on the composite coating layer is in the cofferdam, and the cofferdam is filled with a sealing layer.

[0007] The present application is also characterized by: The bottom unit comprises metal layers and insulating layers arranged from bottom to top.

[0008] The material of the cofferdam is epoxy resin, and the sealing layer is an organic silicone gel layer.

[0009] The combined hole unit comprises a laser trigger hole and a plurality of nested multi-holes; the negative electrode is arranged on the side close to the laser trigger hole, and the positive electrode is arranged on the side away from the laser trigger hole. The laser trigger hole is composed of a laser trigger primary hole and a laser trigger secondary hole arranged from top to bottom, the diameter of the laser trigger primary hole is 200-400 mu m, and the diameter of the laser trigger secondary hole is 100-200 mu m. The diameter of the laser trigger primary hole is larger than that of the laser trigger secondary hole; the nested multi-hole is composed of a nested primary hole and a nested secondary hole arranged from top to bottom, the diameter ratio of the nested primary hole to the nested secondary hole is 2:1, the diameter of the nested primary hole ranges from 100 mu m to 300 mu m, and the diameter of the nested primary hole is larger than that of the nested secondary hole; the composite coating layer comprises a SiO2 layer and a Si3N4 layer arranged from top to bottom. The SiO2 layer is arranged at the GaAs layer region corresponding to the edges of the laser trigger primary hole, the plurality of nested primary holes, the positive electrode and the negative electrode. The upper surface of the SiO2 layer, the laser trigger hole and the plurality of nested multi-holes are paved with the SiO2 layer, and the Si3N4 layer is located between the GaAs layer and the SiO2 layer.

[0010] The thickness of the SiO2 layer is 20-60 mu m, and the thickness of the Si3N4 layer is 10-40 mu m.

[0011] The plurality of nested multi-holes are uniformly arranged in an M row by N column array, and M and N are positive integers. The distance between the adjacent two nested multi-holes in each column is equal to the diameter of the nested primary hole; the distance between the columns is equal to 100-300 mu m, and the distance between the rows is equal to 100-300 mu m. The material of the metal layer is copper plate; the material of the insulating layer is Al2O3; and the materials of the positive electrode and the negative electrode are Ni / AuGe / Ni low-resistance alloy.

[0012] The second technical scheme adopted by the present application is a preparation method of the nested multi-hole multi-layer structure of the semi-insulating gallium arsenide photoconductive switch, specifically: Step 1: pretreatment of the gallium arsenide wafer; Step 2: depositing a Si3N4 layer; Step 3: photoetching a primary hole, the photoetched primary hole comprising a laser trigger primary hole and a nested primary hole; Step 4: photoetching secondary holes, the photoetched secondary holes include laser triggered secondary holes and nested secondary holes; Step 5: filling the primary holes and the secondary holes; Step 6: making electrodes; Step 7: dicing, assembling and dam sealing.

[0013] The application is further characterized in that: Step 1 is specifically: using chemical etching method, cleaning the gallium arsenide wafer with hydrochloric acid hydrogen peroxide solution to remove the oxide layer, and then sequentially cleaning the wafer with deionized water, acetone, methanol, new deionized water for 3-5 minutes; then blowing the water on the surface of the gallium arsenide wafer dry with a dry high-pressure nitrogen gun; finally baking in a 100-120℃ oven for 10-20 minutes to evaporate the residual moisture on the surface of the gallium arsenide wafer; The components of the hydrochloric acid hydrogen peroxide solution and the corresponding volume ratio are specifically: HCl:H2O2:H2O = 1:1:5-10; Step 2 is specifically: Depositing a Si3N4 layer on the gallium arsenide wafer treated in step 1, with a thickness of 10-40 μm; Step 3 is specifically: Step 3.1: coating photoresist on the gallium arsenide wafer treated in step 2, using AZ1350J photoresist, with a thickness of 0.8 μm; Step 3.2: soft baking; Heating the gallium arsenide wafer with an 80-90℃ hot plate for 1-3 minutes to volatilize the organic solvent in the photoresist from the photoresist, so that the organic solvent content is reduced to 3-5% after soft baking; Step 3.3: first alignment and exposure; First, fix the nested hole mask on the mask holder, and then fix the soft-baked gallium arsenide wafer on the wafer chuck; use contact exposure to obtain higher spatial resolution and 1:1 conversion size; the exposure dose is 240 mJ / cm 3 , wavelength 365 nm.

[0014] Step 3.4: development; Put the exposed wafer into the developing solution for development, and then put the wafer into deionized water for cleaning. Finally, blow the deionized water on the surface of the wafer dry with a dry nitrogen gun; The developing solution is a tetramethylammonium hydroxide (TMAH) aqueous solution, and the volume of tetramethylammonium hydroxide accounts for 2.38% of the tetramethylammonium hydroxide aqueous solution; Step 3.5: hard baking; The developed wafer is baked on an electric hot plate at 100-120°C for 25-35 minutes to remove the residual solvent in the photoresist and to enhance the adhesion of the photoresist; Step 3.6: etching the primary circular hole, etching the exposed Si3N4 layer on the hard-baked wafer and then etching the exposed GaAs material to a depth of 100-300 μm and a diameter of 100-300 μm.

[0015] Step 3.7: removing the photoresist on the photoetched wafer.

[0016] Step 4 is specifically: Step 4.1: coating the wafer treated in Step 3 with photoresist, using AZ1350J photoresist with a thickness of 0.8 μm; Step 4.2: soft baking the wafer coated with photoresist; using an electric hot plate at 80-90°C for 1-3 minutes to volatilize the solvent from the photoresist, and reducing the solvent content to 3-5% after soft baking; Step 4.3: second alignment and exposure; First, fix the nested hole mask plate on the mask plate holder, and then fix the wafer treated by soft baking on the wafer chuck; use contact exposure to obtain higher spatial resolution and 1:1 conversion size; the exposure dose is 170 mJ / cm 3 , wavelength 365 nm; Step 4.4: development; Put the exposed wafer into the developing solution for development, then wash the wafer in deionized water, and finally dry the wafer surface with a dry nitrogen gun; The developing solution is a tetramethylammonium hydroxide (TMAH) aqueous solution, and the volume of tetramethylammonium hydroxide accounts for 2.38% of the tetramethylammonium hydroxide aqueous solution; Step 4.5: hard baking; Bake the developed wafer on an electric hot plate at 100-120°C for 25-35 minutes to remove the residual solvent in the photoresist and to enhance the adhesion of the photoresist; Step 4.6: etching the secondary circular hole, etching the exposed GaAs material on the hard-baked wafer to a depth of 100-300 μm and a diameter of 50-150 μm; Step 4.7: removing the photoresist on the hard-baked wafer. Step 5 is specifically: Depositing a SiO2 layer on the wafer treated in Step 4 with a thickness of 20-60 μm.

[0017] Step 6 is specifically: Step 6.1: Coating photoresist on the wafer after step 5 processing, using AZ1350J photoresist, thickness 0.8 μm; Step 6.2: Soft baking the wafer; Heating with 80-90 °C hot plate for 1-3 minutes to volatilize the solvent from the photoresist, and the solvent content is reduced to 3-5% after soft baking; First, fix the electrode mask on the mask holder, and then fix the wafer after soft baking on the wafer chuck; contact exposure is used, which can obtain higher spatial resolution and 1:1 conversion size; the exposure dose is 170 mJ / cm 3 , wavelength 365 nm; Step 6.3: Development; Put the exposed wafer into the developer (tetramethylammonium hydroxide (TMAH), volume ratio 2.38%) for development; then put the wafer into deionized water for cleaning; finally, use a dry nitrogen gun to dry the deionized water on the wafer surface; The developer is tetramethylammonium hydroxide (TMAH) aqueous solution, and the volume of tetramethylammonium hydroxide accounts for 2.38% of the tetramethylammonium hydroxide aqueous solution; Step 6.4: Hard baking; Bake the developed wafer on a hot plate at 100-120 °C for 25-35 minutes to remove the remaining solvent in the photoresist and enhance the adhesion of the photoresist; Step 6.5: Etching the SiO2 layer, Si3N4 layer and GaAs layer in turn, and then depositing Ge layer with thickness of 50-100 nm, Ni layer with thickness of 80-120 nm and Au layer with thickness of 200-300 nm on the etched wafer in turn; The treated wafer is heated to 350-500 °C under the protection of inert gas (N2 or A r ), and kept for 3-5 minutes; the positive and negative electrodes of Ni / AuGe / Ni low resistance alloy are formed on the wafer; Remove the photoresist on the treated wafer to form two ohmic contact alloy electrodes on the wafer; Step 7 is as follows: Step 7.1: Dicing the wafer after step 6 processing, and using a dicing machine to dice the chip; Step 7.2: Place the switch unit chip peeled off after dicing on the insulating layer made of Al2O3 to form a microstrip line structure; the metal layer made of copper is arranged below the Al2O3 insulating layer; Step 7.3: Set up a cofferdam on the switch unit, set up a cofferdam on the chip with epoxy, and the cofferdam size is: height 0.2mm-0.5mm, length 3mm-8mm, width 40mm-60mm, wall thickness 0.1mm-0.2mm; prevent overflow when the silicone gel is cured; Step 7.4: Dry and heat the combined chip in a drying oven, bake on a hot plate at 50-60°C for 15-30 minutes to reduce air adhesion on the surface of the chip; Step 7.5: Pouring glue, pouring silicone gel into the cofferdam to form a sealing layer; Step 7.6: Put the device treated in step 7.5 into a vacuum box and vacuum for 30-60 minutes to remove air in the glue; Step 7.7: Dry the device treated in step 7.6 in a drying oven for 24-48 hours until the silicone gel is cured.

[0018] The beneficial effects of the present application are: (1) The nested multi-hole multi-layer structure of the semi-insulating gallium arsenide photoconductive switch can effectively suppress the generation of surface secondary electrons compared with the traditional single-hole or single-channel structure. Especially, the nested structure with a larger aspect ratio can more effectively suppress the electron multiplication in the trap, further improving the suppression effect of secondary electrons. Again, these nested holes are filled with SiO2 to form an electron barrier layer on the surface of the semi-insulating gallium arsenide, so that electrons can only flow from the semi-insulating gallium arsenide body, thereby avoiding surface electron escape. Finally, the micro-trap structure is distributed randomly, which helps to further reduce the probability of surface flashover.

[0019] (2) The present application adopts a multi-layer coating method to further suppress the surface secondary electron emission, which has the following effects: first, it fills the pores left by the multi-hole structure to form an electron barrier layer; second, the evaporation of the insulating layer film can effectively improve the uniformity of the surface and reduce the secondary electron emission coefficient; third, through multi-layer coating, the average free path of electrons can be effectively reduced, and the energy of secondary electrons can be reduced; fourth, the thickness of the SiO2 layer and the Si3N4 layer is reasonably set to increase the laser transmittance and improve the effective energy of the laser.

[0020] (3) The present application sets embedded laser trigger holes, which has the following effects compared with the traditional photoconductive switch without trigger holes: first, it is more convenient for SI-GaAs PCSS to enter the nonlinear working mode; second, it effectively prevents electron escape caused by external photoelectric effect, thereby producing flashover; third, it is more convenient for focusing and fixing the trigger laser.

[0021] (4) The present application adopts the electrode of Ni / AuGe / Ni low-resistance alloy to form ohmic contact, preventing the emission of hot electrons caused by thermal effect. The cofferdam process is adopted to prevent the overflow of glue material during packaging. The vacuum glue filling technology can remove the oxygen adsorbed on the surface of the material, thereby improving the voltage resistance.

[0022] In summary, the present application combines the surface plating technology, surface configuration technology and vacuum cofferdam glue filling process, and designs the nested multi-hole multi-layer structure of the semi-insulating gallium arsenide photoconductive switch, effectively reduces the secondary electron emission coefficient of the surface of the semi-insulating gallium arsenide material, reduces the energy of the secondary electrons, reduces the probability of photoelectron emission and hot electron emission, and can effectively improve the voltage resistance and performance. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 FIG. 1 is a structural schematic diagram of the nested multi-hole multi-layer structure of the semi-insulating gallium arsenide photoconductive switch of the present application; Figure 2 FIG. 2 is a cross-sectional view of the nested multi-hole multi-layer structure of the semi-insulating gallium arsenide photoconductive switch of the present application; Figure 3 FIG. 3 is a schematic diagram of the working principle of the nested multi-hole of the nested multi-hole multi-layer structure of the semi-insulating gallium arsenide photoconductive switch of the present application; Figure 4 FIG. 4 is a partial schematic diagram of the multi-layer film in the cofferdam of the photoconductive switch of the present application; Figure 5 FIG. 5 is a top view of the photoconductive switch of the present application; Figure 6 FIG. 6 is a manufacturing flowchart of steps 1-4 of the preparation method of the present application.

[0024] 1. Positive electrode, 2. Laser triggered hole, 3. Nested multi-hole, 4. Cofferdam, 5. GaAs layer, 6. Insulating layer, 7. Metal layer, 8. Composite plating layer, 9. Sealing layer, 10. Negative electrode, 11. Photoresist, 12. Electron; 2-1. Laser triggered primary hole, 2-2. Laser triggered secondary hole; 3-1. Nested primary hole, 3-2. Nested secondary hole; 8-1. SiO2 layer, 8-2. Si3N4 layer. DETAILED DESCRIPTION

[0025] The present application will be described in detail below in combination with the drawings and specific embodiments.

[0026] The present application provides a nested multi-hole multi-layer structure of a semi-insulating gallium arsenide photoconductive switch, as shown in Figures 1-2 and Figures 4-5As shown, it comprises a bottom layer unit and a GaAs layer 5 arranged in sequence from bottom to top; a combined hole unit is formed on the upper surface of the GaAs layer 5; a composite plating film layer 8 is laid on the upper surface of the GaAs layer 5, and the composite plating film layer 8 is used to fill the combined hole unit; The composite plating film layer 8 is embedded with a positive electrode 1 and a negative electrode 10, and the bottom surfaces of the positive electrode 1 and the negative electrode 10 are in embedded contact with the upper surface of the GaAs layer 5; The combined hole unit is located in the GaAs layer 5 region between the positive electrode 1 and the negative electrode 10; a cofferdam 4 is arranged on the upper surface of the composite plating film layer 8 between the positive electrode 1 and the negative electrode 10, the projection of the combined hole unit on the composite plating film layer 8 is within the cofferdam 4, and the cofferdam 4 is filled with a sealing layer 9.

[0027] The bottom layer unit comprises a metal layer 7 and an insulating layer 6 arranged in sequence from bottom to top.

[0028] The material of the cofferdam 4 is epoxy resin; and the sealing layer 9 is a silicone gel layer.

[0029] The combined hole unit comprises a laser trigger hole 2 and a plurality of nested multi-holes 3; the negative electrode 10 is arranged on the side close to the laser trigger hole 2, and the positive electrode 1 is arranged on the side away from the laser trigger hole 2; The laser trigger hole 2 is composed of a laser trigger primary hole 2-1 and a laser trigger secondary hole 2-2 arranged in sequence from top to bottom, and the diameter of the laser trigger primary hole 2-1 is greater than that of the laser trigger secondary hole 2-2; The laser trigger hole 2 is arranged near the negative electrode 10, the diameter of the laser trigger primary hole 2-1 is 200 μm-400 μm, and the diameter of the laser trigger secondary hole 2-2 is 100 μm-200 μm, i.e. the diameter of the primary hole and the diameter of the secondary hole are in a 2:1 relationship.

[0030] The metal electrode is a metal deposition layer of Ni / AuGe / Ni, the electrode gap is 3 mm-8 mm, the electrode close to the laser trigger hole 2 is the negative electrode 10, and the electrode away from the laser trigger hole 2 is the positive electrode 1.

[0031] The nested multi-hole 3 is composed of a nested primary hole 3-1 and a nested secondary hole 3-2 arranged in sequence from top to bottom, and the diameter of the nested primary hole 3-1 is greater than that of the nested secondary hole 3-2; As shown, Figure 3 A cylindrical micro-trap structure with a large aspect ratio, i.e. the nested multi-hole 3, is etched on the surface of the semi-insulating gallium arsenide material, the diameter ratio of the nested primary hole 3-1 to the nested secondary hole 3-2 is 2:1, and the diameter of the nested primary hole 3-1 ranges from 100 μm to 300 μm, which is more conducive to the capture of electrons 12.

[0032] The nested micro-trap structure is formed on the surface of semi-insulating gallium arsenide by a multi-exposure lithography mode, the interval between columns is equal to 100-300 mu m, the interval between rows is equal to 100-300 mu m, and the gap between the adjacent two nested multi-holes 3 and the diameter of the nested primary hole 3-1 are in a 1:1 relationship, that is, the distance between every two column holes is separated by a primary hole, which is conducive to inhibiting the development of flashover.

[0033] The composite coating layer 8 comprises a SiO2 layer 8-1 and a Si3N4 layer 8-2 arranged in sequence from top to bottom; The GaAs layer 5 region corresponding to the edge of the laser trigger primary hole 2-1, the plurality of nested primary holes 3-1, the positive electrode 1 and the negative electrode 10 is provided with a SiO2 layer 8-1; The upper surface of the SiO2 layer 8-1, the laser trigger hole 2 and the plurality of nested multi-holes 3 are paved with the SiO2 layer 8-1, and the Si3N4 layer 8-2 is located between the GaAs layer 5 and the SiO2 layer 8-1.

[0034] The plurality of nested multi-holes 3 are uniformly arranged in an M-row-by-N-column array, and M and N are positive integers; The interval between the adjacent two nested multi-holes 3 in each column is equal to the diameter of the nested primary hole 3-1; the interval between columns is equal to 100-300 mu m, and the interval between rows is equal to 100-300 mu m.

[0035] The material of the metal layer 7 is copper plate; the material of the insulating layer 6 is Al2O3; and the materials of the positive electrode 1 and the negative electrode 10 are both Ni / AuGe / Ni low-resistance alloy.

[0036] The semi-insulating gallium arsenide photoconductive switch with the nested multi-hole multi-layer structure of the application adopts a surface microstructure, and combines the surface coating and vacuum cofferdam glue filling technology to suppress the secondary emission coefficient of the material surface. Specifically, a new type of two-level nested micro-trap structure array is realized by using a multi-exposure technology (Litho-Etch-Litho-Etch, LELE), and a multi-layer coating is used to effectively suppress the generation of secondary electrons on the material surface. Finally, high-temperature cofferdam vacuum glue filling is realized to realize the suppression of the total secondary electron emission on the surface, so as to achieve the purpose of improving the withstand voltage capacity.

[0037] Compared with the conventional single-hole or single-channel structure, the nested multi-hole array of the nested multi-hole multi-layer structure semi-insulating gallium arsenide photoconductive switch can effectively suppress the generation of surface secondary electrons. In particular, the nested structure with a larger aspect ratio can more effectively suppress the electron multiplication in the trap, further improving the suppression effect on the secondary electrons. Again, since the nested holes are filled with SiO2, an electron blocking layer is formed on the surface of the semi-insulating gallium arsenide, so that electrons can only flow from the semi-insulating gallium arsenide body, thereby avoiding the escape of surface electrons. Finally, the staggered distribution of the micro-trap structure helps to further reduce the probability of surface flashover.

[0038] The nested multi-hole multi-layer structure semi-insulating gallium arsenide photoconductive switch is sequentially provided with an organic silicone gel layer, an SiO2 layer, an Si3N4 layer, a two-dimensional two-stage nested micro-trap structure gallium arsenide material layer, an Al2O3 insulating layer, and a copper plate layer from top to bottom. The refractive index of the multi-layer dielectric coating increases in turn.

[0039] Finally, the high-temperature cofferdam vacuum glue filling process is used on the outside of the switch, and the organic silicone gel is used for packaging.

[0040] In summary, the multi-hole multi-layer structure semi-insulating gallium arsenide photoconductive switch of the present application can effectively reduce the secondary electron emission coefficient of the surface of the semi-insulating gallium arsenide material, suppress the occurrence of switch surface flashover, improve the withstand voltage capability of the switch, and improve the performance of the switch.

[0041] The present application also provides a preparation method of the above-mentioned nested multi-hole multi-layer structure semi-insulating gallium arsenide photoconductive switch, specifically comprising: Step 1: pretreatment of gallium arsenide wafer; Step 1 specifically comprises: using a chemical etching method to clean the gallium arsenide wafer with a hydrochloric acid hydrogen peroxide solution to remove the oxide layer, and then sequentially cleaning the wafer with deionized water, acetone, methanol, and new deionized water for 3-5 minutes; then using a dry high-pressure nitrogen gas gun to dry the water on the surface of the gallium arsenide wafer; and finally baking in a 100-120℃ oven for 10-20 minutes to evaporate the residual moisture on the surface of the gallium arsenide wafer; The components of the hydrochloric acid hydrogen peroxide solution and the corresponding volume ratio are specifically HCl:H2O2:H2O = 1:1:5-10. Step 2: depositing an Si3N4 layer 8-2; Step 2 specifically comprises: An Si3N4 layer 8-2 is deposited on the gallium arsenide wafer treated in step 1, with a thickness of 10-40 μm; Step 3: photoetching of primary holes, including laser trigger primary holes 2-1 and nested primary holes 3-1; Step 3 specifically comprises: Step 3.1: After the GaAs wafer is treated in Step 2, photoresist 11 is coated on the wafer, and AZ1350J photoresist 11 is used, with a thickness of 0.8 μm; Step 3.2: Soft baking; The GaAs wafer is heated using an 80-90°C hot plate for 1-3 minutes to volatilize the organic solvent in the photoresist 11, and the organic solvent content is reduced to 3-5% after soft baking; Step 3.3: First alignment and exposure; First, the nested hole mask plate is fixed on the mask plate holder, and then the soft-baked GaAs wafer is fixed on the wafer chuck; contact exposure is used to obtain high spatial resolution and 1:1 conversion size; the exposure dose is 240 mJ / cm 3 , and the wavelength is 365 nm.

[0042] Step 3.4: Development; The exposed wafer is placed in a developing solution for development, and then the wafer is placed in deionized water for cleaning. Finally, the wafer surface is blown dry with a dry nitrogen gun; The developing solution is a tetramethylammonium hydroxide (TMAH) aqueous solution, and the volume of TMAH accounts for 2.38% of the TMAH aqueous solution; Step 3.5: Hard baking; The developed wafer is baked on a 100-120°C hot plate for 25-35 minutes to remove the remaining solvent in the photoresist 11 and enhance the adhesion of the photoresist 11; Step 3.6: Etching primary circular holes, etching away the exposed Si3N4 layer on the hard-baked wafer, and then etching the exposed GaAs material to a depth of 100-300 μm and a circular hole diameter of 100-300 μm.

[0043] Step 3.7: Removing the photoresist 11 on the wafer after lithography.

[0044] Step 4: Lithography of secondary holes, including laser trigger secondary holes 2-2 and nested secondary holes 3-2; Step 4 is as follows: Step 4.1: Coating photoresist 11 on the wafer treated in Step 3, using AZ1350J photoresist, with a thickness of 0.8 μm; Step 4.2: Soft baking of the wafer coated with photoresist 11; The wafer is heated using an 80-90°C hot plate for 1-3 minutes to volatilize the solvent in the photoresist 11, and the solvent content is reduced to 3-5% after soft baking; Step 4.3: Second alignment and exposure; First, fix the nest hole mask on the mask holder, then fix the wafer on the wafer chuck after soft baking treatment; adopt contact exposure, so as to obtain higher spatial resolution and 1:1 conversion size; the exposure dose is 170 mJ / cm 3 , wavelength 365 nm; Step 4.4: Development; Put the exposed wafer into the developing solution for development; then put the wafer into deionized water for cleaning; finally, dry the wafer surface with a dry nitrogen gun; The developing solution is a tetramethyl ammonium hydroxide (TMAH) aqueous solution, and the volume of the tetramethyl ammonium hydroxide accounts for 2.38% of the tetramethyl ammonium hydroxide aqueous solution; Step 4.5: Hard baking; Bake the developed wafer on the electric hot plate at 100-120°C for 25-35 minutes to remove the residual solvent in the photoresist 11 and enhance the adhesion of the photoresist 11; Step 4.6: Etching secondary circular hole, etching the exposed GaAs material on the wafer after hard baking, depth 100-300 μm, secondary circular hole diameter 50-150 μm; Step 4.7: Remove the photoresist 11 on the wafer after hard baking; The specific process of steps 1-4 is shown in Figure 6 ; Step 5: Fill the primary hole and the secondary hole; Step 5 is specifically: Depositing a SiO2 layer 8-1 on the wafer after step 4 processing, thickness 20-60 μm.

[0045] Step 6: Make electrode; Step 6 is specifically: Step 6.1: Apply photoresist 11 on the wafer after step 5 processing, using AZ1350J photoresist 11, thickness 0.8 μm; Step 6.2: Soft baking of wafer; Heat with 80-90°C electric hot plate for 1-3 minutes to volatilize the solvent from the photoresist 11, and reduce the solvent content to 3-5% after soft baking; First, fix the electrode mask on the mask holder, then fix the wafer on the wafer chuck after soft baking treatment; adopt contact exposure, so as to obtain higher spatial resolution and 1:1 conversion size; the exposure dose is 170 mJ / cm 3 , wavelength 365 nm; Step 6.3: Development; The exposed wafer is placed in a developing solution for development, then the wafer is placed in deionized water for cleaning, and finally the wafer surface is blown dry with a dry nitrogen gun; The developing solution is a tetramethylammonium hydroxide (TMAH) aqueous solution, and the volume of the tetramethylammonium hydroxide accounts for 2.38% of the tetramethylammonium hydroxide aqueous solution; Step 6.4: hard baking; The developed wafer is baked on a hot plate at 100-120°C for 25-35 minutes to remove the remaining solvent in the photoresist 11 and enhance the adhesion of the photoresist 11; Step 6.5: sequentially etching the SiO2 layer 8-1, the Si3N4 layer 8-2, and the GaAs layer 5, and then sequentially depositing a Ge layer with a thickness of 50-100 nm, a Ni layer with a thickness of 80-120 nm, and an Au layer with a thickness of 200-300 nm on the etched wafer; The treated wafer is heated to 350-500°C under the protection of inert gas N2 or A r The positive electrode 1 and the negative electrode 10 of Ni / AuGe / Ni low-resistance alloy are formed on the wafer; The photoresist 11 on the treated wafer is removed, and two ohmic contact alloy electrodes are formed on the wafer; Step 7: dicing, assembling, and dike sealing.

[0046] Step 7 is specifically: Step 7.1: dicing the wafer treated in step 6 using a dicing machine to dice the chip; Step 7.2: placing the switch unit chip peeled off after dicing on the Al2O3 insulating layer 6 to form a microstrip structure, and the Al2O3 insulating layer 6 is provided below with a metal layer 7 made of copper; Step 7.3: setting a dike 4 on the switch unit, and using epoxy resin to set the dike 4 on the chip, the dike 4 has a size of 0.2-0.5 mm in height, 3-8 mm in length, 40-60 mm in width, and 0.1-0.2 mm in wall thickness, to prevent overflow of the silicone gel during solidification; Step 7.4: placing the assembled chip into a drying box for drying and heating, and baking on a hot plate at 50-60°C for 15-30 minutes to reduce air adhesion on the surface of the chip; Step 7.5: pouring silicone gel into the dike 4 to form a sealing layer 9; Step 7.6: placing the device treated in step 7.5 into a vacuum box for vacuumizing for 30-60 minutes to remove air in the gel; Step 7.7: Put the device treated in step 7.6 into a drying oven for drying for 24-48 hours until the silicone gel is solidified.

[0047] Embodiment 1 The nested multi-hole multi-layer structure of the semi-insulating gallium arsenide photoconductive switch comprises a bottom layer unit and a GaAs layer 5 arranged from bottom to top; a combined hole unit is formed on the upper surface of the GaAs layer 5; a composite plating layer 8 is laid on the upper surface of the GaAs layer 5, and the composite plating layer 8 is used to fill the combined hole unit; The composite plating layer 8 is embedded with a positive electrode 1 and a negative electrode 10, and the bottom surfaces of the positive electrode 1 and the negative electrode 10 are in embedded contact with the upper surface of the GaAs layer 5; The combined hole unit is located in the GaAs layer 5 region between the positive electrode 1 and the negative electrode 10; a cofferdam 4 is arranged on the upper surface of the composite plating layer 8 between the positive electrode 1 and the negative electrode 10, the projection of the combined hole unit on the composite plating layer 8 is in the cofferdam 4, and the cofferdam 4 is filled with a sealing layer 9.

[0048] The bottom layer unit comprises a metal layer 7 and an insulating layer 6 arranged from bottom to top.

[0049] The material of the cofferdam 4 is epoxy resin, and the sealing layer 9 is an organic silicone gel layer.

[0050] The combined hole unit comprises a laser trigger hole 2 and a plurality of nested multi-holes 3; the negative electrode 10 is arranged on the side close to the laser trigger hole 2, and the positive electrode 1 is arranged on the side away from the laser trigger hole 2; The laser trigger hole 2 is composed of a laser trigger primary hole 2-1 and a laser trigger secondary hole 2-2 arranged from top to bottom, and the diameter of the laser trigger primary hole 2-1 is greater than that of the laser trigger secondary hole 2-2; The laser trigger hole 2 is arranged near the negative electrode 10, the diameter of the laser trigger primary hole 2-1 is 200 μm, and the diameter of the laser trigger secondary hole 2-2 is 100 μm, i.e. the diameter of the primary hole is in a 2:1 relationship with the diameter of the secondary hole.

[0051] The metal electrode is a metal deposition layer of Ni / AuGe / Ni, the electrode gap is 3 mm, the electrode close to the laser trigger hole 2 is the negative electrode 10, and the electrode away from the laser trigger hole 2 is the positive electrode 1.

[0052] The nested multi-hole 3 is composed of a nested primary hole 3-1 and a nested secondary hole 3-2 arranged from top to bottom, and the diameter of the nested primary hole 3-1 is greater than that of the nested secondary hole 3-2; A cylindrical micro-trap structure with a large aspect ratio, i.e. the nested multi-hole 3, is etched on the surface of the semi-insulating gallium arsenide material, the diameter ratio of the nested primary hole 3-1 to the nested secondary hole 3-2 is 2:1, and the diameter of the nested primary hole 3-1 is 100 μm, which is more conducive to the capture of electrons 12.

[0053] The nested micro-trap structures are formed on the surface of the semi-insulating gallium arsenide by a multiple-exposure photolithography mode, the distance between columns is equal to 100 mu m, the distance between rows is equal to 100 mu m, and the distance between the gaps of the adjacent two nested multi-holes 3 and the diameter of the nested primary hole 3-1 is in a 1:1 relationship, that is, the distance between every two column holes is separated by a primary hole, which is conducive to inhibiting the development of flashover.

[0054] The composite coating layer 8 comprises a SiO2 layer 8-1 and a Si3N4 layer 8-2 arranged in sequence from top to bottom. The GaAs layer 5 region corresponding to the edge of the laser trigger primary hole 2-1, the plurality of nested primary holes 3-1, the positive electrode 1 and the negative electrode 10 is provided with a SiO2 layer 8-1. The upper surface of the SiO2 layer 8-1, the laser trigger hole 2 and the plurality of nested multi-holes 3 are paved with a SiO2 layer 8-1, and the Si3N4 layer 8-2 is located between the GaAs layer 5 and the SiO2 layer 8-1.

[0055] The thickness of the SiO2 layer 8-1 is 20 mu m-60 mu m, and the thickness of the Si3N4 layer 8-2 is 10 mu m-40 mu m.

[0056] The plurality of nested multi-holes 3 are uniformly arranged in an M row by N column array, and M and N are positive integers. The distance between the adjacent two nested multi-holes 3 in each column is equal to the diameter of the nested primary hole 3-1; the distance between columns is equal to 100 mu m, and the distance between rows is equal to 100 mu m.

[0057] Embodiment 2 The nested multi-hole multi-layer structure of the semi-insulating gallium arsenide photoconductive switch comprises a bottom unit and a GaAs layer 5 arranged in sequence from bottom to top; a combined hole unit is opened on the upper surface of the GaAs layer 5; a composite coating layer 8 is paved on the upper surface of the GaAs layer 5, and the composite coating layer 8 is used to fill the combined hole unit; The positive electrode 1 and the negative electrode 10 are embedded in the composite coating layer 8, and the bottom surfaces of the positive electrode 1 and the negative electrode 10 are in embedded contact with the upper surface of the GaAs layer 5; The combined hole unit is located in the GaAs layer 5 region between the positive electrode 1 and the negative electrode 10; a cofferdam 4 is arranged on the upper surface of the composite coating layer 8 between the positive electrode 1 and the negative electrode 10, the projection of the combined hole unit on the composite coating layer 8 is in the cofferdam 4, and the cofferdam 4 is filled with a sealing layer 9.

[0058] The bottom unit comprises a metal layer 7 and an insulating layer 6 arranged in sequence from bottom to top.

[0059] The material of the cofferdam 4 is epoxy resin; and the sealing layer 9 is an organic silicone gel layer.

[0060] The combined hole unit comprises a laser trigger hole 2 and a plurality of nested multi-holes 3; the negative electrode 10 is arranged on the side close to the laser trigger hole 2, and the positive electrode 1 is arranged on the side away from the laser trigger hole 2; The laser trigger hole 2 is composed of a laser trigger primary hole 2-1 and a laser trigger secondary hole 2-2 arranged from top to bottom, and the diameter of the laser trigger primary hole 2-1 is greater than that of the laser trigger secondary hole 2-2; The laser trigger hole 2 is arranged near the negative electrode 10, the diameter of the laser trigger primary hole 2-1 is 400 μm, and the diameter of the laser trigger secondary hole 2-2 is 200 μm, that is, the diameter of the primary hole is in a 2:1 relationship with the diameter of the secondary hole.

[0061] The metal electrode is a metal deposition layer of Ni / AuGe / Ni, the electrode gap is 8 mm, and the electrode close to the laser trigger hole 2 is the negative electrode 10, and the electrode away from the laser trigger hole 2 is the positive electrode 1.

[0062] The nested multi-hole 3 is composed of a nested primary hole 3-1 and a nested secondary hole 3-2 arranged from top to bottom, and the diameter of the nested primary hole 3-1 is greater than that of the nested secondary hole 3-2; The nested multi-hole 3 is etched on the surface of the semi-insulating gallium arsenide material to form a cylindrical micro-trap structure with a large aspect ratio, the diameter ratio of the nested primary hole 3-1 to the nested secondary hole 3-2 is 2:1, and the diameter of the nested primary hole 3-1 is 300 μm, which is more conducive to the capture of electrons 12.

[0063] The nested micro-trap structure is formed on the surface of the semi-insulating gallium arsenide by a multiple exposure lithography mode, the spacing between the columns and the rows is equal to 300 μm, and the gap between the two adjacent nested multi-holes 3 is in a 1:1 relationship with the diameter of the nested primary hole 3-1, that is, the distance between every two columns of holes is separated by a primary hole, which is conducive to the suppression of the development of flashover.

[0064] The composite coating layer 8 comprises a SiO2 layer 8-1 and a Si3N4 layer 8-2 arranged from top to bottom; The SiO2 layer 8-1 is arranged at the edge of the laser trigger primary hole 2-1, the plurality of nested primary holes 3-1, the positive electrode 1 and the negative electrode 10 corresponding to the GaAs layer 5 region; The SiO2 layer 8-1 is arranged on the upper surface of the SiO2 layer 8-1, the laser trigger hole 2 and the plurality of nested multi-holes 3, and the Si3N4 layer 8-2 is located between the GaAs layer 5 and the SiO2 layer 8-1.

[0065] The plurality of nested multi-holes 3 are uniformly arranged in an M row × N column array, and M and N are positive integers; The distance between two adjacent nested multi-holes 3 in each column is equal to the diameter of the nested primary hole 3-1; the distance between columns is equal to 300 μm, and the distance between rows is equal to 300 μm.

[0066] Embodiment 3 The nested multi-hole multilayer structure of the semi-insulating gallium arsenide photoconductive switch comprises a bottom unit and a GaAs layer 5 arranged in sequence from bottom to top; a combined hole unit is arranged on the upper surface of the GaAs layer 5; a composite plating layer 8 is arranged on the upper surface of the GaAs layer 5, and the composite plating layer 8 is used to fill the combined hole unit; The composite plating layer 8 is embedded with a positive electrode 1 and a negative electrode 10, and the bottom surfaces of the positive electrode 1 and the negative electrode 10 are in embedded contact with the upper surface of the GaAs layer 5; The combined hole unit is located in the GaAs layer 5 region between the positive electrode 1 and the negative electrode 10; a cofferdam 4 is arranged on the upper surface of the composite plating layer 8 between the positive electrode 1 and the negative electrode 10, the projection of the combined hole unit on the composite plating layer 8 is in the cofferdam 4, and the cofferdam 4 is filled with a sealing layer 9.

[0067] The bottom unit comprises a metal layer 7 and an insulating layer 6 arranged in sequence from bottom to top.

[0068] The material of the cofferdam 4 is epoxy resin, and the sealing layer 9 is an organic silicone gel layer.

[0069] The combined hole unit comprises a laser trigger hole 2 and a plurality of nested multi-holes 3; the negative electrode 10 is arranged on the side close to the laser trigger hole 2, and the positive electrode 1 is arranged on the side away from the laser trigger hole 2; The laser trigger hole 2 is composed of a laser trigger primary hole 2-1 and a laser trigger secondary hole 2-2 arranged in sequence from top to bottom, and the diameter of the laser trigger primary hole 2-1 is greater than the diameter of the laser trigger secondary hole 2-2; The laser trigger hole 2 is arranged near the negative electrode 10, the diameter of the laser trigger primary hole 2-1 is 300 μm, and the diameter of the laser trigger secondary hole 2-2 is 150 μm, i.e. the diameter of the primary hole and the diameter of the secondary hole are in a 2:1 relationship.

[0070] The metal electrode is a metal deposition layer of Ni / AuGe / Ni, the electrode gap is 6 mm, the electrode close to the laser trigger hole 2 is the negative electrode 10, and the electrode away from the laser trigger hole 2 is the positive electrode 1.

[0071] The nested multi-hole 3 is composed of a nested primary hole 3-1 and a nested secondary hole 3-2 arranged in sequence from top to bottom, and the diameter of the nested primary hole 3-1 is greater than the diameter of the nested secondary hole 3-2; The micro-trap structure of the large aspect ratio cylindrical micro-hole 3, i.e. the nested primary hole 3-1 and the nested secondary hole 3-2, is etched on the surface of the semi-insulating gallium arsenide material, and the diameter ratio of the nested primary hole 3-1 to the nested secondary hole 3-2 is 2:1, and the diameter of the nested primary hole 3-1 is 200 μm, which is more conducive to the capture of electrons 12.

[0072] The nested micro-trap structure is formed on the surface of the semi-insulating gallium arsenide by a multiple exposure lithography mode, the distance between the columns and the distance between the rows are both 200 μm, and the distance between the gap of the adjacent two nested micro-holes 3 and the diameter of the nested primary hole 3-1 is in a 1:1 relationship, i.e. the distance between every two columns of holes is separated by a primary hole, which is conducive to the suppression of the development of flashover.

[0073] The composite coating layer 8 comprises a SiO2 layer 8-1 and a Si3N4 layer 8-2 arranged in sequence from top to bottom; The GaAs layer 5 region corresponding to the edge of the laser trigger primary hole 2-1, the plurality of nested primary holes 3-1, the anode 1 and the cathode 10 is provided with a SiO2 layer 8-1; The upper surface of the SiO2 layer 8-1, the laser trigger hole 2 and the plurality of nested micro-holes 3 are paved with the SiO2 layer 8-1, and the Si3N4 layer 8-2 is located between the GaAs layer 5 and the SiO2 layer 8-1.

[0074] The plurality of nested micro-holes 3 are uniformly arranged in an M row by N column array, and M and N are both positive integers; The distance between the adjacent two nested micro-holes 3 in each column is equal to the diameter of the nested primary hole 3-1; the distance between the columns and the distance between the rows are both 200 μm.

[0075] Embodiment 4 The preparation method of the semi-insulating gallium arsenide photoconductive switch with the nested micro-hole multilayer structure, specifically comprises: Step 1: pretreatment of the gallium arsenide wafer; Step 1 specifically comprises: using a chemical etching method, cleaning the gallium arsenide wafer with a hydrochloric acid hydrogen peroxide solution to remove the oxide layer, and then sequentially cleaning the wafer with deionized water, acetone, methanol, and new deionized water for 3 minutes; then the water on the surface of the gallium arsenide wafer is blown dry with a dry high-pressure nitrogen gas gun; finally, the wafer is baked in a 100℃ oven for 10 minutes to evaporate the residual moisture on the surface of the gallium arsenide wafer; wherein the components and corresponding volume ratio of the hydrochloric acid hydrogen peroxide solution are specifically HCl:H2O2:H2O = 1:1:5; Step 2: depositing the Si3N4 layer 8-2; Step 2 specifically comprises: depositing the Si3N4 layer 8-2 on the gallium arsenide wafer treated in Step 1, with a thickness of 10 μm; Step 3: photoetching primary holes, the photoetched primary holes include laser triggered primary holes 2-1 and nested primary holes 3-1; Step 3 is specifically: Step 3.1: coating photoresist 11 on the GaAs wafer processed in Step 2, using AZ1350J photoresist 11, thickness 0.8 μm; Step 3.2: soft baking; using an 80-90°C hot plate to heat the GaAs wafer for 1-3 minutes to volatilize the organic solvent in the photoresist 11, so that the organic solvent content is reduced to 5% after soft baking; Step 3.3: first alignment and exposure; first fix the nested hole mask plate on the mask plate holder, and then fix the soft-baked GaAs wafer on the wafer chuck; using contact exposure, which can obtain higher spatial resolution and 1:1 conversion size; exposure dose is 240 mJ / cm 3 , wavelength 365 nm. Step 3.4: development; put the exposed wafer into the developer for development; then put the wafer into deionized water for cleaning. Finally, use a dry nitrogen gun to blow off the deionized water on the wafer surface; wherein the developer is a tetramethylammonium hydroxide (TMAH) aqueous solution, and the volume of tetramethylammonium hydroxide accounts for 2.38% of the TMAH aqueous solution; Step 3.5: hard baking; bake the developed wafer on a 100°C hot plate for 25 minutes to remove the remaining solvent in the photoresist 11 and enhance the adhesion of the photoresist 11; Step 3.6: etching primary circular holes, etching away the exposed Si3N4 layer on the hard-baked wafer, and then etching the exposed GaAs material to a depth of 100 μm and a circular hole diameter of 100 μm. Step 3.7: removing the photoresist 11 on the wafer after photoetching.

[0076] Step 4: photoetching secondary holes, the photoetched secondary holes include laser triggered secondary holes 2-2 and nested secondary holes 3-2; Step 4 is specifically: Step 4.1: coating photoresist 11 on the wafer processed in Step 3, using AZ1350J photoresist, thickness 0.8 μm; Step 4.2: soft baking the wafer coated with photoresist 11; using an 80°C hot plate to heat for 1-3 minutes to volatilize the solvent from the photoresist 11, so that the solvent content is reduced to 3% after soft baking; Step 4.3: second alignment and exposure; first fix the nested hole mask plate on the mask plate holder, and then fix the soft-baked wafer on the wafer chuck; using contact exposure, which can obtain higher spatial resolution and 1:1 conversion size; exposure dose is 170 mJ / cm 3, wavelength 365nm; Step 4.4: Development; Place the exposed wafer in a developer for development; Then place the wafer in deionized water for cleaning; Finally, use a dry nitrogen gun to blow dry the deionized water on the wafer surface; Wherein, the developer is a tetramethylammonium hydroxide (TMAH) aqueous solution, and the volume of tetramethylammonium hydroxide accounts for 2.38% of the tetramethylammonium hydroxide aqueous solution; Step 4.5: Hard baking; The developed wafer is baked on a hot plate at 100°C for 25 minutes to remove the remaining solvent in the photoresist 11 and enhance the adhesion of the photoresist 11; Step 4.6: Etch secondary circular holes to etch the GaAs material exposed on the wafer after hard baking, with a depth of 100μm and a secondary circular hole diameter of 50μm; Step 4.7: Remove the photoresist 11 on the wafer after hard baking; Step 5: Filling the primary holes and the secondary holes; Step 5 specifically comprises: depositing a SiO2 layer 8-1 with a thickness of 20 μm on the wafer processed in step 4.

[0077] Step 6: Make electrodes; Step 6 specifically includes: Step 6.1: Apply photoresist 11 on the wafer processed in Step 5, using AZ1350J photoresist 11 with a thickness of 0.8μm; Step 6.2: Soft bake the wafer; Heat it on an 80℃-90℃ hot plate for 1 minute to evaporate the solvent from the photoresist 11, and reduce the solvent content to 3% after soft baking; First, fix the electrode mask on the mask holder, and then fix the soft-baked wafer on the wafer chuck; Use contact exposure to obtain higher spatial resolution and 1:1 conversion size; The exposure dose is 170mJ / cm 3 , wavelength 365nm; step 6.3: development; the exposed wafer is placed in a developer for development; the wafer is then placed in deionized water for cleaning; finally, the deionized water on the wafer surface is blown dry with a dry nitrogen gun; wherein the developer is a tetramethylammonium hydroxide (TMAH) aqueous solution, and the volume of tetramethylammonium hydroxide accounts for 2.38% of the tetramethylammonium hydroxide aqueous solution; step 6.4: hard baking; the developed wafer is baked on a hot plate at 100°C for 25 minutes to remove the remaining solvent in the photoresist 11 and enhance the adhesion of the photoresist 11; step 6.5: sequentially etch the SiO2 layer 8-1, the Si3N4 layer 8-2 and the GaAs layer 5, and then sequentially deposit a Ge layer with a thickness of 50nm, a Ni layer with a thickness of 80nm and an Au layer with a thickness of 200nm on the etched wafer; the processed wafer is heated under an inert gas N2 or A r Under protection, heating to 350°C and keeping the temperature for 3 minutes; forming a positive electrode 1 and a negative electrode 10 made of Ni / AuGe / Ni low-resistance alloy on the wafer; removing the photoresist 11 on the processed wafer, forming two ohmic contact alloy electrodes on the wafer; Step 7: scribing, assembling and damming glue. Step 7 specifically comprises: Step 7.1: scribing the wafer after the treatment in Step 6, and using a scribe machine to scribe the chip; Step 7.2: placing the switch unit chip peeled off after scribing on the insulating layer 6 made of Al2O3 to form a microstrip line structure; wherein the insulating layer 6 made of Al2O3 is provided below with a metal layer 7 made of copper; Step 7.3: setting a dam 4 on the switch unit, and using epoxy resin to set the dam 4 on the chip, the dam 4 having a size of: height 0.2 mm, length 3 mm, width 40 mm, and wall thickness 0.1 mm; preventing overflow of the silicone gel during solidification; Step 7.4: placing the assembled chip into a drying box for drying and heating, baking on a 50℃ hot plate for 15 minutes to reduce air adhesion on the surface of the chip; Step 7.5: pouring glue, pouring silicone gel into the dam 4 to form a sealing layer 9; Step 7.6: placing the device treated in Step 7.5 into a vacuum box for vacuumizing for 30 minutes to remove air in the glue; Step 7.7: placing the device treated in Step 7.6 into a drying box for drying for 24 hours until the silicone gel is solidified.

[0078] Example 5 The preparation method of the semi-insulating gallium arsenide photoconductive switch with a nested porous multilayer structure specifically comprises: Step 1: pretreatment of a gallium arsenide wafer; Step 1 specifically comprises: using a chemical etching method to clean the gallium arsenide wafer with a hydrochloric acid hydrogen peroxide solution to remove the oxide layer, and then sequentially cleaning the wafer with deionized water, acetone, methanol, and new deionized water for 5 minutes; then blowing the water on the surface of the gallium arsenide wafer with a dry high-pressure nitrogen gun; and finally baking in a 120℃ oven for 20 minutes to evaporate the residual water on the surface of the gallium arsenide wafer; wherein the components and corresponding volume ratio of the hydrochloric acid hydrogen peroxide solution are specifically: HCl:H2O2:H2O = 1:1:10; Step 2: depositing a Si3N4 layer 8-2; Step 2 specifically comprises: depositing a Si3N4 layer 8-2 on the gallium arsenide wafer treated in Step 1, with a thickness of 40μm; Step 3: photoetching primary holes, the photoetched primary holes include laser triggered primary holes 2-1 and nested primary holes 3-1; Step 3 specifically comprises: Step 3.1: coating photoresist 11 on the GaAs wafer processed in Step 2, using AZ1350J photoresist 11, thickness 0.8 μm; Step 3.2: soft baking; using an 80-90°C hot plate to heat the GaAs wafer for 1-3 minutes to volatilize the organic solvent in the photoresist 11, so that the organic solvent content is reduced to 5% after soft baking; Step 3.3: first alignment and exposure; first fix the nested hole mask plate on the mask plate holder, then fix the soft-baked GaAs wafer on the wafer chuck; using contact exposure, so that higher spatial resolution and 1:1 conversion size can be obtained; exposure dose is 240 mJ / cm 3 , wavelength 365 nm. Step 3.4: development; put the exposed wafer into the developer for development; then put the wafer into deionized water for cleaning. Finally, use a dry nitrogen gun to dry the wafer surface deionized water; wherein the developer is a tetramethylammonium hydroxide (TMAH) aqueous solution, the volume of tetramethylammonium hydroxide accounts for 2.38% of the tetramethylammonium hydroxide aqueous solution; Step 3.5: hard baking; bake the developed wafer on a 120°C hot plate for 35 minutes to remove the remaining solvent in the photoresist 11 and enhance the adhesion of the photoresist 11; Step 3.6: etching primary circular holes, etching away the exposed Si3N4 layer on the hard-baked wafer, then etching the exposed GaAs material, depth 300 μm, circular hole diameter 300 μm. Step 3.7: removing the photoresist 11 on the wafer after photoetching.

[0079] Step 4: photoetching secondary holes, the photoetched secondary holes include laser triggered secondary holes 2-2 and nested secondary holes 3-2; Step 4 specifically comprises: Step 4.1: coating photoresist 11 on the wafer processed in Step 3, using AZ1350J photoresist, thickness 0.8 μm; Step 4.2: soft baking the wafer coated with photoresist 11; using a 90°C hot plate to heat for 3 minutes to volatilize the solvent from the photoresist 11, so that the solvent content is reduced to 5% after soft baking; Step 4.3: second alignment and exposure; first fix the nested hole mask plate on the mask plate holder, then fix the soft-baked wafer on the wafer chuck; using contact exposure, so that higher spatial resolution and 1:1 conversion size can be obtained; exposure dose is 170 mJ / cm 3, wavelength 365nm; Step 4.4: Development; Place the exposed wafer in a developer for development; Then place the wafer in deionized water for cleaning; Finally, use a dry nitrogen gun to blow dry the deionized water on the wafer surface; Wherein, the developer is a tetramethylammonium hydroxide (TMAH) aqueous solution, and the volume of tetramethylammonium hydroxide accounts for 2.38% of the tetramethylammonium hydroxide aqueous solution; Step 4.5: Hard baking; Bake the developed wafer on a hot plate at 120°C for 35 minutes to remove the remaining solvent in the photoresist 11 and enhance the adhesion of the photoresist 11; Step 4.6: Etch secondary circular holes to etch the GaAs material exposed on the wafer after hard baking, with a depth of 300μm and a secondary circular hole diameter of 150μm; Step 4.7: Remove the photoresist 11 on the wafer after hard baking; Step 5: Filling the primary holes and the secondary holes; Step 5 specifically comprises: depositing a SiO2 layer 8-1 with a thickness of 60 μm on the wafer processed in step 4.

[0080] Step 6: Make electrodes; Step 6 specifically includes: Step 6.1: Apply photoresist 11 on the wafer processed in Step 5, using AZ1350J photoresist 11 with a thickness of 0.8 μm; Step 6.2: Soft bake the wafer; Heat on a 90°C hot plate for 3 minutes to evaporate the solvent from the photoresist 11, and reduce the solvent content to 5% after soft baking; First, fix the electrode mask on the mask holder, and then fix the soft-baked wafer on the wafer chuck; Use contact exposure to obtain higher spatial resolution and 1:1 conversion size; The exposure dose is 170 mJ / cm 3 , wavelength 365nm; step 6.3: development; the exposed wafer is placed in a developer for development; the wafer is then placed in deionized water for cleaning; finally, the deionized water on the wafer surface is blown dry with a dry nitrogen gun; wherein the developer is a tetramethylammonium hydroxide (TMAH) aqueous solution, and the volume of tetramethylammonium hydroxide accounts for 2.38% of the tetramethylammonium hydroxide aqueous solution; step 6.4: hard baking; the developed wafer is baked on a hot plate at 120°C for 35 minutes to remove the remaining solvent in the photoresist 11 and enhance the adhesion of the photoresist 11; step 6.5: sequentially etch the SiO2 layer 8-1, the Si3N4 layer 8-2 and the GaAs layer 5, and then sequentially deposit a Ge layer with a thickness of 100nm, a Ni layer with a thickness of 120nm and an Au layer with a thickness of 300nm on the etched wafer; the processed wafer is heated under an inert gas N2 or A r Under protection, heating to 500°C and keeping the temperature for 4 minutes; forming a positive electrode 1 and a negative electrode 10 made of Ni / AuGe / Ni low-resistance alloy on the wafer; removing the photoresist 11 on the processed wafer, forming two ohmic contact alloy electrodes on the wafer; Step 7: scribing, assembling and damming glue. Step 7 specifically comprises: Step 7.1: scribing the wafer after the treatment in Step 6, and using a scribing machine to scribe the chip; Step 7.2: placing the switch unit chip peeled off after scribing on the insulating layer 6 made of Al2O3 to form a microstrip line structure; wherein the insulating layer 6 made of Al2O3 is provided below with a metal layer 7 made of copper; Step 7.3: setting a dam 4 on the switch unit, and using epoxy resin to set the dam 4 on the chip, the dam 4 having a size of: height 0.5 mm, length 8 mm, width 60 mm, and wall thickness 0.2 mm; preventing overflow of the silicone gel during solidification; Step 7.4: placing the assembled chip into a drying box for drying and heating, baking on an electric hot plate at 60°C for 30 minutes to reduce air adhesion on the surface of the chip; Step 7.5: pouring glue, pouring silicone gel into the dam 4 to form a sealing layer 9; Step 7.6: placing the device treated in Step 7.5 into a vacuum box for vacuum pumping for 60 minutes to remove air in the glue; Step 7.7: placing the device treated in Step 7.6 into a drying box for drying for 48 hours until the silicone gel is solidified.

[0081] Example 6 The preparation method of the nested porous multilayer structure of the semi-insulating gallium arsenide photoconductive switch specifically comprises: Step 1: pretreatment of a gallium arsenide wafer; Step 1 specifically comprises: using a chemical etching method, cleaning the gallium arsenide wafer with a hydrochloric acid hydrogen peroxide solution to remove the oxide layer, and then sequentially cleaning the wafer with deionized water, acetone, methanol, and new deionized water for 4 minutes; then blowing the water on the surface of the gallium arsenide wafer with a dry high-pressure nitrogen gun; and finally baking in a 100°C-120°C oven for 15 minutes to evaporate the residual moisture on the surface of the gallium arsenide wafer; wherein the components and corresponding volume ratio of the hydrochloric acid hydrogen peroxide solution are specifically: HCl:H2O2:H2O = 1:1:6; Step 2: depositing a Si3N4 layer 8-2; Step 2 specifically comprises: depositing a Si3N4 layer 8-2 on the gallium arsenide wafer treated in Step 1, with a thickness of 30 μm; Step 3: photoetching primary holes, the photoetched primary holes include laser triggered primary holes 2-1 and nested primary holes 3-1; Step 3 specifically comprises: Step 3.1: coating photoresist 11 on the GaAs wafer processed in Step 2, using AZ1350J photoresist 11, thickness 0.8 μm; Step 3.2: soft baking; using an 80-90°C hot plate to heat the GaAs wafer for 2 minutes to volatilize the organic solvent in the photoresist 11, so that the organic solvent content is reduced to 4% after soft baking; Step 3.3: first alignment and exposure; first fix the nested hole mask on the mask holder, then fix the soft-baked GaAs wafer on the wafer chuck; using contact exposure, which can obtain higher spatial resolution and 1:1 conversion size; exposure dose is 240 mJ / cm 3 , wavelength 365 nm; Step 3.4: development; put the exposed wafer into the developer for development; then put the wafer into deionized water for cleaning. Finally, use a dry nitrogen gun to dry the wafer surface deionized water; wherein the developer is a tetramethylammonium hydroxide (TMAH) aqueous solution, the volume of tetramethylammonium hydroxide accounts for 2.38% of the tetramethylammonium hydroxide aqueous solution; Step 3.5: hard baking; bake the developed wafer on a 100-120°C hot plate for 30 minutes to remove the remaining solvent in the photoresist 11 and enhance the adhesion of the photoresist 11; Step 3.6: etching primary circular holes, etching away the exposed Si3N4 layer on the hard-baked wafer, and then etching the exposed GaAs material to a depth of 200 μm and a circular hole diameter of 200 μm. Step 3.7: removing the photoresist 11 on the wafer after photoetching.

[0082] Step 4: photoetching secondary holes, the photoetched secondary holes include laser triggered secondary holes 2-2 and nested secondary holes 3-2; Step 4 specifically comprises: Step 4.1: coating photoresist 11 on the wafer processed in Step 3, using AZ1350J photoresist, thickness 0.8 μm; Step 4.2: soft baking the wafer coated with photoresist 11; using an 80-90°C hot plate to heat for 1-3 minutes to volatilize the solvent from the photoresist 11, so that the solvent content is reduced to 4% after soft baking; Step 4.3: second alignment and exposure; first fix the nested hole mask on the mask holder, then fix the soft-baked wafer on the wafer chuck; using contact exposure, which can obtain higher spatial resolution and 1:1 conversion size; exposure dose is 170 mJ / cm 3 , wavelength 365 nm; Step 4.4: Development; Place the exposed wafer in a developer for development; then place the wafer in deionized water for cleaning; finally, use a dry nitrogen gun to blow dry the deionized water on the wafer surface; wherein the developer is a tetramethylammonium hydroxide (TMAH) aqueous solution, and the volume of the tetramethylammonium hydroxide accounts for 2.38% of the tetramethylammonium hydroxide aqueous solution; Step 4.5: Hard Bake; Bake the developed wafer on a hot plate at 110°C for 30 minutes to remove the remaining solvent in the photoresist 11 and enhance the adhesion of the photoresist 11; Step 4.6: Etch secondary circular holes to etch the GaAs material exposed on the wafer after hard baking to a depth of 200 μm and a secondary circular hole diameter of 120 μm; Step 4.7: Remove the photoresist 11 on the wafer after hard baking; Step 5: Filling the primary holes and the secondary holes; Step 5 specifically comprises: depositing a SiO2 layer 8-1 with a thickness of 50 μm on the wafer processed in step 4.

[0083] Step 6: Make electrodes; Step 6 specifically includes: Step 6.1: Apply photoresist 11 on the wafer processed in Step 5, using AZ1350J photoresist 11 with a thickness of 0.8μm; Step 6.2: Soft bake the wafer; Heat on an 80℃-90℃ hot plate for 1 minute to 3 minutes to evaporate the solvent from the photoresist 11, and reduce the solvent content to 4% after soft baking; First, fix the electrode mask on the mask holder, and then fix the soft-baked wafer on the wafer chuck; Use contact exposure to obtain higher spatial resolution and 1:1 conversion size; The exposure dose is 170mJ / cm 3 , wavelength 365nm; step 6.3: development; the exposed wafer is placed in a developer for development; the wafer is then placed in deionized water for cleaning; finally, the deionized water on the wafer surface is blown dry with a dry nitrogen gun; wherein the developer is a tetramethylammonium hydroxide (TMAH) aqueous solution, and the volume of tetramethylammonium hydroxide accounts for 2.38% of the tetramethylammonium hydroxide aqueous solution; step 6.4: hard baking; the developed wafer is baked on a hot plate at 110°C for 30 minutes to remove the remaining solvent in the photoresist 11 and enhance the adhesion of the photoresist 11; step 6.5: sequentially etch the SiO2 layer 8-1, the Si3N4 layer 8-2 and the GaAs layer 5, and then sequentially deposit a Ge layer with a thickness of 60nm, a Ni layer with a thickness of 90nm and an Au layer with a thickness of 260nm on the etched wafer; the processed wafer is heated under an inert gas N2 or A r Under protection, heating to 400°C and keeping the temperature for 4 minutes; forming a positive electrode 1 and a negative electrode 10 made of Ni / AuGe / Ni low-resistance alloy on the wafer; removing the photoresist 11 on the processed wafer, forming two ohmic contact alloy electrodes on the wafer; Step 7: scribing, assembling and damming. Step 7 specifically comprises: Step 7.1: scribing the wafer after the treatment in Step 6, and using a scribing machine to scribe the chip; Step 7.2: placing the switch unit chip peeled off after scribing on the insulating layer 6 made of Al2O3 to form a microstrip line structure; wherein the insulating layer 6 made of Al2O3 is provided below with a metal layer 7 made of copper; Step 7.3: setting a dam 4 on the switch unit, and using epoxy resin to set the dam 4 on the chip, the dam 4 having a size of: height 0.4 mm, length 5 mm, width 50 mm, and wall thickness 0.1 mm; preventing overflow of the silicone gel during solidification; Step 7.4: placing the assembled chip into a drying box for drying and heating, baking on an electric hot plate at 55°C for 20 minutes to reduce air adhesion on the surface of the chip; Step 7.5: pouring the silicone gel into the dam 4 to form a sealing layer 9; Step 7.6: placing the device treated in Step 7.5 into a vacuum box for vacuumizing for 40 minutes to remove air in the gel; Step 7.7: placing the device treated in Step 7.6 into a drying box for drying for 30 hours until the silicone gel is solidified.

Claims

1. A nested, porous, multilayered structure, semi-insulating gallium arsenide photoconductive switch, characterized in that, The bottom layer unit and the GaAs layer (5) are sequentially arranged from bottom to top; the GaAs layer (5) is provided with a combined hole unit on the upper surface; the GaAs layer (5) is paved with a composite plating film layer (8) on the upper surface, and the composite plating film layer (8) is used for filling the combined hole unit; The composite plating film layer (8) is embedded with the positive electrode (1) and the negative electrode (10), and the bottom surfaces of the positive electrode (1) and the negative electrode (10) are in embedded contact with the upper surface of the GaAs layer (5); The upper surface of the composite plating film layer (8) between the positive electrode (1) and the negative electrode (10) is provided with a cofferdam (4), the projection of the combined hole unit on the composite plating film layer (8) is in the cofferdam (4), and the cofferdam (4) is filled with a sealing layer (9).

2. The nested, porous, multilayered structure, semi-insulating gallium arsenide photoconductive switch of claim 1, wherein, The bottom layer unit comprises a metal layer (7) and an insulating layer (6) sequentially arranged from bottom to top.

3. The nested, porous, multilayered structure, semi-insulating gallium arsenide photoconductive switch of claim 1, wherein, The material of the cofferdam (4) is epoxy resin; and the sealing layer (9) is a silicone gel layer.

4. The nested, porous, multilayered structure, semi-insulating gallium arsenide photoconductive switch of claim 2, wherein, The combined hole unit comprises a laser trigger hole (2) and a plurality of nested holes (3); the negative electrode (10) is arranged on one side close to the laser trigger hole (2), and the positive electrode (1) is arranged on the side away from the laser trigger hole (2); The laser trigger hole (2) is composed of a laser trigger primary hole (2-1) and a laser trigger secondary hole (2-2) sequentially arranged from top to bottom, the diameter of the laser trigger primary hole (2-1) is 200-400 μm, and the diameter of the laser trigger secondary hole (2-2) is 100-200 μm; The nested hole (3) is composed of a nested primary hole (3-1) and a nested secondary hole (3-2) sequentially arranged from top to bottom, the diameter ratio of the nested primary hole (3-1) to the nested secondary hole (3-2) is 2:1, and the diameter of the nested primary hole (3-1) is 100-300 μm; The composite plating film layer (8) comprises a SiO2 layer (8-1) and a Si3N4 layer (8-2) sequentially arranged from top to bottom; the thickness of the SiO2 layer (8-1) is 20-60 μm, and the thickness of the Si3N4 layer (8-2) is 10-40 μm; The region of the GaAs layer (5) corresponding to the edges of the laser trigger primary hole (2-1), the plurality of nested primary holes (3-1), the positive electrode (1) and the negative electrode (10) is provided with the SiO2 layer (8-1); The upper surface of the SiO2 layer (8-1), the laser trigger hole (2) and the plurality of nested holes (3) are paved with the SiO2 layer (8-1), and the Si3N4 layer (8-2) is located between the GaAs layer (5) and the SiO2 layer (8-1).

5. The nested, porous, multilayered structure, semi-insulating gallium arsenide photoconductive switch of claim 3, wherein, The plurality of nested holes (3) are uniformly arranged in an M row by N column array, and M and N are positive integers; The distance between the two adjacent nested holes (3) in each column is equal to the diameter of the nested primary hole (3-1); the distance between the columns is 100-300 μm, and the distance between the rows is 100-300 μm.

6. The nested, porous, multilayered structure, semi-insulating gallium arsenide photoconductive switch of claim 3, wherein, The material of the metal layer (7) is copper plate; the material of the insulating layer (6) is Al2O3; and the materials of the positive electrode (1) and the negative electrode (10) are both Ni / AuGe / Ni low-resistance alloy.

7. A method of fabricating a nested porous multilayer structure of a semi-insulating gallium arsenide photoconductive switch, characterized in that, Specifically, Step 1: GaAs wafer pretreatment; Step 2: Deposit Si3N4 layer (8-2); Step 3: Primary hole lithography, the primary hole lithography includes laser triggered primary hole (2-1) and nested primary hole (3-1); Step 4: Secondary hole lithography, the secondary hole lithography includes laser triggered secondary hole (2-2) and nested secondary hole (3-2); Step 5: Fill the primary hole and the secondary hole; Step 6: Make electrodes; Step 7: Dicing, assembly and coffer sealing.

8. The method of producing a nested porous multilayered structure of a semi-insulating gallium arsenide photoconductive switch according to claim 7, characterized by, Step 1 specifically: using chemical etching method, using hydrochloric acid hydrogen peroxide solution to clean the GaAs wafer to remove the oxide layer, and then sequentially using deionized water, acetone, methanol, new deionized water to ultrasonic clean the wafer for 3-5 minutes; then use dry high pressure nitrogen gun to blow dry the surface of GaAs wafer; finally, bake in 100-120℃ oven for 10-20 minutes to evaporate the residual moisture on the surface of GaAs wafer; Among them, the components and corresponding volume ratio of hydrochloric acid hydrogen peroxide solution are specifically: HCl:H2O2:H2O = 1:1:5-10; Step 2 specifically: Deposit Si3N4 layer (8-2) on the GaAs wafer treated in step 1, thickness is 10-40 μm; Step 3 specifically: Step 3.1: on the GaAs wafer treated in step 2, coat photoresist (11), using AZ1350J photoresist (11), thickness is 0.8 μm; Step 3.2: soft bake; Use 80-90℃ hot plate to heat the GaAs wafer for 1-3 minutes; Step 3.3: first alignment and exposure; First, the nested hole mask is fixed on the mask frame, and then the soft-baked gallium arsenide wafer is fixed on the wafer chuck; the contact exposure is adopted, the exposure dose is 240 mJ / cm 3 , and the wavelength is 365 nm; Step 3.4: development; Put the exposed wafer into the developing solution for development; then put the wafer into deionized water for cleaning; finally, use dry nitrogen gun to blow dry the deionized water on the surface of the wafer; Among them, the developing solution is tetramethylammonium hydroxide aqueous solution, the volume of tetramethylammonium hydroxide accounts for 2.38% of the tetramethylammonium hydroxide aqueous solution; Step 3.5: hard bake; Put the developed wafer on the 100-120℃ hot plate for 25-35 minutes; Step 3.6: etch primary hole, etch the exposed Si3N4 layer on the wafer after hard bake, and then etch the exposed GaAs material, depth is 100-300 μm, hole diameter is 100-300 μm; Step 3.7: remove the photoresist (11) on the wafer after lithography.

9. The method of producing a nested porous multilayered structure of a semi-insulating gallium arsenide photoconductive switch according to claim 7, characterized by, Step 4 specifically: Step 4.1: coat photoresist (11) on the wafer treated in step 3, using AZ1350J photoresist, thickness is 0.8 μm; Step 4.2: soft bake the wafer coated with photoresist (11); Use 80-90℃ hot plate to heat for 1-3 minutes; Step 4.3: second alignment and exposure; First, the nested hole mask is fixed on the mask frame, and then the wafer after soft baking is fixed on the wafer chuck; the contact exposure is adopted, the exposure dose is 170 mJ / cm 3 , and the wavelength is 365 nm; Step 4.4: development; Put the exposed wafer into the developing solution for development; then put the wafer into deionized water for cleaning; finally, use dry nitrogen gun to blow dry the deionized water on the surface of the wafer; The developing solution is a tetramethylammonium hydroxide aqueous solution, and the volume of the tetramethylammonium hydroxide accounts for 2.38% of the tetramethylammonium hydroxide aqueous solution; Step 4.5: hard baking; The developed wafer is baked on an electric hot plate at 100-120℃ for 25-35 minutes; Step 4.6: etching secondary circular holes, etching the exposed GaAs material on the wafer after hard baking, the depth is 100-300μm, and the diameter of the secondary circular hole is 50-150μm; Step 4.7: removing the photoresist (11) on the wafer after hard baking; Step 5 is specifically: A SiO2 layer (8-1) is deposited on the wafer after step 4 processing, and the thickness is 20-60μm.

10. The method of producing a nested, porous, multilayered structure of a semi-insulating gallium arsenide photoconductive switch according to claim 7, characterized in that, Step 6 is specifically: Step 6.1: applying photoresist (11) on the wafer after step 5 processing, using AZ1350J photoresist (11), and the thickness is 0.8μm; Step 6.2: soft baking the wafer; Heating with an electric hot plate at 80-90℃ for 1-3 minutes; First, the electrode mask plate is fixed on the mask plate frame, and then the wafer after soft baking treatment is fixed on the wafer chuck; contact exposure is adopted, and the exposure dose is 170 mJ / cm 3 , wavelength 365 nm; Step 6.3: developing; The exposed wafer is developed in a developing solution, then washed in deionized water, and finally the deionized water on the wafer surface is blown dry with a dry nitrogen gun; The developing solution is a tetramethylammonium hydroxide aqueous solution, and the volume of the tetramethylammonium hydroxide accounts for 2.38% of the tetramethylammonium hydroxide aqueous solution; Step 6.4: hard baking; The developed wafer is baked on an electric hot plate at 100-120℃ for 25-35 minutes; Step 6.5: etching the SiO2 layer (8-1), the Si3N4 layer (8-2) and the GaAs layer (5) in turn, and then depositing a Ge layer with a thickness of 50-100nm, a Ni layer with a thickness of 80-120nm and an Au layer with a thickness of 200-300nm on the etched wafer in turn; The processed wafer is heated to 350-500℃ under inert gas protection for 3-5 minutes, and the positive electrode (1) and the negative electrode (10) made of Ni / AuGe / Ni low-resistance alloy are formed on the wafer; The photoresist (11) on the processed wafer is removed, and two ohmic contact alloy electrodes are formed on the wafer; Step 7 is specifically: Step 7.1: dicing the wafer after step 6 processing, and using a dicing machine to dice the chip; Step 7.2: placing the switch unit chip peeled off after dicing on an insulating layer (6) made of Al2O3 to form a microstrip structure, and a metal layer (7) made of copper is arranged below the Al2O3 insulating layer (6); Step 7.3: arranging a cofferdam (4) on the switch unit, using epoxy resin to arrange the cofferdam (4) on the chip, and the size of the cofferdam (4) is: height 0.2-0.5mm, length 3-8mm, width 40-60mm, and wall thickness 0.1-0.2mm; preventing overflow when the silicone gel solidifies; Step 7.4: placing the combined chip into a drying oven for drying and heating, baking on an electric hot plate at 50-60℃ for 15-30 minutes to reduce the air adhesion on the surface of the chip; Step 7.5: Glue filling, pouring silicone gel into the cofferdam (4) to form a sealing layer (9); Step 7.6: Put the device treated in step 7.5 into a vacuum box, and vacuumize for 30-60 minutes to remove air in the glue; Step 7.7: Put the device treated in step 7.6 into a drying box for drying for 24-48 hours until the silicone gel is solidified.

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