Light emitting diode with improved EOS and preparation method thereof

Abstract

The invention provides a light emitting diode for improving EOS and a preparation method thereof, and belongs to the technical field of photoelectron manufacturing. The light-emitting diode comprises an epitaxial layer, an insulating layer and a metal reflecting layer, the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are stacked in sequence, and the surface of the second semiconductor layer is provided with a concave hole for exposing the first semiconductor layer; the insulating layer is located on the surface of the second semiconductor layer and in the concave hole, the surface of the insulating layer is provided with a first through hole and a second through hole which penetrate through the insulating layer, and the aperture of the first through hole is larger than that of the second through hole; the distance from the first through hole to the concave hole is smaller than the distance from the second through hole to the concave hole. According to the embodiment of the invention, the reflection effect of the light-emitting diode can be ensured, and the EOS capability of the light-emitting diode can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of optoelectronic manufacturing, and particularly relates to a light emitting diode with improved EOS and a preparation method thereof. BACKGROUND

[0002] Light emitting diode (LED) is a new product with great influence in the optoelectronic industry. EOS (Electrical Over Stress) refers to the maximum voltage or maximum current that the product device can withstand. After exceeding the maximum specified limit, the function of the LED will be weakened or damaged.

[0003] In the related art, the flip silver mirror LED chip includes an epitaxial layer, an insulating layer and a silver mirror reflection layer. The insulating layer is located on the surface of the epitaxial layer, the surface of the insulating layer has a through hole exposing the epitaxial layer, and the metal reflection layer is located on the surface of the insulating layer away from the epitaxial layer and is connected with the epitaxial layer through the through hole.

[0004] In order to improve the EOS capability of the LED, the through hole of the insulating layer is usually increased. However, increasing the size of the through hole of the insulating layer will result in a decrease in the area of the insulating layer, thereby resulting in weakened reflection and reduced brightness. SUMMARY

[0005] The present disclosure provides a light emitting diode with improved EOS and a preparation method thereof, which can ensure the reflection effect of the light emitting diode and improve the EOS capability of the light emitting diode. The technical solution is as follows:

[0006] In one aspect, the present disclosure provides a light emitting diode, which includes an epitaxial layer, an insulating layer and a metal reflection layer. The epitaxial layer includes a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer which are stacked in sequence. The surface of the second semiconductor layer has a recess hole exposing the first semiconductor layer. The insulating layer is located on the surface of the second semiconductor layer and in the recess hole. The surface of the insulating layer has a first through hole and a second through hole penetrating the insulating layer. The aperture of the first through hole is larger than the aperture of the second through hole. The distance from the first through hole to the recess hole is smaller than the distance from the second through hole to the recess hole.

[0007] In one implementation manner of the present disclosure, a plurality of the first through holes are uniformly distributed in a circular region with the center of the circular region being the central axis of the recess hole.

[0008] In another implementation manner of the present disclosure, the radius of the circular region is greater than or equal to three times the radius of the recess hole, and the radius of the circular region is less than or equal to five times the radius of the recess hole.

[0009] In a further implementation form of the disclosure, the radius of the recess is 12 μm to 30 μm.

[0010] In a further implementation form of the disclosure, the radius of the first through hole is greater than or equal to twice the radius of the second through hole.

[0011] In a further implementation form of the disclosure, the radius of the first through hole is 6 μm to 12 μm, and the radius of the second through hole is 2 μm to 8 μm.

[0012] In a further implementation form of the disclosure, the maximum withstand voltage of the light emitting diode is greater than 85 V.

[0013] In a further implementation form of the disclosure, the light emitting diode further comprises a transparent conductive layer on the surface of the second semiconductor layer, the insulating layer covers the transparent conductive layer, the first through hole and the second through hole both expose the transparent conductive layer, and the metal reflective layer is electrically connected with the transparent conductive layer through the first through hole and the second through hole.

[0014] The disclosure provides a preparation method of a light emitting diode, which comprises: preparing an epitaxial layer, the epitaxial layer comprising a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer stacked in sequence, the surface of the second semiconductor layer having a recess exposing the first semiconductor layer; preparing an insulating layer on the surface of the second semiconductor layer and in the recess, the surface of the insulating layer having a first through hole and a second through hole penetrating the insulating layer, the aperture of the first through hole being greater than the aperture of the second through hole, and the distance from the first through hole to the recess being less than the distance from the second through hole to the recess.

[0015] In a further implementation form of the disclosure, the preparation of the insulating layer on the surface of the second semiconductor layer and in the recess comprises: depositing an insulating layer on the surface of the second semiconductor layer and in the recess; etching the surface of the insulating layer to form the first through hole and the second through hole, a plurality of the first through holes being circumferentially distributed in a circular region with the central axis of the recess as the center, the radius of the circular region being greater than or equal to three times the radius of the recess, and the radius of the circular region being less than or equal to five times the radius of the recess.

[0016] The technical scheme provided by the embodiments of the disclosure has at least the following beneficial effects:

[0017] The light emitting diode provided by the embodiments of the disclosure forms an insulating layer on the surface of the epitaxial layer, and the surface of the insulating layer has a first through hole and a second through hole. A metal emitting layer is further arranged on the surface of the insulating layer, and the metal reflective layer can be electrically connected with the epitaxial layer below through the first through hole and the second through hole, so as to facilitate the power supply to the epitaxial layer.

[0018] wherein, on the surface of the second semiconductor layer of the epitaxial layer, a recess hole is further provided to expose the first semiconductor layer. The recess hole is usually used to set an electrode, so that the current can be transmitted to different semiconductor layers of the epitaxial layer through the electrode. Therefore, the current density near the recess hole where the electrode is set is usually large, and the insulating layer mainly plays a reflecting role, so the size of the through hole on the insulating layer is usually small, which also increases the current density of the insulating layer at the through hole position. The first through hole near the recess hole (i.e. near the electrode) has a larger aperture in the embodiment of the present disclosure, which is beneficial to increase the diffusion capacity of the current in the area near the recess hole, so that the area near the recess hole can carry larger current injection, prevent the local current in the area near the recess hole from being too large to generate a large amount of heat and cause damage, and improve the overload electrical stress of the light emitting diode.

[0019] At the same time, the aperture of the second through hole far away from the recess hole is smaller than that of the first through hole, so as to prevent all the through holes on the insulating layer from being provided with a larger aperture, thereby ensuring that the total area of the insulating layer remains unchanged or increases, so as to improve the reflection effect and improve the brightness of the light emitting diode. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0021] Figure 1 is a top view of a light emitting diode provided by the related art;

[0022] Figure 2 is a top view of a light emitting diode provided by the embodiment of the present disclosure;

[0023] Figure 3 is a level diagram of a light emitting diode provided by the embodiment of the present disclosure;

[0024] Figure 4 is Figure 2 is a local enlarged schematic view of N in the related art;

[0025] Figure 5 is a brightness performance experimental data diagram of a light emitting diode provided by the embodiment of the present disclosure;

[0026] Figure 6 is a flowchart of a preparation method of a light emitting diode provided by the embodiment of the present disclosure.

[0027] The various marks in the drawings represent the following:

[0028] 10, substrate;

[0029] 20, epitaxial layer; 21, first semiconductor layer; 22, multi-quantum well layer; 23, second semiconductor layer; 24, recess;

[0030] 30, insulating layer; 31, first via; 32, second via;

[0031] 41, first insulating layer; 42, second insulating layer;

[0032] 50, metal reflective layer;

[0033] 61, first electrode; 62, second electrode;

[0034] 71, first pad; 72, second pad;

[0035] 80, transparent conductive layer. DETAILED DESCRIPTION

[0036] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will further describe the embodiments of the present disclosure in conjunction with the accompanying drawings.

[0037] Unless otherwise defined, technical terms or scientific terms used herein should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", "third" and similar terms used in the specification and claims of the present patent application do not denote any order, quantity or importance, but are used to distinguish different components. Similarly, the terms "one" or "a" or similar terms do not denote a quantity limitation, but mean that at least one exists. The terms "include" or "contain" or similar terms mean that the elements or objects appearing before the terms "include" or "contain" cover the elements or objects listed after the terms "include" or "contain" and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "up", "down", "left", "right", "top", "bottom", etc. are only used to indicate relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships may also change accordingly.

[0038] Figure 1 is a top view of a light emitting diode provided by the related art. As shown in FIG. 1, the light emitting diode includes a substrate 10, a first semiconductor layer 21, a multi-quantum well layer 22, a second semiconductor layer 23, and a metal reflective layer 50. Figure 1As shown, in the related art, the through holes X on the insulating layer are dispersedly arranged around the recess hole 24 of the epitaxial layer 20. Since the aperture of the through hole X on the insulating layer is usually about 8 μm, that is, the aperture of the through hole X on the insulating layer is small, the current near the through hole X of the insulating layer is large, and the recess hole 24 is a region for depositing an electrode, which makes the current density of the region near the recess hole 24 very large. Under the impact of a large current, the region where the through hole X of the insulating layer near the recess hole 24 is easily damaged due to too large current injection.

[0039] To this end, the embodiment of the present disclosure provides a light emitting diode. Figure 2 is a top view of a light emitting diode provided by the embodiment of the present disclosure. Figure 3 is a hierarchical diagram of a light emitting diode provided by the embodiment of the present disclosure. Figure 3 is a cross-sectional view taken along the MM section line in Figure 2 Figure 4 is a cross-sectional view taken along the MM section line in Figure 2 is a local enlarged view of N provided in the embodiment of the present disclosure.

[0040] As shown in the embodiment of the present disclosure, the light emitting diode comprises an epitaxial layer 20, an insulating layer 30 and a metal reflection layer 50. Figure 3 As shown in the embodiment of the present disclosure, the light emitting diode comprises an epitaxial layer 20, an insulating layer 30 and a metal reflection layer 50.

[0041] As shown in the embodiment of the present disclosure, the light emitting diode comprises an epitaxial layer 20, an insulating layer 30 and a metal reflection layer 50. Figure 2 3 As shown in the embodiment of the present disclosure, the epitaxial layer 20 comprises a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 which are sequentially stacked, and the surface of the second semiconductor layer 23 has a recess hole 24 exposing the first semiconductor layer 21.

[0042] As shown in the embodiment of the present disclosure, the epitaxial layer 20 comprises a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 which are sequentially stacked, and the surface of the second semiconductor layer 23 has a recess hole 24 exposing the first semiconductor layer 21. Figures 2 to 4 As shown in the embodiment of the present disclosure, the insulating layer 30 is located on the surface of the second semiconductor layer 23 and in the recess hole 24, and the surface of the insulating layer 30 has a first through hole 31 and a second through hole 32 penetrating the insulating layer 30.

[0043] Figure 4 As shown in the embodiment of the present disclosure, the aperture of the first through hole 31 is larger than the aperture of the second through hole 32, and the distance L1 from the first through hole 31 to the recess hole 24 is smaller than the distance L2 from the second through hole 32 to the recess hole 24.

[0044] Exemplarily, the distance from the first through hole 31 to the recess hole 24 can be the distance between the center of the first through hole 31 and the center of the recess hole 24.

[0045] Exemplarily, the distance from the second through hole 32 to the recess hole 24 can be the distance between the center of the second through hole 32 and the center of the recess hole 24.

[0046] ​​​The light-emitting diode provided in the embodiment of the present disclosure has a rear insulating layer 30 formed on the surface of the epitaxial layer 20. The surface of the insulating layer 30 has a first through-hole 31 and a second through-hole 32. A metal emission layer is also provided on the surface of the insulating layer 30. The metal reflective layer 50 can be electrically connected to the underlying epitaxial layer 20 through the first through-hole 31 and the second through-hole 32 to facilitate power supply to the epitaxial layer 20.

[0047] Among them, a concave hole 24 exposing the first semiconductor layer 21 is also provided on the surface of the second semiconductor layer 23 of the epitaxial layer 20. The concave hole 24 is usually used to set an electrode so that the current can be transmitted to the different semiconductor layers of the epitaxial layer 20 through the electrode. Therefore, the current density near the concave hole 24 where the electrode is set is usually very large. At the same time, the insulating layer 30 mainly plays a reflective role, so the size of the through hole on the insulating layer 30 is usually small, which also increases the current density of the insulating layer 30 at the through hole position. The embodiment of the present disclosure makes the aperture of the first through hole 31 close to the concave hole 24 (that is, close to the electrode) larger, which is conducive to increasing the diffusion capacity of the current in the area near the concave hole 24, allowing the area near the concave hole 24 to carry a larger current injection, preventing the local current in the area near the concave hole 24 from being too large and generating a large amount of heat and causing damage, thereby improving the overload electrical stress of the light-emitting diode.

[0048] At the same time, the aperture of the second through hole 32 farther from the recessed hole 24 is made smaller than that of the first through hole 31 to prevent all through holes on the insulating layer 30 from having larger apertures, thereby ensuring that the total area of ​​the insulating layer 30 remains unchanged or increases, thereby enhancing the reflective effect and increasing the brightness of the light-emitting diode.

[0049] Alternatively, as Figure 4 As shown, the plurality of first through holes 31 are uniformly distributed circumferentially within a circular area Q with the central axis of the recessed hole 24 as the center.

[0050] By arranging the first through holes 31 in a circular area around the recessed hole 24 with the central axis of the recessed hole 24 as the center, the through holes around the recessed hole 24 are all through holes with larger apertures, which is beneficial to increasing the diffusion capacity of the current in the area near the recessed hole 24 and preventing the local current in the area near the recessed hole 24 from being too large to generate a large amount of heat and cause damage.

[0051] At the same time, the multiple first through holes 31 in the circular area are evenly distributed circumferentially. The first through holes 31 are arranged in such a uniform manner so that current can be injected evenly and the current injection density can be evenly dispersed to avoid excessive local current, thereby enhancing the anti-EOS capability of the light-emitting diode.

[0052] Optionally, the radius L of the circular area is greater than or equal to three times the radius R of the concave hole 24 , and the radius L of the circular area is less than or equal to five times the radius R of the concave hole 24 .

[0053] By setting the radius of the circular region within the above range, the radius of the circular region can be prevented from being too small, so that the number of the first through holes 31 is small, and the effect of dispersing the current is poor. Also, the radius of the circular region can be prevented from being too large, so that a large number of first through holes 31 with large apertures are formed on the insulating layer 30, the total area of the insulating layer 30 is reduced, and the light reflection effect of the light-emitting diode is affected.

[0054] Optionally, the radius of the concave hole 24 is 12 μm to 30 μm.

[0055] In the embodiments of the present disclosure, by setting the radius of the concave hole 24 within the above range, the concave hole 24 has a large aperture, which is more conducive to uniformly distributing the current and reducing heat accumulation caused by excessively high local current density.

[0056] For example, the radius of the concave hole 24 can be 20 μm.

[0057] For example, the radius of the circular region can be three times the radius of the concave hole 24. When the radius of the concave hole 24 is 20 μm, the radius of the circular region can be 60 μm.

[0058] Optionally, the radius of the first through hole 31 is greater than or equal to twice the radius of the second through hole 32.

[0059] By making the radius of the first through hole 31 more than twice the radius of the second through hole 32, the size of the first through hole 31 is large enough to expand the cross-sectional area of the current path, reduce the local current density, and avoid heat generation and efficiency decay caused by current accumulation.

[0060] The first through hole 31 with a large aperture and the metal reflective layer 50 with high conductivity can reduce resistance heating. Meanwhile, the second through hole 32 with a small aperture exists in the insulating layer 30. By reasonably setting the ratio of the first through hole 31 to the second through hole 32, most of the light can be effectively reflected, and the local current density can be reduced to achieve a balance between heat dissipation and light extraction.

[0061] Optionally, the radius of the first through hole 31 is 6 μm to 12 μm, and the radius of the second through hole 32 is 2 μm to 8 μm.

[0062] For example, the radius of the first through hole 31 can be 10 μm, and the radius of the second through hole 32 can be 4 μm.

[0063] In the related art, the apertures of the through holes on the insulating layer 30 are about 8 μm. In this way, the radius of the first through hole 31 exceeds the apertures of the through holes on the insulating layer 30 in the related art, which can increase the diffusion capacity of the current in the area around the concave hole 24, enable the area around the concave hole 24 to carry a larger current injection, and improve the overload electrical stress of the light-emitting diode.

[0064] Meanwhile, the radius of the second via hole 32 is smaller than the hole diameter of the via hole on the insulating layer 30 in the related art, and the area loss of the insulating layer 30 caused by the increase of the first via hole 31 is compensated by reducing the second via hole 32, so that the total area of the insulating layer 30 is kept unchanged or increased, thereby improving the reflection effect and increasing the brightness of the light-emitting diode.

[0065] Optionally, as shown in Figure 3 The light-emitting diode further includes a transparent conductive layer 80 located on the surface of the second semiconductor layer 23, the insulating layer 30 covers the transparent conductive layer 80, and the first via hole 31 and the second via hole 32 both expose the transparent conductive layer 80, and the metal reflective layer 50 is electrically connected to the transparent conductive layer 80 through the first via hole 31 and the second via hole 32.

[0066] Illustratively, the transparent conductive layer 80 can be an Indium Tin Oxide (ITO) layer or an Indium Zinc Oxide (IZO) layer.

[0067] Illustratively, the transparent conductive layer 80 is an Indium Tin Oxide layer. The Indium Tin Oxide layer has good transmittance and low resistivity, and the use of the Indium Tin Oxide layer with low resistivity facilitates the conduction of carriers and improves the injection efficiency.

[0068] Illustratively, the transparent conductive layer 80 is an Indium Zinc Oxide layer. The Indium Zinc Oxide layer has good transmittance and low resistivity, and the use of the Indium Zinc Oxide layer with low resistivity facilitates the conduction of carriers and improves the injection efficiency.

[0069] Illustratively, the thickness of the transparent conductive layer 80 is 100 angstroms to 300 angstroms. For example, the thickness of the transparent conductive layer 80 is 200 angstroms.

[0070] In the above implementation, by arranging the transparent conductive layer 80 between the metal reflective layer 50 and the epitaxial layer 20, the current conduction efficiency between the metal reflective layer 50 and the epitaxial layer 20 can be improved.

[0071] By arranging the metal reflective layer 50, the light emitted from the epitaxial layer 20 can be reflected, so that more light is emitted from the light-emitting surface of the epitaxial layer 20, thereby improving the luminous intensity of the light-emitting diode.

[0072] Optionally, the metal reflective layer 50 can include at least one of Ag, Ni, Ti, TiW, Al, AlCu, Pt, and Au.

[0073] As an example, the metal reflective layer 50 includes an Ag layer, a Ni layer, and a TiW layer stacked in sequence.

[0074] Since Ag has good reflection effect, the Ag layer arranged in the reflection layer can enhance the reflection of the reflection layer to light, and improve the light brightness of the light emitting surface of the light emitting diode.

[0075] The Ni layer has good corrosion resistance and wear resistance, the TiW layer can be successfully deposited on other thin films as an adhesion layer without peeling or cracking. The alternately stacked Ni layer and TiW layer can protect the silver mirror as a barrier layer.

[0076] For example, the thickness of the Ag layer is 1500 angstroms.

[0077] For example, the thickness of the Ni layer is 200 angstroms.

[0078] For example, the thickness of the TiW layer is 800 angstroms.

[0079] In other implementations, the metal reflection layer 50 can further include an Ag layer, a Ni layer, a TiW layer, a Cr layer, an Al layer, a Ti layer, an Al layer, a Ti layer, an Al layer, a Cr layer, a Pt layer and a Ti layer which are sequentially stacked.

[0080] The Cr layer, the Al layer, the Ti layer, the Al layer, the Ti layer, the Al layer, the Cr layer, the Pt layer and the Ti layer can act as a protective layer to prevent Ag migration in the metal reflection layer 50.

[0081] For example, the thicknesses of the Cr layer, the Al layer, the Ti layer, the Al layer, the Ti layer, the Al layer, the Cr layer, the Pt layer and the Ti layer are 30 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 500 angstroms, 2000 angstroms and 500 angstroms, respectively.

[0082] Optionally, as shown in FIG. 1, the light emitting diode further includes a substrate 10, and the epitaxial layer 20 is located on the surface of the substrate 10. Figure 3

[0083] For example, the substrate is a sapphire substrate. The sapphire substrate has relatively high light transmittance, i.e., the substrate is a transparent substrate. In addition, the sapphire material is relatively hard and has stable chemical properties, so that the light emitting diode has good light emitting effect and stability.

[0084] In the embodiment of the present disclosure, the substrate has a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 which are sequentially stacked thereon, and the surface of the second semiconductor layer 23 has a recess hole 24 exposing the first semiconductor layer 21.

[0085] ​In the embodiments of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0086] For example, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0087] Optionally, the first semiconductor layer 21 is an n-type silicon-doped GaN layer. The thickness of the n-type GaN layer can be 0.5 μm to 3 μm.

[0088] Optionally, the multi-quantum well layer 22 includes InGaN quantum well layers and GaN quantum barrier layers alternately grown. The multi-quantum well layer 22 can include 3 to 8 periods of InGaN quantum well layers and GaN quantum barrier layers alternately stacked.

[0089] For example, in the embodiments of the present disclosure, the multi-quantum well layer 22 includes 5 periods of InGaN quantum well layers and GaN quantum barrier layers alternately stacked.

[0090] Optionally, the thickness of the multi-quantum well layer 22 can be 150 nm to 200 nm.

[0091] Optionally, the second semiconductor layer 23 is a p-type magnesium-doped GaN layer. The thickness of the p-type GaN layer can be 0.5 μm to 3 μm.

[0092] In an implementation, the insulating layer 30 includes a silicon oxide layer, and the thickness of the silicon oxide layer is 3000 angstroms to 12000 angstroms.

[0093] The silicon oxide material has good barrier effect on metal Ag, which can avoid the Ag particles generated to damage the silicon oxide layer and form cracks on the silicon oxide layer, thereby preventing the problem of light-emitting diode failure due to leakage.

[0094] In another implementation, the insulating layer 30 includes a plurality of silicon oxide layers and a plurality of titanium oxide layers alternately stacked.

[0095] The plurality of periodically and alternately stacked SiO2 layers and TiO2 layers can form a distributed Bragg reflection (DBR) layer.

[0096] For example, the number of periods of the DBR layer can be 20 to 50. For example, the number of periods of the DBR layer is 32.

[0097] The thickness of the SiO2 layer in the DBR layer can be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer can be 500 angstroms to 900 angstroms.

[0098] The DBR layer has a passivation effect and reflects light emitted from the multi-quantum well layer 22 to the substrate, thereby improving light emission.

[0099] Optionally, as shown in Figure 3 The light emitting diode further comprises a first insulating layer 41, a first electrode 61 and a second electrode 62.

[0100] As shown in Figure 3 The first insulating layer 41 is located on a surface of the insulating layer 30 away from the epitaxial layer 20, and the first insulating layer 41 covers the metal reflective layer 50. The first insulating layer 41 has a through hole exposing the metal reflective layer 50, and the first insulating layer 41 has a through hole exposing the recess hole 24.

[0101] As shown in Figure 3 The first electrode 61 and the second electrode 62 are arranged on the surface of the first insulating layer 41 away from the epitaxial layer 20, at least part of the first electrode 61 is located in the recess hole 24 and electrically connected with the epitaxial layer 20, and the second electrode 62 is electrically connected with the metal reflective layer 50 through the through hole.

[0102] In the embodiment of the present disclosure, the epitaxial layer 20 comprises a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 stacked. The first insulating layer 41 has a recess hole 24 exposing the epitaxial layer 20, which can be a recess hole 24 exposing the first semiconductor layer 21. In this way, the first electrode 61 can be electrically connected with the first semiconductor layer 21 through the recess hole 24. The second electrode 62 is located on the metal reflective layer 50 above the second semiconductor layer 23 and is electrically connected with the metal reflective layer 50 through the through hole, thereby achieving the purpose of electrically connecting the second electrode 62 with the second semiconductor layer 23.

[0103] Exemplarily, the first electrode 61 and the second electrode 62 can each comprise Cr layer, Al layer, Ti layer, Al layer, Ti layer, Al layer, Cr layer, Pt layer and Ti layer stacked in sequence. The thickness of each metal layer is 30 angstrom, 2000 angstrom, 1000 angstrom, 2000 angstrom, 1000 angstrom, 2000 angstrom, 500 angstrom, 2000 angstrom and 500 angstrom, respectively.

[0104] Optionally, as shown in Figure 3 The light emitting diode further comprises a second insulating layer 42, a first pad 71 and a second pad 72. The second insulating layer 42 is located on a surface of the first insulating layer 41 away from the epitaxial layer 20, and the second insulating layer 42 covers the first electrode 61 and the second electrode 62. The second insulating layer 42 has through holes respectively exposing the first electrode 61 and the second electrode 62.

[0105] The first pad 71 is electrically connected with the first electrode 61 through the through hole, and the second pad 72 is electrically connected with the second electrode 62 through the through hole.

[0106] Optionally, the first pad 71 and the second pad 72 each include at least one of a Ti layer, an Al layer, a Pt layer, a Ni layer, and an Au layer.

[0107] The metal material described above has good heat dissipation performance, and thus the pad prepared by using the metal material also has good heat dissipation performance, which can improve the heat dissipation effect of the light emitting diode.

[0108] Optionally, the first pad 71 and the second pad 72 each include a first Ti layer, an Al layer, a second Ti layer, a Pt layer, a Ni layer, and an Au layer which are sequentially stacked.

[0109] Illustratively, the thickness of the first Ti layer is 20 angstroms to 100 angstroms. For example, the thickness of the first Ti layer is 50 angstroms.

[0110] Illustratively, the thickness of the Al layer is 10,000 angstroms to 20,000 angstroms. For example, the thickness of the Al layer is 15,000 angstroms.

[0111] Illustratively, the thickness of the second Ti layer is 500 angstroms to 1,500 angstroms. For example, the thickness of the second Ti layer is 1,000 angstroms.

[0112] Illustratively, the thickness of the Pt layer is 500 angstroms to 1,500 angstroms. For example, the thickness of the Pt layer is 1,000 angstroms.

[0113] Illustratively, the thickness of the Ni layer is 60,000 angstroms to 80,000 angstroms. For example, the thickness of the Ni layer is 70,000 angstroms.

[0114] Illustratively, the thickness of the Au layer is 1,500 angstroms to 2,500 angstroms. For example, the thickness of the Au layer is 2,000 angstroms.

[0115] As an example, in the embodiments of the present disclosure, the first insulating layer 41 and the second insulating layer 42 each include a plurality of silicon oxide layers and a plurality of titanium oxide layers which are alternately stacked.

[0116] The plurality of periodically and alternately stacked SiO2 layers and TiO2 layers can form a distributed Bragg reflector layer.

[0117] Illustratively, the number of periods of the DBR layer can be between 20 and 50. For example, the number of periods of the DBR layer is 32.

[0118] The thickness of the SiO2 layer in the DBR layer can be 800 angstroms to 1,200 angstroms, and the thickness of the TiO2 layer can be 500 angstroms to 900 angstroms.

[0119] In addition to the passivation effect, the DBR layer is also used to reflect light emitted from the multi-quantum well layer 22 to the substrate, thereby improving the light emission effect.

[0120] Optionally, the thickness of the first insulating layer 41 and the second insulating layer 42 is 3-5 μm. For example, in the embodiment of the present disclosure, the thickness of the first insulating layer 41 is 3 μm, and the thickness of the second insulating layer 42 is 6 μm.

[0121] The EOS performance experimental data of the light-emitting diode provided by the embodiment of the present disclosure is shown in Table 1 below.

[0122] Table 1

[0123]

[0124]

[0125] According to the test results in Table 1, using the lightning surge generator for EOS impact, the chip test voltage of the light-emitting diode provided by the embodiment of the present disclosure is 0 after the instantaneous voltage reaches 85 V, that is, the light-emitting diode is damaged after the instantaneous voltage reaches 85 V. It can be seen that the highest withstand voltage of the light-emitting diode provided by the embodiment of the present disclosure is greater than 85 V.

[0126] In the related art, the chip test voltage of the light-emitting diode is 0 after the instantaneous voltage reaches 65 V, that is, the light-emitting diode is damaged after the instantaneous voltage reaches 65 V. Compared with the related technical solution, the EOS of the embodiment of the present disclosure is improved by 20 V.

[0127] The luminance performance experimental data of the light-emitting diode provided by the embodiment of the present disclosure is shown in Table 1. Figure 5 Using the same Run wafer source for verification, the light-emitting diode provided by the embodiment of the present disclosure has a yield comparable to the conventional technical solution, and the luminance is increased by 1.46%.

[0128] Figure 6 is a flowchart of a preparation method of a light-emitting diode provided by the embodiment of the present disclosure. As shown in Figure 6 , the preparation method comprises the following steps.

[0129] Step S11: preparing an epitaxial layer.

[0130] The epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are stacked in sequence, and the surface of the second semiconductor layer has a recess hole exposing the first semiconductor layer.

[0131] Step S12: preparing an insulating layer on the surface of the second semiconductor layer and in the recess hole.

[0132] The surface of the insulating layer has a first through hole and a second through hole penetrating the insulating layer, the aperture of the first through hole is larger than the aperture of the second through hole, and the distance from the first through hole to the recess hole is smaller than the distance from the second through hole to the recess hole.

[0133] The light emitting diode provided by the embodiment of the present disclosure forms an insulating layer on the surface of the epitaxial layer, and the surface of the insulating layer has a first through hole and a second through hole. A metal emitting layer is further arranged on the surface of the insulating layer, and the metal reflecting layer can be electrically connected to the epitaxial layer below through the first through hole and the second through hole, so as to facilitate the power supply to the epitaxial layer.

[0134] In the embodiment of the present disclosure, a recess hole exposing the first semiconductor layer is further arranged on the surface of the second semiconductor layer of the epitaxial layer. The recess hole is usually used for arranging an electrode, so that the current can be transmitted to different semiconductor layers of the epitaxial layer through the electrode. Therefore, the current density near the recess hole where the electrode is arranged is usually large, and the insulating layer mainly plays a reflecting role, so the size of the through hole on the insulating layer is usually small, which also increases the current density of the insulating layer at the position of the through hole. The first through hole near the recess hole (i.e., near the electrode) has a larger aperture in the embodiment of the present disclosure, which is beneficial to increase the diffusion capacity of the current in the area near the recess hole, so that the area near the recess hole can bear a larger current injection, prevent the local current near the recess hole from being too large to generate a large amount of heat and cause damage, and improve the overload electrical stress of the light emitting diode.

[0135] At the same time, the aperture of the second through hole far from the recess hole is smaller than that of the first through hole, so as to prevent all the through holes on the insulating layer from being arranged with a larger aperture, thereby ensuring that the total area of the insulating layer remains unchanged or increases, improving the reflection effect, and improving the brightness of the light emitting diode.

[0136] The step S11 can include the following steps:

[0137] Firstly, an epitaxial layer is grown on a substrate.

[0138] The substrate can be a sapphire substrate, a silicon substrate or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0139] For example, in the embodiment of the present disclosure, the substrate is a sapphire substrate. The sapphire substrate is a commonly used substrate, which is mature in technology and low in cost. Specifically, the sapphire substrate can be a patterned sapphire substrate or a sapphire flat substrate.

[0140] For example, in the embodiment of the present disclosure, the sapphire substrate is subjected to baking treatment for 15 minutes in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber.

[0141] Specifically, the baking temperature can be 1000-1200°C, and the pressure in the MOCVD reaction chamber during baking can be 100-200 mbar.

[0142] Growth of the epitaxial layer on the substrate can include sequentially forming a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer on a sapphire substrate by MOCVD technology.

[0143] The first semiconductor layer is an n-type layer, and the second semiconductor layer is a p-type layer.

[0144] Optionally, the first semiconductor layer is an n-type silicon-doped GaN layer. The thickness of the n-type GaN layer can be 0.5 μm to 3 μm.

[0145] The growth temperature of the n-type GaN layer can be 1000°C to 1100°C, and the growth pressure of the n-type GaN layer can be 100 torr to 300 torr.

[0146] Optionally, the multi-quantum well layer includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer can include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0147] When growing the multi-quantum well layer, the MOCVD reaction chamber pressure is controlled at 200 torr. When growing the InGaN quantum well layer, the reaction chamber temperature is 760°C to 780°C. When growing the GaN quantum barrier layer, the reaction chamber temperature is 860°C to 890°C.

[0148] As an example, in the embodiments of the present disclosure, the multi-quantum well layer includes 5 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0149] Optionally, the thickness of the multi-quantum well layer can be 150 nm to 200 nm.

[0150] Optionally, the second semiconductor layer is a p-type magnesium-doped GaN layer. The thickness of the p-type GaN layer can be 0.5 μm to 3 μm.

[0151] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer can be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer can be 800°C to 1000°C.

[0152] After forming the epitaxial layer, the preparation method further includes etching the second semiconductor layer to form a recess exposing the first semiconductor layer.

[0153] In the second step, a transparent conductive layer is formed on the surface of the epitaxial layer.

[0154] Specifically, the transparent conductive layer can be sputtered on the epitaxial layer.

[0155] Exemplarily, the transparent conductive layer is an indium tin oxide layer or an indium zinc oxide layer.

[0156] Exemplarily, the thickness of the transparent conductive layer is 100 angstroms to 300 angstroms. For example, the thickness of the transparent conductive layer is 250 angstroms.

[0157] Step S12 can include:

[0158] First, depositing an insulating layer on the surface of the second semiconductor layer and in the recess.

[0159] The depositing the insulating layer can include: depositing a silicon oxide layer on the surface of the epitaxial layer.

[0160] Exemplarily, the thickness of the silicon oxide layer is 3000 angstroms to 12000 angstroms.

[0161] Then, etching the surface of the insulating layer to form the first through hole and the second through hole.

[0162] The plurality of first through holes are circumferentially distributed in a circular region with the central axis of the recess as the center, the radius of the circular region is greater than or equal to three times the radius of the recess, and the radius of the circular region is less than or equal to five times the radius of the recess.

[0163] Specifically, it can include: etching the silicon oxide layer away from the surface of the epitaxial layer to form the first through hole and the second through hole.

[0164] After step S12, it can further include: forming a metal reflective layer on the surface of the insulating layer away from the surface of the epitaxial layer.

[0165] The metal reflective layer is electrically connected to the transparent conductive layer through the first through hole. The metal reflective layer includes Ag layer, Ni layer, TiW layer, Cr layer, Al layer, Ti layer, Al layer, Ti layer, Al layer, Cr layer, Pt layer and Ti layer which are stacked in sequence.

[0166] Exemplarily, the thickness of the Ag layer is 1400 angstroms to 1700 angstroms. For example, the thickness of the Ag layer is 1500 angstroms.

[0167] Exemplarily, the thickness of the Ni layer is 100 angstroms to 300 angstroms. For example, the thickness of the Ni layer is 200 angstroms.

[0168] Exemplarily, the thickness of the TiW layer is 700 angstroms to 1000 angstroms. For example, the thickness of the TiW layer is 800 angstroms.

[0169] After step S12, it can further include the following steps:

[0170] First, forming a first insulating layer on the surface of the insulating layer away from the surface of the epitaxial layer.

[0171] The first insulating layer is a DBR layer, and the DBR layer includes a plurality of silicon oxide layers and a plurality of titanium oxide layers. The thickness of the DBR layer is 3 μm to 4 μm.

[0172] In the second step, the first electrode and the second electrode are formed by evaporation on the surface of the first insulating layer.

[0173] For example, the first electrode and the second electrode each include a Cr layer, an Al layer, a Ti layer, an Al layer, a Ti layer, an Al layer, a Cr layer, a Pt layer and a Ti layer which are stacked in sequence. The thickness of each metal layer is 30 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 500 angstroms, 2000 angstroms and 500 angstroms, respectively.

[0174] The first electrode and the second electrode are arranged on the surface of the first insulating layer away from the epitaxial layer, at least part of the first electrode is located in the recess hole and electrically connected to the epitaxial layer, and the second electrode is electrically connected to the metal reflection layer through the through hole.

[0175] In the third step, the second insulating layer is formed on the surface of the first insulating layer, in the recess hole and on the surface of the electrode, and the through hole exposing the electrode is formed on the second insulating layer by photolithography.

[0176] For example, the second insulating layer is a DBR layer, and the DBR layer includes a plurality of silicon oxide layers and a plurality of titanium oxide layers. The thickness of the DBR layer is 3 μm to 4 μm.

[0177] In the fourth step, the first pad and the second pad are formed by evaporation on the surface of the second insulating layer.

[0178] The first pad is electrically connected to the first electrode through the through hole, and the second pad is electrically connected to the second electrode through the through hole.

[0179] Optionally, the first pad and the second pad each include a first Ti layer, an Al layer, a second Ti layer, a Pt layer, a Ni layer and an Au layer which are stacked in sequence.

[0180] For example, the thickness of the first Ti layer is 20 angstroms to 100 angstroms. For example, the thickness of the first Ti layer is 50 angstroms.

[0181] For example, the thickness of the Al layer is 10000 angstroms to 20000 angstroms. For example, the thickness of the Al layer is 15000 angstroms.

[0182] For example, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms. For example, the thickness of the second Ti layer is 1000 angstroms.

[0183] For example, the thickness of the Pt layer is 500 angstroms to 1500 angstroms. For example, the thickness of the Pt layer is 1000 angstroms.

[0184] For example, the thickness of the Ni layer is 60000 angstroms to 80000 angstroms. For example, the thickness of the Ni layer is 70000 angstroms.

[0185] Exemplarily, the thickness of the Au layer is 1500 angstroms to 2500 angstroms. For example, the thickness of the Au layer is 2000 angstroms.

[0186] The above merely provides the optional embodiments of the present disclosure, but does not intend to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized by, The light emitting diode comprises an epitaxial layer (20), an insulating layer (30) and a metal reflective layer (50); The epitaxial layer (20) comprises a first semiconductor layer (21), a multi-quantum well layer (22) and a second semiconductor layer (23) which are sequentially stacked, and the surface of the second semiconductor layer (23) has a recess hole (24) exposing the first semiconductor layer (21); The insulating layer (30) is located on the surface of the second semiconductor layer (23) and in the recess hole (24), and the surface of the insulating layer (30) has a first through hole (31) and a second through hole (32) penetrating through the insulating layer (30), the aperture of the first through hole (31) is larger than that of the second through hole (32), and the distance from the first through hole (31) to the recess hole (24) is smaller than that from the second through hole (32) to the recess hole (24).

2. The light emitting diode of claim 1, wherein, A plurality of the first through holes (31) are circumferentially distributed in a circular region with the center at the central axis of the recess hole (24).

3. The light emitting diode of claim 2, wherein, The radius of the circular region is greater than or equal to three times the radius of the recess hole (24), and the radius of the circular region is less than or equal to five times the radius of the recess hole (24).

4. The light emitting diode of claim 3, wherein, The radius of the recess hole (24) is 12 μm to 30 μm.

5. The light emitting diode of claim 1, wherein, The radius of the first through hole (31) is greater than or equal to twice the radius of the second through hole (32).

6. The light emitting diode of claim 5, wherein, The radius of the first through hole (31) is 6 μm to 12 μm, and the radius of the second through hole (32) is 2 μm to 8 μm.

7. The light emitting diode according to any one of claims 1 to 6, wherein The highest withstand voltage of the light emitting diode is greater than 85 V.

8. The light emitting diode according to any one of claims 1 to 6, wherein The light emitting diode further comprises a transparent conductive layer (80) located on the surface of the second semiconductor layer (23), the insulating layer (30) covers the transparent conductive layer (80), the first through hole (31) and the second through hole (32) both expose the transparent conductive layer (80), and the metal reflective layer (50) is electrically connected with the transparent conductive layer (80) through the first through hole (31) and the second through hole (32).

9. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: Preparation of an epitaxial layer comprising a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are sequentially stacked, and the surface of the second semiconductor layer has a recess hole exposing the first semiconductor layer; Preparation of an insulating layer on the surface of the second semiconductor layer and in the recess hole, and the surface of the insulating layer has a first through hole and a second through hole penetrating through the insulating layer, the aperture of the first through hole is larger than that of the second through hole, and the distance from the first through hole to the recess hole is smaller than that from the second through hole to the recess hole.

10. The method of claim 9, wherein, Preparation of an insulating layer on the surface of the second semiconductor layer and in the recess hole comprises: Deposition of an insulating layer on the surface of the second semiconductor layer and in the recess hole; Etching the surface of the insulating layer to form a first via hole and the second via hole, a plurality of the first via holes are uniformly distributed in a circular region with the central axis of the recess hole as the center, the radius of the circular region is greater than or equal to three times the radius of the recess hole, and the radius of the circular region is less than or equal to five times the radius of the recess hole.

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