Display panel

Abstract

There is provided a display panel including: a substrate including a display area, an open area within the display area, and an intermediate area between the open area and the display area; a light emitting diode in the display area and including a sub-pixel electrode, a counter electrode over the sub-pixel electrode, and an intermediate layer between the sub-pixel electrode and the counter electrode; an organic pattern layer over the substrate in the intermediate region and defining a first groove and a second groove; a conductive pattern layer in the second groove and including a tip having an end protruding toward a center of the first groove in a plan view; and a line electrically connected to the conductive pattern layer and passing through the display area.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0054278, filed on April 23, 2024, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0002] One or more embodiments relate to a display panel including a light emitting diode. BACKGROUND

[0003] In recent years, as the use of display panels has diversified and the display panels have become thinner and lighter, their range of use has expanded. As the area occupied by a display area within the display panel has increased, various functions have been added in combination with or linked to the display panel. To further increase the area and add more functions, research has been conducted to use a portion of the display area for functions other than the function of representing an image. SUMMARY

[0004] One or more embodiments include a display panel including an opening area and an electronic device including the display panel.

[0005] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description and drawings or can be learned by practice of the presented embodiments.

[0006] According to one or more embodiments, a display panel includes a substrate including a display area, an opening area within the display area, and an intermediate area between the opening area and the display area; a light emitting diode in the display area and including a sub-pixel electrode, a counter electrode over the sub-pixel electrode, and an intermediate layer between the sub-pixel electrode and the counter electrode; an organic pattern layer over the substrate in the intermediate area and defining a first recess and a second recess; a conductive pattern layer in the second recess and including a tip having an end projecting toward a center of the first recess in a plan view; and a wire electrically connected to the conductive pattern layer and passing through the display area.

[0007] The display panel can further include a cover layer over the conductive pattern layer and including a conductive material.

[0008] The cover layer can include a first portion over an upper surface of the conductive pattern layer and a second portion in the first recess and separated from the first portion.

[0009] The first portion can at least partially cover the tip of the conductive pattern layer.

[0010] The cover layer can continuously extend along the upper surface of the conductive pattern layer, the side surface and the lower surface of the tip, and the side surface and the upper surface of the portion of the organic pattern layer in which the first groove is formed.

[0011] The cover layer and the sub-pixel electrode can include the same material.

[0012] The line can be integral with the conductive pattern layer.

[0013] The line can be under the conductive pattern layer and can contact the conductive pattern layer in a region in which the line overlaps the second groove.

[0014] The insulating layer can be between the conductive pattern layer and the line, wherein the line is electrically connected to the conductive pattern layer through a contact hole in the insulating layer.

[0015] The line can include a scan line, a data line, or a voltage line.

[0016] The conductive pattern layer can surround the opening region in a plan view.

[0017] The counter electrode of the light emitting diode can extend toward the middle region and can include a first portion and a second portion separated from each other with respect to the tip, the second portion being in the first groove and directly contacting the tip of the conductive pattern layer.

[0018] According to one or more embodiments, a display panel includes: a substrate including a first region, a second region at least partially surrounding the first region, and a third region between the first region and the second region; a light emitting diode in the second region and including a sub-pixel electrode, a counter electrode over the sub-pixel electrode, and a middle layer between the sub-pixel electrode and the counter electrode; a partition in the third region; a cover layer over the partition and including a conductive material; and a line passing through the second region, wherein the partition includes: an organic pattern layer over the substrate and defining a groove; and a conductive pattern layer electrically connected to the line, over an upper surface of the organic pattern layer, and including a tip extending toward a center of the groove in a plan view and having at least a portion covered by the cover layer.

[0019] The cover layer can include a first portion over the conductive pattern layer and a second portion in the groove and separated from the first portion.

[0020] The cover layer can continuously extend by completely covering the conductive pattern layer and the portion of the organic pattern layer in which the groove is formed.

[0021] The cover layer and the sub-pixel electrode can include the same material.

[0022] The line can be integral with the conductive pattern layer.

[0023] The line can be between the substrate and the conductive pattern layer, and can contact the conductive pattern layer.

[0024] The insulating layer can be between the conductive pattern layer and the line, wherein the line is electrically connected to the conductive pattern layer through a contact hole in the insulating layer.

[0025] The line can include a scan line, a data line, or a voltage line.

[0026] The partition can surround the first area in a plan view.

[0027] The display panel can further include an electrode layer including a first portion above an upper surface of the conductive pattern layer and a second portion in the recess and separated from the first portion.

[0028] The electrode layer can be above the cover layer.

[0029] The second portion of the electrode layer can directly contact the tip of the conductive pattern layer.

[0030] The electrode layer and the counter electrode can include the same material. BRIEF DESCRIPTION OF DRAWINGS

[0031] The above and other aspects of certain embodiments disclosed herein will become more apparent by describing in detail certain embodiments thereof with reference to the attached drawings in which: Figure 1 is a perspective view schematically illustrating an electronic device according to one or more embodiments; Figure 2 is a plan view schematically illustrating a display panel according to one or more embodiments; Figure 1 is a cross-sectional view taken along line II-II' of the electronic device of Figure 3 is a plan view schematically illustrating a display panel according to one or more embodiments; Figure 4 is an equivalent circuit diagram schematically illustrating a light emitting diode of a sub-pixel arranged in a display area and a driving circuit electrically connected to the light emitting diode according to one or more embodiments; Figure 5 is a cross-sectional view illustrating a portion of a display area of a display panel according to one or more embodiments; Figure 6 is a plan view illustrating a portion of a display panel according to one or more embodiments; Figure 7 is a cross-sectional view taken along line VII-VII' of a portion of the display panel of Figure 6 Figure 8 is a cross-sectional view taken along line VIII-VIII' of a portion of the display panel according to one or more embodiments;​Figure 6 a cross-sectional view of a portion of the display panel of FIG. 1 ; Figure 9 is a plan view showing a portion of the display panel according to one or more embodiments; Figure 6 a cross-sectional view of a portion of the display panel of FIG. 1 ; Figure 10 is a plan view showing a portion of the display panel according to one or more embodiments; Figure 11 is a cross-sectional view of a portion of the display panel of FIG. 1 taken along line X-X'; Figure 10 a cross-sectional view of a portion of the display panel of FIG. 1 ; Figure 12 is a cross-sectional view of a portion of the display panel of FIG. 1 taken along line X-X'; Figure 10 a cross-sectional view of a portion of the display panel of FIG. 1 ; Figure 13 is a cross-sectional view of a portion of the display panel of FIG. 1 taken along line X-X'; Figure 10 a cross-sectional view of a portion of the display panel of FIG. 1 ; Figure 14 is a cross-sectional view of a portion of the display panel of FIG. 1 taken along line X-X'; Figure 10 a cross-sectional view of a portion of the display panel of FIG. 1 ; Figure 15 is an enlarged cross-sectional view showing region XIV of FIG. 1 ; Figure 14 is a cross-sectional view of a portion of the display panel of FIG. 1 taken along line X-X'; Figure 16 Figure 10 is an enlarged cross-sectional view showing region XVI of FIG. 1 ; Figure 17 is an enlarged cross-sectional view showing region XVI of FIG. 1 ; Figure 16 is a cross-sectional view of a portion of the display panel of FIG. 1 taken along line X-X'; Figure 18 a cross-sectional view of a portion of the display panel of FIG. 1 ; Figure 10 is a cross-sectional view of a portion of the display panel of FIG. 1 taken along line X-X'; Figure 19 is a cross-sectional view of a portion of the display panel of FIG. 1 taken along line X-X';

[0032] ​​Aspects of some embodiments of the present disclosure and methods of implementing them can be more readily understood by reference to the following detailed description, taken with the accompanying drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the scope of the aspects of the present disclosure to those skilled in the art. Therefore, redundant, related, or irrelevant processes, elements, and techniques that are well known in the art or that are not necessary for the understanding of the aspects of the present disclosure can be omitted or only briefly described. Identical reference numerals, symbols or their combinations, throughout the drawings and the written description, indicate and refer to identical or corresponding parts, and thus a repeated description of which can be omitted.

[0033] The described embodiments can have various modifications and can be implemented in different forms and should not be interpreted as being limited to the embodiments shown herein. In describing the embodiments, the use of "may" or "can" corresponds to one or more embodiments of the present disclosure.

[0034] In view of the entire disclosure, those of ordinary skill in the art will understand that various suitable features of the various embodiments of the present disclosure can be combined, in part or whole, with each other, and can be technically interlocked and operated in various suitable ways, and unless otherwise stated or implied, the various embodiments can be implemented independently of each other or in combination with each other in any suitable manner.

[0035] In the drawings, the relative sizes of elements, layers, and regions can be exaggerated for clarity and / or descriptive purposes. In other words, since the sizes and thicknesses of the elements in the drawings have been arbitrarily shown for the purpose of facilitating description, the disclosure is not limited thereto. Additionally, the use of cross-hatching and / or shading in the drawings is generally provided to make the boundaries of the elements more clearly understood. As such, unless specifically referred to as, the presence or absence of cross-hatching or shading is not a indicator or conveyer of any preference or requirement for particular materials, material properties, dimensions, ratios, commonalities between illustrated elements, and / or any other characteristics, attributes, properties, etc. of the elements.

[0036] Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments and / or intermediate structures of embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Additionally, the specific structural and functional details disclosed herein are merely illustrative. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of elements as illustrated and described herein but can include deviations in shapes that result, for example, from manufacturing.

[0037] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0038] For ease of explanation, spatially relative terms such as “below,” “beneath,” “lower,” “underside,” “beneath,” “above,” “upper,” “over (throughout),” “higher,” “upper,” “side (e.g., as in “sidewall”)” and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below,” “beneath,” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “beneath” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. Similarly, when a first portion is described as being disposed “on” a second portion, this indicates that the first portion is disposed at the upper side or lower side of the second portion, and is not limited to the upper side of the second portion based on the gravity direction.

[0039] In addition, the phrase "in a plan view" means when viewing an object portion from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section taken by vertically cutting an object portion from the side. The term "superimposed" or "overlapping" means that the first object can be above, below, or to the side of the second object, and vice versa. Additionally, the term "superimposed" may include stacking, facing, or facing, extending over, covering, or partially covering, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art. The expression "not superimposed" may include meanings such as "spaced apart from," "on the side of," or "deviation from," as well as any other suitable equivalents as will be appreciated and understood by those of ordinary skill in the art. The terms "facing" and "facing" may mean that the first object can be directly or indirectly opposite to the second object. In the case where a third object is interposed between the first and second objects, although the first and second objects still face each other, the first and second objects may be understood to be indirectly opposite to each other.

[0040] It will be understood that when an element, layer, region or component is referred to as being "formed on" or "formed over" another element, layer, region or component, it can be directly or indirectly formed on, over, connected to or bonded to the other element, layer, region or component, such that one or more intervening elements, layers, regions or components can be present. In addition, it can be uniformly meant to be directly or indirectly joined or connected as well as integrally or non-integrally joined or connected. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically joined" to another layer, region or component, it can be directly electrically connected or directly electrically joined to the other layer, region and / or component, or one or more intervening layers, regions or components can be present. The one or more intervening components can include switches, resistors, and / or capacitors, etc. In describing embodiments, unless explicitly described as directly connected, expressions of connection indicate electrical connection, and "directly connected / directly joined" or "directly on" refer to one component directly connected or directly joined to another component or directly on another component without intervening components.

[0041] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the direction of formation is not limited to the upward direction, but includes forming the part on a side surface or in a downward direction. Conversely, when a part of a layer, film, region, plate, etc. is formed "under" another part, this not only includes the case where the part is "directly under" the other part, but also includes the case where there is yet another part between the part and the other part. Meanwhile, other expressions such as "between", "immediately between", or "adjacent to" and "directly adjacent to" describing the relationship between components can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers can also be present.

[0042] For purposes of this disclosure, the expression “at least one of (a / n), (b / n), and (c / n)” when preceding a list of two or more items, modifies the list as a whole and does not modify the individual items of the list. For example, without limitation, “at least one of a, b, and c” is interpreted as a, b, c, or any combination thereof (e.g., a and b, b and c, or a, b, and c). Similarly, the expression “one or more of (a / n), (b / n), and (c / n)” can include a, b, or c. As used herein, “or” is generally employed in its sense including at least one of the items so conjoined, and the terms “and / or” are intended to mean “and” or “or.” For example, a “and / or,” b “and / or,” or a and / or b can include a, b, or a and b. As used herein, when the expression “at least one of (a / n), (b / n), and (c / n)” or other similar expressions (e.g., “one or more of (a / n), (b / n), and (c / n)”) follows a list of two or more items, “at least one of (a / n), (b / n), and (c / n)” or other similar expressions modifies the list as a whole and does not modify the individual items of the list. When the expression “C to D” is used, it means C or more and D or less, unless otherwise noted.

[0043] It will be understood that, although the terms “first,” “second,” “third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure. As used herein, the term “first” element, component, region, layer or section can not necessarily mean that a “second” element, component, region, layer or section is present or is necessarily limited to a second element, component, region, layer or section. The term “first” can be used herein to distinguish different categories or groups of elements. For the sake of brevity, the terms “first,” “second,” etc. can each be respectively represented as “first category (or first group),” “second category (or second group),” etc.

[0044] In examples, the x-axis, the y-axis, and / or the z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0045] The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0046] As used herein, the terms "substantially," "approximately," "about," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. For example, "substantially" can include a range of + / - 5% from a corresponding value. As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art to which the discussion pertains and which is associated with the measurement of the particular quantity. For example, "about" can mean within one or more standard deviations, or within + / - 30%, + / - 20%, + / - 10%, + / - 5% of the stated value. Furthermore, the use of "may" indicates "one or more embodiments of the present disclosure" when describing embodiments of the present disclosure.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0048] Figure 1 FIG. 1 is a perspective view schematically illustrating an electronic device 1 according to one or more embodiments.

[0049] Referring to Figure 1The electronic device 1 is configured to display a moving image or a still image, and can be used as a display screen of various products such as a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device, as well as a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation, an ultra-mobile PC (UMPC). In addition, the electronic device 1 according to one or more embodiments can be used for a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head-mounted display (HMD). In addition, the electronic device 1 according to one or more embodiments can be used as a display for a dashboard of a vehicle, a central information display (CID) disposed on a center console or an instrument panel of a vehicle, a mirror display replacing a side mirror of a vehicle, or as a display disposed on a rear surface of a front seat as entertainment for a rear seat of a vehicle. For ease of description, Figure 1 A case in which the electronic device 1 according to one or more embodiments is used as a smart phone is illustrated.

[0050] In a plan view, the electronic device 1 can have a rectangular shape. For example, as illustrated in FIG. 1A, the electronic device 1 can have a rectangular planar shape having a short side in an x direction (or referred to as an "x-axis") and a long side in a y direction (or referred to as a "y-axis"). Figure 1 In a plan view, the electronic device 1 can have a rectangular shape. For example, as illustrated in FIG. 1A, the electronic device 1 can have a rectangular planar shape having a short side in an x direction (or referred to as an "x-axis") and a long side in a y direction (or referred to as a "y-axis").

[0051] The electronic device 1 (or the base 100) can include an opening area OA and a display area DA (e.g., in a plan view) surrounding at least the opening area OA. The electronic device 1 can include an intermediate area MA positioned between the opening area OA and the display area DA, and a peripheral area PA disposed outside the display area DA, e.g., surrounding the display area DA. The intermediate area MA can have a closed loop shape that completely surrounds the opening area OA in a plan view.

[0052] The opening area OA can be positioned inside the display area DA. In one or more embodiments, as illustrated in FIG. 1A, the opening area OA can be disposed in an upper center of the display area DA. Alternatively, the opening area OA can be disposed in various ways, such as an upper left side of the display area DA or an upper right side of the display area DA. In Figure 1 Figure 1 In FIG. 1A, one opening area OA is illustrated. However, in one or more other embodiments, a plurality of opening areas OA can be provided.

[0053] ​In one or more embodiments, the opening area OA may be the first area, the display area DA may be the second area, and the middle area MA may be the third area.

[0054] Figure 2 is a simplified diagram illustrating a method according to one or more embodiments Figure 1 sectional view of the electronic device 1 taken along line II-II'.

[0055] Reference Figure 2 , the electronic device 1 may include a display panel 2 and a component 3 arranged in an opening area OA of the display panel 2 . The display panel 2 and the component 3 may be accommodated in a housing 4 .

[0056] The display panel 2 may include an image generation layer 10 , an input detection layer 20 , an optical function layer 30 , an adhesive layer 40 , and a cover window 50 .

[0057] To display images, the image generation layer 10 may include a display element that emits light. The display element may include a light-emitting diode, for example, an organic light-emitting diode including an organic emissive layer. In one or more other embodiments, the light-emitting diode may be an inorganic light-emitting diode comprising an inorganic material. The inorganic light-emitting diode may include a PN junction diode comprising an inorganic semiconductor material. When voltage is applied to the PN junction diode in the forward direction, holes and electrons are injected, and the energy generated by the recombination of the holes and electrons can be converted into light energy to emit light of a corresponding color. The inorganic light-emitting diode may have a width ranging from several microns to several hundred microns, or from several nanometers to several hundred nanometers. In some embodiments, the image generation layer 10 may include a quantum dot light-emitting diode. For example, the emissive layer of the image generation layer 10 may include an organic material, an inorganic material, quantum dots, both an organic material and quantum dots, or both an inorganic material and quantum dots.

[0058] The input detection layer 20 can obtain coordinate information based on external input (e.g., a touch event). The input detection layer 20 may include touch electrodes (or sensing electrodes) and traces connected to the touch electrodes. The input detection layer 20 may be located on the image generation layer 10. The input detection layer 20 may detect external input using a mutual capacitance method or / and a self-capacitance method.

[0059] The input detection layer 20 may be formed directly on the image generation layer 10, or may be formed separately and then bonded to the input detection layer 20 via an adhesive layer (such as an optically clear adhesive). For example, the input detection layer 20 may be formed continuously after the process of forming the image generation layer 10, in which case the adhesive layer may not be between the input detection layer 20 and the image generation layer 10. Figure 2In the middle, the input detection layer 20 is between the image generation layer 10 and the optical function layer 30. However, in one or more other embodiments, the input detection layer 20 can be on the optical function layer 30.

[0060] The optical function layer 30 can include an anti-reflection layer. The anti-reflection layer can reduce the reflectance of light (external light) incident from the outside toward the display panel 2 through the cover window 50. The anti-reflection layer can include a retarder and a polarizer. In one or more other embodiments, the anti-reflection layer can include a black matrix and a color filter. The color filter can be arranged by considering the color of light emitted from each of the light emitting diodes of the image generation layer 10.

[0061] To improve the transmittance of the open area OA, the display panel 2 can include an opening 2OP passing through some of the layers included in the display panel 2. The opening 2OP can include first to third openings 10OP, 20OP, and 30OP passing through the image generation layer 10, the input detection layer 20, and the optical function layer 30, respectively. The first opening 10OP defined in the image generation layer 10, the second opening 20OP defined in the input detection layer 20, and the third opening 30OP defined in the optical function layer 30 can be superposed on each other and can form the opening 2OP defined in the display panel 2.

[0062] The cover window 50 can be on the optical function layer 30. The cover window 50 can be combined to the optical function layer 30 through an adhesive layer 40 including an optically clear adhesive (OCA) located between the cover window 50 and the optical function layer 30. The cover window 50 can cover the first opening 10OP defined in the image generation layer 10, the second opening 20OP defined in the input detection layer 20, and the third opening 30OP defined in the optical function layer 30.

[0063] The cover window 50 can include a glass material or a plastic material. The glass material can include Samsung Ultra Thin Glass ® (Samsung Ultra Thin Glass ® is a registered trademark of Samsung Display Co., Ltd., Korea). The plastic material can include polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0064] The open area OA can be a component area (e.g., a sensor area, a camera area, a speaker area, etc.) in which a component 3 for adding various functions to the electronic device 1 is positioned.

[0065] The assembly 3 can include an electronic element. For example, the assembly 3 can be an electronic element using light or sound. For example, the electronic element can include a sensor using light such as an infrared sensor, a camera receiving light and capturing an image, a sensor outputting and detecting light and sound to measure a distance or recognize a fingerprint, a small light outputting light, a speaker outputting sound, and the like. The electronic element using light can use light in various wavebands such as visible light, infrared light, and ultraviolet light. The opening area OA can correspond to an area through which light or / and sound traveling from the assembly 3 to the outside or from the outside toward the electronic element can pass.

[0066] Figure 3 is a plan view schematically showing a display panel 2 according to one or more embodiments.

[0067] Referring to Figure 3 , the display panel 2 can include a plurality of sub-pixels PX in a display area DA, and the display panel 2 can display an image by using light emitted from each of the sub-pixels PX. Each of the sub-pixels PX can emit red light, green light, or blue light by using a light-emitting diode. The light-emitting diode of each of the sub-pixels PX can be electrically connected to a scan line SL and a data line DL.

[0068] In one or more embodiments, in the peripheral area PA, a scan driver 11 for providing a scan signal to each of the sub-pixels PX, a data driver 12 for providing a data signal to each of the sub-pixels PX, and a first main power line and a second main power line for providing a first power voltage (e.g., a driving voltage) and a second power voltage (e.g., a common voltage) can be arranged. The scan drivers 11 can be arranged at opposite sides of the display area DA with the display area DA therebetween. In this case, the sub-pixels PX arranged at the left side of the opening area OA can be connected to the scan driver 11 arranged at the left side, and the sub-pixels PX arranged at the right side of the opening area OA can be connected to the scan driver 11 arranged at the right side.

[0069] The intermediate area MA can surround the opening area OA. The intermediate area MA is an area in which a display element (such as a light-emitting diode) that emits light is not arranged, and a trace for providing a signal to the sub-pixel PX disposed around the opening area OA can pass through the intermediate area MA. For example, the data line DL and / or the scan line SL can pass through the display area DA, and a portion of the data line DL and / or the scan line SL can bypass the intermediate area MA along an edge of the opening area OA.

[0070] In Figure 3 , the data driver 12 is arranged to be spaced apart from the substrate 100 (see Figure 5The side surface of the data driver 12 is adjacent to the side surface of the display panel 2. However, according to one or more other embodiments, the data driver 12 can be located on a printed circuit board electrically connected to pads (or called “lands”) arranged on one side of the display panel 2. The printed circuit board can be flexible, and a portion of the printed circuit board can be bent to be positioned under the rear surface of the display panel 2.

[0071] Figure 4 is a schematic circuit diagram illustrating a light emitting diode LED and a drive circuit PC electrically connected to the light emitting diode LED of a sub-pixel arranged in the display area DA according to one or more embodiments.

[0072] The drive circuit PC can be electrically connected to a first gate line GWL configured to transmit a first gate signal GW, a second gate line GIL configured to transmit a second gate signal GI, a third gate line GRL configured to transmit a third gate signal GR, a fourth gate line EML configured to transmit a fourth gate signal EM, a fifth gate line EMBL configured to transmit a fifth gate signal EMB, and a data line DL configured to transmit a data signal DATA. It can be understood that each of the first gate line GWL, the second gate line GIL, the third gate line GRL, the fourth gate line EML, and the fifth gate line EMBL transmits a scan signal to a corresponding transistor. Because the emission of the light emitting diode LED is controlled by the fourth gate signal EM and the fifth gate signal EMB, the fourth gate signal EM and the fifth gate signal EMB can be referred to as emission control signals, and the fourth gate line EML and the fifth gate line EMBL can be referred to as emission control lines. The drive circuit PC can be electrically connected to a drive voltage line PL configured to transmit a drive voltage ELVDD, a reference voltage line VRL configured to transmit a reference voltage Vref, a first initialization voltage line VAL configured to transmit a first initialization voltage Vaint, and a second initialization voltage line VIL configured to transmit a second initialization voltage Vint.

[0073] In one or more embodiments, the plurality of transistors included in the drive circuit PC can be N-type oxide thin film transistors. The oxide thin film transistor can be a low temperature polyoxide (LTPO) in which a semiconductor layer includes an oxide. However, this is merely an example, and the transistors of one or more embodiments are not limited thereto. For example, the semiconductor layer included in the N-type transistor can include an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon) or an organic semiconductor.

[0074] The driving circuit PC can include first to seventh transistors T1, T2, T3, T4, T5, T6, and T7, a first capacitor C1 and a second capacitor C2, and an auxiliary capacitor Ca. The first transistor T1 can be a driving transistor for outputting a driving current corresponding to a data signal DATA, and the second to seventh transistors T2, T3, T4, T5, T6, and T7 can be switching transistors for transmitting a signal. A first terminal (or a first electrode) and a second terminal (or a second electrode) of each of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 can be a source (or a source electrode) or a drain (or a drain electrode) according to a voltage at the first terminal and the second terminal. For example, the first terminal can be a drain and the second terminal can be a source, or the first terminal can be a source and the second terminal can be a drain according to a voltage at the first terminal and the second terminal. Hereinafter, a node to which a first-1 gate of the first transistor T1 is connected can be defined as a first node N1, and a node to which a second terminal of the first transistor T1 is connected can be defined as a second node N2.

[0075] The first transistor T1 can be connected to a driving voltage line PL and a light emitting diode LED. The first transistor T1 can be connected between the fifth transistor T5 and the sixth transistor T6. The first transistor T1 can include a gate (or a gate electrode), a first terminal, and a second terminal connected to the second node N2. The first transistor T1 can include a first-1 gate connected to the first node N1. The first transistor T1 can further include a first-2 gate connected to the second terminal thereof. The first-1 gate and the first-2 gate can be located in different layers to face each other. For example, the first-1 gate and the first-2 gate of the first transistor T1 can face each other with a semiconductor layer therebetween. Hereinafter, the gate (or the gate electrode) of the first transistor T1 can indicate the first-1 gate that participates in turning on and off the first transistor T1.

[0076] The gate of the first transistor T1 can be connected to the second terminal of the second transistor T2, connected to the first terminal of the third transistor T3, and connected to the first capacitor C1. The first-2 gate of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, connected to the first capacitor C1, and connected to the second capacitor C2. The first terminal of the first transistor T1 can be connected to the driving voltage line PL via the fifth transistor T5, and the second terminal of the first transistor T1 can be connected to the sub-pixel electrode (e.g., anode) of the light emitting diode LED via the sixth transistor T6. The first terminal of the first transistor T1 can be connected to the second terminal of the fifth transistor T5. The second terminal of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, connected to the first capacitor C1, and connected to the second capacitor C2. The first transistor T1 can receive the data signal DATA according to the switching operation of the second transistor T2, and can control the amount of current of the driving current flowing to the light emitting diode LED.

[0077] The second transistor T2 can be connected to the data line DL, and connected to the gate of the first transistor T1. The second transistor T2 can include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second terminal of the second transistor T2 can be connected to the gate of the first transistor T1, connected to the first terminal of the third transistor T3, and connected to the first capacitor C1. The second transistor T2 can be turned on according to the first gate signal GW received via the first gate line GWL, and can electrically connect the data line DL and the first node N1 to each other and transmit the data signal DATA received via the data line DL to the first node N1.

[0078] The third transistor T3 can be connected to the gate of the first transistor T1, and connected to the reference voltage line VRL. The third transistor T3 can include a gate connected to the third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL. The first terminal of the third transistor T3 can be connected to the gate of the first transistor T1, connected to the second terminal of the second transistor T2, and connected to the first capacitor C1. The third transistor T3 can be turned on according to the third gate signal GR received via the third gate line GRL, and can transmit the reference voltage Vref received via the reference voltage line VRL to the first node N1.

[0079] The fourth transistor T4 can be connected to the sixth transistor T6 and to the first initialization voltage line VAL. The fourth transistor T4 can be connected between the light emitting diode LED and the first initialization voltage line VAL. The fourth transistor T4 can include a gate connected to the second gate line GIL, a first terminal connected to the third node N3, and a second terminal connected to the first initialization voltage line VAL. The first terminal of the fourth transistor T4 can be connected to the second terminal of the sixth transistor T6 and to the sub-pixel electrode (e.g., anode) of the light emitting diode LED. The fourth transistor T4 can be turned on according to the second gate signal GI received via the second gate line GIL, and can transmit the first initialization voltage Vaint received via the first initialization voltage line VAL to the third node N3, and can initialize the sub-pixel electrode (e.g., anode) of the light emitting diode LED.

[0080] The fifth transistor T5 can be connected to the driving voltage line PL and to the first transistor T1. The fifth transistor T5 can include a gate connected to the fourth gate line EML, a first terminal connected to the driving voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 can be turned on or turned off according to the fourth gate signal EM received via the fourth gate line EML.

[0081] The sixth transistor T6 can be connected to the first transistor T1 and to the light emitting diode LED. The sixth transistor T6 can be connected between the second node N2 and the third node N3. The sixth transistor T6 can include a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The first terminal of the sixth transistor T6 can be connected to the second terminal of the first transistor T1, to the first capacitor C1, and to the second capacitor C2. The second terminal of the sixth transistor T6 can be connected to the first terminal of the fourth transistor T4 and to the sub-pixel electrode (e.g., anode) of the light emitting diode LED. The sixth transistor T6 can be turned on or turned off according to the fifth gate signal EMB received via the fifth gate line EMBL.

[0082] The seventh transistor T7 can be connected between the first transistor T1 and the second initialization voltage line VIL. The seventh transistor T7 can include a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the second initialization voltage line VIL. The first terminal of the seventh transistor T7 can be connected to the second terminal of the first transistor T1, to the first terminal of the sixth transistor T6, to the first capacitor C1, and to the second capacitor C2. The seventh transistor T7 can be turned on according to the second gate signal GI received via the second gate line GIL, and can transmit the second initialization voltage Vint received via the second initialization voltage line VIL to the second node N2.

[0083] The first capacitor C1 can be connected between the gate of the first transistor T1 and the second terminal of the first transistor T1. A first electrode of the first capacitor C1 can be connected to the first node N1, and a second electrode of the first capacitor C1 can be connected to the second node N2. The first electrode of the first capacitor C1 can be connected to the gate of the first transistor T1, to the second terminal of the second transistor T2, and to the first terminal of the third transistor T3. The second electrode of the first capacitor C1 can be connected to the second terminal of the first transistor T1 and the first-2 gate, to the second electrode of the second capacitor C2, and to the first terminal of the sixth transistor T6. The first capacitor C1 is a storage capacitor, and can store a threshold voltage of the first transistor T1 and a voltage corresponding to the data signal DATA.

[0084] The first transistor T1 can be turned on when the third transistor T3 and the fifth transistor T5 are turned on. The first transistor T1 can be turned off when a voltage at the second terminal of the first transistor T1 drops to a difference (Vref-Vth1) between the reference voltage Vref and a threshold voltage (Vth1) of the first transistor T1, and a voltage corresponding to the threshold voltage (Vth1) of the first transistor T1 can be stored in the first transistor T1, thereby compensating for the threshold voltage (Vth1) of the first transistor T1.

[0085] The second capacitor C2 can be connected between the driving voltage line PL and the second node N2. A first electrode of the second capacitor C2 can be connected to the driving voltage line PL. A second electrode of the second capacitor C2 can be connected to the second terminal of the first transistor T1 and the first-2 gate, to the second electrode of the first capacitor C1, and to the first terminal of the sixth transistor T6.

[0086] Capacitances of each of the first capacitor C1 and the second capacitor C2 can vary according to a color of light emitted from the light emitting diode LED.

[0087] The auxiliary capacitor Ca can be electrically connected to the sixth transistor T6, to the sustain voltage line VSSL, and to a sub-pixel electrode (e.g., anode) of the light emitting diode LED. The auxiliary capacitor Ca can store and hold a voltage corresponding to a voltage difference between the sub-pixel electrode (e.g., anode) of the light emitting diode LED and the sustain voltage line VSSL, thereby reducing or preventing an increase in black luminance when the sixth transistor T6 is turned off.

[0088] The light emitting diode LED can be connected to the first transistor T1 through the sixth transistor T6. The light emitting diode LED can include a sub-pixel electrode (anode) connected to the third node N3 and a counter electrode (e.g., cathode) facing the sub-pixel electrode which can receive a common voltage ELVSS. In one or more embodiments, the counter electrode can extend to the display area DA and can be electrically connected to the sustain voltage line VSSL for providing the common voltage ELVSS. From the first transistor T1, a driving current is outputted according to the turned-on fifth transistor T5 and the turned-on sixth transistor T6, flows through the light emitting diode LED, and the light emitting diode LED can emit light having a luminance corresponding to a size of the driving current.

[0089] In Figure 4 , the driving circuit PC includes seven transistors. However, one or more embodiments are not limited thereto. In one or more other embodiments, the driving circuit PC can include six or less transistors or eight or more transistors.

[0090] Figure 5 is a cross-sectional view showing a portion of the display area DA of the display panel 2 according to one or more embodiments.

[0091] Referring to Figure 5 , the image generation layer 10 is in the display area DA. A sub-pixel PX arranged in the image generation layer 10 can include a light emitting diode LED as a display element. In one or more embodiments, in Figure 5 , a portion of the driving circuit PC described with reference to Figure 4 is schematically shown. For example, a thin film transistor TFT connected to the light emitting diode LED of Figure 5 may be a transistor (e.g., the sixth transistor T6 or the first transistor T1) among the transistors shown in Figure 4 .

[0092] The substrate 100 may include a glass material or a polymer resin. In one or more embodiments, the substrate 100 may have an alternating stacking structure of a base layer including a polymer resin and a barrier layer including an inorganic insulating material (such as silicon oxide or silicon nitride). The polymer resin may include, for example, polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate.

[0093] The buffer layer 101 may be located on the substrate 100 (as used herein, "located on..." may mean "over..."). The buffer layer 101 may planarize the upper surface of the substrate 100 and protect the upper surface of the substrate 100. The buffer layer 101 may include an inorganic insulating material (such as silicon oxide (SiO x ), silicon nitride (SiN x ) and / or silicon oxynitride (SiO x N y )), and can be a single layer or multilayer structure of the above materials. In one or more embodiments, a barrier layer can also be between the substrate 100 and the buffer layer 101. The barrier layer can include a material similar to that of the buffer layer 101.

[0094] The thin film transistor TFT may be located on the buffer layer 101. As described above, the thin film transistor TFT may be Figure 4 A brief description of a portion of the driving circuit PC (eg, the first transistor T1 or the sixth transistor T6) is provided. The thin film transistor TFT may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The gate electrode GE may be the same as that described above. Figure 4 The source electrode SE and the drain electrode DE can be the same as those described above. Figure 4 The described first terminal (or first electrode) and second terminal (or second electrode) correspond.

[0095] The active layer ACT may be located on the buffer layer 101 and may include a drain region overlapping the drain electrode DE, a source region overlapping the source electrode SE, and a channel region between the drain and source regions. The source and drain regions of the active layer ACT may be regions doped with impurities.

[0096] The gate insulating layer 103 may be located on the active layer ACT. The gate insulating layer 103 may include an inorganic material including oxide or nitride. For example, the gate insulating layer 103 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N yat least one of silicon oxide (SiO2), silicon nitride (SiN4), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO x ) and can have a single layer or a multi-layer structure of the above-described materials, in which ZnO x may be ZnO or ZnO2.

[0097] The gate electrode GE can be located on the gate insulating layer 103. The gate electrode GE can at least partially overlap the active layer ACT. For example, the gate electrode GE can overlap the channel region of the active layer ACT. The gate electrode GE can include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu) and can have a single layer or a multi-layer structure of the above-described materials.

[0098] The interlayer insulating layer 105 can cover the gate electrode GE. The interlayer insulating layer 105 can include an inorganic material including an oxide or a nitride. For example, the interlayer insulating layer 105 can include at least one of silicon oxide (SiO2), silicon nitride (SiN4), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO x ) and can have a single layer or a multi-layer structure of the above-described materials, in which ZnO x may be ZnO or ZnO2. x y The interlayer insulating layer 105 can cover the gate electrode GE. The interlayer insulating layer 105 can include an inorganic material including an oxide or a nitride. For example, the interlayer insulating layer 105 can include at least one of silicon oxide (SiO2), silicon nitride (SiN4), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO x ) and can have a single layer or a multi-layer structure of the above-described materials, in which ZnO x may be ZnO or ZnO2.

[0099] The gate insulating layer 103 and the interlayer insulating layer 105 can include contact holes overlapping the source region and the drain region of the active layer ACT. The source electrode SE and the drain electrode DE can be located on the interlayer insulating layer 105. The source electrode SE can be arranged to overlap the source region of the active layer ACT, and the drain electrode DE can be arranged to overlap the drain region of the active layer ACT. The source electrode SE and the drain electrode DE can be connected to the active layer ACT through the respective contact holes formed in the gate insulating layer 103 and the interlayer insulating layer 105.

[0100] The organic insulating layer 107 can cover the inorganic insulating layer IIL and the thin film transistor TFT including the buffer layer 101, the gate insulating layer 103, and the interlayer insulating layer 105. The organic insulating layer 107 can include a first organic insulating layer 1071 located on the inorganic insulating layer IIL and a second organic insulating layer 1072 located on the first organic insulating layer 1071.

[0101] ​The first organic insulating layer 1071 may include a contact hole overlapping the drain electrode DE. A contact metal CM may be located on the upper surface of the first organic insulating layer 1071 and may be electrically connected to the drain electrode DE via the contact hole defined in the first organic insulating layer 1071. The second organic insulating layer 1072 may include a contact hole overlapping the contact metal CM. The sub-pixel electrode 121 may be located on the upper surface of the second organic insulating layer 1072 and may be electrically connected to the contact metal CM via the contact hole defined in the second organic insulating layer 1072. Thus, the sub-pixel electrode 121 may be electrically connected to the drain electrode DE of the thin film transistor TFT via the contact metal CM.

[0102] exist Figure 4 , two organic insulating layers (e.g., first organic insulating layer 1071 and second organic insulating layer 1072) and one contact metal CM are shown. However, one or more embodiments are not limited thereto. In one or more other embodiments, N organic insulating layers (N may be a natural number of 3 or greater) and N-1 contact metals may be provided. Alternatively, in one or more other embodiments, the organic insulating layer may be a single layer, and the contact metal may be omitted.

[0103] The organic insulating layer 107, such as the first organic insulating layer 1071 and the second organic insulating layer 1072, may include a general polymer (such as benzocyclobutene, polyimide, hexamethyldisiloxane, polymethyl methacrylate, or polystyrene), a polymer derivative having a phenolic group, an acryl polymer, an imide polymer, an aromatic ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, or a vinyl alcohol polymer, and may have a single-layer or multi-layer structure of the above materials. In one or more embodiments, the first organic insulating layer 1071 and the second organic insulating layer 1072 may include the same material. In one or more embodiments, the first organic insulating layer 1071 and the second organic insulating layer 1072 may include different materials. In one or more embodiments, the first organic insulating layer 1071 and / or the second organic insulating layer 1072 may include multiple layers including different materials.

[0104] The subpixel electrode 121 may be located on an upper surface of the organic insulating layer 107, for example, on an upper surface of the second organic insulating layer 1072. As described above, the subpixel electrode 121 may be electrically connected to the contact metal CM through a contact hole defined in the second organic insulating layer 1072.

[0105] The sub-pixel electrode 121 can include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The sub-pixel electrode 121 can include a reflective film including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof. However, the configuration and material of the sub-pixel electrode 121 are not limited thereto, and various modifications can be made.

[0106] The pixel-defining layer 109 can be located on the organic insulating layer 107, for example, on an upper surface of the second organic insulating layer 1072. The pixel-defining layer 109 can cover edges (or edge regions) of the sub-pixel electrode 121. In other words, the pixel-defining layer 109 can have an opening to expose a portion of a central portion of the sub-pixel electrode 121. The size and shape of an emission region of the light-emitting diode LED can be determined by the opening.

[0107] The intermediate layer 123 can be located on the sub-pixel electrode 121. The intermediate layer 123 can include a functional layer 123f located on the pixel-defining layer 109 and an emission layer 1232 disposed within the opening defined in the pixel-defining layer 109. The functional layer 123f can include a first functional layer 1231 located on the pixel-defining layer 109 and a second functional layer 1233 located on the first functional layer 1231. In one or more embodiments, the first functional layer 1231 can be located on the pixel-defining layer 109, the emission layer 1232 can be located in the opening defined in the pixel-defining layer 109 on the first functional layer 1231, and the second functional layer 1233 can be located on the first functional layer 1231 to cover the emission layer 1232. In other words, the emission layer 1232 can be disposed in the opening defined in the pixel-defining layer 109 and can be between the first functional layer 1231 and the second functional layer 1233.

[0108] The emission layer 1232 can include an organic emission layer including a low molecule or a polymer material. The first functional layer 1231 can include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer 1233 can include a hole transport layer (HTL) and / or a hole injection layer (HIL). In some embodiments, the first functional layer 1231 or the second functional layer 1233 can be omitted. In some embodiments, the positions of the first functional layer 1231 and the second functional layer 1233 can be exchanged.

[0109] The counter electrode 125 can be located on the intermediate layer 123. For example, the counter electrode can be located on the second functional layer 1233. The counter electrode 125 can be arranged to completely cover the intermediate layer 123. The counter electrode 125 can include a conductive material having a low work function. For example, the counter electrode 125 can include a semi-transparent or transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or alloys thereof. Optionally, the counter electrode 125 can further include a layer including ITO, IZO, ZnO, or In2O3 on the (semi)transparent layer including the above-described materials.

[0110] The thin film encapsulation layer TFE can be located on the counter electrode 125, and can completely cover the light emitting diode LED. The thin film encapsulation layer TFE can include at least one inorganic layer and at least one organic layer. In one or more embodiments, the thin film encapsulation layer TFE can include a first inorganic encapsulation layer 131 and a second inorganic encapsulation layer 135, and can include an organic encapsulation layer 133 between the first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 135.

[0111] The first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 135 can include one or more inorganic insulating materials, such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO x ), where ZnO x may be ZnO or ZnO2. The organic encapsulation layer 133 can include a polymer-based material. The polymer-based material can include a silicon-based resin, an acryl-based resin, an epoxy-based resin, polyimide, polyethylene, or the like.

[0112] Figure 5 is a plan view illustrating a portion of the display panel 2 according to one or more embodiments.

[0113] Figure 6 The opening area OA, the intermediate area MA, and the display area DA of the display panel 2 are illustrated. The sub-pixel PX can be arranged in the display area DA. The sub-pixel PX can be arranged (e.g., in a plan view) to surround the opening area OA and the intermediate area MA in the display area DA. The sub-pixel PX is a minimum area that emits light, and can emit light through a display element (e.g., a light emitting diode LED). The position of the sub-pixel PX can correspond to the position of the light emitting diode LED. The sub-pixel PX being located in the display area DA can indicate that the light emitting diode LED is arranged in the display area DA.

[0114] In a plan view, the sub-pixels PX and / or the light emitting diodes LED adjacent to the opening area OA can be arranged spaced apart from each other with respect to the opening area OA. The sub-pixels PX and / or the light emitting diodes LED can be arranged vertically spaced apart from each other with respect to the opening area OA, or can be arranged horizontally spaced apart from each other with respect to the opening area OA.

[0115] The separators SEP can be arranged spaced apart from each other in the middle area MA. In other words, the separators SEP can be arranged spaced apart from each other between the display area DA and the opening area OA or between the display area DA and the opening 2OP. In a plan view (for example, when viewed from a direction perpendicular to the upper surface of the base 100), each of the separators SEP can surround the opening area OA or the opening 2OP. In a plan view, each of the separators SEP can have a closed loop shape. In one or more embodiments, in a plan view, the separators SEP can have a circular shape concentric with the opening area OA or the opening 2OP. In this case, the diameter of the separators SEP can be greater than the diameter of the opening area OA or the opening 2OP. As described above, the separators SEP can include an electrically conductive material.

[0116] A plurality of conductive lines CL can be arranged in the display area DA and the middle area MA. In other words, the conductive lines CL can extend across the display area DA and the middle area MA. The conductive lines CL can include conductive lines CL extending in different directions (for example, conductive lines CL extending in the x direction and conductive lines CL extending in the y direction). In one or more embodiments, a plurality of conductive lines CL extending in the x direction can be arranged spaced apart from each other in the y direction. A plurality of conductive lines CL extending in the y direction can be arranged spaced apart from each other in the x direction.

[0117] The conductive lines CL can include various lines arranged in the display panel 2, such as scan lines SL, data lines DL, and / or voltage lines. For example, together with the Figure 6 Referring to Figure 4 together, the conductive lines CL can include at least one of a first gate line GWL, a second gate line GIL, a third gate line GRL, a fourth gate line EML, a fifth gate line EMBL, a data line DL, a driving voltage line PL, a reference voltage line VRL, a first initialization voltage line VAL, and a second initialization voltage line VIL.

[0118] The conductive lines CL can be connected to the separators SEP in the middle area MA. For example, each of the conductive lines CL can be connected to a corresponding separator SEP in the middle area MA. In one or more embodiments, one of the conductive lines CL disposed on the left side (or -x direction (i.e., a direction opposite to the x direction)) of the opening area OA and one of the conductive lines CL disposed on the right side (or +x direction (i.e., the x direction)) of the opening area OA can be connected to the same separator SEP. By this, the conductive line CL on the left side of the opening area OA and the conductive line CL on the right side of the opening area OA can be electrically connected to each other through the separator SEP in the middle area MA. The conductive lines CL can transmit electric current between the left side and the right side of the opening area OA through the separator SEP. In other words, the separator SEP can serve as an electric path through which electric current can be transmitted within the middle area MA.

[0119] Because a plurality of separators SEP can be disposed in the middle area MA, and because each of the separators SEP can be separated from each other, it can be understood that, in the middle area MA, as many separators SEP that are separated from each other, as many electric paths. Each of the conductive lines CL can obtain an electric path that bypasses the opening area OA by using the separators SEP. In other words, the separators SEP can serve as an electric path through which some of the various lines present in the display panel 2 can bypass the opening area OA.

[0120] Figure 6 is a cross-sectional view of a portion of the display panel 2 taken along the line VII-VII' according to one or more embodiments. Figure 7 is a cross-sectional view of a portion of the display panel 2 taken along the line VII-VII' according to one or more embodiments.

[0121] Referring to Figure 6 , the inorganic insulating layer IIL can be located on the substrate 100. For example, the inorganic insulating layer IIL can include the above-mentioned buffer layer 101 (see Figure 7 ), the gate insulating layer 103 (see Figure 5 ), and the interlayer insulating layer 105 (see Figure 5 ). A plurality of separators SEP can be located on the inorganic insulating layer IIL. The separators SEP can separate the functional layer 123f and the counter electrode 125 into a plurality of portions, which is described below. The separators SEP can include the organic pattern layer 108 and the conductive pattern layer CP.

[0122] The organic pattern layer 108 can be located on the inorganic insulating layer IIL. For example, the organic pattern layer 108 can be located on an upper surface of the inorganic insulating layer IIL. In one or more embodiments, the organic pattern layer 108 and the first organic insulating layer 1071 can include the same material. In one or more embodiments, the organic pattern layer 108 and the first organic insulating layer 1071 can be formed simultaneously or substantially simultaneously.

[0123] The organic pattern layer 108 can include first grooves 108G1 and second grooves 108G2. The first grooves 108G1 and the second grooves 108G2 of the organic pattern layer 108 can be alternately arranged in one direction (e.g., a direction perpendicular to the z-axis). For example, the first grooves 108G1 can be positioned between two adjacent second grooves 108G2, and the second grooves 108G2 can be positioned between two adjacent first grooves 108G1. In one or more embodiments, the first grooves 108G1 can not pass through the organic pattern layer 108 (e.g., the first grooves 108G1 can be defined by the organic pattern layer 108). In one or more embodiments, the first grooves 108G1 can include side surfaces angled with respect to the z-axis. In other words, the side surfaces of the first grooves 108G1 can be tapered with respect to the upper surface of the inorganic insulating layer IIL. In one or more embodiments, the second grooves 108G2 can pass through the organic pattern layer 108. In one or more embodiments, the second grooves 108G2 can include side surfaces angled with respect to the z-axis. In other words, the side surfaces of the second grooves 108G2 can be tapered with respect to the inorganic insulating layer IIL. In one or more embodiments, the angle at which the side surfaces of the first grooves 108G1 are inclined with respect to the z-axis and the angle at which the side surfaces of the second grooves 108G2 are inclined with respect to the z-axis can be equal to each other. However, one or more embodiments are not necessarily limited thereto, and the side surfaces of the first grooves 108G1 and the second grooves 108G2 can be parallel to the z-axis.

[0124] The conductive pattern layer CP can be located on the organic pattern layer 108. The conductive pattern layer CP can include a conductive material. In one or more embodiments, the conductive pattern layer CP and the contact metal CM (see Figure 5 ) can include the same material. In one or more embodiments, the conductive pattern layer CP and the contact metal CM (see Figure 5 ) can be formed simultaneously or substantially simultaneously.

[0125] A portion of the conductive pattern layer CP can be arranged in the second grooves 108G2 of the organic pattern layer 108. In one or more embodiments, the conductive pattern layer CP can be in direct contact with the upper surface of the inorganic insulating layer IIL within the second grooves 108G2. In one or more embodiments, the conductive pattern layer CP can cover the side surfaces of the organic pattern layer 108 and the upper surface of the inorganic insulating layer IIL that are in contact with the second grooves 108G2.

[0126] A portion of the conductive pattern layer CP can protrude (e.g., in a plan view) from the upper surface of the organic pattern layer 108 toward the center of the first groove 108G1. For example, a portion of the conductive pattern layer CP can be located on the upper surface of the organic pattern layer 108, and can protrude from an edge of the upper surface of the organic pattern layer 108 that is in contact with the first groove 108G1. In other words, the conductive pattern layer CP can include a tip CP-T structure that protrudes from an edge of the organic pattern layer 108 toward the center of the first groove 108G1.

[0127] The conductive line CL can be arranged across the display area DA and the intermediate area MA. For example, a portion of the conductive line CL can be positioned in the display area DA, and another portion of the conductive line CL can be positioned in the intermediate area MA. In one or more embodiments, the conductive line CL and the conductive pattern layer CP can include the same material. In one or more embodiments, the conductive line CL and the contact metal CM (see Figure 5 ) can include the same material. In one or more embodiments, the conductive line CL and the conductive pattern layer CP can be integrally formed. Accordingly, the conductive line CL and the conductive pattern layer CP can be electrically connected to each other. In one or more embodiments, the conductive line CL, the conductive pattern layer CP, and the contact metal CM (see Figure 5 ) can be formed at the same time or substantially at the same time. In one or more embodiments, the first organic insulating layer 1071 and the organic pattern layer 108 can be formed at the same time or substantially at the same time, and the contact metal CM (see Figure 5 ), the conductive line CL, and the conductive pattern layer CP can be formed at the same time or substantially at the same time. In this case, the contact metal CM (see Figure 5 ) and the conductive line CL can be located on the first organic insulating layer 1071, and the conductive pattern layer CP can be positioned on the organic pattern layer 108.

[0128] In one or more embodiments, the conductive line CL can be the above-described data line DL (see Figure 5 ). In one or more embodiments, the data line DL (see Figure 3 ), the conductive line CL, and the conductive pattern layer CP can be integrally formed. Accordingly, the data line DL (see Figure 3 ) and the conductive pattern layer CP can be electrically connected to each other.

[0129] The cover layer 122 can be located on the conductive pattern layer CP. The cover layer 122 can include a conductive material. In one or more embodiments, the cover layer 122 and the sub-pixel electrode 121 (see Figure 3 ) can include the same material. In one or more embodiments, the cover layer 122 and the sub-pixel electrode 121 (see Figure 5 ) can be formed at the same time or substantially at the same time.

[0130] A portion of the cover layer 122 can be located on the conductive line CL. Another portion of the cover layer 122 can be located on the conductive pattern layer CP within the second groove 108G2 of the organic pattern layer 108. Another portion of the cover layer 122 (e.g., a first portion 122-1 of the cover layer 122) can be located on the tip CP-T of the conductive pattern layer CP. In one or more embodiments, the first portion 122-1 of the cover layer 122 can cover an upper surface of the tip CP-T of the conductive pattern layer CP. Another portion of the cover layer 122 (e.g., a second portion 122-2 of the cover layer 122) can be disposed in the first groove 108G1 of the organic pattern layer 108. In one or more embodiments, the second portion 122-2 of the cover layer 122 can cover an upper surface of a portion of the organic pattern layer 108 in which the first groove 108G1 is formed. In one or more embodiments, the second portion 122-2 of the cover layer 122 can be in contact with a side surface of the portion of the organic pattern layer 108 in which the first groove 108G1 is formed. The first portion 122-1 and the second portion 122-2 of the cover layer 122 can be spaced apart from each other by the tip CP-T of the conductive pattern layer CP.

[0131] The functional layer 123f can be located on the cover layer 122. A portion of the functional layer 123f can be located on the cover layer 122 within the second groove 108G2. Another portion of the functional layer 123f (e.g., a first portion 123f-1 of the functional layer 123f) can be located on the first portion 122-1 of the cover layer 122. In one or more embodiments, the first portion 123f-1 of the functional layer 123f can cover an upper portion of the first portion 122-1 of the cover layer 122. Another portion of the functional layer 123f (e.g., a second portion 123f-2 of the functional layer 123f) can be located on the second portion 122-2 of the cover layer 122. Accordingly, the second portion 123f-2 of the functional layer 123f can be disposed in the first groove 108G1 of the organic pattern layer 108. In one or more embodiments, the second portion 123f-2 of the functional layer 123f can cover an upper surface of the second portion 122-2 of the cover layer 122. In one or more embodiments, the second portion 123f-2 of the functional layer 123f can be in contact with a side surface of the portion of the organic pattern layer 108 in which the first groove 108G1 is formed. The first portion 123f-1 and the second portion 123f-2 of the functional layer 123f can be spaced apart from each other by the tip CP-T of the conductive pattern layer CP.

[0132] The counter electrode 125 can be located on the functional layer 123f. A portion of the counter electrode 125 can be located on the functional layer 123f within the second groove 108G2. Another portion of the counter electrode 125 (e.g., a first portion 125-1 of the counter electrode 125) can be located on a first portion 123f-1 of the functional layer 123f. In one or more embodiments, the first portion 125-1 of the counter electrode 125 can cover an upper surface of the first portion 123f-1 of the functional layer 123f. Another portion of the counter electrode 125 (e.g., a second portion 125-2 of the counter electrode 125) can be located on a second portion 123f-2 of the functional layer 123f. Accordingly, the second portion 125-2 of the counter electrode 125 can be disposed in the first groove 108G1 of the organic pattern layer 108. In one or more embodiments, the second portion 125-2 of the counter electrode 125 can cover an upper surface of the second portion 123f-2 of the functional layer 123f. In one or more embodiments, the second portion 125-2 of the counter electrode 125 can be in contact with a side surface of a portion of the organic pattern layer 108 in which the first groove 108G1 is formed. The first portion 125-1 and the second portion 125-2 of the counter electrode 125 can be separated from each other due to the tip CP-T of the conductive pattern layer CP.

[0133] The thin film encapsulation layer TFE can completely cover the counter electrode 125. For example, the first inorganic encapsulation layer 131 can completely cover the counter electrode 125. A portion of the first inorganic encapsulation layer 131 can be disposed in the first groove 108G1. A portion of the first inorganic encapsulation layer 131 can be disposed in the second groove 108G2. In the first groove 108G1, the first inorganic encapsulation layer 131 can be in contact with a side surface of the organic pattern layer 108 in which the first groove 108G1 is formed.

[0134] Figure 5 is a cross-sectional view of a portion of the display panel 2 taken along the line VIII-VIII' according to one or more embodiments. Figure 8 is a cross-sectional view of a portion of the display panel 2 taken along the line VIII-VIII' according to one or more embodiments.

[0135] In the corresponding embodiments, the features other than the features described below are substantially the same as the features of the embodiments corresponding to Figure 6 In the corresponding embodiments, the features other than the features described below are substantially the same as the features of the embodiments corresponding to Figure 8 In the corresponding embodiments, the features other than the features described below are substantially the same as the features of the embodiments corresponding to

[0136] Referring to Figure 7The conductive line CL can be located on the inorganic insulating layer IIL. For example, the conductive line CL can be located between the first organic insulating layer 1071 and the inorganic insulating layer IIL. A portion of the conductive line CL can overlap the second recess 108G2 of the organic pattern layer 108. In one or more embodiments, the conductive line CL can be in direct contact with a portion of the conductive pattern layer CP disposed in the second recess 108G2. For example, an upper surface of the conductive line CL and a lower surface of the conductive pattern layer CP can be in direct contact with each other. Thus, the conductive line CL can be electrically connected to the conductive pattern layer CP.

[0137] In one or more embodiments, the conductive line CL can include the same material as the source electrode SE (see Figure 8 ) and / or the drain electrode DE (see Figure 5 ). In one or more embodiments, the conductive line CL can be formed simultaneously or substantially simultaneously with the source electrode SE (see Figure 5 ) and / or the drain electrode DE (see Figure 5 ).

[0138] In one or more embodiments, the conductive line CL can be the scan line SL (see Figure 5 ) described above. In one or more embodiments, the scan line SL (see Figure 3 ), the conductive line CL, and the conductive pattern layer CP can be integrally formed.

[0139] Figure 3 is a cross-sectional view of a portion of the display panel 2 of FIG. 1 taken along the line IX-IX' according to one or more embodiments. Figure 9

[0140] Among the features of the embodiments corresponding to Figure 6 , the features other than those described below are substantially the same as the embodiments corresponding to Figure 9 .

[0141] Referring to Figure 7 , the conductive line CL can be disposed in the inorganic insulating layer IIL. For example, a portion of the inorganic insulating layer IIL can be between the conductive line CL and the conductive pattern layer CP or between the conductive line CL and the organic pattern layer 108. In other words, an upper surface of the conductive line CL can be spaced apart from a lower surface of the organic pattern layer 108. The conductive line CL can overlap the second recess 108G2 of the organic pattern layer 108. In the region overlapping the second recess 108G2 of the organic pattern layer 108, the inorganic insulating layer IIL between the conductive line CL and the conductive pattern layer CP can include a contact hole. The conductive line CL and the conductive pattern layer CP can be in direct contact with each other through the contact hole. By this, the conductive line CL can be electrically connected to the conductive pattern layer CP.

[0142] ​In one or more embodiments, the conductive lines CL can include the same material as the gate electrodes GE (see Figure 9 In one or more embodiments, the conductive lines CL can be formed at the same time or substantially at the same time as the gate electrodes GE (see Figure 5

[0143] Figure 5 is a plan view showing a portion of the display panel 2 according to one or more other embodiments.

[0144] In the corresponding embodiment, features other than those described below are substantially the same as in the embodiment corresponding to Figure 10 Figure 10

[0145] Referring to Figure 6 Some of each of the scan lines SL extending in the x-axis and the data lines DL extending in the y-axis can be arranged in the middle area MA. For example, the scan lines SL and the data lines DL can be arranged in the display area DA and the middle area MA. Each of the scan lines SL and the data lines DL can bypass the opening area OA or the opening 2OP so as not to be arranged in the opening area OA. For example, at least one of the scan lines SL can extend in the x-axis in the middle area MA and then along a path forming a concentric circular shape with the opening area OA, and can extend again in the x-axis and can bypass the opening area OA. Similarly, at least one of the data lines DL can extend in the y-axis in the middle area MA and then along a path forming a concentric circular shape with the opening area OA, and can extend again in the y-axis and can bypass the opening area OA.

[0146] A plurality of conductive lines can be arranged in the display area DA and the middle area MA. In one or more embodiments, the first conductive line CL1 can be positioned at the right side (or +x side) of the opening area OA and can extend along the x-axis. In one or more embodiments, the second conductive line CL2 can be positioned above the opening area OA (or at the +y side) and can extend along the y-axis. In one or more embodiments, the third conductive line CL3 can be positioned at the left side (or -x side) of the opening area OA and can extend along the x-axis. In one or more embodiments, the fourth conductive line CL4 can be positioned below the opening area OA (or at the -y side) and can extend along the y-axis. In one or more embodiments, the display panel 2 can include at least one of the first conductive line CL1 to the fourth conductive line CL4.

[0147] ​​​The scan line SL can be positioned above (or on the +y side) or below (or on the -y side) the first conductive line CL1 and the third conductive line CL3. The scan line SL positioned above (or on the +y side) the first conductive line CL1 and the third conductive line CL3 can extend along an area positioned above (or on the +y side) the opening area OA and can bypass the opening area OA. The scan line SL positioned below (or on the -y side) the first conductive line CL1 and the third conductive line CL3 can extend along an area positioned below (or on the -y side) the opening area OA and can bypass the opening area OA.

[0148] The data line DL can be arranged on the right (or on the +x side) or left (or on the -x side) of the second conductive line CL2 and the fourth conductive line CL4. The data line DL positioned on the right (or on the +x side) of the second conductive line CL2 and the fourth conductive line CL4 can extend along an area positioned on the right (or on the +x side) of the opening area OA and can bypass the opening area OA. The data line DL positioned on the left (or on the -x side) of the second conductive line CL2 and the fourth conductive line CL4 can extend along an area positioned on the left (or on the -x side) of the opening area OA and can bypass the opening area OA.

[0149] The plurality of separators SEP can be arranged within the middle area MA. In one or more embodiments, the separators SEP can be between the opening area OA and the scan line SL and between the opening area OA and the data line DL. In one or more embodiments, the separators SEP can surround the opening area OA in a plan view. Each of the separators SEP can have a closed loop shape. In one or more embodiments, the separators SEP can have a circular shape concentric with the opening area OA or the opening 2OP in a plan view. In one or more embodiments, at least one of the first conductive line CL1 to the fourth conductive line CL4 can be connected to at least one of the separators SEP. In Figure 10 In one or more embodiments, a case in which the first conductive line CL1 to the fourth conductive line CL4 are connected to the separators SEP arranged at the outermost sides is shown. In one or more other embodiments, only some of the first conductive line CL1 to the fourth conductive line CL4 can be connected to the separators SEP. In one or more other embodiments, each of the first conductive line CL1 to the fourth conductive line CL4 can be connected to a different separator SEP, respectively.

[0150] In one or more embodiments, the plurality of separators SEP can be respectively electrically connected to each other. For example, the separators SEP can be electrically connected to each other by the conductive layer described below. The separators SEP are electrically connected to each other to function as a single electrical path within the intermediate area MA. For example, the separators SEP, the first conductive line CL1, the second conductive line CL2, the third conductive line CL3, and the fourth conductive line CL4 can all be respectively electrically connected to each other. In other words, the first conductive line CL1 to the fourth conductive line CL4 can be electrically connected to each other through the separators SEP. Because the separators SEP are electrically connected to each other, the first conductive line CL1 to the fourth conductive line CL4 can be electrically connected to each other even if the first conductive line CL1 to the fourth conductive line CL4 are respectively electrically connected to different separators SEP. The separators SEP are connected to each other to function as a single electrical path, and thus can function as an electrical path that bypasses the opening area OA in the intermediate area MA, and the electrical resistance thereof can be reduced.

[0151] In one or more embodiments, the first conductive line CL1 to the fourth conductive line CL4 can be voltage lines. For example, at least one of the first conductive line CL1 to the fourth conductive line CL4 can be a sustain voltage line VSSL (see Figure 10 ) for supplying a common voltage ELVSS (see Figure 4 ) to a counter electrode (cathode) of a light emitting diode LED (see Figure 4 ). Using the structure of the separators SEP that form the single electrical path described above, when the sustain voltage line VSSL (see Figure 4 ) is arranged to supply the common voltage ELVSS (see Figure 4 ) to the light emitting diode LED (see Figure 4 ), the electrical resistance acting within the sustain voltage line VSSL (see Figure 4 ) can be reduced compared to when the sustain voltage line VSSL (see Figure 4 ) is arranged to bypass the intermediate area MA and the opening area OA at the same time or substantially at the same time. However, one or more embodiments are not limited to the case in which the first conductive line CL1 to the fourth conductive line CL4 are voltage lines.

[0152] Hereinafter, various embodiments in which the third conductive line CL3 is connected to the separators SEP and in which each of the separators SEP is electrically connected to each other are described with reference to Figure 4 . Although the case of the third conductive line CL3 is mainly described below, this is for convenience of description, and the structures of the embodiments described below can be similarly applied to the first conductive line CL1, the second conductive line CL2, and the fourth conductive line CL4.

[0153] Figure 11 to Figure 18 is a cross-sectional view taken along the line X-X' of the structure according to one or more embodiments Figure 11is an example of a cross-sectional view of a portion of the display panel 2 according to one or more embodiments.

[0154] In features of the corresponding embodiments, features other than those described below can be substantially identical to the corresponding features of the embodiments described above with respect to Figure 10 In features of the corresponding embodiments, features other than those described below can be substantially identical to the corresponding features of the embodiments described above with respect to Figure 11 In features of the corresponding embodiments, features other than those described below can be substantially identical to the corresponding features of the embodiments described above with respect to

[0155] Referring to Figure 7 The cover layer 122 can be located on the organic pattern layer 108 and the conductive pattern layer CP, and can be integrally formed. Thus, the cover layer 122 can be entirely over the organic pattern layer 108 and the conductive pattern layer CP. For example, the cover layer 122 can continuously extend to cover an upper surface of the conductive pattern layer CP, cover side surfaces and a lower surface of the tip CP-T of the conductive pattern layer CP, and cover or define a portion of the first groove 108G1 (e.g., cover a portion of the organic pattern layer 108 in the first groove 108G1). Thus, the cover layer 122 can cover the side surfaces and the upper surface of the organic pattern layer 108 in which the first groove 108G1 is formed. Because the cover layer 122 covers the first groove 108G1, the second portion 123f-2 of the functional layer 123f and the second portion 125-2 of the counter electrode 125 can be spaced apart from the side surfaces of the organic pattern layer 108 in which the first groove 108G1 is formed.

[0156] The cover layer 122 and the conductive pattern layer CP can include a conductive material. Thus, two tips CP-T of the conductive pattern layer CP (e.g., in a plan view) that are spaced apart from each other and between which the first groove 108G1 is located can be electrically connected to each other by the cover layer 122. Because the cover layer 122 continuously extends, each of the portions of the conductive pattern layer CP that are arranged apart from each other can all be electrically connected to each other. Thus, each of the separators SEP can be electrically connected to each other, and can form a single electrical path.

[0157] The third conductive line CL3 can be located on the first organic insulating layer 1071. In one or more embodiments, the third conductive line CL3 and the conductive pattern layer CP can include the same material. In one or more embodiments, the third conductive line CL3 and the conductive pattern layer CP can be integrally formed. Thus, the third conductive line CL3, the conductive pattern layer CP, and the cover layer 122 can be electrically connected to each other.

[0158] Figure 11 is an example of a cross-sectional view of a portion of the display panel 2 according to one or more embodiments. Figure 12 is an example of a cross-sectional view of a portion of the display panel 2 according to one or more embodiments.

[0159] In features of the corresponding embodiments, features other than those described below can be substantially identical to the corresponding features of the embodiments described above with respect to Figure 10 In features of the corresponding embodiments, features other than those described below can be substantially identical to the corresponding features of the embodiments described above with respect toFigure 12 The embodiments are basically the same.

[0160] Reference Figure 11 , the third conductive line CL3 may be located on the inorganic insulating layer 111L. For example, the third conductive line CL3 may be located between the first organic insulating layer 1071 and the inorganic insulating layer 111L. A portion of the third conductive line CL3 may overlap with the second groove 108G2 of the organic pattern layer 108. In one or more embodiments, the third conductive line CL3 may directly contact a portion of the conductive pattern layer CP arranged in the second groove 108G2. For example, the upper surface of the third conductive line CL3 and the lower surface of the conductive pattern layer CP may directly contact each other. Therefore, the third conductive line CL3, the conductive pattern layer CP, and the cover layer 122 may be electrically connected to each other.

[0161] In one or more embodiments, the third conductive line CL3 may be connected to the source electrode SE (see Figure 12 ) and / or drain electrode DE (see Figure 5 ) include the same material. In one or more embodiments, the third conductive line CL3 may be connected to the source electrode SE (see Figure 5 ) and / or drain electrode DE (see Figure 5 ) are formed simultaneously or substantially simultaneously.

[0162] Figure 5 is taken along line XX' according to one or more embodiments Figure 13 FIG. 1 is an example of a cross-sectional view of a portion of the display panel 2 .

[0163] In with Figure 10 Among the features of the corresponding embodiment, the features other than those described below are the same as those of the corresponding embodiment. Figure 13 The embodiments are basically the same.

[0164] Reference Figure 11 , the third conductive line CL3 may be arranged within the inorganic insulating layer 111L. For example, a portion of the inorganic insulating layer 111L may be between the third conductive line CL3 and the conductive pattern layer CP or between the third conductive line CL3 and the first organic insulating layer 1071. In other words, the upper surface of the third conductive line CL3 may be spaced apart from the lower surface of the first organic insulating layer 1071. The third conductive line CL3 may overlap with the second groove 108G2 of the organic pattern layer 108. In the area overlapping with the second groove 108G2 of the organic pattern layer 108, the inorganic insulating layer 111L between the third conductive line CL3 and the conductive pattern layer CP may include a contact hole. The third conductive line CL3 and the conductive pattern layer CP may be in direct contact with each other through the contact hole. Through this, the third conductive line CL3, the conductive pattern layer CP, and the cover layer 122 may be electrically connected to each other.

[0165] In one or more embodiments, the third conductive line CL3 can include the same material as the gate electrode GE (see Figure 13 In one or more embodiments, the third conductive line CL3 can be formed at the same time or substantially at the same time as the gate electrode GE (see Figure 5

[0166] Figure 5 is an example of a cross-sectional view of a portion of the display panel 2 taken along the line X-X' according to one or more embodiments. Figure 14 is an example of a cross-sectional view of a portion of the display panel 2 taken along the line X-X' according to one or more embodiments. Figure 10 is an enlarged cross-sectional view illustrating the region XIV of Figure 15

[0167] Referring to Figure 14 and Figure 14 together, the second portion 125-2 of the counter electrode 125 can be in direct contact with the tip CP-T of the conductive pattern layer CP. As shown in Figure 15 , the tip CP-T of the conductive pattern layer CP can include an upper surface CP-T-1, a side surface CP-T-2, and a lower surface CP-T-3. The upper surface CP-T-1 and the side surface CP-T-2 of the tip CP-T of the conductive pattern layer CP can be covered with the first portion 122-1 of the cover layer 122. The second portion 125-2 of the counter electrode 125 can be in direct contact with the lower surface CP-T-3 of the tip CP-T of the conductive pattern layer CP. For example, the second portion 125-2 of the counter electrode 125 can include a contact portion CNT in contact with the lower surface CP-T-3 of the tip CP-T of the conductive pattern layer CP. A portion of the lower surface CP-T-3 of the tip CP-T other than the portion in contact with the contact portion CNT can be covered with the first inorganic encapsulation layer 131.

[0168] In this case, the first groove 108G1 can include a side surface 108G1-1 and a lower surface 108G1-2. The lower surface 108G1-2 of the first groove 108G1 can be covered with the second portion 122-2 of the cover layer 122. A portion of the side surface 108G1-1 of the first groove 108G1 can be covered with the second portion 122-2 of the cover layer 122. Another portion of the side surface 108G1-1 of the first groove 108G1 can be covered with the second portion 125-2 of the counter electrode 125. In other words, the side surface 108G1-1 of the first groove 108G1 can be completely covered with the second portion 122-2 of the cover layer 122 and the second portion 125-2 of the counter electrode 125. The second portion 123f-2 of the functional layer 123f can be spaced apart from the side surface 108G1-1 of the first groove 108G1.

[0169] ​​The counter electrode 125 may include a conductive material. Because the second portion 125-2 of the counter electrode 125 contacts the tip CP-T of the conductive pattern layer CP, the tips CP-T of the conductive pattern layer CP that are spaced apart from each other and between which the first groove 108G1 is located can be electrically connected to each other. Therefore, the spaced-apart portions of the conductive pattern layer CP can be electrically connected to each other. The conductive pattern layer CP can form a single electrical path through the second portion 125-2 of the counter electrode 125 that electrically connects the tips CP-T to each other. Therefore, each of the separators SEP can form a single electrical path.

[0170] The third conductive line CL3 may be located on the inorganic insulating layer 111L. For example, the third conductive line CL3 may be located between the first organic insulating layer 1071 and the inorganic insulating layer 111L. A portion of the third conductive line CL3 may overlap the second groove 108G2 of the organic pattern layer 108. In one or more embodiments, the third conductive line CL3 may directly contact a portion of the conductive pattern layer CP disposed in the second groove 108G2. For example, the upper surface of the third conductive line CL3 and the lower surface of the conductive pattern layer CP may directly contact each other. Therefore, the third conductive line CL3, the conductive pattern layer CP, and the second portion 125-2 of the counter electrode 125 may be electrically connected to each other.

[0171] In one or more embodiments, the third conductive line CL3 may be connected to the source electrode SE (see Figure 15 ) and / or drain electrode DE (see Figure 5 ) include the same material. In one or more embodiments, the third conductive line CL3 may be connected to the source electrode SE (see Figure 5 ) and / or drain electrode DE (see Figure 5 ) are formed simultaneously or substantially simultaneously.

[0172] Figure 5 is taken along line XX' according to one or more embodiments Figure 16 FIG. 1 is an example of a cross-sectional view of a portion of the display panel 2 . Figure 10 It shows Figure 17 An enlarged cross-sectional view of region XVI.

[0173] Refer to it together Figure 16 and Figure 16 , the organic pattern layer 108 may not include the second groove and may include only the first groove 108G1. In one or more embodiments, the first groove 108G1 may pass through the organic pattern layer 108. In one or more embodiments, the second portion 122-2 of the capping layer 122 may directly contact the upper surface of the inorganic insulating layer 11L.

[0174] The second portion 125-2 of the counter electrode 125 can directly contact the tip CP-T of the conductive pattern layer CP. Accordingly, the conductive pattern layer CP can form a single electrical path through the second portion 125-2 of the counter electrode 125. The structure in which the conductive pattern layer CP forms a single electrical path is substantially the same as the structure described above with reference to Figure 17 and Figure 14 .

[0175] The third conductive line CL3 can be located on the inorganic insulating layer IIL. For example, the third conductive line CL3 can be located between the first organic insulating layer 1071 and the inorganic insulating layer IIL. The third conductive line CL3 can directly contact the conductive pattern layer CP through a contact hole defined in the first organic insulating layer 1071 (or the organic pattern layer 108). Accordingly, the third conductive line CL3, the conductive pattern layer CP, and the second portion 125-2 of the counter electrode 125 can be electrically connected to each other.

[0176] In one or more embodiments, the third conductive line CL3 can include the same material as the source electrode SE (see Figure 15 ) and / or the drain electrode DE (see Figure 5 ). In one or more embodiments, the third conductive line CL3 can be formed simultaneously or substantially simultaneously with the source electrode SE (see Figure 5 ) and / or the drain electrode DE (see Figure 5 ).

[0177] Figure 5 is an example of a cross-sectional view of a portion of the display panel 2 of Figure 18 along the line X-X' according to one or more embodiments.

[0178] With reference to Figure 10 , the organic pattern layer 108 can not include the second recess, and can include the first recess 108G1. In one or more embodiments, the first recess 108G1 can pass through the organic pattern layer 108.

[0179] The cover layer 122 can be located on the organic pattern layer 108, and the cover layer 122 can be integrally formed. Thus, the cover layer 122 can completely cover the organic pattern layer 108 and the conductive pattern layer CP. For example, the cover layer 122 can continuously extend to cover the upper surface of the conductive pattern layer CP, the side surface and the lower surface of the tip CP-T of the conductive pattern layer CP, and the first groove 108G1. Thus, the cover layer 122 can cover the side surface and the upper surface of the portion of the organic pattern layer 108 in which the first groove 108G1 is formed. Because the cover layer 122 covers the first groove 108G1, the second portion 123f-2 of the functional layer 123f and the second portion 125-2 of the counter electrode 125 can be spaced apart from the side surface of the portion of the organic pattern layer 108 in which the first groove 108G1 is formed. In one or more embodiments, the cover layer 122 can be in direct contact with the upper surface of the inorganic insulating layer IIL within the first groove 108G1.

[0180] The cover layer 122 and the conductive pattern layer CP can include a conductive material. Thus, the tips CP-T of the conductive pattern layer CP that are spaced apart from each other and between which the first groove 108G1 is located can be electrically connected to each other by the cover layer 122. Because the cover layer 122 continuously extends, each of the portions of the conductive pattern layer CP that are arranged to be spaced apart from each other can all be electrically connected to each other. Thus, each of the separators SEP can be electrically connected to each other, and a single electrical path can be formed.

[0181] The third conductive line CL3 can be located on the inorganic insulating layer IIL. For example, the third conductive line CL3 can be located between the first organic insulating layer 1071 and the inorganic insulating layer IIL. The third conductive line CL3 can be in direct contact with the conductive pattern layer CP through a contact hole defined in the first organic insulating layer 1071 (or the organic pattern layer 108). Thus, the third conductive line CL3, the conductive pattern layer CP, and the cover layer 122 can be electrically connected to each other.

[0182] In one or more embodiments, the third conductive line CL3 can include the same material as the source electrode SE (see Figure 18 ) and / or the drain electrode DE (see Figure 5 ). In one or more embodiments, the third conductive line CL3 can be formed simultaneously or substantially simultaneously with the source electrode SE (see Figure 5 ) and / or the drain electrode DE (see Figure 5 ).

[0183] Figure 5 is a cross-sectional view illustrating a portion of the display panel 2 according to one or more embodiments.

[0184] Figure 19 is a cross-sectional view illustrating the entire middle area MA. Reference is made toFigure 19 The display area DA is shown on the left side of the middle area MA, and the opening area OA is shown on the right side of the middle area MA. The first dam DM1, the second dam DM2, and the third dam DM3 can be arranged in order from left to right, or in order from the display area DA toward the opening area OA. The plurality of separators SEP can be arranged on the left side of the first dam DM1, between the first dam DM1 and the second dam DM2, between the second dam DM2 and the third dam DM3, and on the right side of the third dam DM3. For ease of description, the separators SEP on the left side of the first dam DM1 can include the organic pattern layer 108 and the conductive pattern layer CP, the separators SEP between the first dam DM1 and the second dam DM2 can include the first organic pattern layer 1081 and the first conductive pattern layer CP1, the separators SEP between the second dam DM2 and the third dam DM3 can include the second organic pattern layer 1082 and the second conductive pattern layer CP2, and the separators SEP on the right side of the third dam DM3 can include the third organic pattern layer 1083 and the third conductive pattern layer CP3.

[0185] The first dam DM1 can include a first layer 1071D1, a second layer 1072D1, and a third layer 109D1. The second dam DM2 can include a first layer 1071D2 and a second layer 109D2. The third dam DM3 can include a first layer 1071D3 and a second layer 109D3.

[0186] The first layer 1071D1 of the first dam DM1, the first layer 1071D2 of the second dam DM2, and the first layer 1071D3 of the third dam DM3 can include the same material as the first organic insulating layer 1071, the organic pattern layer 108, the first organic pattern layer 1081, the second organic pattern layer 1082, and the third organic pattern layer 1083. In one or more embodiments, the first organic insulating layer 1071, the organic pattern layer 108, the first layer 1071D1 of the first dam DM1, the first organic pattern layer 1081, the first layer 1071D2 of the second dam DM2, the second organic pattern layer 1082, the first layer 1071D3 of the third dam DM3, and the third organic pattern layer 1083 can be formed simultaneously or substantially simultaneously.

[0187] The second layer 1072D1 of the first dam DM1 can include the same material as the second organic insulating layer 1072 (see Figure 19 ). In one or more embodiments, the second layer 1072D1 of the first dam DM1 and the second organic insulating layer 1072 (see Figure 5 ) can be formed simultaneously or substantially simultaneously.

[0188] The third layer 109D1 of the first dam DM1, the second layer 109D2 of the second dam DM2, and the second layer 109D3 of the third dam DM3 can include the same material as the pixel definition layer 109 (seeFigure 5 ) include the same material. In one or more embodiments, the pixel definition layer 109 (see Figure 5 ) can be formed simultaneously or substantially simultaneously with the third layer 109D1 of the first dam DM1, the second layer 109D2 of the second dam DM2, and the second layer 109D3 of the third dam DM3.

[0189] The conductive pattern layer CP, the first conductive pattern layer CP1, the second conductive pattern layer CP2, and the third conductive pattern layer CP3 can include the same material as each other. In one or more embodiments, the conductive pattern layer CP, the first conductive pattern layer CP1, the second conductive pattern layer CP2, and the third conductive pattern layer CP3 can be formed simultaneously or substantially simultaneously. Referring to Figure 5 The connection structure of the conductive lines described above can be formed in the conductive pattern layer CP. However, one or more embodiments are not limited thereto, and the connection structure can be formed in one or more layers among the first conductive pattern layer CP1, the second conductive pattern layer CP2, and the third conductive pattern layer CP3.

[0190] In one or more embodiments, the cover layer 122 can be located on the separator SEP and can integrally extend within the middle area MA. In this case, the conductive pattern layer CP, the first conductive pattern layer CP1, the second conductive pattern layer CP2, and the third conductive pattern layer CP3 can all be electrically connected to each other and can form a single electrical path within the middle area MA. In this case, referring to Figure 6 to Figure 18 The connection structure of the conductive lines described above can be available.

[0191] In one or more other embodiments, each of the portions of the conductive pattern layer CP, the first conductive pattern layer CP1, the second conductive pattern layer CP2, and the third conductive pattern layer CP3 can be spaced apart from each other and can form separate electrical paths. In this case, the conductive lines described above can be selectively connected to one of the portions among each of the portions of the conductive pattern layer CP, the first conductive pattern layer CP1, the second conductive pattern layer CP2, and the third conductive pattern layer CP3. In this case, referring to Figure 10 to Figure 18 Figure 6 to Figure 9 The connection structure of the conductive lines described above can be available.

[0192] According to one or more embodiments, the conductive pattern layer of the separator around the opening area of the display panel can be used for the connection line, so that the length of the line that bypasses the opening area can be reduced. Furthermore, as the length of the line is reduced, the electrical resistance of the line can also be reduced. However, these aspects are merely examples, and the scope of one or more embodiments is not limited thereby.

[0193] It is to be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope as defined by the following claims and the equivalents thereof.

Claims

1. A display panel, comprising: a substrate including a display area, an opening area within the display area, and an intermediate area between the opening area and the display area; a light emitting diode in the display area and including a sub-pixel electrode, a counter electrode over the sub-pixel electrode, and an intermediate layer between the sub-pixel electrode and the counter electrode; an organic pattern layer over the substrate in the intermediate area and defining a first recess and a second recess; a conductive pattern layer in the second recess and including a tip having an end projecting toward a center of the first recess in a plan view; and a wire electrically connected to the conductive pattern layer and passing through the display area. 2.The display panel of claim 1, further comprising a cover layer over the conductive pattern layer and including a conductive material.

3. The display panel of claim 2, wherein, The cover layer includes a first portion over an upper surface of the conductive pattern layer and a second portion in the first recess and separated from the first portion.

4. The display panel of claim 3, wherein, The first portion at least partially covers the tip of the conductive pattern layer.

5. The display panel of claim 2, wherein, The cover layer continuously extends along an upper surface of the conductive pattern layer, side and lower surfaces of the tip, and side and upper surfaces of a portion of the organic pattern layer in which the first recess is formed.

6. The display panel of claim 2, wherein, The cover layer and the sub-pixel electrode include the same material.

7. The display panel of claim 1, wherein, The wire is integral with the conductive pattern layer.

8. The display panel of claim 1, wherein, The wire is under the conductive pattern layer and contacts the conductive pattern layer in a region in which the wire overlaps the second recess.

9. The display panel of claim 8, wherein, An insulating layer is between the conductive pattern layer and the wire, and wherein the wire is electrically connected to the conductive pattern layer through a contact hole in the insulating layer.

10. The display panel of claim 1, wherein, The wire includes a scan line, a data line, or a voltage line.

11. The display panel of claim 1, wherein, The conductive pattern layer surrounds the opening area in a plan view.

12. The display panel of claim 1, wherein, The counter electrode of the light emitting diode extends toward the intermediate area and includes a first portion and a second portion separated from each other with respect to the tip, the second portion being in the first recess and directly contacting the tip of the conductive pattern layer. 13.A display panel, comprising: a substrate including a first area, a second area at least partially surrounding the first area, and a third area between the first area and the second area; a light emitting diode in the second area and including a sub-pixel electrode, a counter electrode over the sub-pixel electrode, and an intermediate layer between the sub-pixel electrode and the counter electrode; a partition in the third area; a cover layer over the partition and including a conductive material; and a wire passing through the second area, wherein the partition includes an organic pattern layer over the substrate and defining a recess, and a conductive pattern layer electrically connected to the wire, over an upper surface of the organic pattern layer, and including a tip extending toward a center of the recess in a plan view and having at least a portion covered by the cover layer. ​ 14. The display panel of claim 13, wherein, The cover layer includes a first portion over the conductive pattern layer and a second portion in the recess and separate from the first portion.

15. The display panel of claim 13, wherein, The cover layer continuously extends by completely covering the portions of the conductive pattern layer and the organic pattern layer where the recess is formed.

16. The display panel of claim 13, wherein, The cover layer and the sub-pixel electrode include the same material.

17. The display panel of claim 13, wherein, The line is integral with the conductive pattern layer.

18. The display panel of claim 13, wherein, The line is between the substrate and the conductive pattern layer and contacts the conductive pattern layer.

19. The display panel of claim 18, wherein, An insulating layer is between the conductive pattern layer and the line, and wherein the line is electrically connected to the conductive pattern layer through a contact hole in the insulating layer.

20. The display panel of claim 13, wherein, The line includes a scan line, a data line, or a voltage line.

21. The display panel of claim 13, wherein, The divider surrounds the first area in plan view.

22. The display panel of claim 13, further comprising an electrode layer including a first portion over an upper surface of the conductive pattern layer and a second portion in the recess and separate from the first portion.

23. The display panel of claim 22, wherein, The electrode layer is over the cover layer.

24. The display panel of claim 22, wherein, The second portion of the electrode layer directly contacts the tip of the conductive pattern layer.

25. The display panel of claim 22, wherein, The electrode layer and the counter electrode include the same material.

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