SOT-MTJ device preparation method and SOT-MTJ device
By doping and annealing the free layer of SOT-MTJ devices, combined with self-aligned etching, the problem of writing uncertainty in the absence of an external magnetic field was solved, achieving deterministic writing with pure electronic control and high-yield production.
Patent Information
- Application Number
- CN202410476878.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-19
- Publication Date
- 2025-10-24
AI Technical Summary
Existing SOT-MTJ devices are difficult to achieve deterministic writing in the absence of an external magnetic field. The introduction of an external magnetic field increases writing power consumption and is not conducive to the design of high-density storage cells.
By doping the free layer and performing rapid thermal annealing or laser annealing in the SOT-MTJ device, the symmetry perpendicular to the write current direction is broken, generating an equivalent magnetic field to achieve deterministic writing without an external magnetic field. A self-aligned etching process is used to avoid short-circuit problems caused by metal deposition on the sidewalls of the barrier layer.
This enables deterministic writing under conditions without an external magnetic field, reduces writing power consumption, and improves device yield.
Smart Images
Figure CN120835733A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of magnetic memory, in particular to a preparation method of SOT-MTJ device and SOT-MTJ device. BACKGROUND
[0002] Spin-orbit torque magnetic tunnel junction (SOT-MTJ) as a new MTJ device is the core unit of the new generation of magnetic random storage technology. SOT-MTJ device mainly uses the spin-polarized current generated by the SOT orbit layer of heavy metal to flip the magnetic moment of the free layer to realize the writing of data. Compared with the spin transfer torque magnetic tunnel junction (STT-MTJ) device, the SOT-MTJ device has the characteristics of fast writing speed, unlimited times of erasing and writing, and separation of reading and writing.
[0003] The deterministic writing of SOT-MTJ device is one of the main difficulties of current industrialization. Limited by the writing mechanism of SOT-MTJ device, for SOT-MTJ device with perpendicular magnetic anisotropy, external magnetic field is needed to assist to realize deterministic writing. The introduction of external magnetic field not only increases the writing power consumption, but also is not conducive to the design of high-density storage unit, so how to realize deterministic writing without external magnetic field is still an important technical challenge for SOT-MTJ device. SUMMARY
[0004] In order to solve the above problems, the present application provides a preparation method of SOT-MTJ device and SOT-MTJ device, which can realize deterministic writing without external magnetic field.
[0005] In the first aspect, the present application provides a preparation method of SOT-MTJ device, comprising:
[0006] Depositing each layer film for forming pinning layer, reference layer, barrier layer, free layer, SOT orbit layer and buffer layer on the substrate in sequence;
[0007] Using the same photoetching pattern to etch each layer film to obtain a laminated structure, the laminated structure comprising pinning layer, reference layer, barrier layer, free layer, SOT orbit layer and buffer layer stacked from bottom to top in sequence;
[0008] Forming a covering layer on the side wall and the upper surface of the laminated structure;
[0009] Depositing insulating medium and planarizing treatment, so that the part of the covering layer on the upper surface of the laminated structure is completely exposed;
[0010] forming a processing window on the exposed covering layer by a photoetching process with photoresist as a barrier layer, the processing window having a size smaller than the overall size of the upper surface of the layer stack;
[0011] doping the free layer through the processing window and then performing a rapid thermal annealing process on the layer stack, or performing a laser annealing process on the layer stack through the processing window.
[0012] Optionally, the doping of the free layer through the processing window comprises:
[0013] The doping of the free layer is performed by ion implantation.
[0014] Optionally, the implanted ions include any one of N, B, Ga and As.
[0015] Optionally, the buffer layer is made of a high-resistivity conductive material having a resistivity greater than 10 times the resistivity of the SOT orbit layer.
[0016] Optionally, the thickness of the buffer layer and the covering layer is less than 10 nm.
[0017] Optionally, the processing window has any one of a square, triangular, trapezoidal, circular and elliptical shape.
[0018] In a second aspect, the present application provides an SOT-MTJ device, comprising:
[0019] a substrate;
[0020] a layer stack on the substrate, the layer stack comprising, from bottom to top, a pinned layer, a reference layer, a barrier layer, a free layer, an SOT orbit layer and a buffer layer;
[0021] The pinned layer, the reference layer and the free layer have perpendicular magnetic anisotropy.
[0022] The SOT orbit layer is configured to provide a spin-orbit torque.
[0023] The buffer layer is configured to protect the SOT orbit layer and has the functions of etching barrier layer and ion implantation mask layer.
[0024] The free layer is doped and the layer stack is rapidly thermally annealed, or the layer stack is laser annealed, so as to generate an equivalent magnetic field in a direction parallel to the write current, assisting the magnetic moment of the free layer to realize deterministic flipping.
[0025] Optionally, the pinning layer, the reference layer, the barrier layer, the free layer, the SOT track layer and the buffer layer have the same feature size.
[0026] Optionally, the material of the buffer layer is a high-resistivity conductive material, and the resistivity of the material is greater than 10 times the resistivity of the SOT track layer.
[0027] Optionally, the free layer is partially locally doped with any one of ions of N, B, Ga and As.
[0028] The SOT-MTJ device and the preparation method thereof provided by the application can effectively perform doping treatment or laser annealing treatment on the free layer, thereby destroying the symmetry in the direction perpendicular to the write current, and an equivalent magnetic field is generated in the direction parallel to the write current, under the action of the equivalent magnetic field, the magnetic moment of the free layer can realize deterministic flipping without an external magnetic field, and the SOT-MTJ device realizes deterministic writing in a purely electrically controlled manner without an external magnetic field. In addition, the SOT track layer is located above the free layer, the SOT track layer, the free layer, the barrier layer and the reference layer are etched using the same photolithography pattern, which is a self-alignment etching method, can avoid the problem of short circuit caused by metal deposition on the sidewall of the barrier layer, increase the etching process window, and improve the device yield. BRIEF DESCRIPTION OF DRAWINGS
[0029] Figures 1 to 8 The figure is a process flow diagram of the preparation method of the SOT-MTJ device in an embodiment of the application.
[0030] Figure 9 The figure is a top view of the processing window in an embodiment of the application. DETAILED DESCRIPTION
[0031] To make the purpose, technical scheme and advantages of the embodiments of the application clearer, the technical scheme in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application, but it should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present disclosure. Based on the embodiments in the application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of the present application. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessary confusion of the concepts of the present disclosure.
[0032] Various structural diagrams according to embodiments of the present disclosure are shown in the drawings. These diagrams are not drawn to scale, in which certain details are exaggerated for clarity and others omitted. The shapes of various regions, layers, and their relative sizes and positional relationships shown in the drawings are merely exemplary, and in actuality can deviate due to manufacturing tolerances or technical limitations, and regions / layers with different shapes, sizes, and relative positions can be additionally designed according to actual needs by those skilled in the art.
[0033] In the context of the present disclosure, when a layer / element is referred to as being located "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intervening layer / element therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.
[0034] Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features in the embodiments can be combined with each other without conflict.
[0035] The present application first defines a coordinate system, taking the thin film plane of the SOT-MTJ device as the XY plane, and defining the direction of the write current as the X direction, the direction perpendicular to the write current as the Y direction, and the direction perpendicular to the thin film plane as the Z direction.
[0036] An embodiment of the present application provides a preparation method of a SOT-MTJ device, Figures 1 to 8 The flowchart of the preparation method is shown in the form of a cross-sectional view of the XZ plane of the device structure. The specific process flow is as follows:
[0037] As shown in Figure 1 A substrate 100 is provided, which has completed the growth of the front layer circuit pattern and formed the required circuit structure, including a bottom electrode 101.
[0038] As shown in Figure 2 On the substrate 100, thin films for forming the pinning layer, reference layer, barrier layer, free layer, SOT track layer, and buffer layer are sequentially deposited. Figure 2 Among them, 1021 represents the pinning layer thin film, 1031 represents the reference layer thin film, 1041 represents the barrier layer thin film, 1051 represents the free layer thin film, 1061 represents the SOT track layer thin film, and 1071 represents the buffer layer thin film.
[0039] As shown in Figure 3As shown, the above-mentioned layers of thin films, i.e. the pinned layer thin film 1021, the reference layer thin film 1031, the barrier layer thin film 1041, the free layer thin film 1051, the SOT orbit layer thin film 1061 and the buffer layer thin film 1071, are etched using the same lithography pattern to obtain a layer stack structure, which comprises the pinned layer 102, the reference layer 103, the barrier layer 104, the free layer 105, the SOT orbit layer 106 and the buffer layer 107 stacked in order from bottom to top. In this embodiment, since the layers of thin films are etched using the same lithography pattern, the pinned layer 102, the reference layer 103, the barrier layer 104, the free layer 105, the SOT orbit layer 106 and the buffer layer 107 have the same feature size. This is a self-aligned etching method, which can avoid the problem of short circuit caused by metal deposition on the sidewall of the barrier layer 104, increase the etching process window and improve the device yield.
[0040] After obtaining the above-mentioned layer stack structure, a capping layer 108 is formed on the sidewall and the upper surface of the layer stack structure.
[0041] As shown in FIG. 1C, an insulating medium is deposited and planarized to expose the part of the capping layer 108 on the upper surface of the layer stack structure. Figure 4
[0042] As shown in FIG. 1D, a processing window is formed on the exposed capping layer 108 by a lithography process using the photoresist 109 as a barrier layer. The size of the processing window is smaller than the overall size of the upper surface of the layer stack structure. The processing window serves as an operation area for subsequent doping treatment or laser annealing treatment. A layer of photoresist is first spin-coated, and the photoresist is exposed and developed to obtain the processing window. Figure 5
[0043] As shown in FIG. 1E, the free layer 105 is first subjected to doping treatment using the above-mentioned processing window, and then the entire layer stack structure is subjected to rapid thermal annealing treatment; or, the entire layer stack structure is directly subjected to laser annealing treatment using the above-mentioned processing window. It is explained here that, when laser annealing treatment is performed, the free layer does not need to be doped. Figure 6 As an implementation manner, the free layer 105 is subjected to doping treatment by ion implantation. The implanted ions include but are not limited to any one of the following ions: N, B, Ga and As.
[0044] It can be understood that the implanted ions are only distributed in part of the free layer 105, so as to generate an equivalent magnetic field in the direction parallel to the write current, which can assist the magnetic moment of the free layer 105 to realize deterministic flipping when the SOT orbit layer 106 flows through the write current.
[0045]
[0046] This application does not limit the specific working conditions of ion implantation and laser annealing, as long as the free layer meets the requirements after treatment. When ion implantation is performed on the free layer, the ion implantation position is controlled by controlling the energy of the ion implantation, and then the stacked structure is subjected to rapid thermal annealing.
[0047] When laser annealing is performed on a stacked structure, the annealing position is controlled by controlling the energy of the laser annealing.
[0048] It should also be noted that in this embodiment, the buffer layer 107 serves the following functions: it acts as an etch stop, protects the SOT track layer from oxidation, and serves as an ion implantation mask. The buffer layer 107 can be made of a high-resistivity conductive material, such as tantalum nitride (TaN). The resistivity of the buffer layer 107 is generally required to be greater than 10 times that of the SOT track layer 106. This ensures that the write current flowing through the SOT track layer 106 is not shunted by the buffer layer 107.
[0049] In order to facilitate ion implantation, its thickness needs to be controlled within 10 nm. In addition, the thickness of the cover layer 108 should also be as thin as possible, preferably controlled within 10 nm.
[0050] like Figure 7 As shown, after the free layer 105 is doped / the stacked structure is subjected to rapid thermal annealing or the stacked structure is subjected to laser annealing, the photoresist is removed, an insulating dielectric is deposited, and the structure is planarized.
[0051] like Figure 8 As shown, a back-end process is performed to form two top electrodes 110 .
[0052] Further, corresponding to Figure 5 , Figure 9 FIG. 4 shows a top view of the XY plane after the processing window is formed. Figure 9 As shown, the shape of the processing window is a rectangle, but it is not limited thereto. The shape of the processing window can be any shape, including square, triangle, trapezoid, circle, and ellipse.
[0053] The preparation method of the SOT-MTJ device provided by the embodiment of the present application can prepare a bottom-pinned SOT-MTJ device. Since the free layer is close to the top of the device, the free layer can be effectively doped and then subjected to rapid thermal annealing or laser annealing, so that the symmetry of the free layer along the direction (Y direction) perpendicular to the direction (X direction) of the write current is destroyed, which is equivalent to generating an equivalent magnetic field in the direction parallel to the write current. Under the action of the equivalent magnetic field, the magnetic moment of the free layer can realize deterministic flipping without an external magnetic field, so that the SOT-MTJ device realizes deterministic writing in a purely electrically controlled manner without an external magnetic field. In addition, the SOT track layer is located above the free layer, and the SOT track layer, the free layer, the barrier layer and the reference layer are etched using the same photolithography pattern, which is a self-alignment etching method, can avoid the problem of short circuit caused by metal deposition on the sidewall of the barrier layer, increase the etching process window, and improve the device yield.
[0054] In another aspect, an embodiment of the present application provides a SOT-MTJ device, and the structure of the SOT-MTJ device can refer to Figure 8 As shown in Figure 8 The SOT-MTJ device comprises:
[0055] a substrate 100, which has completed the growth of a front layer circuit pattern and formed a required circuit structure, including a bottom electrode 101;
[0056] a stacked structure on the substrate 100, which comprises a pinning layer 102, a reference layer 103, a barrier layer 104, a free layer 105, a SOT track layer 106 and a buffer layer 107 stacked in order from bottom to top;
[0057] The pinning layer 102, the reference layer 103 and the free layer 105 have perpendicular magnetic anisotropy;
[0058] The SOT track layer 106 is used to provide a spin-orbit torque;
[0059] The buffer layer 107 is used to protect the SOT track layer and has the functions of etching stop layer and ion implantation mask layer;
[0060] The free layer 105 is subjected to doping treatment and the stacked structure is subjected to rapid thermal annealing, or the stacked structure is subjected to laser annealing, so that an equivalent magnetic field is generated in the direction parallel to the write current, which assists the magnetic moment of the free layer 105 to realize deterministic flipping.
[0061] In one embodiment, the cross-sectional shape of the laminated structure of the pinning layer 102, the reference layer 103, the barrier layer 104, the free layer 105, the SOT orbit layer 106 and the buffer layer 107 in the XY plane can be any shape, and a typical design scheme is that the cross-section of the laminated structure is a long strip shape, the MTJ size is 300nm*60nm, the long axis of the MTJ is along the direction of the write current (X direction), and the magnetization direction of the MTJ is along the direction perpendicular to the film plane (Z direction).
[0062] In one embodiment, the pinning layer 102, the reference layer 103, the barrier layer 104, the free layer 105, the SOT orbit layer 106 and the buffer layer 107 have the same feature size.
[0063] In one embodiment, the material of the buffer layer 107 is a high resistivity conductive material, and the resistivity is greater than 10 times the resistivity of the SOT orbit layer 106. The thickness of the buffer layer 107 and the cover layer 108 is less than 10nm.
[0064] In one embodiment, part of the free layer 105 is locally doped with any one of N, B, Ga and As ions.
[0065] It can be understood that the SOT-MTJ device provided by the embodiment of the present application is obtained based on the foregoing preparation method and has the same technical effect.
[0066] In the above description, the patterning, etching and other technical details of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions and the like with the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.
[0067] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any changes or replacements within the technical range disclosed by the present application can be easily thought of by those skilled in the art, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A method for preparing a SOT-MTJ device, characterized in that: The method comprises: sequentially depositing each thin film for forming a pinning layer, a reference layer, a barrier layer, a free layer, an SOT track layer and a buffer layer on a substrate; etching the each thin film using the same photoetching pattern to obtain a laminated structure, the laminated structure comprising the pinning layer, the reference layer, the barrier layer, the free layer, the SOT track layer and the buffer layer sequentially laminated from bottom to top; forming a covering layer on the side wall and the upper surface of the laminated structure; depositing an insulating medium and performing a planarization treatment so that the covering layer is completely exposed on the part of the upper surface of the laminated structure; forming a processing window on the exposed covering layer by a photoetching process using photoresist as a barrier layer, the processing window having a size smaller than the overall size of the upper surface of the laminated structure; performing a doping treatment on the free layer using the processing window, and then performing a rapid thermal annealing treatment on the laminated structure, or performing a laser annealing treatment on the laminated structure using the processing window.
2. The method of claim 1, wherein, The doping treatment on the free layer using the processing window comprises: performing a doping treatment on the free layer by ion implantation.
3. The method of claim 2, wherein, The implanted ions include any one of N, B, Ga and As.
4. The method of claim 1, wherein, The material of the buffer layer is a high-resistivity conductive material, and the resistivity of the material is greater than 10 times the resistivity of the SOT track layer.
5. The method of claim 1, wherein, The thickness of the buffer layer and the covering layer is less than 10 nm.
6. The method of claim 1, wherein, The processing window has any one of a square, triangular, trapezoidal, circular and elliptical shape.
7. An SOT-MTJ device, comprising: Comprise: a substrate; a laminated structure on the substrate, the laminated structure comprising a pinning layer, a reference layer, a barrier layer, a free layer, an SOT track layer and a buffer layer sequentially laminated from bottom to top; wherein the pinning layer, the reference layer and the free layer have perpendicular magnetic anisotropy; the SOT track layer is used to provide a spin-orbit torque; the buffer layer is used to protect the SOT track layer and has the functions of an etching barrier layer and an ion implantation mask layer; the free layer is subjected to a doping treatment and the laminated structure is subjected to a rapid thermal annealing treatment, or the laminated structure is subjected to a laser annealing treatment, so that an equivalent magnetic field is generated in a direction parallel to a write current to assist the magnetic moment of the free layer to realize a deterministic flip.
8. The SOT-MTJ device of claim 7, wherein, The pinning layer, the reference layer, the barrier layer, the free layer, the SOT track layer and the buffer layer have the same feature size.
9. The SOT-MTJ device of claim 7, wherein, The material of the buffer layer is a high-resistivity conductive material, and the resistivity of the material is greater than 10 times the resistivity of the SOT track layer.
10. The SOT-MTJ device of claim 7, wherein, Part of the free layer is locally doped with any one of N, B, Ga and As.