Memory device, memory system and operating method thereof

Abstract

A method of operating a memory system includes performing a first read operation with a first read voltage of a first single read stage; performing a first shift read operation using the first read voltage plus a first offset voltage; subtracting the first offset voltage from the first read voltage to perform a second shift read operation; and in response to a difference between first bit flipping information of the first shift read operation and second bit flipping information of the second shift read operation being equal to or lower than a threshold value, determining that the first read voltage is a first optimal read voltage. The first single read stage of a first page is under a multi-stage architecture.

Description

BACKGROUND

[0001] The disclosure relates to a memory device, a memory system, and an operating method thereof.

[0002] In a non-volatile memory device, as a multiple-bit-per-cell storage architecture emerges and becomes more popular within the industry, a read margin becomes narrower, and thus the memory device is more susceptible to noise, program / read disturbance, coupling issues, charge loss, etc. Accordingly, more read errors occur during a read operation. Therefore, several solutions are introduced to minimize the raw bit error rate (RBER) of a memory cell. SUMMARY

[0003] In one aspect, a method of operating a memory system includes performing a first read operation with a first read voltage of a first single read level, performing a first shifted read operation with the first read voltage plus a first offset voltage, performing a second shifted read operation with the first read voltage minus the first offset voltage, and in response to a difference between first bit flip information of the first shifted read operation and second bit flip information of the second shifted read operation being equal to or below a threshold value, determining that the first read voltage is a first optimal read voltage, the first single read level of a first page is under a multi-level architecture.

[0004] In some embodiments, the method further includes, in response to the difference between the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation being above the threshold value, determining that the first read voltage is not the first optimal read voltage.

[0005] In some embodiments, after determining that the first read voltage is not the first optimal read voltage, the method further includes performing a second read operation with a second read voltage. The second read voltage is determined based on the difference between the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation.

[0006] In some embodiments, determining the second read voltage based on the difference between the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation further includes, in response to the first bit flip information of the first shifted read operation being higher than the second bit flip information of the second shifted read operation, determining the second read voltage to be higher than the first read voltage, and in response to the first bit flip information of the first shifted read operation being lower than the second bit flip information of the second shifted read operation, determining the second read voltage to be lower than the first read voltage.

[0007] In some embodiments, in response to the first bit flip information of the first shift read operation being higher than the second bit flip information of the second shift read operation, the second read voltage is determined as the first read voltage minus half of the first offset voltage; and in response to the first bit flip information of the first shift read operation being lower than the second bit flip information of the second shift read operation, the second read voltage is determined as the first read voltage plus half of the first offset voltage.

[0008] In some embodiments, the first bit flip information of the first shift read operation is determined by a first bit flip count between the first shift read operation and the first read operation, and the second bit flip information of the second shift read operation is determined by a second bit flip count between the second shift read operation and the first read operation.

[0009] In some embodiments, before performing a first read operation with a first read voltage, the method further comprises determining the first single read level.

[0010] In some embodiments, in response to determining that the first read voltage is the first optimal read voltage, the method further comprises determining a second single read level.

[0011] In some embodiments, whether the first read voltage is the first optimal read voltage is further determined based on a threshold voltage normal distribution characteristic.

[0012] In some embodiments, in response to determining all optimal read voltages, the method further comprises performing a normal read operation based on all optimal read voltages.

[0013] In some embodiments, the method further comprises performing a first pre-read operation with a first pre-read voltage and a second pre-read operation with a second pre-read voltage to determine first pre-read bit flip information; determining a first read offset based on the first pre-read bit flip information in the first single read level and a first relationship between bit flip information and read offset; and determining a first optimal read voltage based on the first pre-read voltage and the first read offset.

[0014] In some embodiments, the method further comprises determining a second read voltage based on a second single read level using the first relationship of the first single read level.

[0015] In some embodiments, the method further includes performing a first pre-read operation with a first pre-read voltage and a second pre-read operation with a second pre-read voltage to determine first pre-read bit flip information, determining a first read offset based on the first pre-read bit flip information in the first single read level, determining other read offsets based on the first read offset, and determining the first read voltage based on the first pre-read voltage and the first read offset.

[0016] In some embodiments, the first pre-read voltage and the second pre-read voltage in the first single read level of the first page are under a multi-level architecture.

[0017] In some embodiments, the method further includes performing a first pre-read operation with a first pre-read voltage and a second pre-read operation with a second pre-read voltage to determine first pre-read bit flip information, performing the first pre-read operation with the first pre-read voltage and a third pre-read operation with a third pre-read voltage to determine second pre-read bit flip information, determining a first read offset based on a difference between the first pre-read bit flip information and the second pre-read bit flip information and a first relationship between a difference in bit flip information in the first single read level and a read offset, and determining the first read voltage based on the first pre-read voltage and the first read offset.

[0018] In another aspect, a method for reading an array of memory cells includes determining all optimal read voltages. Determining all optimal read voltages includes performing a first read operation with a first read voltage, performing a first shifted read operation with the first read voltage plus a first offset voltage, performing a second shifted read operation with the first read voltage minus the first offset voltage, and determining whether the first read voltage is a first optimal read voltage based on a comparison between first bit flip information of the first shifted read operation and second bit flip information of the second shifted read operation, and performing a normal read operation based on all optimal read voltages to read out data.

[0019] In some embodiments, the determining all optimal read voltages further includes correcting any errors in data using an error correction code (ECC) algorithm.

[0020] In some embodiments, the method further includes performing a read retry operation.

[0021] In some embodiments, the method further includes performing a firmware initial read operation.

[0022] In some implementations, the method further includes decoding data read from the array of memory cells prior to correcting any errors in the data using an error correction code (ECC) algorithm.

[0023] In yet another aspect, a memory device includes an array of memory cells. The array of memory cells includes memory cells, and a peripheral circuit is coupled to the array of memory cells. The peripheral circuit is configured to: apply a first read voltage to a target memory cell in a first read operation; apply the first read voltage plus a first offset voltage to the target memory cell in a first shifted read operation; apply the first read voltage minus the first offset voltage to the target memory cell in a second shifted read operation; in response to first bit flip information of the first shifted read operation being higher than second bit flip information of the second shifted read operation, apply the first read voltage minus half of the first offset voltage; and in response to the first bit flip information being lower than the second bit flip information, apply the first read voltage plus half of the first offset voltage.

[0024] In some implementations, the peripheral circuit is further configured to store the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation to a page buffer of the peripheral circuit or in the array of memory cells.

[0025] In yet another aspect, a memory system includes a memory device and a memory controller coupled to the memory device. The memory device includes an array of memory cells having memory cells and a peripheral circuit coupled to the array of memory cells. The memory controller is configured to: instruct the peripheral circuit to perform a first read operation with a first read voltage of a first single read level; instruct the peripheral circuit to perform a first shifted read operation with the first read voltage plus a first offset voltage; instruct the peripheral circuit to perform a second shifted read operation with the first read voltage minus the first offset voltage; and in response to a difference between first bit flip information of the first shifted read operation and second bit flip information of the second shifted read operation being equal to or below a threshold value, determine that the first read voltage is a first optimal read voltage. The first single read level of a first page is under a multi-level architecture.

[0026] In some implementations, the memory controller is further configured to calculate the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation.

[0027] In some embodiments, the memory controller is further configured to store the first bit flip information of the first shift read operation and the second bit flip information of the second shift read operation into a cache memory of the memory controller.

[0028] In some embodiments, the memory controller is further configured to perform a read retry operation.

[0029] In some embodiments, the memory controller is further configured to perform a normal read operation to read out data based on all best read voltages, and to correct errors in the data using an error correction code (ECC) algorithm when the read retry operation fails.

[0030] In some embodiments, the memory controller is further configured to perform a firmware initial read operation.

[0031] In some embodiments, the memory controller is further configured to decode data read from the array of memory cells.

[0032] In yet another aspect, a non-transitory computer readable medium storing instructions that, when executed by a processor, cause the processor to perform a method comprising: performing a first read operation with a first read voltage in a first single read level; performing a first shift read operation with the first read voltage plus a first offset voltage; performing a second shift read operation with the first read voltage minus the first offset voltage; and determining that the first read voltage is a first best read voltage in response to a difference between first bit flip information of the first shift read operation and second bit flip information of the second shift read operation being equal to or below a threshold. The first single read level of the first page is under a multi-level architecture. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0034] Figure 1 A schematic circuit diagram of an exemplary memory device including peripheral circuitry is shown in accordance with some embodiments of the present disclosure.

[0035] Figure 2 A block diagram of an exemplary memory device including an array of memory cells and peripheral circuitry is shown in accordance with some embodiments of the present disclosure.

[0036] Figure 3A block diagram illustrating an exemplary memory system including a host, a memory controller, and a memory device, in accordance with some embodiments of the present disclosure, is shown.

[0037] Figure 4 A read recovery flow diagram during operation of an exemplary memory system, in accordance with some embodiments of the present disclosure, is shown.

[0038] Figure 5A A table illustrating an exemplary method for determining an optimal read voltage, in accordance with some embodiments of the present disclosure, is shown.

[0039] Figure 5B A table illustrating an exemplary method for determining an optimal read voltage, in accordance with some embodiments of the present disclosure, is shown.

[0040] Figure 5C A voltage distribution and corresponding bit information during a read operation illustrating an exemplary method for determining an optimal read voltage, in accordance with some embodiments of the present disclosure, is shown.

[0041] Figure 5D A table illustrating an exemplary method for determining an optimal read voltage, in accordance with some embodiments of the present disclosure, is shown.

[0042] Figure 6A A voltage distribution illustrating an exemplary method for determining an optimal read voltage, in accordance with some embodiments of the present disclosure, is shown.

[0043] Figure 6B A voltage distribution during a read operation illustrating an exemplary method for determining an optimal read voltage, in accordance with some embodiments of the present disclosure, is shown.

[0044] Figure 6C A table illustrating an exemplary method for determining an optimal read voltage, in accordance with some embodiments of the present disclosure, is shown.

[0045] Figure 6D A voltage distribution and corresponding bit information during a read operation illustrating an exemplary method for determining an optimal read voltage, in accordance with some embodiments of the present disclosure, is shown.

[0046] Figure 7A A flow diagram for determining an optimal read voltage, in accordance with some embodiments of the present disclosure, is shown.

[0047] Figure 7B A flow diagram for determining an optimal read voltage, in accordance with some embodiments of the present disclosure, is shown.

[0048] Figure 7C A flow diagram for determining an optimal read voltage, in accordance with some embodiments of the present disclosure, is shown.

[0049] Figure 8A Voltage distributions during read operations and a correspondence between read offsets and number of bit counts are shown in accordance with some embodiments of the present disclosure.

[0050] Figure 8B Relationships in different optimal read voltage levels are shown in accordance with some embodiments of the present disclosure.

[0051] Figure 9A A flowchart for determining an optimal read voltage is shown in accordance with some embodiments of the present disclosure.

[0052] Figure 9B A flowchart for determining an optimal read voltage is shown in accordance with some embodiments of the present disclosure.

[0053] Figure 9C A flowchart for determining an optimal read voltage is shown in accordance with some embodiments of the present disclosure.

[0054] Figure 10 A block diagram of an exemplary system with a memory device is shown in accordance with some embodiments of the present disclosure.

[0055] Figure 11A A diagram of an exemplary memory card with a memory device is shown in accordance with some embodiments of the present disclosure.

[0056] Figure 11B A diagram of an exemplary solid state drive (SSD) with a memory device is shown in accordance with some embodiments of the present disclosure.

[0057] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0058] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Other configurations and arrangements can be employed without departing from the scope of the present disclosure. Moreover, the present disclosure can also be employed in a variety of other applications. The described features and structural and functional characteristics described in the present disclosure can be combined in one or more ways to produce the desired descriptions of the present disclosure. Such combinations have been described in general terms herein, although specific embodiments can be shown in the attached figures.

[0059] In general, terms should be understood, at least in part, by their use in the context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular, or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" may also be understood to convey singular usage or plural usage, depending, at least in part, on the context. Furthermore, the term "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, but rather to allow for the presence of other factors that may not be explicitly stated, again depending, at least in part, on the context.

[0060] In non-volatile memory devices, storage architectures with multiple bits per memory cell are emerging and becoming more prevalent in the industry. Read margins are becoming narrower, making memory devices more susceptible to noise, program / read disturb, coupling issues, charge loss, and the like. For example, multi-level cell (MLC) technology significantly reduces the read margin between different threshold voltage (Vth) levels used to store multiple bits in a single memory cell. However, the Vth level of a memory cell may shift beyond the read reference voltage (Vref) (i.e., the voltage used to distinguish the cell's Vth level), resulting in more read errors.

[0061] One of the solutions is to apply a read retry operation. The read retry operation can be used to determine the optimal read voltage of the memory device. However, a large number of read retry operations may cause significant performance degradation due to read latency by introducing multiple read retry steps of rereading the target page using an adjusted read reference voltage (Vref). Another solution is to apply an error correction code (ECC) that can detect and correct raw bit errors. However, ECC may only detect and correct a limited number of errors. Accordingly, more solutions can be applied in combination with these solutions to reduce the read bit error rate while maintaining the performance of the memory system.

[0062] To address one or more of the issues described above, the present disclosure introduces solutions to determine the optimal read voltage for each read level using several methods. In particular, the present disclosure introduces solutions that can utilize single-level reading to determine the optimal read voltage, thereby reducing the computation time and improving overall performance. Further, the present disclosure also provides solutions that implement various methods for data recovery to correct data and reduce RBER. It is noted that single-level reading is a type of read operation that reads at least one bit (as a first order bit "0" or "1") of data stored in a memory cell using a single reference voltage level (e.g., a single read reference voltage level). The data stored in the memory cell can include multiple bits (e.g., 110, 001, or 011). The single reference voltage level can be, for example, a first single read level (RV1) that distinguishes between adjacent program states (e.g., L0 and LI). For example, the first single read level (RV1) voltage (V RV1 ) can be applied to a word line connected to a target memory cell, and other word lines are applied with a voltage. Next, at least one bit of data stored in the target memory cell can be determined as "0" or "1" depending on whether a current is detected in a bit line connected to the target memory cell at the first single read level voltage V RV1 . It is noted that in some embodiments, the bit count disclosed herein is the number of bits that are either bit=l or bit=0 under a single-level read operation.

[0063] Figure 1 A schematic circuit diagram of a memory device 100 including a peripheral circuit is shown in accordance with some aspects of the present disclosure. The memory device 100 can include a memory cell array 101 and a peripheral circuit 102 coupled to the memory cell array 101. In some embodiments, the memory cell array 101 can be a NAND flash memory cell array in which the memory cells 106 are provided in the form of an array of three-dimensional (3D) NAND memory strings 108 each extending vertically above a substrate (not shown). In some embodiments, each 3D NAND memory string 108 includes a plurality of memory cells 106 coupled in series and disposed vertically stacked. Each memory cell 106 is capable of holding a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons trapped within a region of the memory cell 106. Each memory cell 106 can be a "floating gate" type of memory cell that includes a floating gate transistor, or can be a "charge trap" type of memory cell that includes a charge-trapping transistor. Each array made up of 3D NAND memory strings 108 can include one or more 3D memory devices.

[0064] In some embodiments, each memory cell 106 is a single-level cell (SLC) that has two possible memory states and thus is capable of storing one bit of data. For example, a first memory state "0" can correspond to a first range of voltages and a second memory state "1" can correspond to a second range of voltages. In some embodiments, each memory cell 106 is a multi-level cell (MLC) that is capable of storing more than one bit of data in four or more memory states. For example, an MLC can store two bits per cell, three bits per cell (also referred to as a triple-level cell (TLC)), or four bits per cell (also referred to as a quad-level cell (QLC)). Each MLC can be programmed to exhibit a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erased state to exhibit one of three possible programmed levels by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used as an erased state. It is noted that the multi-level architecture in this disclosure includes MLC architecture, TLC architecture, or QLC architecture, etc., or combinations thereof.

[0065] As shown in Figure 1 Each 3D NAND memory string 108 can include a source select transistor 110 at its source end and a drain select transistor 112 at its drain end, as shown in FIG. 1. The source select transistors 110 and the drain select transistors 112 can be configured to activate a selected 3D NAND memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of the source select transistors 110 of the 3D NAND memory strings 108 in the same block 104 are coupled to, for example, ground, by the same source line (SL) 114 (e.g., a common SL). According to some embodiments, the drain select transistors 112 of each 3D NAND memory string 108 are coupled to a respective bit line 116 from which data can be read or to which data can be programmed via an output bus (not shown). In some embodiments, each 3D NAND memory string 108 is configured to be selected or deselected by applying a select signal (e.g., a select voltage that exceeds a threshold voltage of the drain select transistor 112) or a deselect signal (e.g., a deselect voltage such as 0V) to the respective drain select transistor 112 via one or more drain select lines 113 and / or by applying a select voltage (e.g., exceeds a threshold voltage of the source select transistor 110) or a deselect voltage (e.g., 0V) to the respective source select transistor 110 via one or more source select lines 115.

[0066] As shown in Figure 1As shown in FIG. 1, the 3D NAND memory string 108 can be organized into a plurality of blocks 104, each of which can have a common source line 114. In some embodiments, each block 104 is the basic unit of data for an erase operation, i.e., all memory cells 106 on the same block 104 are erased at the same time. The memory cells 106 can be coupled by word lines 118, which select which row of memory cells 106 is affected by read and program operations. In some embodiments, each word line 118 is coupled to a row of memory cells 106, which is the basic unit of data for program and read operations. Each word line 118 can be coupled to a plurality of control gates (gate electrodes) at each memory cell 106 in the corresponding row and a gate line that couples the control gates.

[0067] The peripheral circuitry 102 can be coupled to the memory cell array 101 by the bit lines 116, the word lines 118, the source lines 114, the source select lines 115, and the drain select lines 113. As described above, the peripheral circuitry 102 can include any suitable circuitry for facilitating the operation of the memory cell array 101, which facilitates the operation by applying voltage and / or current signals to and sensing voltage and / or current signals from each target memory cell 106 via the bit lines 116 through the word lines 118, the source lines 114, the source select lines 115, and the drain select lines 113. The peripheral circuitry 102 can include various types of peripheral circuitry formed using complementary metal-oxide-semiconductor (CMOS) technology. For example, Figure 2 An exemplary peripheral circuitry 102 is shown, which includes a page buffer 204, a column decoder / bit line driver 206, a row decoder / word line driver 208, a voltage generator 210, control logic 212, registers 214, an interface (I / F) 216, and a data bus 218. It should be understood that other peripheral circuitry 102 can also be included in some examples.

[0068] The page buffer 204 can be configured to buffer data read from or written to the memory cell array 101 according to control signals of the control logic 212. In one example, the page buffer 204 can store a page or pages of program data (write data) to be programmed into a row or rows of the memory cell array 101. In another example, the page buffer 204 also performs program verify operations to ensure that the data has been correctly programmed into the memory cells 106 coupled to the selected word lines 118. In yet another example, the page buffer 204 can also store bit information, bit flip information, offset information, intermediate calculation data, data tables, or other information used to implement the methods in the present disclosure.

[0069] Row decoders / word line drivers 208 can be configured to be controlled by control logic 212 and to select or not select blocks 104 of memory cell array 101 and to select or not select word lines 118 of blocks 104. Row decoders / word line drivers 208 can be further configured to drive memory cell array 101. For example, row decoders / word line drivers 208 can use word line voltages generated by voltage generator 210 to drive memory cells 106 coupled to selected word lines 118. In some embodiments, row decoders / word line drivers 208 can include decoders and string drivers (drive transistors) coupled to local word lines and word lines 118.

[0070] Voltage generator 210 can be configured to be controlled by control logic 212 and to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.) to be provided to memory cell array 101. In some embodiments, voltage generator 210 is part of a voltage source that provides various levels of voltages for different peripheral circuits 102, as described in detail below. In some embodiments, voltage generator 210 provides voltages to row decoders / word line drivers 208 and page buffer 204 that are higher than certain levels sufficient to perform memory operations, in accordance with the scope of the present disclosure. For example, the voltage provided to page buffer 204 can be between 2V and 3.3V, such as 3.3V, and the voltage provided to row decoders / word line drivers 208 can be greater than 3.3V, such as between 3.3V and 30V.

[0071] Column decoders / bit line drivers 206 can be configured to be controlled by control logic 212 and to select one or more 3D NAND memory strings 108 by applying bit line voltages generated by voltage generator 210. For example, column decoders / bit line drivers 206 can apply column signals to select a set of N-bit data from page buffer 204 to be output in a read operation.

[0072] Control logic 212 can be coupled to each peripheral circuit 102 and configured to control the operation of peripheral circuits 102. Registers 214 can be coupled to control logic 212 and include status registers, command registers, and address registers to store status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit 102. Control logic 212 is configured to control the operation in embodiments of the present disclosure.

[0073] The interface 216 can be coupled to the control logic 212 and configured to interface the memory cell array 101 with a memory controller (not shown). In some embodiments, the interface 216 acts as a control buffer to buffer control commands received from the memory controller and / or a host (not shown) and forward them to the control logic 212, and to buffer status information received from the control logic 212 and forward them to the memory controller and / or the host. The interface 216 can also be coupled to the page buffer 204 and the column decoder / bit line driver 206 via a data bus 218 and act as an input / output (I / O) interface and data buffer to buffer program data received from the memory controller and / or the host and forward them to the page buffer 204, and to buffer read data from the page buffer 204 and forward them to the memory controller and / or the host. In some embodiments, the interface 216 and the data bus 218 are part of the I / O circuitry of the peripheral circuitry 102.

[0074] Figure 3 An exemplary memory system 350 including a host 357, a memory controller 300, and a memory device 100 is shown in accordance with some embodiments of the present disclosure. The memory controller 300 includes a microprocessor 351, a controller / memory device interface (I / F) 355 coupled between the microprocessor 351 and the host 357, and a controller / memory device interface 359 coupled between the microprocessor 351 and the memory device 100. The controller / host interface 355 is configured to implement standard communication protocols including embedded multimedia card (EMMC), universal serial bus (USB), universal flash storage (UFS), parallel advanced technology attachment (parallel ATA or PATA), serial advanced technology attachment (SATA), etc., to communicate with the host 357. The controller / memory device interface 359 is configured to translate commands into corresponding control signals to control the memory device 100.

[0075] The memory controller 300 can manage data stored in the memory device 100 and communicate with the host 357. The memory controller 300 can be configured to control operations of the memory device 100, such as read, erase, program operations, data recovery operations, or other operations according to some embodiments of the present disclosure. The memory controller 300 can be configured to control the operations by sending a command (e.g., a read command) or a command with a data address. In some embodiments, the memory controller 300 can also include a controller memory 353 (e.g., a volatile cache memory and / or a non-volatile memory) that stores data tables, intermediate calculation information, offset information, verification information, failure bit count information, bit information, bit flip information, or other information in embodiments of the present disclosure. The memory controller 300 can also be configured to manage various functions related to data stored in or to be stored in the memory device 100, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 300 is also configured to process error correction codes (ECCs) related to data read from or written to the memory device 100. In some embodiments, the memory controller 300 is also configured to execute or issue instructions to perform operations including a best read voltage determination operation, a read retry operation, or other operations in embodiments of the present disclosure. The memory controller 300 can also perform any other suitable functions, such as causing the memory device 100 to format. The memory controller 300 can communicate with external devices (e.g., the host 357) according to a particular communication protocol. The host 357 can be a processor of an electronic device, such as a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)). The host 357 can be configured to send or receive data to or from the memory device 100 through the memory controller 300.

[0076] Figure 4 A read recovery flow diagram during operation of an exemplary memory system according to some embodiments of the present disclosure is shown. First, the firmware can instruct the memory controller 300 to read with an initial threshold voltage and attempt a hard decode of the read information. If the initial threshold voltage is selected well such that the initial read passes, then the hard decode will succeed and the decoded read information is sent to the host 357. Otherwise, if the hard decode fails, then the initial read also fails, and the firmware can instruct the memory controller 300 to perform a read retry operation, a best read voltage determination operation, or a combination thereof.

[0077] In some embodiments, the best read voltage determination operation can be performed upon a failure of the initial read operation. Thereafter, the best read voltage determination operation can start the implementation of the best read voltage determination operation using the default read voltage of the initial read operation as the first read voltage (i.e., as the initial read voltage of the best read voltage determination operation). It is noted that the first read voltage in the first read operation in the present disclosure can be the single read level voltage in the single read level operation.

[0078] In some embodiments, the best read voltage determination operation can be performed within the read retry operation. For example, during the read retry operation, a read offset voltage can be obtained by checking a read retry table (RRT). The RRT can include a plurality of offset voltage values or include corresponding values from which the offset voltage values can be obtained by calculation. The offset voltage obtained by the RRT during the read retry operation can be used directly or can be used to determine the read retry voltage by calculation.

[0079] In some embodiments, the read retry voltage can be used directly as the first read voltage of the best read voltage determination operation, thereby starting the implementation of the best read voltage determination operation.

[0080] In some embodiments, the read retry voltage can be used to perform a normal read operation. If the normal read operation passes, the best read voltage determination operation is not needed. Otherwise, if the normal read operation fails, the read retry voltage is used as the first read voltage of the best read voltage determination operation, thereby starting the implementation of the best read voltage determination operation.

[0081] In some embodiments, the best read voltage determination operation can be performed upon a failure of the read retry operation.

[0082] As shown in Figure 4 The read retry operation can include a read operation and a hard decode operation for each read retry operation, as shown in the above. However, the best read voltage determination operation can only require a plurality of read operations along with a best hard decode or soft decode operation. Accordingly, the best read voltage determination operation reduces the cost and latency compared to the read retry operation and improves the efficiency of obtaining the best read voltage for each read level.

[0083] To further improve error correction capability, the memory controller 300 can examine a log likelihood ratio (LLR) table generated during characterization of the memory device. The input of the LLRs provides statistical information of the memory device regarding the most likely correct value of each data bit. For example, the LLRs can provide probabilities of determining how likely a received bit ("0" or "1") has flipped or not. These probabilities are taken from the LLR table in a look-up table that has been generated and stored into the memory controller 300. This can be implemented before, during, or after the read retry operation or the best read voltage determination operation.

[0084] In some embodiments, the ECC mechanism can also be implemented before, during, or after the read retry operation or the best read voltage determination operation.

[0085] If all read retry operations and best read voltage determination operations fail, then it is determined that there can be a defective memory cell (e.g., a stuck cell) and thus an uncorrectable ECC failure (or UECC) exists. The redundant array of independent disks (RAID) and corresponding components (i.e., dies / planes / blocks / pages) can be reconstructed accordingly. For example, the RAID operation can recover a failed component in a RAID stripe by using the remaining successful components in the RAID stripe.

[0086] Figures 5A-5D An exemplary method for determining a best read voltage is shown in accordance with some embodiments of the present disclosure. As shown in Figure 5A This example uses TLC NAND as one embodiment, as shown in It is noted that embodiments in the present disclosure can not be limited to TLC architecture. It can also include MLC or QLC architecture. Since the read operation in this embodiment is not a single level read operation, a level indicator is needed to indicate all types of pages (i.e., lower page (LP), middle page (MP), or upper page (UP)) to which the read operation is applied. For example, the level indicator can be obtained by reading the page information of other page types in the same word line. In the read operation of the UP, the read voltage of the LP can be used as the level indicator; while in another read operation of the LP, the read voltage of the UP can be used as the level indicator, so that when a bit flip occurs, it can be determined as the value in a different page.

[0087] In Figure 5B In the implementation of the best read voltage determination operation in the LP, the reference voltage V00 of the UP is used as the level indicator, and V0 is the initial read voltage.

[0088] Figure 7A An exemplary method for determining a best read voltage is shown in accordance with some embodiments of the present disclosure. As shown in Figures 5A-5Da flowchart of the method 700 of determining the optimal read voltage in the example.

[0089] The method 700 begins at operation 702, in which a UP (i.e., another page than the target page) is set to have a level indicator of data00 read.

[0090] Next, with reference to operation 704, a first read operation is performed on the current page data (i.e., the target page). The LP is read with V0 and thus data0 is obtained; the UP is read with V00 and thus data00 is obtained. An AND operation is performed on data0 and data00 to obtain data_temp0, and an OR operation is performed on data0 and data00 to obtain data_temp1. Next, the number of bits "1" in data_temp0 is counted and stored as a number N01, and the number of bits "0" in data_temp1 is counted and stored as a number N00, where N01 corresponds to the program state Vrd_p1 and N00 corresponds to the program state Vrd_p5.

[0091] Next, with reference to operation 706, the read voltage V0 is shifted to V0 plus a first shift value as a read voltage V1, and data1 is then obtained. An AND operation is performed on data1 and data00 to obtain data_temp2, and an OR operation is performed on data1 and data00 to obtain data_temp3. The number of bits "1" in data_temp2 is counted and stored as a number N11, and the number of bits "0" in data_temp3 is counted and stored as a number N10.

[0092] Next, with reference to operation 708, the read voltage V0 is shifted to V0 minus the first shift value as a read voltage V2, and data2 is then obtained. An AND operation is performed on data2 and data00 to obtain data_temp4, and an OR operation is performed on data2 and data00 to obtain data_temp5. The number of bits "1" in data_temp4 is counted and stored as a number N21, and the number of bits "0" in data_temp5 is counted and stored as a number N20.

[0093] Next, referring to operation 710, in this operation, by comparing the bit flip count value from 0 to 1 with the bit flip count value from 1 to 0, it is determined in operation 712 whether V1 is closer to V0 or V2 is closer to V0. That is, if the bit flip count value from 0 to 1 is higher than the bit flip count value from 1 to 0, then the next read voltage V3 should be determined to be shifted from V0 toward V1; if the bit flip count value from 1 to 0 is higher than the bit flip count value from 0 to 1, then the next read voltage V3 should be determined to be shifted from V0 toward V2.

[0094] In the next iteration, referring to operation 714, a next read voltage V3 can be determined and, after determining the voltage shift direction, set to a voltage between V1 and V0 or a voltage between V2 and V0. For example, when the voltage should be shifted toward V1, the next read voltage V3 can be set to half the sum of V1 and V0. By repeating the above process, an optimal read voltage can be found when no further shifting is required. That is, when the 0 to 1 bit flip count value and the 1 to 0 bit flip count value are equal for both sides or the difference between them is less than a threshold, the next read voltage V3 is determined to be the optimal read voltage for the read stage, and no further shifting is required. For example, when the difference between the 0 to 1 bit flip count and the 1 to 0 bit flip count is determined to be below a threshold (i.e., the 1 to 0 bit flip count is almost equal to the 0 to 1 bit flip count), the read voltage V3 is determined to be the optimal read voltage for the read stage.

[0095] Figure 6A Figure 1 shows a voltage distribution illustrating an exemplary method for determining an optimal read voltage according to some embodiments of the present disclosure. To find the optimal read voltage, one can rely on a Vth normal distribution, thereby being able to determine the offset of the read voltage using the bit count distribution. For example, Figure 6A As shown in , among the left side of the distribution, the threshold voltage shift toward the left has a lower probability than the voltage shift toward the right. That is, the bit count of the voltage shifted toward the left is necessarily lower than the bit count of the voltage shifted toward the right. On the contrary, among the right side of the distribution, the threshold voltage shift toward the left has a higher probability than the voltage shift toward the right. That is, the bit count of the voltage shifted toward the left is necessarily higher than the bit count of the voltage shifted toward the right. By comparing the bit flip information, for example, the bit flip count, the direction of the voltage shift can be determined, and thus the optimal read voltage (i.e., the bottom of the distribution) can be determined by iterating these processes. It should be noted that in some embodiments, the bit flip information or the bit flip count represents the number of bit flips from "0" to "1" or from "1" to "0".

[0096] Figure 7B Some embodiments of the present disclosure are shownFigures 6A-6D a flowchart of the method 720 of determining the optimal read voltage in the example. It is noted that this implementation can be performed under a multi-level architecture including an MLC architecture, a TLC architecture, or a QLC architecture.

[0097] First, reference is made to operation 722 in which an initial single-level read (SLR) voltage is determined for the current page (i.e., the target page). Unlike the previous example in which a level indicator is needed for different read levels, this implementation does not require a level indicator. That is, by using a single-level read operation, the optimal read voltage can be determined. For example, the current page can be an LP in a TLC architecture.

[0098] Next, reference is made to operation 724 in which a first read operation is performed on the current page data (i.e., the target page). The current page is read with V0 as shown in Figure 6B , and the data including bit count information is obtained thereafter. For example, as shown in Figure 6C , in the first read operation, the bit count of bit “0” is N00 and the bit count of bit “1” is N01. In some implementations, as mentioned above, the initial single-level read voltage includes the read retry voltage during the previous read retry operation or the default read voltage. It is noted that the actual bit count data collected is not limited to the memory cells of the current page. It can be the bit count of the target memory cells, the bit count of the partial memory cells in the target page (e.g., at least the memory cells of the target page that are in a programmed state), the bit count of all memory cells in the target page, the bit count of the memory cells in one or more pages including the target page, the bit count of all memory cells in all pages. It should also be noted that the actual bit count data collected can include the bit count of the target group of memory cells or the target group of pages, and the target optimal read voltage is the optimal read voltage of the target group of memory cells or pages. Thus, the address of the read operation for determining the actual bit count can be the address of the corresponding target group of memory cells or pages.

[0099] Next, reference is made to operation 726 in which the read voltage V0 is shifted to V0 minus a first shift value as the read voltage V1 during a second read operation. For example, as shown in Figure 6C , in the second read operation, the bit count of bit “0” is counted and stored as N10, and the bit count of bit “1” is counted and stored as N11. That is, the bit flipping information of bit “0” switching to “1” can be calculated and obtained. Thereafter, the bit flipping information can be used to determine whether the read voltage Vth should be shifted to the left or to the right to find the optimal read voltage.

[0100] Next, referring to operation 728, in this operation, the read voltage V0 is shifted to V0 plus the first shift value, which serves as the read voltage V2 during the third read operation. Figure 6C As shown in FIG, in the third read operation, the bit count of bit "0" is counted and stored as N20, and the bit count of bit "1" is counted and stored as N21. In other words, the bit flip information of whether bit "0" switches to "1" or "1" switches to "0" can be calculated and obtained. The bit flip information is then used to determine whether the read voltage Vth should be shifted to the left or right, thereby finding the optimal read voltage.

[0101] Next, referring to operation 730 , in this operation, bit flip information of bit “0” switching to “1” and bit “1” switching to “0” is calculated and determined.

[0102] Next, referring to operation 732, as mentioned above, when the bit flip information for bit "0" to switch to "1" is greater than the bit flip information for bit "1" to switch to "0", the firmware or memory controller 300 may search for the optimal read voltage toward the left. Thereafter, in operation 734, a new read voltage V3 is determined for the next read operation, and the next read operation 724 is repeated. In some embodiments, read voltage V3 may be determined as half the sum of V0 and V1. In some embodiments, read voltage V3 may be determined as any voltage value between V0 and V1, depending on the distribution analysis. Furthermore, when the bit flip information for bit "0" to switch to "1" is less than the bit flip information for bit "1" to switch to "0", the firmware or memory controller 300 may search for the optimal read voltage toward the right. Thereafter, a new read voltage V3 is determined for the next read operation. In some embodiments, read voltage V3 may be determined as half the sum of V0 and V2. In some embodiments, the read voltage V3 can be determined to be any voltage value between V0 and V1 , depending on the distribution analysis.

[0103] Next, referring to operation 738, in this operation, by comparing the bit flip information value of the bit flip information when the bit is switched from "1" to "0" with the bit flip information value when the bit is switched from "0" to "1", it is determined whether V1 is closer to V0 or V2 is closer to V0. In other words, it can be determined whether V0 should be shifted in the direction closer to V1 or in the direction closer to V2. When the comparison of the bit flip information value when the bit is switched from "1" to "0" and the bit flip information value when the bit is switched from "0" to "1" is equal to or less than a threshold value, no further shifting is required. Accordingly, the read voltage is determined to be the optimal read voltage for the read stage.

[0104] Next, reference is made to operation 739, in which, after determining one of the read levels in the current page one best read voltage, it is determined whether the SLR read for the current page is complete for all read levels. If not, the next SLR level on the current page is determined, as in operation 736. A new read voltage is also determined and thus another read operation 724 is initiated. The flow is repeated until all SLR levels in the current page have found their respective best read voltage.

[0105] Figure 7C A flowchart of a method 740 of determining a best read voltage is shown, in accordance with some embodiments of the present disclosure. The method can begin with a coarse best read voltage operation, for example, in operation 742. Based on the randomness characteristic of the programmed data, and by using the count of bits "0" or "1" that should ideally be equal, each read level should have an expected number of bit counts out of the total bit count. For example, in SLC mode, levels L0 and LI should share the total bit count. That is, each of levels L0 and LI should have half of the total bit count. Thus, by comparing each expected bit count number and the bit count obtained via a read operation, the voltage shift in the next iteration can be determined. By repeating these procedures, the coarse best read voltage determination operation is able to find a coarse best read voltage. Thereafter, the coarse best read voltage can be used as a default read voltage or a first read voltage to start the fine best read voltage procedure, as in operation 744. For example, in Figure 7B The fine best read voltage determination operation is disclosed in detail in the corresponding description.

[0106] Figure 9A A flowchart of a method 900 for determining a best read voltage is shown, in accordance with some embodiments of the present disclosure.

[0107] The method 900 begins with operation 902, in which an initial SLR level of a current page is determined. The initial SLR level is determined as a first read level. For example, the programmed level PI in the current page LP can be determined as the first read level of the current page LP, and the programmed level P5 in the current page LP can be determined as the second read level of the current page LP.

[0108] Reference is made to operation 904, in which a first read operation is performed with a first read voltage of the first read level. In some embodiments, as mentioned above, the initial single-level read voltage includes a read retry voltage during a previous read retry operation, a default read voltage, or any best read voltage obtained in the present disclosure.

[0109] Referring to operation 906, in this operation, a first shifted read operation is performed with the first read voltage plus a first offset voltage. In some embodiments, the first offset voltage can be determined according to a threshold voltage normal distribution characteristic or a read margin of the memory device. For example, the first offset voltage can be between 0.01 V and 1.0 V. It is noted that the lower the first offset voltage (i.e., the smaller the shift step), the more iterations the optimal read voltage determination operation needs.

[0110] Referring to operation 908, in this operation, a second shifted read operation is performed with the first read voltage minus the first offset voltage.

[0111] Referring to operation 910, in this operation, the first read voltage is determined to be the first optimal read voltage in response to a difference between the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation being equal to or lower than a threshold value. Conversely, the first read voltage is determined not to be the first optimal read voltage in response to the difference between the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation being higher than the threshold value.

[0112] After determining that the first read voltage is not the first optimal read voltage, the method 900 can begin performing a second read operation with a second read voltage, where the second read voltage is determined based on a difference between the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation. Specifically, the second read voltage is determined to be higher than the first read voltage in response to the first bit flip information of the first shifted read operation being higher than the second bit flip information of the second shifted read operation, and the second read voltage is determined to be lower than the first read voltage in response to the first bit flip information of the first shifted read operation being lower than the second bit flip information of the second shifted read operation. In some embodiments, the second read voltage is determined to be the first read voltage minus half of the first offset voltage in response to the first bit flip information of the first shifted read operation being higher than the second bit flip information of the second shifted read operation, and the second read voltage is determined to be the first read voltage plus half of the first offset voltage in response to the first bit flip information of the first shifted read operation being lower than the second bit flip information of the second shifted read operation. By using multiple iterations to approach the optimal read voltage, the optimal read voltage for the current page can be found.

[0113] In some embodiments, the first bit flip information of the first shifted read operation is determined by a first bit flip count between the first shifted read operation and the first read operation, and the second bit flip information of the second shifted read operation is determined by a second bit flip count between the second shifted read operation and the first read operation. These detailed calculations can refer to the embodiments in Figures 6A-6D and Figure 7B .

[0114] In some embodiments, the method 900 can further include determining a second single-level read level for the current page in response to determining that the first read voltage is the first optimal read voltage for the first page. Once all optimal read voltages for all corresponding read levels of the current page are determined, the same operation can be performed for the next page.

[0115] In some embodiments, after all optimal read voltages for all corresponding read levels of the current page are determined, the method 900 can further include performing a normal read operation based on all optimal read voltages for the current page. It is noted that the normal read operation is not a single-level read operation.

[0116] Figure 9B A flowchart of a method 920 for determining optimal read voltages is shown in accordance with some embodiments of the present disclosure.

[0117] The method 920 begins at operation 922, in which a relationship between bit flipping information and corresponding offsets for each read level of a current page is determined. As shown in Figure 8A As shown in the middle, a voltage distribution for read levels (e.g., read levels between programmed states P2 and P3 and between P6 and P7) and a corresponding relationship between read offsets and bit count numbers in each read level are obtained and calculated or determined based on a big data analysis of the memory device.

[0118] In some embodiments, the big data analysis is accomplished by: (1) reading all bit count information for all corresponding Vths of the NAND; (2) defining an estimated range for each read level; (3) calculating delta values, which include a difference between two bit count information using two corresponding Vths; (4) calculating a relationship between the delta values and offsets of optimal read voltages for each read level; and (5) storing the relationship into firmware. In calculating the relationship, at least two single-level read operations are performed to obtain the delta values. Thus, by using the relationship and the obtained delta values, the optimal read voltages can be determined. It is noted that the bit count information includes a number of bit counts or a number of bit counts that are being processed or biased.

[0119] Referring to operation 924, in this operation, at least two read operations of each read level of the current page are performed to determine a difference in bit flip information between the at least two read operations of each read level. In some embodiments, the method 920 includes performing a first pre-read operation with a first pre-read voltage Vo and performing a second pre-read operation with a second pre-read voltage Vi to determine first pre-read bit flip information (e.g., first shift bit counts). A first read offset is determined based on the first pre-read bit flip information in the first read level and a first relationship (e.g., a linear relationship) between bit flip information and read offset. Thereafter, a first optimal read voltage is determined by using the first read offset and the first pre-read voltage Vo, as in operation 926. Note that the first read offset is an estimated voltage offset (e.g., a left or right shift of a read voltage) toward the optimal read voltage to be determined. In other embodiments of the above-mentioned optimal read voltage determination operations (e.g., the optimal read voltage determination operations shown in Figures 6A-6D and Figure 7B the first optimal read voltage can be used as the first read voltage. Doing so will significantly reduce the number of iterations in the other optimal read voltage determination operations.

[0120] In some embodiments, more than two pre-read operations are used. For example, the method 920 can include performing a first pre-read operation with a first pre-read voltage and performing a second pre-read operation with a second pre-read voltage to determine first pre-read bit flip information; performing a first pre-read operation with the first pre-read voltage and performing a third pre-read operation with a third pre-read voltage to determine second pre-read bit flip information; and determining a first read offset based on a difference between the first pre-read bit flip information and the second pre-read bit flip information and a first relationship (e.g., a linear relationship) between the difference and a read offset in the first read level. Thereafter, a first optimal read voltage is determined by using the first read offset and the first pre-read voltage Vo, as in operation 926.

[0121] Once one of the read levels (e.g., the first read level of the first page) is determined, as shown in Figure 8B the relationship in the current read level of the current page can be further mapped to other read levels of the current page. For example, the relationship of other read levels of the first page can be determined by using the first relationship of the first read level of the first page.

[0122] Figure 9CA flowchart of a method 940 for read recovery is shown in accordance with some embodiments of the present disclosure. The method 940 begins at operation 942, in which a firmware initial read operation is performed. If the firmware initial read operation fails, the method 940 proceeds to operation 944, in which a read retry operation is performed. Next, if the read retry operation fails, the method 940 proceeds to operation 946, in which all best read voltages for a first page of the memory cell array are determined. It is noted that the best read voltage determination operation can be performed before, within, or after the read retry operation, as mentioned above. The best read voltage found in the read retry operation can be used as the initial read voltage in the best read voltage determination operation, or vice versa. Accordingly, the best read voltage can be determined as precisely as possible without degrading the overall performance of the memory device. Next, the method 940 proceeds to operation 948, in which a normal read operation is performed based on all the best read voltages for the first page of the memory cell array to read out the data. Next, the method 940 proceeds to operation 950, in which an error correction code (ECC) is used to detect and correct any errors in the data. It is noted that the ECC can also be performed before, within, or after the read retry operation.

[0123] Figure 10 A block diagram of a system 1000 having a memory device is shown in accordance with some aspects of the present disclosure. The system 1000 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other electronic device having a storage component located therein. As shown in Figure 10 The system 1000 can include a host 1008 and a memory system 1002 having one or more memory devices 1004 and a memory controller 1006, as shown in FIG. 1. The host 1008 can be a processor of an electronic device, such as a central processing unit (CPU), or can be a system on a chip (SoC), such as an application processor (AP). The host 1008 can be configured to send or receive data to or from the memory device 1004.

[0124] The memory device 1004 can be any memory device disclosed herein, such as the memory device 100. In some embodiments, each memory device 1004 includes a memory device as described in detail above.

[0125] According to some embodiments, the memory controller 1006 is coupled to the memory devices 1004 and the host 1008 and is configured to control the memory devices 1004. The memory controller 1006 can be any of the memory controllers disclosed herein, for example, the memory controller 300. In some embodiments, each memory controller 1006 includes a memory controller as described in detail above. The memory controller 1006 can manage data stored in the memory devices 1004 and communicate with the host 1008. In some embodiments, the memory controller 1006 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 1006 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc. and enterprise storage arrays. The memory controller 1006 can be configured to control operations of the memory devices 1004, such as read, erase, and program operations. The memory controller 1006 can also be configured to manage various functions related to data stored in or to be stored in the memory devices 1004, including but not limited to bad block management, garbage collection, logical to physical address translations, wear leveling, etc. In some embodiments, the memory controller 1006 is further configured to process error correction codes (ECCs) related to data read from or written to the memory devices 1004. Any other suitable functions can also be performed by the memory controller 1006, for example, formatting the memory devices 1004. The memory controller 1006 can communicate with external devices (e.g., the host 1008) according to a particular communication protocol. For example, the memory controller 1006 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0126] The memory controller 1006 and the one or more memory devices 1004 can be integrated into various types of memory devices, for example, contained in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 1002 can be implemented and packaged into different types of end electronic products. In some embodiments, the memory system 1002 is implemented and packaged into a memory card, a memory stick, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, aFigure 11A In one example shown, the memory controller 1006 and the single memory device 1004 can be integrated into a memory card 1102. The memory card 1102 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 1102 can further include a memory card connector 1104 that couples the memory card 1102 with a host (e.g., the host 1008 in Figure 10 In another example shown, the memory controller 1006 and the multiple memory devices 1004 can be integrated into an SSD 1106. The SSD 1106 can further include an SSD connector 1108 that couples the SSD 1106 with a host (e.g., the host 1008 in Figure 11B Figure 10 In some implementations, the storage capacity and / or operating speed of the SSD 1106 is higher than that of the memory card 1102.

[0127] The foregoing description of specific implementations has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Many modifications and variations are possible in light of the teaching and

[0128] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined in accordance with the following claims and their equivalents.​

Claims

1. A method of operating a memory system, comprising: performing a first read operation with a first read voltage of a first single read level; performing a first shifted read operation with the first read voltage plus a first offset voltage; performing a second shifted read operation with the first read voltage minus the first offset voltage; and in response to a difference between a first bit flip information of the first shifted read operation and a second bit flip information of the second shifted read operation being at or below a threshold value, determining that the first read voltage is a first optimal read voltage, wherein the first single read level of a first page is under a multi-level architecture.

2. The method of claim 1, further comprising: in response to the difference between the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation being above the threshold value, determining that the first read voltage is not the first optimal read voltage. after determining that the first read voltage is not the first optimal read voltage, the method further comprising:

3. The method of claim 2, wherein, performing a second read operation with a second read voltage, wherein the second read voltage is determined based on the difference between the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation. determining the second read voltage based on the difference between the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation further comprises:

4. The method of claim 3, wherein, in response to the first bit flip information of the first shifted read operation being higher than the second bit flip information of the second shifted read operation, determining the second read voltage to be higher than the first read voltage; and in response to the first bit flip information of the first shifted read operation being lower than the second bit flip information of the second shifted read operation, determining the second read voltage to be lower than the first read voltage.

5. The method of claim 4, wherein: in response to the first bit flip information of the first shifted read operation being higher than the second bit flip information of the second shifted read operation, determining the second read voltage to be the first read voltage minus half of the first offset voltage; and in response to the first bit flip information of the first shifted read operation being lower than the second bit flip information of the second shifted read operation, determining the second read voltage to be the first read voltage plus half of the first offset voltage. the first bit flip information of the first shifted read operation is determined by a first bit flip count between the first shifted read operation and the first read operation, and the second bit flip information of the second shifted read operation is determined by a second bit flip count between the second shifted read operation and the first read operation. before performing a first read operation with a first read voltage, the method further comprising:

6. The method of claim 1, wherein, determining the first single read level.

7. The method of claim 1, wherein, in response to determining that the first read voltage is the first optimal read voltage, the method further comprising: determining a second single read level.

8. The method of claim 7, wherein, ​ ​ 9. The method of claim 1, wherein, determining whether the first read voltage is the first optimal read voltage further based on threshold voltage normal distribution characteristics.

10. The method of claim 9, wherein, In response to determining all optimal read voltages, the method further comprises: performing normal read operations based on all optimal read voltages.

11. The method of claim 1, further comprising: performing a first pre-read operation with a first pre-read voltage and a second pre-read operation with a second pre-read voltage to determine first pre-read bit flip information; determining a first read offset based on the first pre-read bit flip information in the first single read level and a first relationship between bit flip information and read offset; and determining a first read voltage based on the first pre-read voltage and the first read offset.

12. The method of claim 11, further comprising: determining a second read voltage based on a second single read level using the first relationship of the first single read level.

13. The method of claim 1, further comprising: performing a first pre-read operation with a first pre-read voltage and a second pre-read operation with a second pre-read voltage to determine first pre-read bit flip information; determining a first read offset based on the first pre-read bit flip information in the first single read level; determining other read offsets based on the first read offset; and determining the first read voltage based on the first pre-read voltage and the first read offset.

14. The method of claim 13, wherein, The first pre-read voltage and the second pre-read voltage in the first single read level of the first page are under the multi-level architecture.

15. The method of claim 1, further comprising: performing a first pre-read operation with a first pre-read voltage and a second pre-read operation with a second pre-read voltage to determine first pre-read bit flip information; performing the first pre-read operation with the first pre-read voltage and a third pre-read operation with a third pre-read voltage to determine second pre-read bit flip information; determining a first read offset based on a difference between the first pre-read bit flip information and the second pre-read bit flip information and a first relationship between a difference in bit flip information in the first single read level and read offset; and determining the first read voltage based on the first pre-read voltage and the first read offset.

16. A method for reading an array of memory cells, comprising: determining all optimal read voltages, wherein determining all optimal read voltages comprises: performing a first read operation with a first read voltage; performing a first shifted read operation with the first read voltage plus a first offset voltage; performing a second shifted read operation with the first read voltage minus the first offset voltage; and determining whether the first read voltage is a first optimal read voltage based on a comparison between first bit flip information of the first shifted read operation and second bit flip information of the second shifted read operation; and performing normal read operations based on all optimal read voltages to read out data.

17. The method of claim 16, wherein, The determining all optimal read voltages further includes: correcting any errors in the data using an error correction code (ECC) algorithm.

18. The method of claim 17, further comprising: performing a read retry operation.

19. The method of claim 18, further comprising: performing a firmware initial read operation.

20. The method of claim 19, wherein, prior to correcting any errors in the data using an error correction code (ECC) algorithm, the method further comprises: decoding data read from the array of memory cells.

21. A memory device, comprising: an array of memory cells including memory cells; and a peripheral circuit coupled to the array of memory cells, wherein the peripheral circuit is configured to: apply a first read voltage to a target memory cell in a first read operation; apply the first read voltage plus a first offset voltage to the target memory cell in a first shifted read operation; apply the first read voltage minus the first offset voltage to the target memory cell in a second shifted read operation; in response to first bit flip information of the first shifted read operation being higher than second bit flip information of the second shifted read operation, apply the first read voltage minus half of the first offset voltage; and in response to the first bit flip information being lower than the second bit flip information, apply the first read voltage plus half of the first offset voltage.

22. The memory device of claim 21, wherein, the peripheral circuit is further configured to: store the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation to a page buffer of the peripheral circuit or the array of memory cells.

23. A memory system, comprising: a memory device; and a memory controller coupled to the memory device, wherein the memory device comprises: an array of memory cells including memory cells; and a peripheral circuit coupled to the array of memory cells, wherein the memory controller is configured to: instruct the peripheral circuit to perform a first read operation with a first read voltage of a first single read level; instruct the peripheral circuit to perform a first shifted read operation with the first read voltage plus a first offset voltage; instruct the peripheral circuit to perform a second shifted read operation with the first read voltage minus the first offset voltage; and in response to a difference between first bit flip information of the first shifted read operation and second bit flip information of the second shifted read operation being equal to or lower than a threshold value, determine that the first read voltage is a first optimal read voltage, wherein the first single read level of a first page is under a multi-level architecture.

24. The memory system of claim 23, wherein, the memory controller is further configured to: calculate the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation.

25. The memory system of claim 24, wherein, the memory controller is further configured to: store the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation to a cache memory of the memory controller.

26. The memory system of claim 25, wherein, the memory controller is further configured to: performing a read retry operation.

27. The memory system of claim 26, wherein, The memory controller is further configured to: perform a normal read operation based on all the best read voltages to read out data; and correct errors in the data using an error correction code (ECC) algorithm when the read retry operation fails.

28. The memory system of claim 27, wherein, The memory controller is further configured to: perform a firmware initial read operation.

29. The memory system of claim 27, wherein, The memory controller is further configured to: decode data read from the array of memory cells.

30. A non-transitory computer readable medium storing instructions that, when executed by a processor, cause the processor to perform a method comprising: performing a first read operation with a first read voltage in a first single read level; performing a first shifted read operation with the first read voltage plus a first offset voltage; performing a second shifted read operation with the first read voltage minus the first offset voltage; and in response to a difference between first bit flip information of the first shifted read operation and second bit flip information of the second shifted read operation being equal to or below a threshold value, determining that the first read voltage is a first best read voltage, wherein the first single read level of a first page is under a multi-level architecture.

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