Data processing apparatus and method

Abstract

According to the data processing equipment and method provided by the invention, a processing circuit comprises a multi-core processor, and the multi-core processor comprises sub-processors with K cores and is used for participating in a target process of generating result data by performing N data processing on target data. Specifically, the processing circuit obtains the target data, determines N target computing power corresponding to the N-channel data processing, and determines the distribution of the K kernels on the execution of the N-channel data processing according to the N target computing power and a preset optimization purpose in the target process. Visibly, through the scheme provided by the invention, in the operation process of the data processing equipment, the computing power provided by the K kernels for the N channels of data processing respectively can be determined, and the corresponding target computing power is adaptively allocated to each channel of data processing, so that the flexibility of computing power allocation is improved.

Description

Data processing device and method Technical Field

[0001] This specification relates to the field of data processing, and in particular to a data processing device and method. Background Art

[0002] Data processing equipment can perform multi-channel data processing. For example, a data processing equipment that processes audio signals can perform sampling, noise reduction, Bluetooth sub-band coding (SBC), and Bluetooth radio frequency processing on the audio signals. It is understandable that the above multi-channel data processing process can be implemented through hardware, some data processing can be implemented through algorithms, and some data processing can be implemented through both hardware and algorithms. For data processing implemented through algorithms, computing power must be provided for the processing. A chip of an existing data processing device provides at least two cores for the data processing process, and plans in advance the data processing that each core is responsible for. For example, core 1 provides computing power for sampling and noise reduction, and core 2 provides computing power for Bluetooth SBC and Bluetooth radio frequency.

[0003] The content of the background technology section is merely information known to the inventor personally, and does not mean that the above information has entered the public domain before the application date of this disclosure, nor does it mean that it can become the prior art of the present disclosure.

[0004] Summary of the Invention

[0005] This specification provides a data processing device and method that can improve the flexibility of computing power allocation for data processing.

[0006] In a first aspect, a data processing device is provided, comprising: at least one storage medium storing at least one set of instruction sets, wherein the at least one set of instruction sets is used to schedule computing power in a target process of generating result data by subjecting target data to N data processing steps; and a processing circuit comprising a multi-core processor and being communicatively connected to the at least one storage medium, wherein the multi-core processor comprises K core sub-processors to participate in the target process, K being an integer greater than 1, wherein, when the data processing device is running, the processing circuit executes the at least one set of instruction sets to: obtain target data, determine N target computing powers corresponding to the N data processing steps, and, in the target process, determine the allocation of the K cores in executing the N data processing steps according to the N target computing powers and a preset optimization purpose.

[0007] In some embodiments, in order to determine the allocation of the above-mentioned K cores in performing the above-mentioned N data processing, the above-mentioned processing circuit executes the above-mentioned at least one set of instruction sets to: determine M initial allocation schemes based on the above-mentioned N target computing powers to allocate corresponding cores to the above-mentioned N data processing, wherein each of the above-mentioned initial allocation schemes satisfies that the computing power provided by each of the above-mentioned cores is greater than or equal to the sum of the computing powers required for the above-mentioned data processing, and M is an integer greater than or equal to 1; and based on the above-mentioned optimization purpose, determine the first target allocation scheme from the above-mentioned M initial allocation schemes to execute.

[0008] In some embodiments, in order to determine the above-mentioned M initial allocation schemes, the above-mentioned processing circuit executes the above-mentioned at least one set of instruction sets to: determine the target total computing power required to execute the above-mentioned target process based on the above-mentioned N target computing powers; determine the initial operating frequency of the above-mentioned K cores based on the above-mentioned target total computing power; determine the K available computing powers corresponding to the above-mentioned K cores respectively based on the above-mentioned initial operating frequency; and determine the M initial allocation schemes based on the above-mentioned N target computing powers and the above-mentioned K available computing powers.

[0009] In some embodiments, each of the above-mentioned M initial allocation schemes includes: at least one core participating in the above-mentioned target process, and the actual provided computing power of the above-mentioned at least one core participating in the above-mentioned target process and / or the actual operating frequency of the above-mentioned at least one core participating in the above-mentioned target process.

[0010] In some embodiments, in order to determine the distribution of the above-mentioned K cores in executing the above-mentioned N data processing, the above-mentioned processing circuit executes the above-mentioned at least one set of instruction sets to: based on a preset algorithm, according to the above-mentioned N target computing powers, the K available computing powers corresponding to the above-mentioned K cores and the above-mentioned optimization purpose, determine at least one core participating in the above-mentioned target process among the above-mentioned K cores, and determine the actual operating frequency of the above-mentioned at least one core participating in the above-mentioned target process.

[0011] In some embodiments, the optimization purpose is to select an allocation scheme in which the target statistical value of the K cores actually providing computing power is minimized from a plurality of optional allocation schemes, where the statistical value is the variance or standard deviation.

[0012] In some embodiments, the optimization objectives include: maintaining the lowest overall power consumption and / or the most balanced load of the K cores.

[0013] In some embodiments, the processing circuit also executes at least one set of instruction sets to: determine that the K cores have insufficient computing power during the execution of the target; and increase the operating frequency of the K cores to increase the computing power provided by the sub-processor to avoid data processing stalls.

[0014] In some embodiments, the processing circuit further executes the at least one set of instruction sets to: determine, during the execution of the target, that there are O cores among the K cores that have insufficient computing power, where O is a positive integer not greater than K; and increase the operating frequency of the O cores to increase the computing power of the qth core to avoid stalls in the data processing process.

[0015] In some embodiments, the insufficient computing power includes: the computing power occupancy rate of any one of the K cores exceeds a first threshold.

[0016] In some embodiments, the processing circuit further executes the at least one set of instruction sets to: determine, during the execution of the target process, whether there is an idle core among the K cores whose computing power occupancy rate is less than a second threshold, and stop the idle core from performing corresponding data processing; determine L reallocation schemes based on the N target computing powers and at least one working core among the K cores other than the idle core, wherein under each of the reallocation schemes, the total computing power provided by the at least one working core is greater than or equal to the total computing power required to execute the target process, and L is an integer greater than or equal to 1; and

[0017] Based on the above optimization purpose, a second target allocation scheme is determined from the above L reallocation schemes, and the computing power of the above at least one working core in executing the above N data processing is allocated through the above second target allocation scheme.

[0018] In some embodiments, in order to achieve the above-mentioned optimization goal, the above-mentioned processing circuit also executes the above-mentioned at least one set of instruction sets to: in the process of executing the above-mentioned goal, determine that the computing power provided by the p-th core for the j-th data processing is insufficient; determine that the q-th core from the above-mentioned K cores provides computing power for the above-mentioned j-th data processing; and transfer the execution of the above-mentioned j-th data processing from the above-mentioned p-th core to the above-mentioned q-th core.

[0019] In some embodiments, the processing circuit further executes the at least one set of instruction sets to: before transferring the execution of the j-th data processing from the p-th core to the q-th core, increase the operating frequency of the q-th core to increase the computing power of the q-th core to avoid data processing stalls.

[0020] In some embodiments, the processing circuit further executes the at least one set of instruction sets to: in the process of executing the above-mentioned target, determine that there are R cores among the above-mentioned K cores that have insufficient computing power, where R is a positive integer not greater than K; in the case that there are idle cores among the above-mentioned K cores whose computing power occupancy rate is less than a second threshold, transfer at least part of the data processing corresponding to the above-mentioned R cores to the above-mentioned idle cores, wherein after the transfer, the computing power that can be provided by each of the above-mentioned cores is greater than or equal to the sum of the computing power required for the corresponding data processing.

[0021] In some embodiments, the at least one storage medium is also associated with storing: attributes of the target data and target computing power corresponding to at least one data processing of the target data; in order to determine the N target computing powers corresponding to the N data processings, the processing circuit executes the at least one set of instruction sets to: search the at least one storage medium according to the attributes of the obtained target data, and obtain the N target computing powers corresponding to the N data processings of the target data.

[0022] In some embodiments, the processing circuit executes the at least one set of instruction sets to: calculate the N target computing powers required for the N data processing steps of the target data of the target attribute when the at least one storage medium does not store the N target computing powers corresponding to the N data processing steps of the target data of the target attribute; and associate the N target computing powers corresponding to the N data processing steps of the target data of the target attribute with the target attribute and store them in the at least one storage medium.

[0023] In some embodiments, the at least one storage medium further stores: for multiple attributes of the target data, the kernel identifications for processing the target data of each attribute and providing computing power for the N data processing respectively; in order to determine the distribution of the K kernels in executing the N data processing respectively, the processing circuit executes the at least one set of instruction sets to: search the at least one storage medium according to the target attributes of the obtained target data, and obtain the kernel identifications for processing the target data of the target attributes and providing computing power for the N data processing respectively, thereby determining the distribution of the K kernels in executing the N data processing respectively.

[0024] In some embodiments, the data processing device is a headset.

[0025] In the second aspect, the present application provides a data processing method, including: obtaining target data, determining N target computing powers corresponding to N data processings, and in the target process, according to the above-mentioned N target computing powers and preset optimization purposes, determining the distribution of K cores in the multi-core processor participating in the above-mentioned target process in executing the above-mentioned N data processings, where K is an integer greater than 1; wherein the above-mentioned target process is the process of generating result data by subjecting the above-mentioned target data to the above-mentioned N data processings.

[0026] In some embodiments, the above-mentioned determination of the allocation of the above-mentioned K cores in executing the above-mentioned N data processing includes: based on the above-mentioned N target computing powers, determining M initial allocation schemes to allocate corresponding cores to the above-mentioned N data processing, wherein each of the above-mentioned initial allocation schemes satisfies that the computing power provided by each of the above-mentioned cores is greater than or equal to the sum of the computing powers required for the corresponding data processing, and M is an integer greater than or equal to 1; and based on the above-mentioned optimization purpose, determining a first target allocation scheme from the above-mentioned M initial allocation schemes to execute.

[0027] In some embodiments, determining the M initial allocation schemes includes: determining the target total computing power required to execute the target process based on the N target computing powers; determining the initial operating frequencies of the K cores based on the target total computing power; determining the K available computing powers corresponding to the K cores based on the initial operating frequencies; and determining the M initial allocation schemes based on the N target computing powers and the K available computing powers.

[0028] In some embodiments, each of the above-mentioned M initial allocation schemes includes: at least one core participating in the above-mentioned target process, and the actual provided computing power of the above-mentioned at least one core participating in the above-mentioned target process and / or the actual operating frequency of the above-mentioned at least one core participating in the above-mentioned target process.

[0029] In some embodiments, in order to determine the distribution of the above-mentioned K cores in executing the above-mentioned N data processing, the above-mentioned processing circuit executes the above-mentioned at least one set of instruction sets to: based on a preset algorithm, according to the above-mentioned N target computing powers, the K available computing powers corresponding to the above-mentioned K cores and the above-mentioned optimization purpose, determine at least one core participating in the above-mentioned target process among the above-mentioned K cores, and determine the actual operating frequency of the above-mentioned at least one core participating in the above-mentioned target process.

[0030] In some embodiments, the optimization purpose is to select an allocation scheme in which the target statistical value of the K cores actually providing computing power is minimized from a plurality of optional allocation schemes, where the statistical value is the variance or standard deviation.

[0031] In some embodiments, the optimization objectives include: maintaining the lowest overall power consumption and / or the most balanced load of the K cores.

[0032] In some embodiments, the above method also includes: determining that the above K cores have insufficient computing power during the execution of the above target; and increasing the operating frequency of the above K cores to increase the computing power provided by the above sub-processors to avoid data processing jams.

[0033] In some embodiments, the above method also includes: in the process of executing the above goal, determining that there are O cores among the above K cores that have insufficient computing power, where O is a positive integer not greater than K; and increasing the operating frequency of the above O cores to increase the computing power of the above qth core to avoid data processing process jams.

[0034] In some embodiments, the insufficient computing power includes: the computing power occupancy rate of any one of the K cores exceeds a first threshold.

[0035] In some embodiments, the above method also includes: in the process of executing the above target, determining that there is an idle core among the above K cores whose computing power occupancy rate is less than a second threshold, and stopping the above idle core from performing corresponding data processing; determining L reallocation schemes based on the above N target computing powers and at least one working core other than the above idle core among the above K cores, wherein under each of the above reallocation schemes, the total computing power provided by the above at least one working core is greater than or equal to the total computing power required to execute the above target process, and L is an integer greater than or equal to 1; and determining a second target allocation scheme among the above L reallocation schemes based on the above optimization purpose, and allocating the computing power of the above at least one working core in executing the above N data processing through the above second target allocation scheme.

[0036] In some embodiments, the method further includes: during execution of the target, determining that the computing power provided by the p-th core for the j-th data processing is insufficient; determining that the q-th core from the K-th cores provides computing power for the j-th data processing; and transferring execution of the j-th data processing from the p-th core to the q-th core.

[0037] In some embodiments, the above method also includes: before transferring the execution of the above j-th data processing from the above p-th core to the above q-th core, increasing the operating frequency of the above q-th core to increase the computing power of the above q-th core to avoid data processing process jams.

[0038] It can be seen from the above technical solutions that the data processing device and method provided by the present application, wherein the processing circuit includes a multi-core processor, and the multi-core processor includes K core sub-processors for participating in the target process of processing the target data through N data processing to generate result data. Specifically, the processing circuit obtains the above target data, and determines the N target computing powers corresponding to the above N data processing, and in the above target process, determines the allocation of the above K cores in executing the above N data processing according to the above N target computing powers and the preset optimization purpose. It can be seen that the solution provided by the present application can determine the computing power provided by the K cores for the N data processing respectively during the operation of the data processing device, and adaptively allocate the corresponding target computing power to each data processing, which is conducive to improving the flexibility of computing power allocation.

[0039] Other features of the data processing devices and methods provided in this specification are partially outlined in the following description. Based on the description, the following figures and examples will be readily apparent to those skilled in the art. The inventive aspects of the data processing devices and methods provided in this specification can be fully explained by practicing or using the methods, apparatuses, and combinations described in the following detailed examples. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of this specification, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] FIG1 is a schematic diagram showing an application scenario provided according to an embodiment of the present application;

[0042] FIG2 shows a schematic structural diagram of a data processing device provided according to an embodiment of the present application;

[0043] 3A-3C respectively show a schematic structural diagram of a processing circuit provided according to an embodiment of the present application;

[0044] FIG4 shows a flow chart of a data processing method according to an embodiment of the present application;

[0045] FIG5 shows a schematic flow chart of a method for initial allocation of computing power according to an embodiment of the present application;

[0046] FIG6 shows a flow chart of a data processing method according to an embodiment of the present application;

[0047] FIG7 shows a schematic flow chart of a method for initial allocation of computing power according to an embodiment of the present application;

[0048] FIG8 shows a schematic diagram illustrating the relationship between the operating frequency of a processor core and the power consumption of the processor, and a schematic diagram illustrating the relationship between the number of operating cores of a processor and the power consumption of the processor according to an embodiment of the present application;

[0049] FIG9 is a flow chart showing a method for reallocating computing power in the event of insufficient computing power according to an embodiment of the present application;

[0050] FIG10 shows a flow chart of a method for redistributing computing power in the case of excess computing power according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] The following description provides specific application scenarios and requirements for this specification, with the goal of enabling those skilled in the art to make and use the contents of this specification. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this specification. Therefore, this specification is not limited to the embodiments shown, but is intended to be accorded the broadest scope consistent with the claims.

[0052] The terms used herein are for the purpose of describing specific example embodiments only and are not intended to be limiting. For example, as used herein, the singular forms "a," "an," and "the" may also include the plural forms unless the context clearly indicates otherwise. When used in this specification, the terms "comprise," "include," and / or "contain" are intended to refer to the presence of the associated integers, steps, operations, elements, and / or components, but do not preclude the presence of one or more other features, integers, steps, operations, elements, components, and / or groups or the addition of other features, integers, steps, operations, elements, components, and / or groups in the system / method.

[0053] These and other features of this specification, as well as the operation and function of the associated elements of the structure, and the economical assembly and manufacture of the components, can be significantly improved with consideration of the following description. Reference is made to the accompanying drawings, all of which form a part of this specification. However, it should be expressly understood that the drawings are for illustration and description purposes only and are not intended to limit the scope of this specification. It should also be understood that the drawings are not drawn to scale.

[0054] The flowcharts used in this specification illustrate operations implemented by systems according to some embodiments of the present specification. It should be clearly understood that the operations of the flowcharts may not be implemented in sequence. Rather, the operations may be implemented in reverse order or simultaneously. Furthermore, one or more additional operations may be added to the flowcharts. One or more operations may be removed from the flowcharts.

[0055] The data processing device provided in the embodiments of the present application can be used for audio data processing, video data processing, text data processing, code processing, etc., and the embodiments of the present application do not limit this. Similarly, the data processing method provided in the embodiments of the present application is not limited to the audio data processing process, video data processing process, text data processing process, code processing process, etc. Taking the data processing device performing audio signal processing as an example, the above-mentioned data processing device can be a speaker for voice playback or various devices equipped with a speaker (such as headphones, speakers, televisions, smart phones, smart home devices, etc.), and can also be used for a microphone for voice reception or various devices equipped with a microphone (such as headphones, smart phones, phone watches, smart home devices, etc.). It can be understood that it can also be a device that includes both a microphone and a speaker, such as headphones, smart phones, etc. In the embodiments of the present application, the data processing device is explained by taking headphones as an example.

[0056] FIG1 is a schematic diagram of an application scenario provided according to an embodiment of the present application. In this embodiment, the data processing device takes a wireless headset 120 as an example, which is a device for performing audio signal processing. Referring to FIG1 , the scenario shown is a call scenario 001 after the electronic device 110 and the wireless headset 120 are connected in communication. It is understandable that the solution provided by the present application can also be applied to other scenarios in which a data processing device is used to transmit and receive audio, such as listening to music through headphones, listening to dialogue while watching a video, etc.

[0057] The electronic device 110 may be a handheld device, an in-vehicle device, a wearable device, a computing device, or other device connected to a wireless modem. The electronic device 110 may include a smartphone, a cellular phone, a tablet computer, a personal digital assistant (PDA), a laptop computer, an in-vehicle computer, a smart watch, a smart wristband, a pedometer, and other electronic devices with a call function. In the embodiments of the present application, a headset is used as an example of a wireless communication device. Headphones can generally be divided into wired headsets (wired headsets) and wireless headsets. Wired headsets are plugged into a jack of an electronic device via a cable to communicate with the electronic device. Wireless headsets communicate with the electronic device 110 using wireless communication technologies (e.g., Bluetooth, infrared radio frequency, 2.4G wireless technology, ultrasound, etc.). Referring to the call scenario 001 shown in FIG1 , the wireless headset 120 is connected to the electronic device 110 via Bluetooth.

[0058] Referring to S1 shown in FIG1 , the wireless headset 120 can serve as a receiving end for audio signals. The speaker of the wireless headset 120 receives the audio signal emitted by the electronic device 110 during a call, and performs a series of processing (e.g., digital-to-analog conversion, signal amplification, etc.) on the received audio signal before converting it into sound waves that the user can hear. Referring to S2 shown in FIG1 , the wireless headset 120 can serve as a transmitting end for audio signals. The microphone of the wireless headset 120 receives the audio signal emitted by the user during a call, and performs a series of processing (e.g., analog-to-digital conversion (ADC) sampling, noise reduction processing, Bluetooth SBC, and Bluetooth radio frequency) on the received audio signal before sending it to the electronic device 110.

[0059] With the expansion of application scenarios, data processing methods have gradually diversified, such as audio signal mixing, resampling modules, Advanced Audio Coding (AAC) encoding and decoding, echo cancellation, noise suppression, etc. At the same time, the computing power required for audio signal processing continues to increase, so the cores used for audio signal processing in the chip of the data processing device are generally set to multiple. In the related art, the data processing that each core is responsible for is generally planned in advance. For example, core 1 provides computing power for sampling and noise reduction, core 2 provides computing power for Bluetooth SBC and Bluetooth radio frequency, core 3 provides computing power for echo cancellation, and so on. However, the above-mentioned computing power allocation method provided by the related art has the problem of inflexible computing power allocation, resulting in insufficient utilization of core computing power and / or insufficient core computing power. For example, core 1 is planned in advance to provide computing power for sampling and noise reduction. However, there is a situation where the computing power required for sampling and noise reduction of audio a is greater than the total computing power that core 1 can provide, that is, there is a problem of insufficient computing power of core 1; for another example, core 3 is planned in advance to provide computing power for echo cancellation, but there is a situation where audio a does not need echo cancellation, that is, there is a problem of insufficient computing power utilization of core 3.

[0060] FIG2 shows a schematic diagram of a data processing device according to an embodiment of the present application. The data processing device 002 can be used for audio data processing, video data processing, text data processing, and the like. For example, an audio data processing device can be a wired headset or a wireless headset. The data processing device 002 can be used in the call scenario shown in FIG1 . It is understood that the data processing device 002 can also be used in other scenarios where audio is transmitted and received using an audio communication device.

[0061] 2 , the data processing device 002 may include: at least one storage medium 210, wherein the storage medium 210 may be a non-transitory storage medium or a temporary storage medium. For example, the data storage device may include: one or more of: Flash Memory 2100, a disk 2101, a read-only memory (ROM) 2102, and a random access memory (RAM) 2103. The above storage includes at least one set of instruction sets, which include instructions. The above instructions are computer program code. The computer program code may include programs, routines, objects, components, data structures, processes, modules, etc. for executing the data processing methods provided in the embodiments of the present application. Specifically, the at least one set of instruction sets stored in the storage medium 210 is used to schedule computing power during the data processing process. It should be noted that in the embodiments of the present application, the data processing process of generating result data through N data processing steps on the target data is referred to as the target process, where N is an integer greater than 1. That is, at least one set of instruction sets stored in the storage medium 210 is used to provide computing power for N data processing steps in the above target process.

[0062] 2 , the data processing device 002 further includes a processing circuit 220. The processing circuit 220 is configured to determine or adjust the computing power allocation for the N data processing steps during the target process. Specifically, when the data processing device 002 is running, the processing circuit 220 reads at least one set of instruction sets stored in the storage medium 210 to obtain target data, determine the N target computing powers corresponding to the N data processing steps, and determine or adjust the computing power allocation for the N data processing steps during the target process. In some embodiments, further, when the data processing device 002 is running, the processing circuit 220 reads at least one set of instruction sets stored in the storage medium 210 to execute the N data processing steps, thereby processing the target data into result data.

[0063] Specifically, the processing circuit 220 includes a multi-core processor 220-A, which is used to provide computing power for N data processing channels in the above-mentioned target process. More specifically, the K cores of the sub-processor 240 included in the multi-core processor 220-A are used to provide computing power for N data processing channels in the above-mentioned target process, where K is an integer greater than 1. It is understood that the above-mentioned K cores can be all cores of the sub-processor 240, or can also be some cores of the sub-processor 240, and this embodiment of the application is not limited to this. Among them, the multi-core processor 220-A can be: a quad-core processor, an octa-core processor, etc., and this embodiment of the application does not limit the number of cores. The embodiments of the present application do not limit the type of the multi-core processor 220-A. Specifically, the types of the multi-core processor 220-A may include, for example: central processing unit (CPU), graphics processing unit (GPU), physical processing unit (PPU), microcontroller unit, digital signal processor (DSP), field programmable gate array (FPGA), programmable logic device (PLD), microcontroller, microprocessor, reduced instruction set computer (RISC), advanced RISC machine (ARM), application specific integrated circuit (ASIC), that is, the multi-core processor 220-A is any circuit or processor that can perform one or more functions, or any combination thereof.

[0064] Specifically, the processing circuit 220 is in communication with the storage medium 210. Referring to FIG2 , in some embodiments, the data processing device 002 may further include an internal communication bus 230, which may connect different system components in the data processing device 002. For example, the processing circuit 220 may be connected to the storage medium 210 via the internal communication bus 230, so that the processing circuit 210 can read at least one set of instructions in the storage medium 210 to obtain target data, determine the N target computing powers corresponding to the N data processing steps, and determine or adjust the computing power allocation for the N data processing steps during the target process, thereby adaptively providing the computing power of the K cores in the sub-processor 240 to the N data processing steps, thereby facilitating the improvement of the flexibility of computing power allocation of the data processing device.

[0065] FIG3A shows a schematic diagram of a structure of a processing circuit provided according to an embodiment of the present application. Referring to the processing circuit 003 shown in the figure, in some embodiments, specifically, the multi-core processor 220-A in the processing circuit 220 includes, in addition to the sub-processor 240 for providing computing power, a processor 220-B. The processor 220-B can be specifically used to read at least one set of instruction sets stored in the storage medium 210 to obtain target data, determine the N target computing powers corresponding to the above-mentioned N data processing, and determine or adjust the computing power allocation for the N data processing in the above-mentioned target process, and, after determining the computing power allocation in the above-mentioned target process, perform the above-mentioned N data processing, thereby processing the above-mentioned target data into result data.

[0066] FIG3B shows another structural diagram of a processing circuit provided according to an embodiment of the present application. Referring to the processing circuit 004 shown in the figure, in some embodiments, specifically, the processing circuit 220 includes, in addition to the multi-core processor 220-A, a processor 220-C independent of the multi-core processor 220-A. The processor 220-C can be specifically used to read at least one set of instruction sets stored in the storage medium 210 to obtain target data, determine the N target computing powers corresponding to the above-mentioned N data processing, and determine or adjust the computing power allocation for the N data processing in the above-mentioned target process, and, after determining the computing power allocation in the above-mentioned target process, perform the above-mentioned N data processing, thereby processing the above-mentioned target data into result data.

[0067] FIG3C shows another structural diagram of a processing circuit provided according to an embodiment of the present application. Referring to the processing circuit 005 shown in the figure, in some embodiments, specifically, the processing circuit 220 includes, in addition to the multi-core processor 220-A, a processor 220-C independent of the multi-core processor 220-A; at the same time, the multi-core processor 220-A includes, in addition to the sub-processor 240 for providing computing power, a processor 220-B. In this embodiment, the processor 220-C and / or the processor 220-B can be specifically used to read at least one set of instruction sets stored in the storage medium 210 to obtain target data, determine the N target computing powers corresponding to the above-mentioned N data processing, and determine or adjust the computing power allocation for the N data processing in the above-mentioned target process. After determining the computing power allocation in the above-mentioned target process, the above-mentioned N data processing is performed, thereby processing the above-mentioned target data into result data. That is to say, the above process of the data processing device can be implemented by processor 220-B alone, or by processor 220-C alone, or by processor 220-B and processor 220-C in a division of labor and cooperation.

[0068] The embodiments of the present application do not limit the types of processors 220-B and 220-C. They may be any of the types of processors described above, or a combination thereof. It is understood that the data processing device 002 shown in FIG2 illustrates a case where only one processor 220-B and one processor 220-C are included. However, it should be noted that the data processing device 002 provided in the embodiments of the present application may also include multiple processors 220-B and multiple processors 220-C.

[0069] It will be understood by those skilled in the art that the processing circuit 220 may also include other hardware circuit structures, which are not limited in the embodiments of the present application, as long as they can meet the functions mentioned in the present application without deviating from the spirit of the present application.

[0070] FIG4 shows a flow chart of a data processing method provided according to an embodiment of the present application. The data processing method P100 can be applied to the data processing device 002 as described above. Specifically, the processing circuit 220 can execute the data processing method P100. For example, the processor 220-B in the processing circuit 220 can execute the data processing method P100. As shown in FIG4 , the data processing method P100 may include: S410-S430, wherein the execution order of S410 and S420 is not particular, the processor 220-B may execute S410 first and then execute S420, the processor 220-B may also execute S420 first and then execute S410, and the processor 220-B may also execute S410 and S420 simultaneously, and the embodiment of the present application does not limit this.

[0071] S410: Obtain target data.

[0072] In some embodiments, processor 220 -B obtains target data.

[0073] In an exemplary embodiment, the target data is an audio signal to be processed by a data processing device. Specifically, it may be an original audio electrical signal received by the data processing device and not processed by the device, such as from an electronic device or a user. Specifically, processor 220-B determines the original audio signal from electronic device 110 or the user as the target data.

[0074] In another exemplary embodiment, for an audio signal processing operation, the "target data" is the intermediate audio signal to be processed. For example, if an audio signal undergoes ADC sampling and noise reduction processing, the target data for the noise reduction processing is the signal after ADC sampling. Similarly, if an audio signal undergoes noise reduction and Bluetooth SBC processing, the target data for the Bluetooth SBC processing is the signal after noise reduction. In some embodiments, after receiving a data processing execution command, processor 220-B determines an intermediate audio signal during the processing as the target data for the data processing to be executed.

[0075] That is to say, since the processing object of the data processing method provided in the embodiment of the present application can be the original audio electrical signal received by the data processing device and not processed by the data processing device, that is, the data processing device can perform the data processing method shown in Figure 4 on the received original audio signal; since the processing object of the data processing method provided in the embodiment of the present application can also be the intermediate audio signal after the audio processing device performs at least one audio signal processing after receiving the original audio electrical signal, that is, the data processing device can perform the data processing method shown in Figure 4 on the intermediate audio signal in the processing process. It can be seen that the data processing method provided in the embodiment of the present application has a wide range of applications and flexible application methods. It can be applied to original audio signals that have just been received and have not been processed, and can also be applied to intermediate audio signals in the processing process.

[0076] In S420 , N target computing powers corresponding to N data processing operations are determined.

[0077] Exemplarily, processor 220-B determines N target computing powers corresponding to performing N data processing operations.

[0078] When the processing object is the original audio signal, the N-channel data processing can refer to a series of processing performed on the original audio signal. For example, referring to Figure 1, the microphone of the wireless headset 120 receives the original audio signal sent by the user during a call. Further, the processor 220-B determines a series of processing for the original audio signal and the computing power required for each processing (i.e., target computing power). For example, if the series of processing for the original audio signal includes: ADC sampling, noise reduction processing, Bluetooth SBC, and Bluetooth radio, then in this embodiment, the target computing power p1 corresponding to ADC sampling, the target computing power p2 corresponding to noise reduction processing, the target computing power p3 corresponding to Bluetooth SBC, and the target computing power p4 corresponding to Bluetooth radio will be determined.

[0079] When the processing object is the intermediate audio signal, the N-channel data processing may refer to a series of processing operations performed on the intermediate audio signal. For example, referring to FIG1 , the microphone of the wireless headset 120 receives the original audio signal emitted by the user during a call and performs ADC sampling on the original audio signal. Furthermore, the processor 220-B determines a series of processing operations on the intermediate audio signal after ADC sampling and the computing power required for each processing operation (i.e., the target computing power). For example, if the series of processing operations on the intermediate audio signal after ADC sampling includes noise reduction processing, Bluetooth SBC processing, and Bluetooth radio frequency processing, then in this embodiment, the target computing power p2 for noise reduction processing, the target computing power p3 for Bluetooth SBC processing, and the target computing power p4 for Bluetooth radio frequency processing will be determined.

[0080] Among them, the computing power measurement indicators can be Million Instructions Per Second (MIPS), Dhrystone Million Instructions executed Per Second (DMIPS), Operations Per Second (OPS), Floating point Operations Per Second (FLOPS), or Hash Per Second (Hash / s), etc.

[0081] In an embodiment of the present application, the method in which the processor 220-B obtains the target computing power corresponding to the target channel data processing in the N channel data processing may be: determining the corresponding target computing power based on the actual operation of the above target channel data processing. Specifically, the processor 220-B may determine the actual time required to run the above target channel data processing on one core × MIPS during system initialization, thereby obtaining the precise value of the target computing power required to run each channel of data processing to process the target data. In an exemplary embodiment, the above storage medium 210 includes a storage area for "scheduling records". After determining the target computing power corresponding to the target data processed by the above target channel data processing, the above target channel primary processing may be associated with its corresponding target computing power and the attributes of the processed target data and stored in the above "scheduling record" storage area (as shown in Table 1).

[0082] Table 1

[0083] Taking an audio signal as an example, the attributes of the target data are related to the size of the space it occupies. For example, the attribute of the audio signal as the target data may be 16-bit, 32-bit, etc. Referring to Table 1, in some embodiments, the processor 220-B determines that the computing power required to run the above-mentioned ADC sampling process on one core to process a 16-bit audio signal is x1, and the processor 220-B determines that the computing power required to run the above-mentioned ADC sampling process on one core to process a 32-bit audio signal is x2.

[0084] In the embodiment of the present application, the target computing power shown in Table 1 can be determined by actually running each data processing channel, and can also be manually set during the system initialization process. For example, the computing power required for the above-mentioned ADC sampling process to process a 32-bit audio signal is set to x4, thereby providing a rich way to determine the target computing power corresponding to each data processing channel. It should be noted that for target data with the same attribute, the computing power required for the same data processing channel is certain. For example, the computing power required for the above-mentioned ADC sampling process to process a 32-bit audio signal recorded in the storage area of ​​the "scheduling record" of the storage medium 210 can only be x4, while the computing power required for the above-mentioned ADC sampling process to process a 32-bit audio signal when different ADC sampling processes exist at the same time can only be x4 and x5, so as to ensure the smooth execution of the data processing method.

[0085] In some embodiments, the target computing power required for each data processing channel can be determined by searching a storage area for "scheduling records" on a storage medium. Specifically, based on the attributes of the target data to be processed, the target computing power required for processing multiple channels of target data with the aforementioned attributes can be quickly obtained, thereby improving the processing efficiency of data (e.g., audio signals).

[0086] If the target computing power is not recorded in the "scheduling record" storage area, the processor 220-B cannot determine the target computing power by searching the "scheduling record" storage area. In some embodiments, another method is provided for the processor 220-B to obtain the target computing power corresponding to the target channel data processing in the N channel data processing:

[0087] Processor 220-B determines the required computing power for executing the target data processing by multiplying the length of the code segment corresponding to the target data processing by a coefficient, thereby obtaining the target computing power corresponding to the target data processing. The coefficient is related to the properties of the target data being processed and can be set based on actual needs, which is not limited in this embodiment of the present application. Furthermore, the calculated target computing power can be stored in the "scheduling record" storage area in the format shown in Table 1, thereby enriching the "scheduling record" storage area and facilitating subsequent searches for the target computing power.

[0088] Continuing to refer to FIG4 , S430 : in the target process, according to the N target computing powers and the preset optimization purpose, determining the allocation of the K cores in the multi-core processor participating in the target process in executing the N data processing.

[0089] As described above, the target process refers to the process of generating result data by subjecting the target data to the N data processing steps. In the embodiment provided herein, during the target process, processor 220-B determines the allocation of the K cores of the sub-processor to execute the N data processing steps based on the N target computing power and the preset optimization objective. It should be noted that the cores participating in the target process may be some of the K cores of the sub-processor, or may be all of the K cores.

[0090] FIG5 illustrates a schematic diagram of a processing circuit according to an embodiment of the present application. Referring to FIG5 , after obtaining the target data 500 and determining the N target computing power 510 corresponding to N data processing steps, the processing circuit 006 according to the embodiment of the present application further allocates the core computing power to smoothly execute the N data processing steps ( S30 ), and the processing circuit 220 (specifically, the processor 220-B) outputs the result data 520 .

[0091] For example, the N data processing paths for the target data can be considered a data processing link for the target data. Referring to FIG5 , the computing power executed by processing circuit 220 (specifically, processor 220-B) includes two allocation methods: initial computing power allocation S10 and computing power reallocation S20. Initial computing power allocation refers to allocating computing power to a data processing link that has not undergone computing power allocation, based on the computing power required for each data processing path in the data processing link and a preset optimization target, to achieve the optimization goal of maximizing overall power consumption and / or balancing the load of the sub-processors, while ensuring that each data processing path can be executed smoothly to enhance the user experience of the data processing device. After at least one computing power allocation has been performed, the computing power required for a data processing path in a data processing link may change, potentially resulting in insufficient or excessive computing power. Further computing power reallocation is required based on the changed computing power required for each data processing path and the preset optimization target. This can be understood as adjusting the current computing power allocation of the data processing link to maintain the optimization goal of maximizing overall power consumption and / or balancing the load of the sub-processors.

[0092] It should be noted that there may be a serial relationship in a data processing link for the target data. For example, when the above-mentioned target data is an audio signal, Bluetooth SBC is performed first and then Bluetooth RF. However, considering the timeliness of audio signal processing, the embodiment of the present application ensures that in the above-mentioned target process of a data processing link, sufficient computing power is continuously provided for all channel data processing, thereby ensuring the timeliness of audio signal processing and improving the user experience of the data processing device.

[0093] FIG6 shows a flow chart of a data processing method provided according to an embodiment of the present application. The data processing method P200 can be applied to the data processing device 002 as described above. Specifically, the processing circuit 220 can execute the data processing method P200. For example, the processor 220-B in the processing circuit 220 can execute the data processing method P200. As shown in FIG6 , S410 and S420 in the data processing method P200 are the same as the specific implementation of the data processing method P100 in FIG4 , and are not repeated here; in addition, a specific implementation of S430 is provided in the data processing method P200 shown in FIG6 , including S10, S610-S630.

[0094] S10: Execute the initial allocation of computing power.

[0095] 5 , after obtaining the target data 500 and determining the N target computing powers 510 corresponding to the N data processing steps, the processing circuit 220 (e.g., processor 220-B) further executes S10 to perform an initial allocation of computing power to determine a target allocation plan. Based on the target allocation plan, the processor 220-B allocates the computing power of the K cores to the N data processing steps, and then performs the N data processing steps.

[0096] FIG7 shows a flow chart of a method for initial allocation of computing power according to an embodiment of the present application. The method for initial allocation of computing power P300 can be used as an implementation of the method for initial allocation of computing power S10, and can be applied to the data processing device 002 as described above. Specifically, in order to determine the allocation of the above-mentioned K cores in executing the above-mentioned N-channel data processing, at least one set of instruction sets stored in the above-mentioned at least one storage medium corresponds to the method for initial allocation of computing power P300, wherein the processing circuit 220 can execute the method for initial allocation of computing power P300. For example, the processor 220-C in the processing circuit 220 can execute the method for initial allocation of computing power P300. As shown in FIG7 , the data processing method P300 may include: S1010-S1020.

[0097] S1010: Based on N target computing powers, determine M initial allocation schemes to allocate corresponding cores for N data processing, where each initial allocation scheme satisfies that the computing power provided by each core is greater than or equal to the sum of the computing powers required for its corresponding data processing, and M is an integer greater than or equal to 1.

[0098] Exemplarily, in order to determine the above-mentioned M initial allocation schemes, at least one set of instruction sets stored in the above-mentioned at least one storage medium specifically includes: S1. Determine the target total computing power required to execute the above-mentioned target process based on the above-mentioned N target computing powers; S2. Determine the initial operating frequency of the above-mentioned K cores based on the above-mentioned target total computing power and the number K of cores providing computing power; S3. Determine the K available computing powers corresponding to the above-mentioned K cores respectively based on the above-mentioned initial operating frequency; and S4. Determine the above-mentioned M initial allocation schemes based on the above-mentioned N target computing powers and the K available computing powers.

[0099] Each of the M initial allocation schemes includes: at least one core participating in the target process, and the actual computing power provided by the at least one core participating in the target process and / or the actual operating frequency of the at least one core participating in the target process. In each initial allocation scheme, the maximum number of cores participating in the target process is K. Exemplarily, in one initial allocation scheme, the operating frequencies of all cores participating in the target process may be the same (such as the initial operating frequency). Of course, the operating frequencies of different cores participating in the target process may also be the same.

[0100] Specifically, the processor 220-B in the processing circuit 220 can execute the above steps S1-S4. Taking the data processing link of the audio signal received by the microphone of the wireless headset 120 during a call as an example, the processor 220-B determines the target computing power corresponding to each data processing channel through the aforementioned embodiment: target computing power p1 for ADC sampling, target computing power p2 for noise reduction processing, target computing power p3 for Bluetooth SBC, and target computing power p4 for Bluetooth RF. Then, the processor 220-B can determine the target total computing power required for the data processing link: P = p1 + p2 + p3 + p4. It can be understood that the factors affecting the FLOPS of computing power include: the number of cores of the sub-processor providing computing power, the operating frequency of a single core, and the floating-point calculation value of a single cycle of the sub-processor. During the initial allocation of computing power, if the initial operating frequencies of the cores in the sub-processor are consistent, and since the target total computing power P required by the data processing link, the number of cores K providing computing power for the sub-processor, and the floating-point calculation value of a single cycle of the sub-processor are known, the initial operating frequency of the above K cores can be determined, assuming it is f0.

[0101] Furthermore, the processor 220-B determines the computing power that each core can provide based on the initial operating frequency f0. The computing power that each core can provide is: f0×the floating-point calculation value of a single cycle of the sub-processor. The processor 220-B can determine M initial allocation schemes (as shown in Table 2) based on the target computing powers p1, p2, p3, and p4 required for N data processing, and the computing power that K (assuming the value is 3) cores can provide. In this embodiment, each initial allocation scheme includes: the core identifier participating in the above target process, and the actual computing power provided by each core participating in the above target process when the operating frequency is f0.

[0102] Table 2

[0103] It should be noted that to ensure the smooth execution of the audio processing process, each initial allocation scheme ensures that the computing power provided by each core is greater than or equal to the sum of the computing power required by the target process, and that the computing power provided by each core is greater than or equal to the actual computing power provided. For example, referring to Table 2, in Initial Allocation Scheme 1, the computing power provided by Core 1 is greater than the actual computing power provided by p1 + p2, the computing power provided by Core 2 is greater than the actual computing power provided by p3, and the computing power provided by Core 3 is greater than the actual computing power provided by p4.

[0104] Continuing to refer to FIG. 7 , S1020 : Based on the optimization purpose, a first target allocation scheme is determined from the M initial allocation schemes to be executed.

[0105] In this embodiment, the first target allocation scheme determined based on the above-mentioned optimization purpose specifically refers to selecting an allocation scheme with the smallest target statistical value of the K cores actually providing computing power among the above-mentioned K cores from among the optional multiple initial allocation schemes, wherein the above-mentioned statistical value is the variance or standard deviation. Alternatively, the first target allocation scheme determined based on the above-mentioned optimization purpose specifically refers to the first target scheme selected from the optional multiple initial allocation schemes that can maintain the lowest overall power consumption and / or the most balanced load of the K cores providing computing power in the sub-processor. Through the above-mentioned optimization goal, a first target allocation scheme that meets the above-mentioned optimization goal can be determined from the above-mentioned M initial allocation schemes, and computing power allocation is performed based on the selected first target scheme. If, based on the above optimization objectives, the first target allocation scheme determined from the multiple initial allocation schemes shown in Table 2 is Initial Allocation Scheme 3, then core 1 provides computing power for Bluetooth SBC, core 2 provides computing power for ADC sampling, and core 3 provides computing power for noise reduction processing and Bluetooth radio. Compared to the other initial matching schemes shown in Table 2, the actual computing power provided by the three cores in Initial Allocation Scheme 3 is p3, p1, and p2 + p4, respectively, which have the lowest statistical value. Alternatively, compared to the other initial matching schemes shown in Table 2, the actual computing power provided by the three cores in Initial Allocation Scheme 3 is p3, p1, and p2 + p4, respectively. In this case, the overall power consumption of the K cores providing computing power in the sub-processor can be minimized and / or the load can be balanced.

[0106] In an exemplary embodiment, the storage medium 210 includes a storage area for "scheduling records." After determining the first target allocation plan, information related to the first target allocation plan may be stored in the "scheduling records" storage area. For example, referring to Table 3, information related to the first target allocation plan stored in the "scheduling records" storage area may include information such as the relationship between each data processing channel in the data processing chain and the core providing computing power for it, the attributes of the target data processed by the data processing chain, and the identifier of the data processing chain.

[0107] Table 3

[0108] It should be noted that after computing power is redistributed for data processing link s1, if the relevant information of the target allocation plan changes, the relevant information of the target allocation plan obtained after the computing power redistribution is used to update the record of the link in the "scheduling record" storage area. This can serve as another implementation of the initial computing power allocation S10. When subsequently allocating computing power to data processing link s1, the computing power allocation plan can be determined by simply searching the above-mentioned scheduling record, which is beneficial for improving the processing efficiency of data (such as audio signals).

[0109] In summary, one implementation method for allocating computing power to the data processing link s1 can be to first determine the initial allocation scheme and then select from the initial allocation scheme as in the above embodiment; another implementation method for allocating computing power to the data processing link s1 is to determine it by searching the table shown in Table 3 in the storage medium. At the same time, the embodiment of this specification also provides another implementation method for allocating computing power to the data processing link s1: based on a preset algorithm, and with the above optimization target as a constraint condition, according to the above N target computing powers and the K available computing powers corresponding to the above K cores, calculations are performed to determine at least one core participating in the above target process among the K cores, and to determine the actual operating frequency of at least one core participating in the above target process. Among them, the above preset algorithm is any algorithm that can implement the above process, and the embodiment of this application does not limit this.

[0110] Referring again to FIG6 , after executing the initial computing power allocation in S10 or after executing a certain computing power redistribution, during the above-mentioned target process, the processing circuit (e.g., processor 220-B) also obtains monitoring results. In the exemplary embodiment of the present application, at least one of the following multiple monitoring methods is executed so that the processing circuit (e.g., processor 220-B) can obtain the monitoring results and then determine whether the computing power allocation needs to be adjusted. The aforementioned multiple monitoring methods include: 1) During the target process, monitoring the computing power required for each data processing channel by the processing circuit 220 (for example, specifically, the processor 220-B) to determine whether the computing power required for each data processing channel has changed. Specifically, each data processing channel provides a monitoring interface for monitoring and outputting the current input data volume, current output data volume, and current processed data volume of the data processing channel, thereby determining whether the computing power required for the data processing channel has changed; 2) During the target process, monitoring whether "frame missing" occurs by hardware such as Direct Memory Access (DMA); 3) During the target process, monitoring the occupancy of the K cores that provide computing power by the processing circuit 220 (for example, specifically, the processor 220-B). The occupancy of a core can be determined by the following formula.

[0111] The monitoring method provided by the above embodiment can determine in real time whether the computing power required for N-channel data processing has changed, thereby dynamically determining whether computing power redistribution is necessary, thereby achieving the lowest power consumption of the device while ensuring that data (such as audio signals) is processed smoothly. The computing power required for N-channel data processing in the data processing chain may increase or decrease, so it is necessary to determine whether computing power redistribution is necessary based on the monitoring results. Specifically referring to FIG5 , if the computing power required for N-channel data processing remains unchanged during the target process, the processing circuit 220 can perform computing power allocation based on the initial computing power allocation (i.e., S10), and result data 520 can be obtained. If the computing power required for N-channel data processing changes during the target process, it is necessary to determine whether computing power redistribution is necessary based on the monitoring results. If computing power redistribution is necessary (i.e., executing S20), the computing power redistribution scheme to be implemented is determined based on the above monitoring results.

[0112] The monitoring results of the above-mentioned monitoring method 1) include: in the above-mentioned target process, if the computing power required for the i-th (i is 1, 2, ..., N) channel data processing changes, and it is further determined that the core providing computing power for the i-th channel data processing is the j-th (j is 1, ..., K) core, the method for determining whether the j-th core has insufficient computing power is: if the audio processing provided by the j-th core is the i-th and i+1-th channels, further, based on the changed required computing power for the i-th channel data processing and the changed required computing power for the i+1-th channel data processing, the occupancy rate of the j-th core is determined; if the occupancy rate is greater than a first threshold value (e.g., 80%), the core providing computing power for the channel data processing may have insufficient computing power; if the occupancy rate is less than a second threshold value (e.g., 40%), the core providing computing power for the channel data processing may have excess computing power.

[0113] The monitoring results of the above-mentioned monitoring method 2) include: during the above-mentioned target process, there is no "missing frame" phenomenon, indicating that all cores providing computing power in the data processing link do not have insufficient computing power, that is, the current target allocation plan for the data processing link can be maintained; during the above-mentioned target process, there is a "missing frame" phenomenon, indicating that at least one core providing computing power in the data processing link has insufficient computing power, and in order to avoid the user having a poor experience of audio stuttering, computing power needs to be redistributed. Among them, the specific implementation method of computing power redistribution will be detailed in subsequent embodiments.

[0114] The monitoring results of the above-mentioned monitoring method 3) include: in the above-mentioned target process, if the kernel occupancy rate of any of the K kernels is greater than the first threshold value (such as 80%), it means that the kernel has insufficient computing power; in the above-mentioned target process, if the kernel occupancy rate of any of the K kernels is less than the second threshold value (such as 40%), it means that the kernel has excess computing power. In order to avoid the user's poor experience of audio stuttering in the event of insufficient computing power, and to optimize the computing power allocation in the event of excess computing power, computing power redistribution is required. Among them, the specific implementation method of computing power redistribution will be introduced in detail in subsequent embodiments.

[0115] According to the above monitoring results, the following situations may exist in the above target process: Situation 1: There are cores with insufficient computing power but no cores with excess computing power, Situation 2: There are cores with both insufficient computing power and excess computing power, Situation 3: There are cores with excess computing power but no cores with insufficient computing power, and Situation 4: There are neither cores with insufficient computing power nor cores with excess computing power (it is possible that the computing power required for accessing N channels of data processing does not change, or the occupancy rate of each core remains within the preset range after the change).

[0116] Since the existence of a kernel with insufficient computing power may affect the smooth execution of N-channel data processing, in order to avoid data (such as audio signal) processing jams, priority is given to the situation where a kernel with insufficient computing power exists (i.e., situation 1 and situation 2). Referring again to Figure 6, execute S620: determine whether there is a kernel with insufficient computing power based on the monitoring results. If so, execute embodiment A, or execute embodiment B, or execute embodiment C, or execute embodiment D. The following embodiments will respectively introduce embodiment A, embodiment B, embodiment C, and embodiment D in detail.

[0117] If it is determined that at least one core has insufficient computing power, the operating frequency of sub-processor 240 is increased to ensure a user experience of the data processing device and to avoid data (such as audio signal processing) lags. Specifically, the following two implementations (i.e., Embodiment A and Embodiment B) are provided for increasing the operating frequency of the sub-processor.

[0118] In exemplary embodiment A for solving the problem of insufficient computing power of at least one core, when it is determined that there is insufficient computing power of at least one core, the operating frequency of the above-mentioned K cores is increased to increase the computing power provided by the above-mentioned sub-processor 240 as a whole, thereby quickly solving the problem of lag in the data (such as audio signal) processing process.

[0119] In exemplary embodiment B for solving the problem of insufficient computing power of at least one core, when it is determined that there is insufficient computing power of at least one core, the core with insufficient computing power is further located, and the operating frequency of the core with insufficient computing power is further increased to specifically improve the computing power provided by the relevant core in the above-mentioned sub-processor 240, thereby being able to solve the problem of data (such as audio signal) processing jamming while avoiding excessive power consumption of the data processing device.

[0120] It can be understood that if the core with insufficient computing power can be accurately located (such as the monitoring results of monitoring method 1) or the monitoring results of monitoring method 3), then exemplary embodiment B for solving the problem of insufficient computing power of at least one core can be executed, so as to solve the problem of data (such as audio signal) processing jamming while avoiding excessive power consumption of the data processing device.

[0121] It is understandable that if the core with insufficient computing power cannot be accurately located (e.g., the monitoring result of monitoring method 2 is a "missing frame" phenomenon), then exemplary embodiment A for resolving insufficient computing power of at least one core is executed to quickly resolve the problem of data (such as audio signal) processing stalls. Of course, using exemplary embodiment A for resolving insufficient computing power of at least one core has the problem of power consumption optimization, but the problem of excessive computing power of at least one core can be resolved by executing exemplary embodiment E, which will be described in detail below.

[0122] FIG8 shows a schematic diagram illustrating the relationship between the operating frequency of a processor core and processor power consumption, as well as a schematic diagram illustrating the relationship between the number of operating cores and processor power consumption, according to an embodiment of the present application. Referring to the relationship diagram 007, the four curves from bottom to top represent the cases of 1 to 4 operating cores, respectively. It can be seen that the operating frequency of the cores in the processor is positively correlated with the processor power consumption, and the number of operating cores in the processor is also positively correlated with the processor power consumption. According to the aforementioned embodiments A and B, when it is determined that at least one core has insufficient computing power, the computing power that can be provided by the core is increased by increasing the core frequency, thereby ensuring the user experience of the data processing device. However, according to the relationship diagram 007 shown in FIG8, increasing the core operating frequency in the aforementioned embodiments A and B may cause the data processing device to have excessive power consumption. In order to avoid excessive power consumption of the data processing device, in the case of insufficient computing power, a computing power redistribution scheme as shown in FIG9 can also be adopted.

[0123] FIG9 illustrates a flow chart of a method for reallocating computing power in the event of insufficient computing power, according to an embodiment of the present application. This computing power reallocation method P400 can serve as exemplary embodiment C for resolving insufficient computing power in at least one core and can be applied to the data processing device 002 described above. The processing circuit 220 can execute P400 in the event of insufficient computing power. For example, the processor 220-B in the processing circuit 220 can execute the computing power reallocation method P400. As shown in FIG9 , the data processing method P400 may include steps S2010-S2030.

[0124] S2010: Determine that the computing power provided by the p-th core for processing the j-th data channel is insufficient.

[0125] In some embodiments, processor 220-B may determine, based on the monitoring results of monitoring method 1) or the monitoring results of monitoring method 3), that the occupancy rate of the second core is 91%, indicating that the second core has insufficient computing power. The second core provides computing power for both the first and third data processing channels. If the occupancy rate of the second core, which provides computing power only for the first data processing channel, is less than a first threshold, and if the occupancy rate of the second core, which provides computing power only for the third data processing channel, is still greater than the first threshold, then it may indicate that the computing power provided by the second core for the third data processing channel is insufficient.

[0126] In this embodiment, processor 220-B may move the third data processing channel from the second core to another core, i.e., adjust the processor 220-B to provide computing power for the third data processing channel using cores other than the second core. This allows the second core to provide computing power only for the first data processing channel, thereby ensuring the smooth execution of the first data processing channel. Specifically, S2020 may be performed: determining the qth core from the K cores to provide computing power for the jth data processing channel, and S2030 may be performed: transferring execution of the jth data processing channel from the pth core to the qth core.

[0127] Specifically, processor 220-B calculates, based on the current occupancy rates of cores other than the second core and the target computing power required for the third data processing channel, which core's occupancy would be less than a first threshold if computing power were provided to the second core. If it is determined that the occupancy rate of the fifth core would reach 70% (less than the first threshold) if it provided computing power for the third data processing channel in addition to providing computing power for the one or more data processing channels originally assigned to it, processor 220-B then determines the fifth core from the K cores to provide computing power for the third data processing channel and transfers execution of the third data processing channel from the second core to the fifth core. In this example, p is 2, j is 3, and q is 5.

[0128] In this embodiment, after the processor 220-B determines that the 5th core from the above-mentioned K cores provides computing power for the above-mentioned 3rd data processing, and before transferring the execution of the above-mentioned 3rd data processing from the above-mentioned 2nd core to the above-mentioned 5th core, it can also increase the operating frequency of the 5th core to increase the computing power of the 5th core, thereby avoiding the data (such as audio signal) processing process from being stuck due to the instantaneous increase in the occupancy rate of the 5th core after the 3rd data processing is transferred.

[0129] In this embodiment, after processor 220-B determines that the computing power provided by the second core for the third data processing is insufficient, it can directly increase the operating frequency of the second core to increase the computing power of the second core, thereby avoiding the lag caused by the third data processing or the first data processing. Of course, if the operating frequency of the second core cannot be increased, the embodiments provided in S2020 and S2030 can be executed to ensure the smooth execution of the data processing link.

[0130] In the case where it is determined based on the monitoring results that there are kernels with insufficient computing power, an embodiment D is also provided: the above-mentioned M types of initial allocation schemes can be screened to determine whether there is an initial allocation scheme that can provide sufficient computing power for the current computing power demand after the computing power changes. If there is an initial allocation scheme that can provide sufficient computing power for the current computing power demand, computing power is allocated according to the initial allocation scheme, and it can be further determined whether there is room for computing power optimization. If there are two or more initial allocation schemes that can provide sufficient computing power for the current computing power demand, the initial allocation schemes that meet the above-mentioned optimization purpose are further screened out for computing power allocation, and it can be further determined whether there is room for computing power optimization. Specifically, in the case where there is room for computing power optimization, the following embodiment E can be executed to achieve the purpose of reducing equipment power consumption while ensuring the smooth execution of N-channel data processing.

[0131] It should be noted that when it is determined based on the monitoring results that there is a core with insufficient computing power, one or more of Example A, Example B, Example C and Example D can be executed based on actual needs, and the embodiments of this application do not limit this.

[0132] Referring again to FIG6 , when it is determined through S620 that there are no cores with insufficient computing power (case 3, case 4), S630 is further executed: it is determined based on the monitoring results whether there are cores with excess computing power. In other words, while giving priority to ensuring the smooth execution of each data processing process, the computing power distribution of N data processing channels is optimized to minimize the power consumption of the device. If it is determined through S630 that there are cores with excess computing power, the current situation is that there are cores with excess computing power but no cores with insufficient computing power. In this embodiment of the application, embodiment E or embodiment F can be executed to optimize the computing power distribution to achieve the effect of reducing the power consumption of the device.

[0133] FIG10 is a flow chart illustrating a method for reallocating computing power in the presence of excess computing power, according to an embodiment of the present application. This computing power reallocation method P500 can serve as exemplary embodiment E for use in the presence of cores with excess computing power and can be applied to the aforementioned data processing device 002. Specifically, processing circuit 220 can execute P500 in the presence of cores with excess computing power and the absence of cores with insufficient computing power. For example, processor 220-B in processing circuit 220 can execute computing power reallocation method P500. As shown in FIG10 , data processing method P500 may include steps S2010′ to S2030′.

[0134] S2010': During the execution of the above-mentioned goal, it is determined that there is an idle core among the above-mentioned K cores whose computing power occupancy rate is less than a second threshold, and the idle core is stopped from executing corresponding data processing.

[0135] When processor 220-B determines that there is a core with excess computing power, that is, there is a core whose occupancy rate is less than the second threshold (denoted as: idle core), in order to optimize device power consumption while ensuring the user's audio listening experience, this embodiment of the application will execute 'S2020' and S2030'.

[0136] In S2020', L reallocation schemes are determined based on the target computing power corresponding to the above-mentioned N data processing channels and at least one working core other than the idle core among the above-mentioned K cores, wherein under each reallocation scheme, the total computing power provided by the above-mentioned at least one working core is greater than or equal to the total computing power required to execute the above-mentioned target process, and L is an integer greater than or equal to 1.

[0137] In an exemplary embodiment, K is 4. If there is a core whose occupancy is less than the second threshold, a reallocation scheme is determined based on the computing power that can be provided by the other three cores excluding the idle core and the target computing power required for the N data processing. If five reallocation schemes are determined, for each of the five reallocation schemes, the total computing power provided by the other three cores excluding the idle core is greater than or equal to the total computing power required for executing the target process, that is, each reallocation scheme can ensure the smooth execution of the target process.

[0138] Specifically, if the number of cores other than the idle core that can provide computing power is Q (an integer greater than 1), determine the specific implementation methods of the above-mentioned L reallocation schemes: in order to determine the above-mentioned M initial allocation schemes, the at least one set of instruction sets stored in the above-mentioned at least one storage medium specifically includes: S1', based on the above-mentioned N target computing powers, determine the target total computing power required to execute the above-mentioned target process; S2', based on the above-mentioned target total computing power, calculate the operating frequency of the above-mentioned Q cores; S3', based on the above-mentioned determined operating frequency and the number Q of cores providing computing power, determine the Q computing powers corresponding to the above-mentioned Q cores respectively; and S4', determine the above-mentioned L initial allocation schemes based on the above-mentioned N target computing powers and the Q computing powers that can be provided.

[0139] Specifically, the processor 220-B in the processing circuit 220 can execute the above-mentioned steps S1'-S4'. Taking the data processing link of the audio signal received by the microphone of the wireless headset 120 during a call as an example, the processor 220-B determines the target computing power corresponding to each data processing channel through the aforementioned embodiment: target computing power q1 for ADC sampling, target computing power q2 for noise reduction processing, target computing power q3 for Bluetooth SBC, and target computing power q4 for Bluetooth radio. Then, the processor 220-B can determine the target total computing power required for this data processing link: P' = q1 + q2 + q3 + q4. It is understandable that the factors affecting the FLOPS of computing power include: the number of cores providing computing power in the sub-processor, the operating frequency of a single core, and the floating-point calculation value of a single cycle of the sub-processor. During the redistribution of computing power, if the initial operating frequencies of the cores in the sub-processor are consistent, and since the target total computing power P' required by the data processing link, the number of cores Q providing computing power by the sub-processor, and the floating-point calculation value of a single cycle of the sub-processor are known, the operating frequencies of the above Q cores can be determined, assuming they are f0'.

[0140] Furthermore, processor 220-B determines the computing power available to each of the Q cores based on operating frequency f0'. The available computing power provided by each core is: f0' × the floating-point calculation value of the sub-processor in a single cycle. Based on the target computing power q1, q2, q3, and q4 required for processing N data channels and the available computing power of Q cores (assuming the value is 3), processor 220-B can determine L initial allocation schemes (as shown in Table 4).

[0141] Table 4

[0142] It should be noted that to ensure smooth audio processing, each reallocation scheme ensures that the computing power provided by each core is greater than or equal to the sum of the computing power required for its corresponding data processing. For example, referring to Table 4, in reallocation scheme 1, the computing power provided by core 1 is greater than q3, the computing power provided by core 2 is greater than q3 + q2, and the computing power provided by core 3 is greater than q4. Of course, in reallocation scheme 1, the sum of the computing power provided by cores 1, 2, and 3 is greater than the target total computing power P' required for the data processing link.

[0143] In S2030′, based on the above optimization objective, a second target allocation scheme is determined from the above L reallocation schemes, and the computing power of the at least one working core in executing the above N data processing is allocated using the above second target allocation scheme.

[0144] In this embodiment, the second target allocation scheme determined based on the above-mentioned optimization purpose specifically refers to selecting an allocation scheme with the smallest target statistical value of the K cores actually providing computing power among the above-mentioned K cores from among the multiple optional reallocation schemes, wherein the above-mentioned statistical value is the variance or standard deviation. Alternatively, the second target allocation scheme determined based on the above-mentioned optimization purpose specifically refers to the second target scheme selected from the multiple optional reallocation schemes that can maintain the lowest overall power consumption and / or the most balanced load of the K cores providing computing power in the sub-processor. Through the above-mentioned optimization goal, a second target allocation scheme that meets the above-mentioned optimization goal can be determined from the above-mentioned L reallocation schemes, and computing power allocation is performed based on the selected second target scheme. If, based on the above optimization objectives, the second target allocation scheme determined from the multiple reallocation schemes shown in Table 4 is reallocation scheme 2, then core 1 provides computing power for Bluetooth SBC, core 2 provides computing power for ADC sampling and Bluetooth radio, and core 3 provides computing power for noise reduction processing. Compared to the other reallocation schemes shown in Table 4, the actual computing power provided by the three cores in reallocation scheme 2 is q1, p2 + p4, and q3, respectively, which have the lowest statistical values. Alternatively, compared to the other reallocation schemes shown in Table 4, the actual computing power provided by the three cores in reallocation scheme 2 is q1, p2 + p4, and q3, respectively. In this case, the overall power consumption of the Q cores providing computing power in the sub-processor can be minimized and / or the load can be balanced.

[0145] When it is determined based on the monitoring results that there is no core with insufficient computing power and that there is a core with excess computing power, embodiment F is also provided: locating the core with excess computing power, and further, based on the first threshold (e.g., 80%) and the second threshold (e.g., 40%) set for the occupancy rate, reducing the operating frequency of the core so that the occupancy rate of the core after the operating frequency is reduced is between the second threshold and the first threshold, that is, there is no excess or insufficient computing power, thereby reducing the power consumption of the sub-processor while ensuring that each data processing channel has sufficient computing power, which is beneficial to reducing the power consumption of the audio processing device.

[0146] Similar to the above embodiment, the storage medium 210 includes a storage area for "scheduling records." After determining the second target allocation plan, the second target allocation plan can be used to update the previous target allocation plan stored in the "scheduling records" storage area, which uses the same data processing link to process the same target data. In example 3, information related to the second target allocation plan stored in the "scheduling records" storage area may include, for example, the relationship between each data processing channel in the data processing link and the core providing computing power for it, the attributes of the target data processed by the data processing link, and the data processing link itself.

[0147] Continuing with reference to FIG6 , if it is determined through S630 that there are no cores with excess computing power, and the current situation is that there are neither cores with excess computing power nor cores with insufficient computing power, then the embodiment of the present application executes S610 again to continuously monitor the computing power required for each data processing channel during the above-mentioned target process, thereby minimizing device power consumption while ensuring that sufficient computing power is allocated to each data processing channel during the entire target process.

[0148] In summary, embodiments of the present application provide a data processing device and data processing method, wherein the processing circuit 220 includes a multi-core processor 220-A, which includes K sub-processors 240 each of which is used to participate in a target process of processing target data through N data processing steps to generate result data. Specifically, the processing circuit 220 obtains the target data and determines N target computing powers corresponding to performing the N data processing steps. During the target process, the processing circuit 220 determines the allocation of the K cores to perform the N data processing steps based on the N target computing powers and a preset optimization objective. It can be seen that the solution provided by the present application can determine the computing power provided by the K cores for each of the N data processing steps during the operation of the data processing device, and adaptively allocate the corresponding target computing power to each data processing step. For example, if one or more data processing steps are added, replaced, or deleted in a data processing chain, the data processing device can adaptively adjust the computing power allocation. It can be seen that the solution provided by the embodiments of the present application is conducive to adapting to the expansion of data processing chains. At the same time, compared with the related art that requires advance planning of one or more data processing channels that each core is responsible for, the method provided by this application is conducive to improving the flexibility of computing power allocation.

[0149] On the other hand, the present application provides a non-transitory storage medium storing at least one set of executable instructions for performing data processing. When the executable instructions are executed by a processor, the executable instructions instruct the processor to implement the steps of the data processing method P100 described in the present application. In some possible embodiments, various aspects of the present application can also be implemented in the form of a program product, which includes program code. When the program product is run on an acoustic system, the program code is used to cause the acoustic system to perform the steps of the data processing method P100 described in the present application. The program product for implementing the above method can use a portable compact disc read-only memory (CD-ROM) to include program code and can be run on the acoustic system. However, the program product of the present application is not limited to this. In the present application, a readable storage medium can be any tangible medium that contains or stores a program that can be used by or in combination with an instruction execution system. The program product can use any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media include: an electrical connection having one or more conductors, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. The computer-readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such a propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing. The computer-readable storage medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the foregoing. Program code for performing the operations of the present application may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and conventional procedural programming languages ​​such as C or similar programming languages. The program code may be executed entirely on the acoustic system, partially on the acoustic system, as a stand-alone software package, partially on the acoustic system and partially on a remote computing device, or entirely on the remote computing device.

[0150] The foregoing description describes specific embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in an order different from that described in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0151] In summary, after reading this detailed disclosure, those skilled in the art will appreciate that the foregoing detailed disclosure may be presented by way of example only and may not be limiting. Although not expressly stated herein, those skilled in the art will understand that the present application requires various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are intended to be proposed by the present application and are within the spirit and scope of the exemplary embodiments of the present application.

[0152] In addition, certain terms in this application have been used to describe embodiments of the application. For example, "one embodiment," "an embodiment," and / or "some embodiments" mean that a particular feature, structure, or characteristic described in conjunction with that embodiment may be included in at least one embodiment of the application. Therefore, it is emphasized and should be understood that two or more references to "an embodiment," "one embodiment," or "an alternative embodiment" in various sections of this application do not necessarily refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be appropriately combined in one or more embodiments of the application.

[0153] It should be understood that in the foregoing description of the embodiments of this application, in order to facilitate understanding of a feature and to simplify this application, this application combines various features into a single embodiment, figure, or description thereof. However, this does not mean that the combination of these features is required. When reading this application, it is entirely possible for a person skilled in the art to mark out some of the devices and understand them as separate embodiments. In other words, the embodiments of this application can also be understood as the integration of multiple secondary embodiments. This also applies when the content of each secondary embodiment is less than all the features of a single aforementioned disclosed embodiment.

[0154] Each patent, patent application, patent application publication, and other materials, such as articles, books, specifications, publications, documents, articles, and the like, cited herein, except any historical prosecution documents to which it relates, any equivalent that may be inconsistent or conflicting with this document, or any equivalent historical prosecution documents that may have a limiting effect on the broadest scope of the claims, is hereby incorporated by reference for all purposes now or hereafter connected with this document. In addition, in the event of any inconsistency or conflict between the descriptions, definitions, and / or use of terms associated with any incorporated material and the terminology, descriptions, definitions, and / or use associated with this document, the terminology in this document shall control.

[0155] Finally, it should be understood that the embodiments of the application disclosed herein are illustrations of the principles of the embodiments of the present application. Other modified embodiments are also within the scope of the present application. Therefore, the embodiments disclosed in the present application are merely examples and not limitations. Those skilled in the art can adopt alternative configurations based on the embodiments in the present application to implement the applications in the present application. Therefore, the embodiments of the present application are not limited to the embodiments precisely described in the application.

Claims

1. A data processing device, characterized in that: include: at least one storage medium storing at least one set of instruction sets, wherein the at least one set of instruction sets is used to perform computing power scheduling in a target process of generating result data by subjecting target data to N data processing steps; and A processing circuit includes a multi-core processor and is communicatively connected to the at least one storage medium, wherein the multi-core processor includes K core sub-processors to participate in the target process, K is an integer greater than 1, Wherein, when the data processing device is running, the processing circuit executes the at least one set of instruction sets to: Get the target data, Determine N target computing powers corresponding to the N data processing, and In the target process, the allocation of the K cores in executing the N data processing is determined according to the N target computing powers and the preset optimization purpose.

2. The data processing device according to claim 1, characterized in that To determine the allocation of the K cores to perform the N data processing, the processing circuit executes the at least one set of instruction sets to: According to the N target computing powers, M initial allocation schemes are determined to allocate corresponding cores to the N data processing, wherein each of the initial allocation schemes satisfies that the computing power provided by each core is greater than or equal to the sum of the computing powers required for the corresponding data processing, and M is an integer greater than or equal to 1; as well as Based on the optimization purpose, a first target allocation scheme is determined from among the M initial allocation schemes for execution.

3. The data processing device according to claim 2, characterized in that To determine the M initial allocation schemes, the processing circuit executes the at least one set of instruction sets to: Determining a target total computing power required to execute the target process according to the N target computing powers; Determining initial operating frequencies of the K cores according to the target total computing power; Determine, according to the initial operating frequency, the K computing powers that correspond to the K cores respectively; as well as M initial allocation schemes are determined according to the N target computing powers and the K available computing powers.

4. The data processing device according to claim 2, characterized in that Each of the M initial allocation schemes includes: at least one core participating in the target process, and the actual provided computing power of the at least one core participating in the target process and / or the actual operating frequency of the at least one core participating in the target process.

5. The data processing device according to claim 1, characterized in that To determine the allocation of the K cores to perform the N data processing, the processing circuit executes the at least one set of instruction sets to: Based on a preset algorithm, according to the N target computing powers, the K computing powers that can be provided respectively corresponding to the K cores, and the optimization purpose, at least one core participating in the target process is determined among the K cores, and the actual operating frequency of the at least one core participating in the target process is determined.

6. The data processing device according to claim 1, characterized in that The optimization purpose is to select, from among multiple optional allocation schemes, an allocation scheme in which the target statistical value of the K cores actually providing computing power is the smallest, wherein the statistical value is the variance or standard deviation.

7. The data processing device according to claim 1, characterized in that The optimization objectives include: The overall power consumption of the K cores is kept to be the lowest and / or the load is kept to be the most balanced.

8. The data processing device according to claim 1, characterized in that The processing circuitry also executes the at least one set of instructions to: During the execution of the target, determining that the K cores have insufficient computing power; and The operating frequencies of the K cores are increased to increase the computing power provided by the sub-processors to avoid data processing stalls.

9. The data processing device according to claim 1, characterized in that The processing circuitry also executes the at least one set of instructions to: In the process of executing the target, determining that there are O cores among the K cores that have insufficient computing power, where O is a positive integer not greater than K; as well as Increase the operating frequency of the O cores to increase the computing power of the qth core to avoid data processing jams.

10. The data processing device according to claim 9, characterized in that The insufficient computing power includes: a computing power occupancy rate of any one of the K cores exceeds a first threshold.

11. The data processing device according to claim 1, characterized in that The processing circuitry also executes the at least one set of instructions to: In the process of executing the target, determining that there is an idle core whose computing power occupancy rate is less than a second threshold value among the K cores, and stopping the idle core from executing corresponding data processing; Determine L reallocation schemes according to the N target computing powers and at least one working core among the K cores except the idle core, wherein under each of the reallocation schemes, a total computing power provided by the at least one working core is greater than or equal to a total computing power required to execute the target process, and L is an integer greater than or equal to 1; as well as Based on the optimization purpose, a second target allocation scheme is determined from the L reallocation schemes, and the computing power of the at least one working core in executing the N data processing is allocated through the second target allocation scheme.

12. The data processing device according to claim 1, characterized in that To achieve the optimization goal, the processing circuit further executes the at least one set of instruction sets to: In the process of executing the objective, it is determined that the computing power provided by the pth core for the jth data processing is insufficient; Determine the qth kernel from the K kernels to provide computing power for the jth data processing; as well as The execution of the j-th data processing is transferred from the p-th core to the q-th core.

13. The data processing device according to claim 12, characterized in that The processing circuitry also executes the at least one set of instructions to: Before transferring the execution of the j-th data processing from the p-th core to the q-th core, increasing the operating frequency of the q-th core to increase the computing power of the q-th core to avoid data processing stalls.

14. The data processing device according to claim 1, characterized in that The processing circuitry also executes the at least one set of instructions to: In the process of executing the target, determining that there are R cores among the K cores that have insufficient computing power, where R is a positive integer not greater than K; When there is an idle core whose computing power utilization rate is less than the second threshold value among the K cores, at least part of the data processing corresponding to the R cores is transferred to the idle core, wherein after the transfer, the computing power that can be provided by each core is greater than or equal to the sum of the computing powers required for the corresponding data processing.

15. The data processing device according to claim 1, characterized in that The at least one storage medium is further associated with storing: attributes of target data and target computing power corresponding to at least one data processing step for the target data; In order to determine the N target computing powers corresponding to the N data processing, the processing circuit executes the at least one set of instruction sets to: According to the attributes of the obtained target data, the at least one storage medium is searched to obtain N target computing powers corresponding to the N data processing operations on the target data.

16. The data processing device according to claim 15, characterized in that The processing circuitry executes the at least one set of instructions to: In a case where the at least one storage medium does not store N target computing powers corresponding to N data processings of the target data of the target attribute, calculating the N target computing powers respectively required for processing the N data processings of the target data of the target attribute; as well as The N target computing powers corresponding to the N data processing steps performed on the target data of the target attribute are associated with the target attribute and stored in the at least one storage medium.

17. The data processing device according to claim 1, characterized in that The at least one storage medium further stores: for multiple attributes of target data, kernel identifiers for processing the target data of each attribute and providing computing power for the N data processing respectively; To determine the allocation of the K cores to perform the N data processing, the processing circuit executes the at least one set of instruction sets to: According to the target attribute of the obtained target data, the at least one storage medium is searched to obtain the kernel identification that processes the target data with the target attribute and provides computing power for the N data processing respectively, thereby determining the allocation of the K kernels in executing the N data processing.

18. The data processing device according to claim 1, characterized in that The data processing device is a headset.

19. A data processing method, characterized in that: include: Get the target data, Determine the N target computing power corresponding to N data processing, and In the target process, according to the N target computing powers and the preset optimization purpose, determining the allocation of K cores in the multi-core processor participating in the target process in executing the N data processing, where K is an integer greater than 1; The target process is a process of generating result data by subjecting the target data to the N data processing steps.

20. The data processing method according to claim 19, characterized in that: The determining of the allocation of the K cores for executing the N data processing comprises: According to the N target computing powers, determine M initial allocation schemes to allocate corresponding cores to the N data processing, wherein each of the initial allocation schemes satisfies that the computing power that can be provided by each core is greater than or equal to the sum of the computing powers required for the corresponding data processing, and M is an integer greater than or equal to 1; and Based on the optimization purpose, a first target allocation scheme is determined from among the M initial allocation schemes for execution.

21. The data processing method according to claim 20, characterized in that: Wherein, determining the M initial allocation schemes comprises: Determining a target total computing power required to execute the target process according to the N target computing powers; Determining initial operating frequencies of the K cores according to the target total computing power; Determine, according to the initial operating frequency, the K computing powers that correspond to the K cores respectively; and M initial allocation schemes are determined according to the N target computing powers and the K available computing powers.

22. The data processing method according to claim 20, characterized in that: Each of the M initial allocation schemes includes: at least one core participating in the target process, and the actual provided computing power of the at least one core participating in the target process and / or the actual operating frequency of the at least one core participating in the target process.

23. The data processing method according to claim 19, characterized in that: To determine the allocation of the K cores to perform the N data processing, the processing circuit executes the at least one set of instruction sets to: Based on a preset algorithm, according to the N target computing powers, the K computing powers that can be provided respectively corresponding to the K cores, and the optimization purpose, at least one core participating in the target process is determined among the K cores, and the actual operating frequency of the at least one core participating in the target process is determined.

24. The data processing method according to claim 19, characterized in that: The optimization purpose is to select, from among multiple optional allocation schemes, an allocation scheme in which the target statistical value of the K cores actually providing computing power is the smallest, wherein the statistical value is the variance or standard deviation.

25. The data processing method according to claim 19, characterized in that: The optimization objectives include: The overall power consumption of the K cores is kept to be the lowest and / or the load is kept to be the most balanced.

26. The data processing method according to claim 19, characterized in that: Also includes: During the execution of the target, it is determined that the K cores have insufficient computing power; as well as The operating frequencies of the K cores are increased to increase the computing power provided by the sub-processors to avoid data processing stalls.

27. The data processing method according to claim 19, characterized in that: Also includes: In the process of executing the target, determining that there are O cores among the K cores that have insufficient computing power, where O is a positive integer not greater than K; as well as Increase the operating frequency of the O cores to increase the computing power of the qth core to avoid data processing jams.

28. The data processing method according to claim 27, characterized in that: The insufficient computing power includes: a computing power occupancy rate of any one of the K cores exceeds a first threshold.

29. The data processing method according to claim 19, characterized in that: Also includes: In the process of executing the target, determining that there is an idle core whose computing power occupancy rate is less than a second threshold value among the K cores, and stopping the idle core from executing corresponding data processing; Determine L reallocation schemes according to the N target computing powers and at least one working core among the K cores except the idle core, wherein under each of the reallocation schemes, a total computing power provided by the at least one working core is greater than or equal to a total computing power required to execute the target process, and L is an integer greater than or equal to 1; as well as Based on the optimization purpose, a second target allocation scheme is determined from the L reallocation schemes, and the computing power of the at least one working core in executing the N data processing is allocated through the second target allocation scheme.

30. The data processing method according to claim 19, characterized in that: Also includes: In the process of executing the objective, it is determined that the computing power provided by the pth core for the jth data processing is insufficient; Determine the qth kernel from the K kernels to provide computing power for the jth data processing; as well as The execution of the j-th data processing is transferred from the p-th core to the q-th core.

31. The data processing method according to claim 30, characterized in that: Also includes: Before transferring the execution of the j-th data processing from the p-th core to the q-th core, increasing the operating frequency of the q-th core to increase the computing power of the q-th core to avoid data processing stalls.

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