Voltage measurement system

Abstract

The circuit section includes: a first circuit section (71) to which a first voltage, which is a voltage based on a reference voltage, is supplied; and a second circuit section (72) to which a second voltage, which is a voltage based on the reference voltage, is supplied. The second circuit unit is supplied with a second voltage of higher precision than the first circuit unit (71), said second voltage being a voltage based on the reference voltage. A voltage measurement system is provided with: a first high-potential-side wiring (25) and a first low-potential-side wiring (27) which are connected so as to sandwich a first circuit unit (71) and which supply a first voltage to the first circuit unit (71); and a second high-potential-side wiring (26) and a second low-potential-side wiring (28) which are connected so as to sandwich the second circuit unit (72) and which supply a second voltage to the second circuit unit (72). The first high-potential-side wiring (25) and the second high-potential-side wiring (26) are separated from each other, and the first low-potential-side wiring (27) and the second low-potential-side wiring (28) are separated from each other.

Description

Technical Field

[0001] This disclosure relates to voltage measurement systems. Background Art

[0002] Conventionally, voltage measurement systems have been proposed that supply voltage generated by a reference voltage circuit section to other circuit sections (for example, see Non-Patent Document 1). For instance, in this voltage measurement system, a structure is proposed that supplies voltage generated by the reference voltage circuit section to an ADC (Analog Digital Converter), which is a circuit section. Furthermore, this ADC includes a first circuit section, a second circuit section, etc. The first circuit section has a resistor divider circuit section, etc., which is supplied with DC current; the second circuit section has a DAC, etc., which is supplied with AC current, and includes functions for performing calculations. In this voltage measurement system, the reference voltage circuit section and the first and second circuit sections of the ADC are connected via shared wiring.

[0003] Existing technical documents

[0004] Non-patent literature

[0005] Non-Patent Document 1: REF62xx High-Precision Voltage Reference with Built-in ADC and Driver / Buffer, Texas INSTRUMENTS, September 2016 Summary of the Invention

[0006] Furthermore, linearity, a crucial characteristic of ADCs, is easily affected by voltage errors supplied to the second circuit section (i.e., the DAC). When the voltage supplied to the second circuit section changes, accuracy decreases. Therefore, it is desirable to supply a voltage to the second circuit section of the ADC with higher accuracy compared to the voltage supplied to the first circuit section.

[0007] However, in the voltage measurement system described above, the reference voltage circuit section is connected to the first and second circuit sections of the ADC via shared wiring. Therefore, in this system, the wiring resistance voltage drop (i.e., voltage reduction) caused by the DC current supplied to the first circuit section may result in errors in the voltage supplied to the second circuit section, which is loaded with AC current. While it's possible to perform pre-checks or similar corrections to reduce the impact of the wiring resistance voltage drop, such corrections become difficult if the DC current changes after the check.

[0008] The purpose of this disclosure is to provide a voltage measurement system capable of suppressing changes in the voltage supplied to the second circuit section.

[0009] According to one aspect of this disclosure, a voltage measurement system includes: a reference voltage circuit section that generates a reference voltage; and a circuit section that is supplied with a voltage based on the reference voltage; the circuit section includes a first circuit section and a second circuit section, wherein the first circuit section is supplied with a first voltage, which is a voltage based on the reference voltage; and the second circuit section is supplied with a second voltage of higher precision than the first circuit section, which is a voltage based on the reference voltage; the voltage measurement system includes: a first high-potential side wiring and a first low-potential side wiring connected in a manner that sandwiches the first circuit section, supplying the first voltage to the first circuit section; and a second high-potential side wiring and a second low-potential side wiring connected in a manner that sandwiches the second circuit section, supplying the second voltage to the second circuit section; the first high-potential side wiring and the second high-potential side wiring are separated; and the first low-potential side wiring and the second low-potential side wiring are separated.

[0010] Therefore, the first high-potential side wiring and the second high-potential side wiring are arranged separately, and the first low-potential side wiring and the second low-potential side wiring are arranged separately. Thus, for the second circuit section, a second voltage is supplied that reduces the effect of the wiring voltage drop of the current flowing in the first circuit section, and the change in the second voltage supplied to the second circuit section based on the current flowing into the first circuit section can be suppressed.

[0011] Furthermore, the parenthesized labels assigned to each constituent element indicate an example of the correspondence between that constituent element and the specific constituent element described in the embodiments described later. Attached Figure Description

[0012] Figure 1 This is a schematic diagram illustrating the voltage measurement system of the first embodiment.

[0013] Figure 2 yes Figure 1 The diagram shows a schematic of an ADC.

[0014] Figure 3 This is a schematic diagram illustrating the voltage measurement system of the second embodiment.

[0015] Figure 4 This is a schematic diagram illustrating the voltage measurement system of the third embodiment.

[0016] Figure 5 This is a schematic diagram illustrating the voltage measurement system of the fourth embodiment. Detailed Implementation

[0017] Hereinafter, embodiments of the present disclosure will be described based on the accompanying drawings. Furthermore, in each of the following embodiments, the same reference numerals will be used to describe the identical or equivalent parts.

[0018] (First Embodiment)

[0019] The first embodiment will be described with reference to the accompanying drawings. Figure 1 As shown, the voltage measurement system of this embodiment includes a reference voltage circuit section 10, terminals 31-34 (1st to 4th), capacitor terminals 41 and 42 (1st and 2nd), capacitor 50, and ADC 70. Furthermore, in this embodiment, the voltage measurement system is configured such that the reference voltage circuit section 10, terminals 31-34 (1st to 4th), and ADC 70 are disposed on a shared IC chip, while capacitor terminals 41 (1st), 42 (2nd), and 50 are disposed as components independent of the IC chip on a wiring substrate on which the IC chip is mounted. IC is short for Integrated Circuit.

[0020] The reference voltage circuit section 10 of this embodiment is configured to include a reference voltage generation circuit section 11, an operational amplifier 12, a control element 13, a first resistor 15, and a second resistor 16.

[0021] The reference voltage generation circuit section 11 is connected to the first wiring 21 and the second wiring 22, generating a potential difference of V between the first wiring 21 and the second wiring 22. ref The reference voltage. Furthermore, the first wiring 21 is connected to the negative input terminal 12a of the operational amplifier 12, and the second wiring 22 is connected to the third terminal 33, which will be described later. In addition, the second wiring 22 in this embodiment is configured to include a portion of wiring disposed within the reference voltage circuit section 10 and connected to the reference voltage generation circuit section 11, and a portion of wiring connected to this portion and disposed outside the reference voltage circuit section 10 and connected to the third terminal 33, which will be described later.

[0022] In this embodiment, the control element 13 is composed of a p-channel transistor or the like, with the source terminal connected to the internal power supply 14 and the gate terminal connected to the output terminal 12c of the operational amplifier 12.

[0023] The first resistor 15 and the second resistor 16 are connected in series between the drain terminal side of the control element 13 and the second wiring 22. Furthermore, the third wiring 23, which is connected to the positive input terminal 12b of the operational amplifier 12, is connected between the first resistor 15 and the second resistor 16. Additionally, the fourth wiring 24 and the fifth wiring 25 are connected between the control element 13 and the second resistor 16. The fourth wiring 24 is configured to include a portion of wiring disposed within the reference voltage circuit section 10, and a portion of wiring connected to this portion and connected to the first terminal 31 described later. The fifth wiring 25 is configured to include a portion of wiring disposed within the reference voltage circuit section 10, and a portion of wiring connected to this portion and connected to the first circuit section 71 of the ADC 70 described later.

[0024] As described above, the negative input terminal 12a of the operational amplifier 12 is connected to the first wiring 21, its positive input terminal 12b is connected to the third wiring 23, and its output terminal 12c is connected to the gate terminal of the control element 13.

[0025] Terminals 31 to 34, for example, are configured on the outer edge of the IC chip housing the reference voltage circuit section 10 and the ADC 70. Terminal 31 is connected to the fourth wiring 24 between the control element 13 and the second resistor 16. Terminal 32 is connected to the second circuit section 72 of the ADC 70 (described later) via the sixth wiring 26.

[0026] The third terminal 33 is connected to the second wiring 22. The fourth terminal 34 is connected to the seventh wiring 27, which is connected to the first circuit section 71 of the ADC 70 described later, and to the eighth wiring 28, which is connected to the second circuit section 72 of the ADC 70 described later.

[0027] The first and second capacitor terminals 41 and 42 are disposed on the wiring substrate, for example, independently of the IC chip that carries the reference voltage circuit section 10 and the ADC70. The first capacitor terminal 41 is connected to the first terminal 31 and the second terminal 32 via bonding wires 81 and 82. The second capacitor terminal 42 is connected to the third terminal 33 and the fourth terminal 34 via bonding wires 83 and 84, and is connected to ground potential 43. In this embodiment, ground potential 43 corresponds to a reference potential source. Furthermore, while this embodiment describes an example where the reference potential source is ground potential 43, the reference potential source may not be ground potential 43 as long as it is maintained at a predetermined potential.

[0028] The capacitor 50 is disposed between the first external wiring 61 connected to the first capacitor terminal 41 and the second external wiring 62 connected to the second capacitor terminal 42. Furthermore, as described above, the capacitor 50 in this embodiment is disposed as a component independent of the IC chip housing the reference voltage circuit section 10 and the ADC 70, and therefore can also be considered an external capacitor. In addition, in this embodiment, the capacitor 50 corresponds to a capacitor section.

[0029] like Figure 2 As shown, in this embodiment, the ADC 70 includes a first circuit section 71, a second circuit section 72, an internal circuit section 73, a first internal wiring 74, a second internal wiring 75, etc., and generates a digital signal based on an analog signal input from an external source and an output signal from the second circuit section 72. Furthermore, in this embodiment, the ADC 70 corresponds to the circuit section.

[0030] In this embodiment, the first circuit section 71 is configured as a resistor divider circuit section comprising a first internal resistor 711 and a second internal resistor 712 connected in series within the first internal wiring 74. Furthermore, in this embodiment, the midpoint between the first internal resistor 711 and the second internal resistor 712 of the first circuit section 71 is connected to the internal circuit section 73 to generate a reference voltage for driving the internal circuit section 73. Additionally, the internal circuit section 73 is configured to include an operational amplifier or the like that performs predetermined processing within the ADC 70.

[0031] The second circuit section 72 is configured to include a DAC 720, which is a functional part for performing calculations, and is connected to the second internal wiring 75 via the first switch 721 and the second switch 722. Furthermore, in this embodiment, the calculation unit is configured to include the DAC 720.

[0032] The first internal wiring 74 and the second internal wiring 75 are arranged separately within the ADC 70. One end of the first internal wiring 74 is connected to the fifth wiring 25, and the other end is connected to the seventh wiring 27. A DC current flows from the fifth wiring 25 side to the seventh wiring 27 side, thereby supplying a voltage after a DC voltage change in addition to the voltage generated by the reference voltage circuit section 10 (e.g., 5V). One end of the second internal wiring 75 is connected to the sixth wiring 26, and the other end is connected to the eighth wiring 28. The second internal wiring 75 is appropriately controlled by the on / off state of the first switch 721 and the second switch 722, thereby allowing a transient current to flow from the capacitor 50 to the eighth wiring 28 side via the sixth wiring 26. Therefore, in addition to the voltage generated by the reference voltage circuit section 10 (e.g., 5V), a voltage after a transient AC voltage change is supplied. In addition, in this embodiment, the constant DC voltage supplied to the first circuit section 71 is equivalent to the first voltage, and the instantaneous AC voltage applied to the DC voltage supplied to the second circuit section 72 is equivalent to the second voltage.

[0033] The above describes the structure of the voltage measurement system according to this embodiment. Furthermore, in this embodiment, the 5th wiring 25 corresponds to the 1st high-potential side wiring, and the 6th wiring 26 corresponds to the 2nd high-potential side wiring. Additionally, in this embodiment, the 7th wiring 27 corresponds to the 1st low-potential side wiring, and the 8th wiring 28 corresponds to the 2nd low-potential side wiring. In this voltage measurement system, as described above, DC current flows through the 1st circuit section 71, and instantaneous AC current flows through the 2nd circuit section 72 depending on the opening and closing of the 1st switch 721 and the 2nd switch 722. At this time, the 2nd circuit section 72 (i.e., DAC 720) performs the functions required for operation and is expected to be supplied with a high-precision voltage. Therefore, in this embodiment, as described above, the 5th wiring 25 and 7th wiring 27, which carry DC current, are arranged separately from the 6th wiring 26 and 8th wiring 28, which carry AC current. That is, the path of the DC current is separated from the path of the AC current. Therefore, it is possible to suppress the voltage supplied to the second circuit section 72 from changing according to the DC current supplied to the first circuit section 71.

[0034] The following examples illustrate this. For instance... Figure 1 As shown, the connection between the first resistor 15 and the second wiring 22 is designated as node N1, the connection between the control element 13 and the second resistor 16 and the fourth wiring 24 is designated as node N2, and the connection between the control element 13 and the second resistor 16 and the fifth wiring 25 is designated as node N3. Furthermore, the current flowing from node N1 to terminal 33 is denoted as I. vref This will be explained further. Additionally, the current I flowing from the first node N1 to the third terminal 33... vref This includes the current flowing through the control element 13 and the current flowing from the reference voltage generation circuit section 11. Furthermore, the following description assumes the resistance value of the first resistor 15 is R1 and the resistance value of the second resistor 16 is R2. Also, the wiring resistance of the portion of the second wiring 22 located between the first node N1 and the third terminal 33 is R. vrefgnd Let the wiring resistance of the 5th wiring 25 be R. dc Let the wiring resistance of the 7th wiring 27 be R. dc、vrefgnd This will be explained further. Furthermore, let's assume the current flowing from the 5th wiring 25 through the ADC70 to the 7th wiring 27 is I. dc The following explanation will be provided. Furthermore, in this embodiment, as described above, the AC current is a transient current flowing from capacitor 50 to the 6th wiring 26 and the 8th wiring 28. Therefore, the wiring resistance of the 6th wiring 26 and the 8th wiring 28 flowing with AC current, as well as the effect of the wiring voltage drop caused by the AC current, can be ignored.

[0035] In this case, since the wiring resistance of the second wiring 22 is R vrefgnd The current flowing through the second wiring 22 is I. vref Therefore, the potential of node N1 is determined by I. vref ×R vrefgnd Furthermore, if the potentials of the second node N2 and the third node N3 are V, then the potential V, with the first node N1 as the reference, is represented by the following equation 1.

[0036] [Formula 1]

[0037]

[0038] And, as Figure 2 As shown, let the potential on the fifth wiring 25 side of the first circuit section 71 of ADC70 be V. vref、dc And let the potential on the 27th side of the 7th wiring be V. vrefgnd、dc Furthermore, let the potential on the sixth wiring 26 side of the second circuit section 72 of the ADC70 be V. vref、ac And let the potential on side 28 of the 8th wiring be V. vrefgnd、ac In this case, since the current flowing from the 5th wiring 25 through the ADC70 to the 7th wiring 27 is I... dc Therefore, the voltage supplied to the first circuit section 71 is represented by the following formula 2. Furthermore, the voltage supplied to the second circuit section 72 is represented by the following formula 3, since the influence of wiring voltage drop caused by AC current can be ignored.

[0039] [Formula 2]

[0040]

[0041] [Formula 3]

[0042]

[0043] Therefore, according to this embodiment, the second circuit section 72 is supplied with a high-precision voltage that reduces the effect of wiring voltage drop caused by the DC current flowing to the first circuit section 71.

[0044] According to the embodiment described above, the fifth wiring 25 and the seventh wiring 27 connected to the first circuit section 71 and the sixth wiring 26 and the eighth wiring 28 connected to the second circuit section 72 are arranged separately. Therefore, for the second circuit section 72, the voltage supplied with reduced wiring voltage drop affecting the current flowing to the first circuit section 71 can suppress changes in the voltage supplied to the second circuit section 72 based on the current flowing to the first circuit section 71.

[0045] (1) In this embodiment, terminals 31-34 (first to fourth) and capacitor terminals 41 and 42 (first and second) are provided, and capacitor 50 is connected to the second circuit section 72 via terminals 31-34 and capacitor terminals 41 and 42. Therefore, compared with the case where capacitor 50 is placed inside the IC chip, the selectivity of capacitor 50 size and placement space can be improved. Furthermore, in this embodiment, the fifth wiring 25 and the sixth wiring 26 are separated, and the seventh wiring 27 and the eighth wiring 28 are separated, and the wiring of the second circuit section 72 that introduces AC current is directly connected to capacitor 50 (i.e., capacitor). Therefore, current can be instantaneously supplied from capacitor 50 for voltage fluctuations caused by AC current, and voltage fluctuations can be further suppressed.

[0046] (2) In this embodiment, the reference voltage circuit section 10 and the first circuit section 71 of the ADC 70 are connected via the fifth wiring 25, and no terminals are provided. Here, when the reference voltage circuit section 10 and the ADC 70 are arranged on a common IC chip as in this embodiment, the reference voltage circuit section 10 and the ADC 70 are generally arranged in the approximate center of the IC chip. Furthermore, the reference voltage circuit section 10 and the ADC 70 are arranged such that the distance between the reference voltage circuit section 10 and the ADC 70 is closer than the distance between the reference voltage circuit section 10 and the ADC 70 and the first to fourth terminals 31 to 34. Therefore, it is easy to make the length of the fifth wiring 25 shorter. In addition, since such a voltage measurement system has dense wiring formed near the first to fourth terminals 31 to 34, by directly connecting the reference voltage circuit section 10 and the first circuit section 71 of the ADC 70 via the fifth wiring 25, it is easy to ensure layout space.

[0047] (Second Implementation)

[0048] The second embodiment will be described. This embodiment has multiple ADCs 70 compared to the first embodiment. Everything else is the same as the first embodiment, so descriptions are omitted here.

[0049] like Figure 3 As shown, the voltage measurement system of this embodiment includes two ADCs 70. Hereinafter, one ADC 70 will be referred to as the first ADC 70a, and the other ADC 70 will be referred to as the second ADC 70b. In addition, the first ADC 70a and the second ADC 70b have the same structure as the ADC 70 described in the first embodiment.

[0050] Two sixth wirings 26 are connected to the second terminal 32. One of the sixth wirings 26 is connected to the second circuit section 72 of the first ADC 70a, and the other sixth wiring 26 is connected to the second circuit section 72 of the second ADC 70b. Two seventh wirings 27 are connected to the fourth terminal 34. One seventh wiring 27 is connected to the first circuit section 71 of the first ADC 70a, and the other seventh wiring 27 is connected to the first circuit section 71 of the second ADC 70b. Two eighth wirings 28 are connected to the fourth terminal 34. One eighth wiring 28 is connected to the second circuit section 72 of the first ADC 70a, and the other eighth wiring 28 is connected to the second circuit section 72 of the second ADC 70b.

[0051] Furthermore, in this embodiment, the fifth wiring 25 is divided into two on the IC chip. One fifth wiring 25 is connected to the first circuit section 71 of the first ADC 70a, and the other fifth wiring 25 is connected to the first circuit section 71 of the second ADC 70b.

[0052] The above describes the structure of the voltage measurement system according to this embodiment. In such a voltage measurement system, since multiple ADCs 70 are provided, the voltage supplied to the first circuit section 71 is represented by the following formula 4.

[0053] [Formula 4]

[0054]

[0055] Furthermore, N in the third term on the right side of Equation 4 represents the number of ADCs 70. In this embodiment, since both the first ADC 70a and the second ADC 70b are present, the number is 2. That is, when multiple ADCs 70 are present, as shown in Equation 4 above, it is confirmed that the more the number of ADCs 70 increases, the greater the error in the voltage supplied to the first circuit section 71. However, in this embodiment, as described above, the fifth wiring 25 and the seventh wiring 27, which flow DC current, are separate from the sixth wiring 26 and the eighth wiring 28, which flow AC current. Therefore, the voltage supplied to the second circuit section 72 is the same as in Equation 3 above. Thus, according to this embodiment, even if the number of ADCs 70 is increased, it is possible to suppress the change in the voltage supplied to the second circuit section 72 based on the current flowing to the first circuit section 71.

[0056] According to the embodiment described above, the fifth wiring 25 and the seventh wiring 27 connected to the first circuit section 71 and the sixth wiring 26 and the eighth wiring 28 connected to the second circuit section 72 are arranged separately. Therefore, the same effects as in the first embodiment described above can be obtained.

[0057] (1) In this embodiment, a plurality of ADCs 70 are provided, but the fifth wiring 25 and the seventh wiring 27 connected to the first circuit section 71 and the sixth wiring 26 and the eighth wiring 28 connected to the second circuit section 72 are arranged separately. Therefore, even if the number of ADCs 70 operating in the system changes, it is possible to suppress the voltage supplied to the second circuit section 72 from changing according to the current flowing to the first circuit section 71.

[0058] (Third Implementation)

[0059] The third embodiment will be described. This embodiment differs from the first embodiment in that the configuration of the reference voltage circuit section 10 is modified. Everything else is the same as in the first embodiment, so further description is omitted here.

[0060] In this embodiment, such as Figure 4 As shown, the reference voltage circuit section 10 replaces the reference voltage generation circuit section 11 with a constant current source 17 and a Zener diode 18. Specifically, the cathode side of the Zener diode 18 is connected to the constant current source 17, and the anode side is connected to the second wiring 22. Furthermore, the first wiring 21 is connected between the constant current source 17 and the Zener diode 18.

[0061] According to the embodiment described above, the fifth wiring 25 and the seventh wiring 27 connected to the first circuit section 71 and the sixth wiring 26 and the eighth wiring 28 connected to the second circuit section 72 are arranged separately. Therefore, the same effects as in the first embodiment described above can be obtained.

[0062] (1) In this embodiment, the reference voltage V ref It is generated in a manner corresponding to the breakdown voltage of Zener diode 18. Therefore, it is easy to generate a high-precision reference voltage V. ref It can suppress the reference voltage V ref A deviation has occurred.

[0063] (Fourth implementation)

[0064] The fourth embodiment will be described. In this embodiment, the connection point of the eighth wiring 28 is changed compared to the first embodiment. Everything else is the same as in the first embodiment, so descriptions are omitted here.

[0065] like Figure 5As shown, in this embodiment, the eighth wiring 28 is configured to connect the first node N1 and the third terminal 33 in the second circuit section 72 and the second wiring 22 of the ADC 70. Therefore, if the connection point between the eighth wiring 28 and the second wiring 22 is set to the fourth node N4, the potential of the low-potential side of the second circuit section 72 is close to the potential of the first node N1. Thus, for example, if the potential of the fourth node N4 is set to be the same as the potential of the first node N1, the voltage applied to the second circuit section 72 is represented by the following formula 5.

[0066] [Formula 5]

[0067]

[0068] Therefore, according to this embodiment, it is also possible to suppress the voltage supplied to the second circuit section 72 from being affected by the current I flowing through the second wiring 22. vref The impact.

[0069] According to the embodiment described above, the fifth wiring 25 and the seventh wiring 27 connected to the first circuit section 71 and the sixth wiring 26 and the eighth wiring 28 connected to the second circuit section 72 are arranged separately. Therefore, the same effects as in the first embodiment described above can be obtained.

[0070] (1) In this embodiment, the eighth wiring 28 is configured to connect the second circuit section 72 of the ADC70 and the first node N1 and the third terminal 33 in the second wiring 22. Therefore, the current I flowing through the second wiring 22 can also be reduced. vref The impact.

[0071] (Other implementation methods)

[0072] This disclosure has been described in accordance with embodiments, but it should be understood that this disclosure is not limited to these embodiments or constructions. This disclosure also includes various modifications or equivalent variations. In addition, various combinations and forms, and further, other combinations and forms that include only one element, or include more or less of those elements, also fall within the scope and spirit of this disclosure.

[0073] In the above embodiments, examples were described where the first voltage is a constant DC voltage and the second voltage is an instantaneous AC voltage applied to the DC voltage. However, depending on the circuit structure, both the first voltage and the second voltage can be set to a constant DC voltage or both can be set to an instantaneous AC voltage applied to the DC voltage.

[0074] In the above embodiments, an ADC 70 having a first circuit section 71 and a second circuit section 72 has been described as an example. However, as long as the first circuit section 71 and the second circuit section 72, which needs to be supplied with a voltage with higher accuracy than that of the first circuit section 71, are included, other structures can be appropriately modified. For example, other components having the first circuit section 71 and the second circuit section 72 may be used instead of the ADC 70, or the first circuit section 71 and the second circuit section 72 may be included in different components.

[0075] Furthermore, in the above embodiments, the capacitor 50 may also be disposed on the IC chip together with the reference voltage circuit section 10 and the ADC 70. In addition, in this structure, since the capacitor 50 is also disposed on the IC chip, the first to fourth terminals 31 to 34 and the first and second capacitor terminals 41 and 42 may not be provided.

[0076] Furthermore, the above embodiments can be appropriately combined. For example, the second embodiment can be combined with the third and fourth embodiments to provide multiple ADCs 70. In addition, the third and fourth embodiments can be combined to provide a constant current source 17 and a Zener diode 18 instead of the reference voltage generation circuit section 11.

Claims

1. A voltage measurement system, have: The reference voltage circuit section generates a reference voltage; and The circuit section is subjected to a voltage based on the aforementioned reference voltage. The aforementioned circuit section includes a first circuit section and a second circuit section. The first circuit section is supplied with a first voltage as a voltage based on the aforementioned reference voltage, and the second circuit section is supplied with a second voltage with higher precision as a voltage based on the aforementioned reference voltage, compared to the first circuit section. The voltage measurement system described above has the following features: The first high-potential side wiring and the first low-potential side wiring are connected in a manner that sandwiches the first circuit section, supplying the first voltage to the first circuit section; and The second high-potential side wiring and the second low-potential side wiring are connected in a manner that sandwiches the second circuit section, and the second voltage is supplied to the second circuit section. The first high-potential side wiring and the second high-potential side wiring mentioned above are separated. The first low-potential side wiring and the second low-potential side wiring mentioned above are separated.

2. The voltage measurement system as described in claim 1, The aforementioned circuit section is an ADC, i.e., an analog-to-digital converter, which includes the first circuit section and the second circuit section described above. The first circuit section described above is configured to include a resistor voltage divider circuit. The second circuit section described above is configured to include an arithmetic unit.

3. The voltage measurement system as described in claim 2, The aforementioned ADC has multiple functions.

4. The voltage measurement system as described in claim 1, The aforementioned reference voltage circuit is configured to include a Zener diode, and the aforementioned reference voltage circuit generates the aforementioned reference voltage based on the breakdown voltage of the aforementioned Zener diode.

5. The voltage measurement system as described in any one of claims 1 to 4, have: First capacitor terminal; The second capacitor terminal is connected to ground potential; The capacitor section is disposed between the first capacitor terminal and the second capacitor terminal. The first terminal is connected to the aforementioned reference voltage circuit section and to the aforementioned first capacitor terminal; The second terminal is connected to the second circuit section via the second high-potential side wiring and is also connected to the first capacitor terminal. The third terminal is connected to the aforementioned reference voltage circuit section and to the aforementioned second capacitor terminal; and The fourth terminal is connected to the first circuit section via the first low-potential side wiring, and is also connected to the second capacitor terminal. AC current is supplied from the capacitor section to the second circuit section.

6. The voltage measurement system as described in claim 5, The second low-potential side wiring is connected to the second circuit section and to the fourth terminal.

7. The voltage measurement system as described in claim 5, The second low-potential side wiring is connected to the second circuit section and to the wiring that connects the third terminal and the reference voltage circuit section.

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