Acquisition board card for traveling wave fault location

Abstract

The invention relates to the technical field of power distribution network safety operation and maintenance, and particularly provides an acquisition board card for traveling wave fault positioning, which comprises a voltage / current sensor, a PGA chip, an ADC chip, an FPGA chip, a Beidou module, an SDRAM chip, a TF card, an SPI and interrupt interface and a main control device. The voltage / current sensor, the PGA chip and the ADC chip are connected in sequence; the PGA chip, the ADC chip, the Beidou module, the SDRAM chip, the TF card, the SPI and the interrupt interface are respectively connected with the FPGA chip; the SPI and the interrupt interface are connected with main control equipment; according to the technical scheme provided by the invention, the FPGA is used as a control core, peripheral equipment such as the PGA, the high-speed ADC and the SDRAM are integrated, a special chip with a higher integration level can be further researched and developed, and the cost can be further greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of power distribution network safety operation and maintenance technology, specifically to a data acquisition board for traveling wave fault location. Background Technology

[0002] Distribution network lines are characterized by a large number of lines, long distances, complex lines, and a large number of users. During operation, they are susceptible to lightning strikes, strong winds, fires, and other factors, resulting in numerous transient faults. Furthermore, the fault locations are often hidden and difficult to locate, requiring a large investigation area and leading to lengthy fault handling cycles, thus affecting power supply reliability. Power outages caused by faults disrupt daily life and interfere with normal business operations.

[0003] The traveling wave fault location system for distribution networks can quickly determine the fault range, reduce labor intensity, improve power supply efficiency, and lay a solid foundation for intelligent distribution network management. For example, existing distribution network traveling wave fault location systems use terminals to monitor the three-phase-to-ground voltage and zero-sequence voltage in real time. When the zero-sequence voltage exceeds a set value U1, the system marks the start time. Simultaneously, when the effective value of the zero-sequence voltage exceeds a set value U2, the system transmits the effective value of the zero-sequence voltage, the effective value of the phase voltage, and the start time data back to the master station via GPRS. The master station then comprehensively analyzes the timestamps sent back by each terminal, along with information such as the terminal's installation location on the line, line characteristics, and branch length, to ultimately determine the location of the fault. For example, the fault location terminal of a medium-voltage line in the time-domain method uses GPS satellite timing, and the time error between each terminal is controlled within an accuracy range of 1μs; a high-precision acquisition chip is used to collect the system zero-sequence voltage in real time, with a sampling frequency of 1MHz and a measurement error of less than 1mV, and the zero-sequence voltage start-up time is recorded; a database is established to calculate and store the conduction speed of zero-sequence voltage in overhead lines and in cable lines in real time, and the location of the fault is determined by using big data analysis, combined with the line topology map and specific algorithms.

[0004] However, existing power distribution network traveling wave fault location devices all use dedicated terminals, which are costly to design and manufacture, hindering large-scale application. Furthermore, the design schemes of various equipment manufacturers differ significantly; some use voltage traveling wave waveforms as the criterion, others use electromagnetic traveling wave waveforms, and still others collect both voltage and current traveling wave waveforms. This results in inconsistent data specifications, complex management of the main station's measuring equipment and data, and is unsuitable for large-scale application. Summary of the Invention

[0005] To overcome the above-mentioned shortcomings, this invention proposes a data acquisition board for traveling wave fault location.

[0006] In a first aspect, a data acquisition board for traveling wave fault location is provided, the data acquisition board for traveling wave fault location includes: a voltage / current sensor, a PGA chip, an ADC chip, an FPGA chip, a Beidou module, an SDRAM chip, a TF card, an SPI and an interrupt interface, and a main control device; The voltage / current sensor, PGA chip, and ADC chip are connected in sequence. The PGA chip, ADC chip, Beidou module, SDRAM chip, TF card, SPI and interrupt interface are respectively connected to the FPGA chip; The SPI and interrupt interface are connected to the master control device; The voltage / current sensor is used to collect voltage / current data; The PGA chip is used to amplify the voltage / current signal collected by the voltage / current sensor to a preset range; The ADC chip is used to convert the analog signal output by the PGA chip into digital data; The SDRAM chip is used to cache the digital data generated by the ADC sampling. The TF card is used to store the working configuration file and the fault traveling wave waveform file; The SPI and interrupt interface are used for data exchange with the host device; The main control device is used to read fault data and send it to the main station; The FPGA chip is used for time synchronization via the Beidou module, to collect voltage / current waveform data via the ADC chip, to perform multi-frequency fault traveling wave head detection, to record the fault occurrence time when a fault is detected, to store the fault traveling wave waveform file to the TF card, and to notify the main control device to read the fault data and send it to the main station via an interrupt pulse output.

[0007] Preferably, the acquisition board includes a power supply for powering the acquisition board.

[0008] Furthermore, the registers of the FPGA chip include: operating status register, interrupt configuration register, PGA configuration register, sampling configuration register, traveling wave detection configuration register, real-time time register, fault time register, and fault waveform configuration register.

[0009] Furthermore, the working status register includes one access address. When the FPGA chip completes time synchronization, the 0th bit of the access address is set. When the FPGA chip detects a fault traveling wave, the 1st bit of the access address is set. When the FPGA chip generates a fault traveling wave waveform file, the 2nd bit of the access address is set. When the FPGA chip detects a PGA chip fault, the 3rd bit of the access address is set. When the FPGA chip detects an ADC chip fault, the 4th bit of the access address is set. When the FPGA chip detects a Beidou module fault, the 5th bit of the access address is set. When the FPGA chip detects an SDRAM chip fault, the 6th bit of the access address is set. When the FPGA chip detects a TF card fault, the 7th bit of the access address is set.

[0010] Furthermore, the interrupt configuration register includes one access address, wherein when the 0th bit of the access address of the working status register is set and the 0th bit of the access address of the interrupt configuration register is set, it indicates that the time synchronization interrupt pulse output is enabled. When the first bit of the access address of the working status register is set and the first bit of the access address of the interrupt configuration register is set, it indicates that the fault traveling wave interrupt pulse output is enabled. When the second bit of the access address of the working status register is set and the second bit of the access address of the interrupt configuration register is set, it indicates that the generation of fault traveling wave waveform file interrupt pulse output is enabled; When the third bit of the access address of the working status register is set and the third bit of the access address of the interrupt configuration register is set, it indicates that the PGA fault interrupt pulse output is enabled; When the 4th bit of the access address of the working status register is set and the 4th bit of the access address of the interrupt configuration register is set, it indicates that the ADC fault interrupt pulse output is enabled. When the 5th bit of the access address of the working status register is set and the 5th bit of the access address of the interrupt configuration register is set, it indicates that the Beidou module fault interrupt pulse output is enabled. When the 6th bit of the access address of the working status register is set and the 6th bit of the access address of the interrupt configuration register is set, it indicates that the SDRAM fault interrupt pulse output is enabled. When the 7th bit of the access address of the working status register is set, and the 7th bit of the access address of the interrupt configuration register is set, it indicates that the TF card fault interrupt pulse output is enabled.

[0011] Furthermore, the PGA configuration register includes eight access addresses, each used to set the channel gain level of its corresponding PGA chip.

[0012] Furthermore, the sampling configuration register includes four access addresses, wherein the first access address is used to set the data bit width of the ADC chip, the second access address is used to set the sampling channel of the ADC chip to use a bitmap, the third access address is used to set the sampling rate of the ADC chip for the high 8 bits, and the fourth access address is used to set the sampling rate of the ADC chip for the low 8 bits.

[0013] Furthermore, the traveling wave detection configuration register includes eight access addresses. The first access address is used to set the high 8 bits of detection frequency point 1, the second access address is used to set the low 8 bits of detection frequency point 1, the third access address is used to set the high 8 bits of detection frequency point 2, the fourth access address is used to set the low 8 bits of detection frequency point 2, the fifth access address is used to set the high 8 bits of detection frequency point 3, the sixth access address is used to set the low 8 bits of detection frequency point 3, the seventh access address is used to set the high 8 bits of detection frequency point 4, and the eighth access address is used to set the low 8 bits of detection frequency point 4.

[0014] Furthermore, the real-time register includes seven access addresses. The first access address is used to generate the highest 8 bits of the real-time second value, the second access address is used to generate the second highest 8 bits of the real-time second value, the third access address is used to generate the second lowest 8 bits of the real-time second value, the fourth access address is used to generate the lowest 8 bits of the real-time second value, the fifth access address is used to generate the second highest 8 bits of the real-time 0.1 microsecond value, the sixth access address is used to generate the second lowest 8 bits of the real-time 0.1 microsecond value, and the seventh access address is used to generate the lowest 8 bits of the real-time 0.1 microsecond value.

[0015] Furthermore, the fault time register includes 7 access addresses. The first access address is used to generate the highest 8 bits of the fault occurrence time in seconds. The second access address is used to generate the second highest 8 bits of the fault occurrence time in seconds. The third access address is used to generate the second lowest 8 bits of the fault occurrence time in seconds. The fourth access address is used to generate the lowest 8 bits of the fault occurrence time in seconds. The fifth access address is used to generate the second highest 8 bits of the fault occurrence time in 0.1 microseconds. The sixth access address is used to generate the second lowest 8 bits of the fault occurrence time in 0.1 microseconds. The seventh access address is used to generate the lowest 8 bits of the fault occurrence time in 0.1 microseconds.

[0016] Furthermore, the fault waveform configuration register includes four access addresses. The first access address is used to set the high 8 bits of the time between the start point of the fault waveform recording and the fault wavehead. The second access address is used to set the low 8 bits of the time between the start point of the fault waveform recording and the fault wavehead. The third access address is used to set the high 8 bits of the time between the end point of the fault waveform recording and the fault wavehead. The fourth access address is used to set the low 8 bits of the time between the end point of the fault waveform recording and the fault wavehead.

[0017] Furthermore, the FPGA chip is specifically used for: detecting peripheral devices; when a fault is detected, outputting the corresponding peripheral device's interrupt pulse to the main control device through the SPI and interrupt interface, loading the corresponding peripheral device's working configuration file from the TF card, performing time synchronization through the Beidou module after configuration, outputting a time synchronization interrupt pulse to the main control device through the SPI and interrupt interface after clock synchronization is completed, and starting the ADC chip to work, collecting voltage / current waveform data and buffering it in SDRAM; performing multi-frequency point fault traveling wave head detection; when a fault is detected, recording the fault occurrence time to the fault time register, outputting a fault traveling wave interrupt pulse to the main control device through the SPI and interrupt interface, storing the fault waveform data to the TF card according to the fault waveform configuration register, generating a fault waveform file, and outputting a fault traveling wave waveform file generation interrupt pulse so that the main control device reads the fault data and sends it to the main station when it detects the generation of the fault traveling wave waveform file interrupt pulse; The peripheral devices include: PGA chip, ADC chip, FPGA chip, Beidou module, SDRAM chip and TF card.

[0018] The above-described technical solutions of the present invention have at least one or more of the following beneficial effects: This invention provides a data acquisition board for traveling wave fault location. The acquisition board includes: a voltage / current sensor, a PGA chip, an ADC chip, an FPGA chip, a Beidou module, an SDRAM chip, a TF card, an SPI and interrupt interface, and a main control device. The voltage / current sensor, PGA chip, and ADC chip are connected sequentially. The PGA chip, ADC chip, Beidou module, SDRAM chip, TF card, SPI, and interrupt interface are respectively connected to the FPGA chip. The SPI and interrupt interface are connected to the main control device. The voltage / current sensor is used to acquire voltage / current data. The PGA chip is used to amplify the voltage / current signal acquired by the voltage / current sensor to a preset range. The ADC chip is used to convert the analog signal output by the PGA chip into digital data; the SDRAM chip is used to buffer the digital data generated by the ADC sampling; the TF card is used to store the working configuration file and the fault traveling wave waveform file; the SPI and interrupt interface are used to exchange data with the master control device; the master control device is used to read the fault data and send it to the master station; the FPGA chip is used for time synchronization through the Beidou module, to collect voltage / current waveform data through the ADC chip, to perform multi-frequency fault traveling wave head detection, to record the fault occurrence time when a fault is detected, to store the fault traveling wave waveform file in the TF card, and to notify the master control device to read the fault data and send it to the master station through an interrupt pulse output. The technical solution provided by this invention uses an FPGA as the control core and integrates peripheral devices such as PGA, high-speed ADC, and SDRAM, which facilitates the further development of dedicated chips with higher integration and can further reduce costs. It adopts a dedicated board design, enabling mass production and reducing manufacturing costs. A single board can be used in multiple ways: it can be integrated into other main control devices, such as FTUs or distribution network switches, or it can be used with an MCU to create dedicated devices. It supports software configuration functions and can flexibly adapt to various types of voltage and current sensors, supporting both single-channel voltage or current fault traveling wave detection and mixed voltage and current multi-channel fault traveling wave detection, possessing wide applicability and meeting various application requirements. Attached Figure Description

[0019] Figure 1 This is a block diagram of the main structure of the acquisition board for traveling wave fault location according to an embodiment of the present invention. Detailed Implementation

[0020] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] As disclosed in the background section, power distribution networks are characterized by a large number of lines, long distances, complex lines, and a large number of users. During operation, they are susceptible to lightning strikes, strong winds, fires, and other disturbances, resulting in numerous transient faults. Furthermore, the fault locations are often hidden and difficult to locate, requiring a large investigation area and leading to lengthy fault handling cycles, thus affecting power supply reliability. Power outages caused by faults disrupt daily life and interfere with normal business operations.

[0023] The traveling wave fault location system for distribution networks can quickly determine the fault range, reduce labor intensity, improve power supply efficiency, and lay a solid foundation for intelligent distribution network management. For example, existing distribution network traveling wave fault location systems use terminals to monitor the three-phase-to-ground voltage and zero-sequence voltage in real time. When the zero-sequence voltage exceeds a set value U1, the system marks the start time. Simultaneously, when the effective value of the zero-sequence voltage exceeds a set value U2, the system transmits the effective value of the zero-sequence voltage, the effective value of the phase voltage, and the start time data back to the master station via GPRS. The master station then comprehensively analyzes the timestamps sent back by each terminal, along with information such as the terminal's installation location on the line, line characteristics, and branch length, to ultimately determine the location of the fault. For example, the fault location terminal of a medium-voltage line in the time-domain method uses GPS satellite timing, and the time error between each terminal is controlled within an accuracy range of 1μs; a high-precision acquisition chip is used to collect the system zero-sequence voltage in real time, with a sampling frequency of 1MHz and a measurement error of less than 1mV, and the zero-sequence voltage start-up time is recorded; a database is established to calculate and store the conduction speed of zero-sequence voltage in overhead lines and in cable lines in real time, and the location of the fault is determined by using big data analysis, combined with the line topology map and specific algorithms.

[0024] However, existing power distribution network traveling wave fault location devices all use dedicated terminals, which are costly to design and manufacture, hindering large-scale application. Furthermore, the design schemes of various equipment manufacturers differ significantly; some use voltage traveling wave waveforms as the criterion, others use electromagnetic traveling wave waveforms, and still others collect both voltage and current traveling wave waveforms. This results in inconsistent data specifications, complex management of the main station's measuring equipment and data, and is unsuitable for large-scale application.

[0025] To address the aforementioned problems, this invention provides a data acquisition board for traveling wave fault location. The acquisition board includes: a voltage / current sensor, a PGA chip, an ADC chip, an FPGA chip, a BeiDou module, an SDRAM chip, a TF card, an SPI interface and an interrupt interface, and a main control device. The voltage / current sensor, PGA chip, and ADC chip are connected sequentially. The PGA chip, ADC chip, BeiDou module, SDRAM chip, TF card, SPI interface, and interrupt interface are respectively connected to the FPGA chip. The SPI interface and interrupt interface are connected to the main control device. The voltage / current sensor is used to acquire voltage / current data. The PGA chip is used to amplify the voltage / current signal acquired by the voltage / current sensor to a preset value. The scope includes: the ADC chip, used to convert the analog signal output by the PGA chip into digital data; the SDRAM chip, used to cache the digital data generated by the ADC sampling; the TF card, used to store the working configuration file and the fault traveling wave waveform file; the SPI and interrupt interface, used to exchange data with the main control device; the main control device, used to read the fault data and send it to the main station; and the FPGA chip, used for time synchronization via the Beidou module, to collect voltage / current waveform data through the ADC chip, to perform multi-frequency fault traveling wave head detection, to record the fault occurrence time when a fault is detected, to store the fault traveling wave waveform file in the TF card, and to notify the main control device to read the fault data and send it to the main station via an interrupt pulse output. The technical solution provided by this invention uses an FPGA as the control core and integrates peripheral devices such as PGA, high-speed ADC, and SDRAM, which facilitates the further development of dedicated chips with higher integration and can further reduce costs. It adopts a dedicated board design, enabling mass production and reducing manufacturing costs. A single board can be used in multiple ways: it can be integrated into other main control devices, such as FTUs or distribution network switches, or it can be used with an MCU to create dedicated devices. It supports software configuration functions and can flexibly adapt to various types of voltage and current sensors, supporting both single-channel voltage or current fault traveling wave detection and mixed voltage and current multi-channel fault traveling wave detection, possessing wide applicability and meeting various application requirements.

[0026] The above plan will be explained in detail below.

[0027] Example 1 See appendix Figure 1 , Figure 1 This is a main structural block diagram of a data acquisition board for traveling wave fault location, according to an embodiment of the present invention. Figure 1 As shown, the acquisition board for traveling wave fault location in this embodiment of the invention mainly includes: a voltage / current sensor, a PGA chip, an ADC chip, an FPGA chip, a Beidou module, an SDRAM chip, a TF card, an SPI and interrupt interface, and a main control device. The voltage / current sensor, PGA chip, and ADC chip are connected in sequence. The PGA chip, ADC chip, Beidou module, SDRAM chip, TF card, SPI and interrupt interface are respectively connected to the FPGA chip; The SPI and interrupt interface are connected to the master control device; The voltage / current sensor is used to collect voltage / current data; The PGA chip is used to amplify the voltage / current signal collected by the voltage / current sensor to a preset range; The ADC chip is used to convert the analog signal output by the PGA chip into digital data; The SDRAM chip is used to cache the digital data generated by the ADC sampling. The TF card is used to store the working configuration file and the fault traveling wave waveform file; The SPI and interrupt interface are used for data exchange with the host device; The main control device is used to read fault data and send it to the main station; The FPGA chip is used for time synchronization via the Beidou module, to collect voltage / current waveform data via the ADC chip, to perform multi-frequency fault traveling wave head detection, to record the fault occurrence time when a fault is detected, to store the fault traveling wave waveform file to the TF card, and to notify the main control device to read the fault data and send it to the main station via an interrupt pulse output.

[0028] In this embodiment, the acquisition board includes a power supply for supplying power to the acquisition board.

[0029] In one specific implementation, the FPGA chip uses a highly integrated, high-performance FPGA as the core for data acquisition and processing, performing functions such as clock synchronization, voltage / current signal waveform data acquisition, fault traveling wave characteristic detection, fault traveling wave waveform storage, and fault event and data transmission. The FPGA has a PGA control interface, a high-speed ADC parallel data interface, a Beidou module control interface, a TF card interface, an SDRAM interface, an SPI communication interface, and interrupt and status indication interfaces.

[0030] PGA chip: Uses a wideband PGA chip with SPI or I2C communication control interface, bandwidth greater than 10MHz, adjustable gain of 128 levels, which can be easily adapted to various types of voltage / current sensors to amplify the sensor signal to a suitable range for ADC data sampling.

[0031] ADC Chip: A high-speed ADC chip is used to convert the analog signal output by the PGA into digital data. The maximum sampling rate is not less than 5Mbps. The FPGA reads the conversion result at high speed according to the sampling rate and buffers the data into SDRAM to form the sampled waveform data.

[0032] BeiDou Module: Utilizes a BeiDou positioning and timing module with high-precision second pulse output. The FPGA receives the positioning and time information output by the BeiDou module via a serial port, and simultaneously detects the rising edge of the second pulse output by the BeiDou module, aligning the FPGA's internal time to the international standard time with a time synchronization accuracy of no more than 0.1µs.

[0033] SDRAM chip: Uses 32MB of high-speed synchronous dynamic random access memory to cache waveform data generated by ADC sampling.

[0034] TF Card: Uses a 4GB industrial-grade TF memory card to store working configuration files and historical fault waveform files.

[0035] SPI and Interrupt Interface: Provides one high-speed SPI interface with a maximum speed of 100Mbps for data exchange with the master device; provides one interrupt output that outputs a high-level pulse when an event occurs; after the master device detects the interrupt event signal, it reads the FPGA's event status register and performs data reading according to the event.

[0036] Power supply: A DC-DC chip with a wide input voltage range is used to convert the 5V-24V input to output voltages such as 5V, 3.3V, and 1.8V to supply the various components on the board.

[0037] This data acquisition board obtains accurate real-time time via BeiDou; it acquires line voltage / current waveform data at high speed via ADC and caches it in SDRAM; simultaneously, it detects fault traveling wave fronts using wavelet transform algorithms; upon detection of a fault traveling wave front, it immediately records the traveling wave front time and generates a fault waveform file containing the waveform data of the first 10ms (configurable) and last 30ms (configurable) of the traveling wave front, storing it in a TF card with the waveform file name "Fault Wave Front Time"; it updates the fault occurrence bit in the status register and outputs an interrupt pulse; after the master control device detects the interrupt pulse output by the board, it reads the status register, the fault occurrence time, and the fault waveform file via the SPI interface, and uploads the fault event and data to the master station.

[0038] In one embodiment, the registers of the FPGA chip include: a working status register, an interrupt configuration register, a PGA configuration register, a sampling configuration register, a traveling wave detection configuration register, a real-time time register, a fault time register, and a fault waveform configuration register.

[0039] In one embodiment, the working status register includes one access address. When the FPGA chip completes time synchronization, the 0th bit of the access address is set. When the FPGA chip detects a fault traveling wave, the 1st bit of the access address is set. When the FPGA chip generates a fault traveling wave waveform file, the 2nd bit of the access address is set. When the FPGA chip detects a PGA chip fault, the 3rd bit of the access address is set. When the FPGA chip detects an ADC chip fault, the 4th bit of the access address is set. When the FPGA chip detects a Beidou module fault, the 5th bit of the access address is set. When the FPGA chip detects an SDRAM chip fault, the 6th bit of the access address is set. When the FPGA chip detects a TF card fault, the 7th bit of the access address is set.

[0040] In one embodiment, the interrupt configuration register includes one access address, wherein when the 0th bit of the access address of the working status register is set and the 0th bit of the access address of the interrupt configuration register is set, it indicates that the time synchronization interrupt pulse output is enabled. When the first bit of the access address of the working status register is set and the first bit of the access address of the interrupt configuration register is set, it indicates that the fault traveling wave interrupt pulse output is enabled. When the second bit of the access address of the working status register is set and the second bit of the access address of the interrupt configuration register is set, it indicates that the generation of fault traveling wave waveform file interrupt pulse output is enabled; When the third bit of the access address of the working status register is set and the third bit of the access address of the interrupt configuration register is set, it indicates that the PGA fault interrupt pulse output is enabled; When the 4th bit of the access address of the working status register is set and the 4th bit of the access address of the interrupt configuration register is set, it indicates that the ADC fault interrupt pulse output is enabled. When the 5th bit of the access address of the working status register is set and the 5th bit of the access address of the interrupt configuration register is set, it indicates that the Beidou module fault interrupt pulse output is enabled. When the 6th bit of the access address of the working status register is set and the 6th bit of the access address of the interrupt configuration register is set, it indicates that the SDRAM fault interrupt pulse output is enabled. When the 7th bit of the access address of the working status register is set, and the 7th bit of the access address of the interrupt configuration register is set, it indicates that the TF card fault interrupt pulse output is enabled.

[0041] In one implementation, the PGA configuration register includes eight access addresses, each used to set the channel gain level of its corresponding PGA chip.

[0042] In one embodiment, the sampling configuration register includes four access addresses, wherein the first access address is used to set the data bit width of the ADC chip, the second access address is used to set the sampling channel of the ADC chip to use a bitmap, the third access address is used to set the sampling rate of the ADC chip to the high 8 bits, and the fourth access address is used to set the sampling rate of the ADC chip to the low 8 bits.

[0043] In one embodiment, the traveling wave detection configuration register includes eight access addresses. The first access address is used to set the high 8 bits of detection frequency 1, the second access address is used to set the low 8 bits of detection frequency 1, the third access address is used to set the high 8 bits of detection frequency 2, the fourth access address is used to set the low 8 bits of detection frequency 2, the fifth access address is used to set the high 8 bits of detection frequency 3, the sixth access address is used to set the low 8 bits of detection frequency 3, the seventh access address is used to set the high 8 bits of detection frequency 4, and the eighth access address is used to set the low 8 bits of detection frequency 4.

[0044] In one embodiment, the real-time register includes seven access addresses: the first access address is used to generate the highest 8 bits of the real-time second value; the second access address is used to generate the second highest 8 bits of the real-time second value; the third access address is used to generate the second lowest 8 bits of the real-time second value; the fourth access address is used to generate the lowest 8 bits of the real-time second value; the fifth access address is used to generate the second highest 8 bits of the real-time 0.1 microsecond value; the sixth access address is used to generate the second lowest 8 bits of the real-time 0.1 microsecond value; and the seventh access address is used to generate the lowest 8 bits of the real-time 0.1 microsecond value.

[0045] In one embodiment, the fault time register includes seven access addresses: the first access address is used to generate the highest 8 bits of the fault occurrence time in seconds; the second access address is used to generate the second highest 8 bits of the fault occurrence time in seconds; the third access address is used to generate the second lowest 8 bits of the fault occurrence time in seconds; the fourth access address is used to generate the lowest 8 bits of the fault occurrence time in seconds; the fifth access address is used to generate the second highest 8 bits of the fault occurrence time in 0.1 microseconds; the sixth access address is used to generate the second lowest 8 bits of the fault occurrence time in 0.1 microseconds; and the seventh access address is used to generate the lowest 8 bits of the fault occurrence time in 0.1 microseconds.

[0046] In one embodiment, the fault waveform configuration register includes four access addresses. The first access address is used to set the high 8 bits of the time elapsed between the start point and the fault wavehead of the fault waveform recording. The second access address is used to set the low 8 bits of the time elapsed between the start point and the fault wavehead of the fault waveform recording. The third access address is used to set the high 8 bits of the time elapsed between the end point and the fault wavehead of the fault waveform recording. The fourth access address is used to set the low 8 bits of the time elapsed between the end point and the fault wavehead of the fault waveform recording.

[0047] In one embodiment, the FPGA chip is specifically used for: detecting peripheral devices; when a fault is detected, outputting an interrupt pulse for the corresponding peripheral device to the main control device through the SPI and interrupt interface, loading the working configuration file of the corresponding peripheral device from the TF card, performing time synchronization through the Beidou module after configuration, outputting a time synchronization interrupt pulse to the main control device through the SPI and interrupt interface after clock synchronization is completed, and starting the ADC chip to work, collecting voltage / current waveform data and buffering it in SDRAM; performing multi-frequency point fault traveling wave head detection; when a fault is detected, recording the fault occurrence time to the fault time register, outputting a fault traveling wave interrupt pulse to the main control device through the SPI and interrupt interface, storing fault waveform data in the TF card according to the fault waveform configuration register, generating a fault waveform file, and outputting a fault traveling wave waveform file generation interrupt pulse, so that when the main control device detects the generation of the fault traveling wave waveform file interrupt pulse, it reads the fault data and sends it to the main station; The peripheral devices include: PGA chip, ADC chip, FPGA chip, Beidou module, SDRAM chip and TF card.

[0048] The fault traveling wave acquisition board introduced in this invention can automatically perform high-precision clock synchronization; automatically acquire multiple voltage / current waveform data synchronously according to the configuration, and synchronously perform multi-frequency fault traveling wave head detection; when a fault is detected, it automatically records the fault occurrence time and stores the fault traveling wave waveform file; and notifies the main control device to read the status and data in a timely manner through interrupt pulse output, and promptly sends the data to the main station.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A data acquisition board for traveling wave fault location, characterized in that, The acquisition board includes: a voltage / current sensor, a PGA chip, an ADC chip, an FPGA chip, a Beidou module, an SDRAM chip, a TF card, an SPI and interrupt interface, and a main control device; The voltage / current sensor, PGA chip, and ADC chip are connected in sequence. The PGA chip, ADC chip, Beidou module, SDRAM chip, TF card, SPI and interrupt interface are respectively connected to the FPGA chip; The SPI and interrupt interface are connected to the master control device; The voltage / current sensor is used to collect voltage / current data; The PGA chip is used to amplify the voltage / current signal collected by the voltage / current sensor to a preset range; The ADC chip is used to convert the analog signal output by the PGA chip into digital data; The SDRAM chip is used to cache the digital data generated by the ADC sampling. The TF card is used to store the working configuration file and the fault traveling wave waveform file; The SPI and interrupt interface are used for data exchange with the host device; The main control device is used to read fault data and send it to the main station; The FPGA chip is used for time synchronization via the Beidou module, to collect voltage / current waveform data via the ADC chip, to perform multi-frequency fault traveling wave head detection, to record the fault occurrence time when a fault is detected, to store the fault traveling wave waveform file to the TF card, and to notify the main control device to read the fault data and send it to the main station via an interrupt pulse output.

2. The acquisition board as described in claim 1, characterized in that, The acquisition board includes a power supply for powering the acquisition board.

3. The acquisition board as described in claim 1, characterized in that, The registers of the FPGA chip include: operating status register, interrupt configuration register, PGA configuration register, sampling configuration register, traveling wave detection configuration register, real-time time register, fault time register, and fault waveform configuration register.

4. The acquisition board as described in claim 3, characterized in that, The working status register includes one access address. When the FPGA chip completes time synchronization, the 0th bit of the access address is set. When the FPGA chip detects a fault traveling wave, the 1st bit of the access address is set. When the FPGA chip generates a fault traveling wave waveform file, the 2nd bit of the access address is set. When the FPGA chip detects a PGA chip fault, the 3rd bit of the access address is set. When the FPGA chip detects an ADC chip fault, the 4th bit of the access address is set. When the FPGA chip detects a Beidou module fault, the 5th bit of the access address is set. When the FPGA chip detects an SDRAM chip fault, the 6th bit of the access address is set. When the FPGA chip detects a TF card fault, the 7th bit of the access address is set.

5. The acquisition board as described in claim 4, characterized in that, The interrupt configuration register includes one access address. When the 0th bit of the access address of the working status register is set, the 0th bit of the access address of the interrupt configuration register is also set, indicating that the time synchronization interrupt pulse output is enabled. When the first bit of the access address of the working status register is set and the first bit of the access address of the interrupt configuration register is set, it indicates that the fault traveling wave interrupt pulse output is enabled. When the second bit of the access address of the working status register is set and the second bit of the access address of the interrupt configuration register is set, it indicates that the generation of fault traveling wave waveform file interrupt pulse output is enabled; When the third bit of the access address of the working status register is set and the third bit of the access address of the interrupt configuration register is set, it indicates that the PGA fault interrupt pulse output is enabled; When the 4th bit of the access address of the working status register is set and the 4th bit of the access address of the interrupt configuration register is set, it indicates that the ADC fault interrupt pulse output is enabled. When the 5th bit of the access address of the working status register is set and the 5th bit of the access address of the interrupt configuration register is set, it indicates that the Beidou module fault interrupt pulse output is enabled. When the 6th bit of the access address of the working status register is set and the 6th bit of the access address of the interrupt configuration register is set, it indicates that the SDRAM fault interrupt pulse output is enabled. When the 7th bit of the access address of the working status register is set, and the 7th bit of the access address of the interrupt configuration register is set, it indicates that the TF card fault interrupt pulse output is enabled.

6. The acquisition board as described in claim 3, characterized in that, The PGA configuration register includes eight access addresses, each used to set the channel gain level of its corresponding PGA chip.

7. The acquisition board as described in claim 3, characterized in that, The sampling configuration register includes four access addresses. The first access address is used to set the data bit width of the ADC chip, the second access address is used to set the sampling channel of the ADC chip to use a bitmap, the third access address is used to set the sampling rate of the ADC chip for the high 8 bits, and the fourth access address is used to set the sampling rate of the ADC chip for the low 8 bits.

8. The acquisition board as described in claim 3, characterized in that, The traveling wave detection configuration register includes eight access addresses. The first access address is used to set the high 8 bits of detection frequency point 1, the second access address is used to set the low 8 bits of detection frequency point 1, the third access address is used to set the high 8 bits of detection frequency point 2, the fourth access address is used to set the low 8 bits of detection frequency point 2, the fifth access address is used to set the high 8 bits of detection frequency point 3, the sixth access address is used to set the low 8 bits of detection frequency point 3, the seventh access address is used to set the high 8 bits of detection frequency point 4, and the eighth access address is used to set the low 8 bits of detection frequency point 4.

9. The acquisition board as described in claim 3, characterized in that, The real-time register includes 7 access addresses. The first access address is used to generate the highest 8 bits of the real-time second value, the second access address is used to generate the second highest 8 bits of the real-time second value, the third access address is used to generate the second lowest 8 bits of the real-time second value, the fourth access address is used to generate the lowest 8 bits of the real-time second value, the fifth access address is used to generate the second highest 8 bits of the real-time 0.1 microsecond value, the sixth access address is used to generate the second lowest 8 bits of the real-time 0.1 microsecond value, and the seventh access address is used to generate the lowest 8 bits of the real-time 0.1 microsecond value.

10. The acquisition board as described in claim 3, characterized in that, The fault time register includes 7 access addresses. The first access address is used to generate the highest 8 bits of the fault occurrence time in seconds. The second access address is used to generate the second highest 8 bits of the fault occurrence time in seconds. The third access address is used to generate the second lowest 8 bits of the fault occurrence time in seconds. The fourth access address is used to generate the lowest 8 bits of the fault occurrence time in seconds. The fifth access address is used to generate the second highest 8 bits of the fault occurrence time in 0.1 microseconds. The sixth access address is used to generate the second lowest 8 bits of the fault occurrence time in 0.1 microseconds. The seventh access address is used to generate the lowest 8 bits of the fault occurrence time in 0.1 microseconds.

11. The acquisition board as described in claim 3, characterized in that, The fault waveform configuration register includes four access addresses. The first access address is used to set the high 8 bits of the time between the start point of the fault waveform recording and the fault wavehead. The second access address is used to set the low 8 bits of the time between the start point of the fault waveform recording and the fault wavehead. The third access address is used to set the high 8 bits of the time between the end point of the fault waveform recording and the fault wavehead. The fourth access address is used to set the low 8 bits of the time between the end point of the fault waveform recording and the fault wavehead.

12. The acquisition board as described in claim 5, characterized in that, The FPGA chip is specifically used for: detecting peripheral devices; when a fault is detected, outputting the corresponding peripheral device interrupt pulse to the main control device through the SPI and interrupt interface, loading the corresponding peripheral device working configuration file from the TF card, performing time synchronization through the Beidou module after configuration, outputting time synchronization interrupt pulse to the main control device through the SPI and interrupt interface after clock synchronization is completed, and starting the ADC chip to work, collecting voltage / current waveform data and caching it in SDRAM. Multi-frequency point fault traveling wave head detection is performed. When a fault is detected, the fault occurrence time is recorded in the fault time register. The fault traveling wave interrupt pulse is output to the main control device through the SPI and interrupt interface. The fault waveform data is stored in the TF card according to the fault waveform configuration register, a fault waveform file is generated, and an interrupt pulse for generating the fault traveling wave waveform file is output so that the main control device can read the fault data and send it to the main station when it detects the generation of the fault traveling wave waveform file interrupt pulse. The peripheral devices include: PGA chip, ADC chip, FPGA chip, Beidou module, SDRAM chip and TF card.

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