Chip, chip collapse test method and chip test method

Abstract

According to the chip, the chip collapse testing method and the chip testing method, automatic collapse can be triggered after the chip is powered on, the collapse progress state can be fed back and monitored in real time through the potential state change of the corresponding IO pin of the chip, and therefore the chip collapse can be automatically tested in the chip collapse period. According to the technical scheme, the testing machine can obtain the collapse progress state of the chip without additionally sending a corresponding instruction to the chip, and when collapse abnormal interruption (such as collapse interruption caused by abnormal power failure of the chip due to poor contact or other reasons) occurs, the testing machine or personnel can find the collapse abnormal interruption in time, so that time waste is avoided.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a chip, a chip collapse testing method, and a chip testing method. Background Technology

[0002] Burn-in testing is a testing and screening method performed on chips during the chip manufacturing process to ensure the reliability of chips after they leave the factory.

[0003] Traditional burst testing is a board-level burst testing method. Before the chip leaves the factory (i.e., before it is officially put into use), it is placed on a test board, and additional test programs are provided (e.g., sending separate read, write, and erase commands to memory chips). This forces the chip to operate under specific conditions for an extended period (i.e., the chip performs burst actions), accelerating the occurrence of potential failures and reliability issues. Through burst testing, chip manufacturers can detect potential electrical problems, temperature sensitivity, instability, and reliability issues. This allows for early screening of defective chips, preventing them from entering the market or failing during use, thereby improving product quality and reliability.

[0004] Traditional chip collapse testing techniques have the following drawbacks:

[0005] 1. It requires a lot of machine time and manpower to complete in the factory, resulting in high costs.

[0006] 2. The chip is greatly affected by external factors such as the stability of the power supply voltage, the good contact of the test board, and the standardization of the test operation method. These factors can easily lead to electrostatic damage, overkill, and damage from external stress during the test, causing unnecessary losses.

[0007] 3. The chip performs stress response actions according to the test instructions (such as the memory chip performing read, write, and erase operations). However, during the stress test, problems such as poor contact of the test board may occur, which may cause the stress test to fail to proceed or end normally. The existing solution cannot monitor these problems in real time and can only wait for a fixed time and then force a power-off to end the stress test. Summary of the Invention

[0008] The purpose of this invention is to provide a chip, a chip collapse test method, and a chip test method that can automatically trigger a collapse after the chip is powered on, and can monitor the progress of the automatic collapse of the chip in real time during the automatic collapse.

[0009] To achieve the above objectives, the present invention provides a chip having I / O pins for reflecting the progress status of an automatic collapse response, and the chip is used to trigger the automatic collapse response after power-on, and to change the potential state of the I / O pins in real time according to the progress status of the automatic collapse response, so as to realize real-time monitoring of the progress status of the automatic collapse response.

[0010] Before power-on, the IO pin is in a high-impedance state; after the automatic collapse is started normally, the potential of the IO pin is pulled to a first level by the chip; after the automatic collapse is completed normally, the potential of the IO pin is pulled to a second level different from the first level by the chip; when the automatic collapse is not started normally or the automatic collapse is abnormally interrupted, the potential of the IO pin is restored to a high-impedance state by the chip.

[0011] Optionally, the chip has a first flag bit written inside. When the chip detects that the value of the first flag bit is equal to the first value after power-on, the automatic crash response is started normally. After the automatic crash response ends normally, the first flag bit is rewritten by the chip to a second value, which is different from the first value.

[0012] Optionally, the number of bits in the first flag bit is greater than or equal to 2; and / or at least one bit in the first value of the first flag bit is rewritten to achieve the rewriting to the second value.

[0013] Optionally, after the chip passes the corresponding wafer-level test and before the chip is packaged, the first flag bit is written to the first value, wherein the first flag bit is stored in the chip's trimming memory area.

[0014] Optionally, the chip also has a second flag bit written inside, the value of which is used to set the number of times the chip is programmed-erase operation is performed in the automatic crash.

[0015] Optionally, the chip further includes:

[0016] The analog circuit module is used to generate a power-on status signal (PWRON) and a collapse status bit signal (EMOSC_EN) when the chip is powered on.

[0017] A digital logic module, coupled to the analog circuit module, is used to read and identify the value of the first flag bit after receiving the power-on status signal, and generate a collapse enable signal (BI_OEN) when the value of the first flag bit is identified as equal to the first value and start the automatic collapse of the chip normally.

[0018] A timing circuit module, coupled to the digital logic module, is used to output a clock signal (SCLK) according to the collapse enable signal;

[0019] The interface circuit module is coupled to the analog circuit module, the digital logic module, the timing circuit module and the IO pin, and is used to perform AND logic operation on the collapse state bit signal and the collapse enable signal, and according to the clock signal and the result of the AND logic operation, pull the potential of the IO pin to the first level or the second level or restore it to the high impedance state.

[0020] Optionally, the interface circuit module includes an AND logic operation circuit and a flip-flop. One input terminal of the AND logic operation circuit is coupled to the analog circuit module to receive the collapse state bit signal. The other input terminal of the AND logic operation circuit is coupled to the digital logic module to receive the collapse enable signal. The output terminal of the AND logic operation circuit is coupled to the input terminal of the flip-flop. The clock terminal of the flip-flop is coupled to the timing circuit module to receive the clock signal. The output terminal of the flip-flop is coupled to the I / O pin.

[0021] Optionally, the digital logic module is further configured to automatically rewrite the first flag bit from the first value to the second value after the automatic crash response has ended.

[0022] Optionally, the chip is a memory chip having a memory array, and during the automatic crash, the chip performs programming-erase operations and / or programming-verify-erase-verify operations on the memory array.

[0023] Based on the same inventive concept, the present invention also provides a chip collapse testing method, which includes the following steps:

[0024] When a chip with I / O pins for reflecting the progress of an automatic crash is powered on, the chip triggers the automatic crash and changes the potential state of the I / O pins in real time according to the progress of the automatic crash.

[0025] The potential status of the IO pins is monitored in real time to obtain the progress status of the automatic crash response of the chip;

[0026] Before power-on, the IO pin is in a high-impedance state; after the automatic collapse is started normally, the potential of the IO pin is pulled to a first level by the chip; after the automatic collapse is completed normally, the potential of the IO pin is pulled to a second level by the chip; when the automatic collapse is not started normally or the automatic collapse is abnormally interrupted, the potential of the IO pin is restored to a high-impedance state by the chip.

[0027] Optionally, the step of the chip changing the potential state of the IO pin in real time according to the progress of the automatic collapse includes:

[0028] After the automatic crash is started normally, the chip connects the IO pin to the power input terminal inside the chip to pull the potential of the IO pin to the first level;

[0029] After the automatic crash is completed, the chip connects the IO pin to the ground terminal inside the chip to pull the potential of the IO pin to the second level;

[0030] When the automatic crash fails to start normally or is abnormally interrupted, the chip disconnects the IO pin from both the power input terminal and the ground terminal to restore the IO pin to the high impedance state.

[0031] Optionally, the chip collapse test method further includes: generating a corresponding reminder signal based on the acquired potential state of the IO pin and providing it to the relevant test equipment so that it can promptly understand the progress status of the automatic collapse of the chip;

[0032] Specifically, when the automatic crash of the chip starts normally, a crash start reminder signal is generated based on the potential change of the IO pin; when the automatic crash of the chip ends normally, a crash end reminder signal is generated based on the potential change of the IO pin; when the automatic crash of the chip fails to start normally or is abnormally interrupted, a crash abnormal reminder signal is generated based on the potential change of the IO pin.

[0033] Based on the same inventive concept, the present invention also provides a chip testing method, which includes:

[0034] Perform wafer-level testing on the wafer containing the chip, and after the wafer-level testing passes, configure the chip, including configurations for automatic collapse.

[0035] The chip is packaged, and after the chip packaging is completed, the chip collapse test method as described in this invention is used to trigger the automatic collapse of the chip. After the automatic collapse of the chip is completed normally, the first flag bit stored inside the chip is rewritten accordingly to indicate that the collapse test of the chip is completed normally.

[0036] Based on the first flag, mass production testing is performed on the chip that has successfully completed the collapse test.

[0037] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0038] 1. After the chip is powered on, it can automatically execute (i.e., automatically trigger) an automatic collapse response, and can monitor the progress of the automatic collapse response in real time through the potential changes of the corresponding I / O pins of the chip. When the chip's automatic collapse is proceeding normally, the I / O pin potential is pulled to the first level (e.g., high level). When the chip's automatic collapse ends normally, the I / O pin potential is pulled to the second level (e.g., low level). When the chip's automatic collapse fails to start normally or is abnormally interrupted, the I / O pin potential is in a high-impedance state. Therefore, during the chip's automatic collapse, the test equipment does not need to send corresponding instructions to the chip to obtain the progress of the chip's automatic collapse response. Moreover, when an abnormal interruption of the automatic collapse occurs (e.g., if the collapse is interrupted due to poor contact or other reasons causing abnormal power loss of the chip), the test equipment or personnel can detect it in time without waiting for a fixed time before forcibly powering down to end the chip's collapse test, thus avoiding wasting time.

[0039] 2. The chip has a first flag bit written inside for automatically triggering the automatic collapse response. This first flag bit is written to the first value after the wafer testing is completed and before the chip is packaged. After power-on, as long as the chip recognizes that the value of the first flag bit is the first value, it can automatically execute the automatic collapse response. Therefore, there is no need to provide an additional test program to send corresponding instructions to the chip to make the chip perform the collapse response action. The execution efficiency is high and the cost is saved.

[0040] 3. The chip can activate the automatic collapse response by recognizing the first value of the first flag. When the automatic collapse response ends, the chip can also automatically rewrite the value of the first flag to the second value, indicating that the automatic collapse response of the chip has ended normally. This ensures that the chip will not trigger the automatic collapse response again after the next power-on. Moreover, the number of bits in the first flag is not less than 2. As a result, the probability of the chip's automatic collapse response being affected by external factors (especially UV state interference) is greatly reduced, effectively preventing false triggering of the chip collapse response test and reducing unnecessary losses.

[0041] 4. The chip collapse test method and chip test method have a simple process, improved test efficiency, and reduced test cost. Attached Figure Description

[0042] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0043] Figure 1 and Figure 2 These are schematic diagrams of two example structures of the chip according to the first embodiment of the present invention.

[0044] Figure 3 This is a schematic diagram of the chip structure according to the second embodiment of the present invention.

[0045] Figure 4 This is a schematic diagram of an example structure of the interface circuit module in the chip of the second embodiment of the present invention.

[0046] Figure 5 This is a schematic diagram of the signal timing of the chip in the second embodiment of the present invention during a stress test.

[0047] Figure 6 This is a schematic flowchart of the chip testing method according to the third embodiment of the present invention. Detailed Implementation

[0048] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0049] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0050] First Embodiment

[0051] Please refer to Figure 1 and Figure 2 This embodiment provides a chip 1, which has an IO pin 12 for reflecting the progress status of an automatic collapse response. The chip 1 automatically triggers an automatic collapse response after power-on and can change the potential state of the IO pin 12 in real time according to the progress status of the automatic collapse response, so as to realize real-time monitoring of the progress status of the automatic collapse response.

[0052] Before power-on, IO pin 12 (which can be considered to be in its initial state) is in a high-impedance state. After the automatic collapse of chip 1 starts normally, the potential of IO pin 12 is pulled to the first level by the internal circuit of chip 1. After the automatic collapse of chip 1 ends normally, the potential of IO pin 12 is pulled to the second level, which is different from the first level, by the internal circuit of chip 1. When chip 1 fails to start its automatic collapse normally or its automatic collapse is abnormally interrupted due to poor contact or other reasons, the potential of the IO pin is restored to the high-impedance state by the internal circuit of chip 1.

[0053] In one example, please refer to Figure 1 The internal circuit of chip 1 has a power input terminal 13 and a ground terminal 14. The power input terminal 13 can be the common power input terminal of part of the internal circuit of chip 1, which can provide the power supply voltage VCC required for normal operation of this part of the internal circuit. The ground terminal 14 can be the system ground of chip 1 or the reference ground of part of the internal circuit of chip 1. This invention does not specifically limit it. After the automatic failure of chip 1 starts normally, the IO pin 12 is connected to the power input terminal 13, and the potential of the IO pin 12 is pulled to a first level (e.g., a high level) by the power input terminal 13. After the automatic failure of chip 1 ends normally, the IO pin 12 is connected to the ground terminal 14, and the potential of the IO pin 12 is pulled to a second level (e.g., a low level) by the ground terminal 14. The second level is lower than the first level.

[0054] In one example, please refer to Figure 1Chip 1 internally includes a trimming memory area (which can be a specific memory area, such as a trim array or mini array) 11. This trimming memory area 11 can be a non-volatile memory space within chip 1, a portion of any internal memory such as Flash, or a register that is not lost when power is off. The memory cells of the trimming memory area can be structurally similar to the memory cells of non-volatile memory within the chip, such as Flash, but functionally different. The memory cells of this trimming memory area can be erased and written normally in test mode, but cannot be rewritten in user mode. In this example, a first flag bit 111 is written in the trimming memory area 11. The value of the first flag bit 111 is pre-written to a first value before chip 1 initiates automatic crash. Therefore, if chip 1 automatically recognizes that the value of the first flag bit 111 is equal to the first value after power-on, it can normally initiate (i.e., automatically trigger) automatic crash. Thus, there is no need to provide an additional test program to send corresponding test instructions to chip 1 to execute the crash action, thereby simplifying the test process, reducing losses, and saving costs. Furthermore, after the automatic collapse of chip 1 has completed normally, the first flag bit 111 is automatically rewritten by chip 1 to a second value different from the first value, serving as a marker that the automatic collapse has ended normally. This ensures that chip 1 will not trigger the automatic collapse again after recognizing that the value of the first flag bit 111 is not equal to the first value upon the next power-on. If an abnormal power outage or poor contact occurs during the automatic collapse of chip 1, causing an abnormal interruption of its automatic collapse, the first flag bit will not be rewritten to the second value, but will remain in the first value state. Thus, after eliminating the abnormal conditions of chip 1, chip 1 can continue to trigger the automatic collapse operation upon the next power-on.

[0055] Preferably, the first flag bit 11 has at least 2 bits, which effectively prevents the automatic collapse test from being falsely triggered. With the first flag bit 11 having at least 2 bits, the probability of the chip's automatic collapse test being affected by external factors (especially UV-state interference) is greatly reduced, effectively preventing false triggering of the chip's collapse test and reducing unnecessary losses.

[0056] In other embodiments of the present invention, at least one bit of the first value of the first flag bit 111 is rewritten (for example, the bit is rewritten from 0 to 1), so that after the automatic crash of the chip 1 ends normally, the value of the first flag bit 111 can be rewritten from the first value to a second value different from the first value.

[0057] Chip 1 can be a chip with any function; for example, please refer to [reference needed]. Figure 2Chip 1 is a memory chip such as Flash, SRAM, DRAM, or ROM, and it has a memory array 10. Its first flag bit 111 and the second flag bit 112 (described below) can both be written into the trimmed memory area (i.e., the first memory area) 11 of the memory array. The remaining memory area serves as the second memory area 15. This trimmed memory area (i.e., the first memory area) 11 is very small compared to the second memory area 15 and can be referred to as a TRIM ARRAY or mini array. The second memory area 15 is used to implement the conventional storage functions of the memory chip. During the automatic crash of chip 1, chip 1 performs at least one operation on the second memory area 15, including read, write, and erase operations. The memory cells of the trimmed memory area 11 may be structurally similar to the memory cells of the second memory area 15, but they differ in function. The memory cells of the trimmed memory area 11 can be normally erased and written in test mode but cannot be rewritten in user mode, while the memory cells of the second memory area 15 can be normally erased and written in user mode.

[0058] In some embodiments, during the automatic collapse of chip 1, chip 1 may first perform several program-erase operations on the second storage area 15 of the storage array, and then perform a program-verify-erase-verify operation, repeating this cycle several times. For products of different quality, the frequency of the erase and programming followed by read verification operations of chip 1 during the automatic collapse process can be selected at different levels. Based on this, optionally, please refer to... Figure 1 The trimming storage area 11 inside chip 1 also contains a second flag bit 112. The value of the second flag bit 112 is used to set the number of programming-erase operations performed on chip 1 during automatic collapse (i.e., in a single collapse cycle). In some embodiments, the second flag bit 112 is further used to set the frequency of the erase and programming followed by the insertion of read verification operations during automatic collapse (i.e., in a single collapse cycle). For products of different quality, the value of the second flag bit 112 can be selected in different levels. By reserving corresponding trim bits in the trimming storage area inside chip 1 as the second flag bit 112, the frequency of the verification operation of chip 1 during automatic collapse can be adjusted. For example, reserving 2 trim bits as the second flag bit 112, the combination of its values ​​00 / 01 / 10 / 11 can configure 4 frequencies (i.e., 4 levels), where the 00 level corresponds to 4 programming-erase followed by 1 programming-verification-erase-verification operation, and so on in a cycle. By reserving 3 tuning bits as the second flag, 8 frequencies (i.e. 8 gear levels) can be combined.

[0059] Alternatively, after completing the wafer-level testing of chip 1 and before packaging chip 1, a test instruction is added to the end of the test program to write the first flag bit 111 and the second flag bit 112 in the adjustment memory area 11 of chip 1. This writes the first flag bit to the first value and the second flag bit to the corresponding value before chip packaging. This avoids the problem of needing to add an extra test program to write the first and second flag bits after chip packaging, and the need for power-down and power-on to trigger automatic crash response. The process is simple and efficient.

[0060] For example, the first flag bit has two bits, bit I and bit II. After the wafer-level test is completed, bit I: bit II = 10 can be written. After the chip 1 automatically crashes and returns to normal, chip 1 automatically rewrites bit I: bit II = 11.

[0061] Please refer to Figure 1 and Figure 2 Based on the chip 1 structure and configuration of this embodiment, this embodiment also provides a chip collapse test method, which includes the following steps:

[0062] First, when chip 1 is powered on, chip 1 will trigger an automatic crash response based on its internal configuration, and change the potential state of its IO pin 12 in real time according to the progress of its automatic crash response.

[0063] Monitor the potential status of I / O pin 12 of chip 1 in real time to obtain the progress status of automatic crash response of chip 1;

[0064] Before powering on chip 1, IO pin 12 is in a high-impedance state. After the automatic collapse of chip 1 starts normally, the potential of IO pin 12 is pulled to a first level (e.g., high level) by chip 1 (e.g., the power input terminal 13 inside chip 1), and this first level remains unchanged during the normal automatic collapse of chip 1. After the normal automatic collapse of chip 1 ends, the potential of IO pin 12 is pulled to a second level (e.g., low level) by chip 1 (e.g., the ground terminal 14 inside chip 1). If the automatic collapse of chip 1 fails to start normally or is abnormally interrupted, the potential of IO pin 12 is restored to a high-impedance state by chip 1.

[0065] In one example, chip 1 can be placed on a corresponding test board (not shown) at room temperature to power on and off chip 1. Furthermore, the test board can test multiple chips 1 simultaneously.

[0066] Optionally, in the chip collapse test method of this embodiment, please combine with Figure 1 and Figure 2 The steps for chip 1 to change the potential state of IO pin 12 in real time according to its collapse progress include:

[0067] After the automatic failure of chip 1 starts normally, chip 1 connects the IO pin 12 to the power input terminal 13 inside chip 1 to pull the potential of IO pin 12 to the first level.

[0068] After the automatic failure of chip 1 is completed, chip 1 connects IO pin 12 to the ground terminal 14 inside chip 1 to pull the potential of IO pin 12 low.

[0069] When the automatic collapse of chip 1 fails to start normally or is abnormally interrupted, chip 1 disconnects IO pin 12 from both power input terminal 13 and ground terminal 14 to restore IO pin 12 to a high impedance state.

[0070] Optionally, the chip collapse test method of this embodiment further includes: after the chip 1 passes the wafer-level test and before the chip 1 is packaged, the first flag bit 111 inside the chip 1 is written to a first value through a corresponding program; and when the chip 1 recognizes that the value of the first flag bit 111 is equal to the first value after power-on, the automatic collapse test is started normally; after the automatic collapse test is completed normally, the chip 1 automatically rewrites the first flag bit 111 to a second value that is different from the first value.

[0071] Optionally, the chip collapse test method of this embodiment further includes: after the chip 1 passes the wafer-level test and before the chip 1 is packaged, writing the second flag bit 112 inside the chip 1 to a corresponding value through a corresponding program, so as to set the number of times the chip 1 is programmed-erase operation is performed in the automatic collapse of the chip 1.

[0072] Optionally, the chip collapse test method of this embodiment further includes: generating a corresponding reminder signal and providing it to the relevant test equipment based on the acquired potential state of the IO pin 12, so that the test equipment or relevant personnel can promptly understand the progress status of the automatic collapse of the chip 1; wherein, when the automatic collapse of the chip 1 starts normally, a collapse start reminder signal is generated based on the potential change of the IO pin 12 (e.g., from a high impedance state to a high level); when the automatic collapse of the chip 1 ends normally, a collapse end reminder signal is generated based on the potential change of the IO pin 12 (e.g., from a high level to a low level); when the automatic collapse of the chip 1 does not start normally or is abnormally interrupted, a collapse abnormal reminder signal is generated based on the potential change of the IO pin 12 (e.g., from a high level to a high impedance state).

[0073] The chip and chip collapse testing method of this embodiment automatically trigger an automatic collapse test after the chip is successfully powered on, eliminating the need for additional test programs. This results in high execution efficiency, cost savings, and real-time monitoring of the chip's automatic collapse progress via I / O pins. This allows for timely identification of abnormal interruptions or failures to start the automatic collapse test, facilitating timely understanding of the chip's status by the testing equipment or personnel. Furthermore, a multi-bit first flag is internally written into the chip, and different values ​​of this first flag are used as indicators of normal start and end of the automatic collapse test. This effectively prevents external interference and avoids false triggering of the automatic collapse test.

[0074] Second embodiment

[0075] Please refer to Figure 3 This embodiment provides a chip 1, which has an I / O pin 12 for reflecting the progress status of an automatic collapse response. The chip 1 triggers an automatic collapse response upon power-up and can change the potential state of the I / O pin 12 in real time according to the progress status of the automatic collapse response, thereby achieving real-time monitoring of the progress status of the automatic collapse response of the chip 1. Before power-up, the I / O pin 12 (which can be considered to be in its initial state) is in a high-impedance state. After the automatic collapse response of the chip 1 starts normally, the potential of the I / O pin 12 is pulled to a first level by the internal circuit of the chip 1. After the automatic collapse response of the chip 1 ends normally, the potential of the I / O pin 12 is pulled to a second level different from the first level by the internal circuit of the chip 1. When the automatic collapse response fails to start normally or is abnormally interrupted due to poor contact or other reasons, the potential of the I / O pin is restored to a high-impedance state by the internal circuit of the chip 1.

[0076] Please refer to Figures 1 to 3 Compared with the first embodiment, the internal circuit of the chip 1 in this embodiment further includes an analog circuit module 16, a digital logic module 17, a timing circuit module 18, and an interface circuit module 19.

[0077] Please combine Figure 3 and Figure 5The analog circuit module 16 generates a power-on status signal PWRON and a collapse status signal EMOSC_EN when chip 1 is powered on. The power-on status signal PWRON is passed to the digital logic module 17, and the collapse status signal EMOSC_EN is passed to the interface circuit module 19. During the power-on process of chip 1, the power-on status signal PWRON is high level "1", and the collapse status signal EMOSC_EN is high level "1". After successful power-on, the power-on status signal PWRON remains low level "0". After the automatic collapse is started normally until it ends normally, the collapse status signal EMOSC_EN remains high level "1". After the automatic collapse ends normally, the collapse status signal EMOSC_EN is low level "0".

[0078] Digital logic module 17 is coupled to analog circuit module 16 and is used to read and identify the value of the first flag bit 111 after receiving the power-on status signal PWRON. When the value of the first flag bit 111 is found to be equal to the first value (e.g., "10"), a collapse enable signal BI_OEN is generated and the automatic collapse of chip 1 is started normally. The collapse enable signal BI_OEN is transmitted to timing circuit module 18 and interface circuit module 19 respectively. During the chip power-on process, the collapse enable signal BI_OEN is low and the automatic collapse is not enabled. After successful power-on, provided that the value of the first flag bit is pre-written to the first value (i.e., the automatic collapse configuration is enabled), digital logic module 17 will identify that the value of the first flag bit 111 is equal to the first value. At this time, chip 1 automatically starts to collapse (e.g., chip 1 is a memory chip and performs corresponding programming-erase operation and / or programming-verification-erase-verification operation through internal state machine). Digital logic module 17 pulls the collapse enable signal BI_OEN high to "1".

[0079] Further optionally, after the automatic crash of chip 1 ends normally, the digital logic module 17 automatically rewrites the value of the first flag bit to the second value (for example, the first flag bit is changed to bit I: bit II = 11, that is, the automatic crash related configuration inside chip 1 is turned off), so that chip 1 will not enter the automatic crash again after power-on.

[0080] The timing circuit module 18 is coupled to the digital logic module 17 and is used to output a clock signal SCLK according to the collapse enable signal BI_OEN. The clock signal SCLK can be a square wave signal with a duty cycle of 50%.

[0081] Interface circuit module 19 is coupled to analog circuit module 16, digital logic module 17, timing circuit module 18, IO pin 12, power input terminal 13 (whose potential is, for example, the system operating voltage VCC), and ground terminal 14 (whose potential is, for example, the system ground VSS). Interface circuit module 19 is used to perform AND logic operation on the collapse state bit signal EMOSC_EN and the collapse enable signal BI_OEN, and according to the clock signal SCLK and the result of the AND logic operation, pulls the potential of IO pin 12 to a high level, a low level, or restores it to a high impedance state. Specifically, after chip 1 is successfully powered on and the automatic collapse is enabled normally, BI_OEN = 1 and EMOSC_EN = 1. The interface circuit module 19 connects IO pin 12 to the power input terminal 13 inside chip 1, making the potential OUTPUT of IO pin 12 high. After the collapse ends normally, BI_OEN = 1 and EMOSC_EN = 0. The interface circuit module 19 connects IO pin 12 to the ground terminal inside chip 1, making the potential OUTPUT of IO pin 12 low. If the automatic collapse of chip 1 is not executed or is abnormally interrupted, BI_OEN and EMOSC_EN will not toggle normally. The interface circuit module 19 disconnects IO pin 12 from both the ground terminal 14 and the power input terminal 13 inside chip 1. The IO pin will not be pulled high or low, and will return to a high impedance state.

[0082] It should be understood that the analog circuit module 16, digital logic module 17, timing circuit module 18 and interface circuit module 19 in this embodiment can be any circuit that can meet the design requirements of chip 1, and the present invention does not make any specific limitation in this regard.

[0083] For example, analog circuit module 16, digital logic module 17, and timing circuit module 18 are all existing functional circuits in existing chips. In this embodiment, chip 1 can be restructured relative to existing chip structures by simply adding an interface circuit module 19, which is coupled to I / O pin 12, power input terminal 13, ground terminal 14, analog circuit module 16, digital logic module 17, and timing circuit module 18. Furthermore, the interface circuit module 19 can be designed as follows: Figure 4 The circuit structure described above allows for lower chip modification costs.

[0084] For example, please refer to Figure 4The interface circuit module 19 includes an AND logic operation circuit and a flip-flop 190. The AND logic operation circuit can be constructed from any suitable electronic component such as an AND gate. One input terminal is coupled to the analog circuit module 16 to receive the collapse state bit signal EMOSC_EN, and the other input terminal is coupled to the digital logic module 17 to receive the collapse enable signal BI_OEN. The output terminal of the AND logic operation circuit is coupled to the input terminal D of the flip-flop 190. The clock terminal ck of the flip-flop 190 is coupled to the timing circuit module 18 to receive the clock signal SCLK. The output terminal Q of the flip-flop 190 is coupled to the IO pin 12 to pull the potential of the IO pin 12 to a high level, a low level, or restore it to a high impedance state.

[0085] The other structures of chip 1 in this embodiment are the same as those in the first embodiment, and will not be described again here.

[0086] Please combine Figures 3 to 5 The operating timing of chip 1 in this embodiment is as follows:

[0087] Before chip 1 is powered on, the initial state of IO pin 12 is high impedance, that is, OUTPUT is in high impedance state;

[0088] When chip 1 is powered on, the analog circuit module 16 generates a power-on status signal PWRON=1 and a collapse status bit signal EMOSC_EN=1. PWRON is transmitted to the digital logic module 17, and EMOSC_EN is transmitted to the AND logic operation circuit of the interface circuit module 19.

[0089] After successful power-on, the power input terminal generates the working voltage VCC of the internal circuit of chip 1. The digital logic module generates the failure enable signal BI_OEN=1, and chip 1 automatically fails and is turned on normally. BI_OEN is then transmitted to the AND logic operation circuits of the timing circuit module 18 and the interface circuit module 19 respectively.

[0090] The timing circuit module 18 generates a clock signal SCLK based on BI_OEN and passes it to the flip-flop 190 of the interface circuit module 19;

[0091] The AND logic operation circuit performs a logical AND operation on the EMOSC_EN and BI_OEN signals to generate the EN signal, which is then passed to the flip-flop 190. The flip-flop 190, in conjunction with the clock signal SCLK, outputs the EN signal as OUTPUT. During the automatic failure and normal start-up process of chip 1, BI_OEN = 1, EMOSC_EN = 1, and OUTPUT = 1.

[0092] Chip 1 should exit normally upon automatic crash. At this time, BI_OEN = 1, EMOSC_EN = 0, and OUTPUT = 0.

[0093] If the automatic crash response of chip 1 is not executed or exits abnormally, BI_OEN and EMOSC_EN will not toggle normally, and OUTPUT will return to the high-impedance state. Therefore, the logic results of BI_OEN, EMOSC_EN, and SCLK can reflect the progress status of the automatic crash response of chip 1.

[0094] Based on the same inventive concept, this embodiment also provides a chip collapse testing method, which includes the following steps:

[0095] When chip 1 is powered on, the digital logic module 17 recognizes that the value of the first flag bit 111 is equal to the first value, and chip 1 performs an automatic collapse response. The interface circuit module 19 inside chip 1 changes the potential state of the IO pin 12 in real time according to the output of the analog circuit module 16, the digital logic module 17 and the timing circuit module 18 (i.e., reflecting the progress of the automatic collapse response of chip 1). When the automatic collapse response ends normally, the digital logic module 17 rewrites the value of the first flag bit 111 to the second value.

[0096] Monitor the potential status of IO pin 12 in real time to obtain the progress status of the automatic crash response of the chip 1;

[0097] Based on the acquired potential state of the IO pin, a corresponding reminder signal is generated and provided to the relevant test equipment or personnel so that they can be informed of the progress of the chip's automatic collapse in a timely manner.

[0098] Before chip 1 is powered on, the IO pin 12 is in a high-impedance state. After the automatic collapse of chip 1 starts normally, the potential of the IO pin 12 is pulled to a first level by the interface circuit module 19. At this time, a collapse start reminder signal is generated based on the potential change of the IO pin 12. When the automatic collapse of chip 1 ends normally, the potential of the IO pin 12 is pulled to a second level by the interface circuit module 19. At this time, a collapse end reminder signal is generated based on the potential change of the IO pin 12. When the automatic collapse of the chip fails to start normally or is abnormally interrupted, the potential of the IO pin 12 is restored to a high-impedance state by the interface circuit module 19. At this time, a collapse abnormal reminder signal is generated based on the potential change of the IO pin 12.

[0099] The chip and its chip collapse test method in this embodiment can utilize the existing structure of the chip's original IO pins 12, power input terminal 13, ground terminal 14, analog circuit module 16, digital logic module 17, and timing circuit module 18, and add an interface circuit module 19 that is coupled to these structures to realize automatic collapse configuration of the chip and real-time monitoring of the collapse progress status. The chip improvement cost and collapse test cost are both low.

[0100] Third embodiment

[0101] Please refer to Figure 6 This embodiment also provides a chip testing method, wherein the chip is the chip described in any embodiment of the present invention, and the chip testing method includes the following steps:

[0102] First, wafer-level testing (including routine tests such as electrical characteristics) is performed on the wafer containing the chip. After the wafer-level testing passes, the corresponding qualified chips on the wafer (which may be one or more chips specified on the wafer) are configured, including for automatic crashing. For example, a test instruction is added at the end of the test program to write the first flag bit of the chip's trimming memory area to write the value of the first flag bit to the first value. For example, bit I and bit II of the first flag bit are written as 10, thereby completing the configuration of the parameter value for automatic crashing.

[0103] Next, chip packaging is performed. Specifically, the wafer can be diced to obtain chip dies. The chip dies are then placed on a substrate separately or together with other functional dies on a substrate. The chip pins are brought out and finally fixed and packaged into a whole, thus completing the packaging of each chip.

[0104] After chip packaging is completed, the chip collapse test method as described in any embodiment of the present invention is used to trigger an automatic collapse upon power-up. After the automatic collapse of the chip ends normally, it automatically rewrites the first flag bit stored inside the chip, including rewriting the value of the first flag bit to a second value. For example, bit I of the first flag bit is rewritten as bit II = 11, which serves as a marker indicating that the collapse test of chip 1 has ended normally. The chip will not trigger an automatic collapse again after recognizing that the value of the first flag bit is equal to the second value the next time it powers on. If an abnormal power outage or poor contact occurs during the automatic collapse of the chip, causing an abnormal interruption of the automatic collapse, the first flag bit will not be rewritten to the second value but will remain in the first value state. After the abnormal condition of the chip is eliminated, the chip can continue to trigger an automatic collapse the next time it powers on.

[0105] Then, based on the first flag, mass production testing is performed on chips that have successfully completed the collapse test.

[0106] The chip testing method of this embodiment configures the chip's automatic collapse response (e.g., writing the first and second flag bits inside the chip) after wafer-level testing and before chip packaging. This enables the automatic collapse response to be triggered after chip packaging and power-on. The process is simple, easy to implement, and has high testing efficiency.

[0107] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A chip, characterized in that, The chip has I / O pins for reflecting the progress status of the automatic collapse response, and the chip is used to trigger the automatic collapse response after power-on, and change the potential state of the I / O pins in real time according to the progress status of the automatic collapse response, so as to realize real-time monitoring of the progress status of the automatic collapse response. Before power-on, the IO pin is in a high-impedance state; after the automatic collapse is started normally, the potential of the IO pin is pulled to a first level by the chip; after the automatic collapse is completed normally, the potential of the IO pin is pulled to a second level different from the first level by the chip; when the automatic collapse is not started normally or the automatic collapse is abnormally interrupted, the potential of the IO pin is restored to the high-impedance state by the chip.

2. The chip as described in claim 1, characterized in that, The chip has a first flag bit written inside. When the chip is powered on, it will start the automatic crash response normally when it recognizes that the value of the first flag bit is equal to the first value. After the automatic crash response ends normally, the first flag bit is rewritten by the chip to a second value, which is different from the first value.

3. The chip as described in claim 2, characterized in that, The first flag bit has a bit length greater than or equal to 2; and / or at least one bit of the first value of the first flag bit is rewritten to achieve the rewriting to the second value.

4. The chip as described in claim 2, characterized in that, After the chip passes the corresponding wafer-level test and before the chip is packaged, the first flag bit is written to the first value, wherein the first flag bit is stored in the chip's trimming memory area.

5. The chip as described in claim 2, characterized in that, The chip also has a second flag bit inside, the value of which is used to set the number of times the chip is programmed-erase operation is performed in the automatic crash.

6. The chip as described in any one of claims 2-5, characterized in that, Also includes: The analog circuit module is used to generate power-on status signals and collapse status bit signals when the chip is powered on. A digital logic module, coupled to the analog circuit module, is used to read and identify the value of the first flag bit after receiving the power-on status signal, and generate a collapse enable signal and start the automatic collapse of the chip normally when the value of the first flag bit is identified as equal to the first value. A timing circuit module, coupled to the digital logic module, is used to output a clock signal according to the collapse enable signal; The interface circuit module is coupled to the analog circuit module, the digital logic module, the timing circuit module and the IO pin, and is used to perform AND logic operation on the collapse state bit signal and the collapse enable signal, and according to the clock signal and the result of the AND logic operation, pull the potential of the IO pin to the first level or the second level or restore it to the high impedance state.

7. The chip as described in claim 6, characterized in that, The interface circuit module includes an AND logic operation circuit and a flip-flop. One input terminal of the AND logic operation circuit is coupled to the analog circuit module to receive the collapse state bit signal. The other input terminal of the AND logic operation circuit is coupled to the digital logic module to receive the collapse enable signal. The output terminal of the AND logic operation circuit is coupled to the input terminal of the flip-flop. The clock terminal of the flip-flop is coupled to the timing circuit module to receive the clock signal. The output terminal of the flip-flop is coupled to the I / O pin.

8. The chip as described in claim 6, characterized in that, The digital logic module is also used to automatically rewrite the first flag bit from the first value to the second value after the automatic crash response ends.

9. The chip as described in any one of claims 1-5 or 7-8, characterized in that, The chip is a memory chip with a memory array. During the automatic crash, the chip performs a program-erase operation and / or a program-verify-erase-verify operation on the memory array.

10. A chip collapse test method, characterized in that, Includes the following steps: When a chip with I / O pins for reflecting the progress of an automatic crash is powered on, the chip triggers the automatic crash and changes the potential state of the I / O pins in real time according to the progress of the automatic crash. The potential status of the IO pins is monitored in real time to obtain the progress status of the automatic crash response of the chip; Before power-on, the IO pin is in a high-impedance state; after the automatic collapse is started normally, the potential of the IO pin is pulled to a first level by the chip; after the automatic collapse is completed normally, the potential of the IO pin is pulled to a second level by the chip; when the automatic collapse is not started normally or the automatic collapse is abnormally interrupted, the potential of the IO pin is restored to a high-impedance state by the chip.

11. The chip collapse test method as described in claim 10, characterized in that, The steps of the chip changing the potential state of the IO pin in real time according to the collapse progress state include: After the automatic crash is started normally, the chip connects the IO pin to the power input terminal inside the chip to pull the potential of the IO pin to the first level; After the automatic crash is completed, the chip connects the IO pin to the ground terminal inside the chip to pull the potential of the IO pin to the second level; When the automatic crash fails to start normally or the automatic crash is abnormally interrupted, the chip disconnects the IO pin from both the power input terminal and the ground terminal to restore the IO pin to the high impedance state.

12. The chip collapse test method as described in claim 10 or 11, characterized in that, Also includes: Based on the acquired potential state of the IO pin, a corresponding reminder signal is generated and provided to the test equipment so that it can promptly understand the progress status of the chip's automatic crash response. Specifically, when the automatic crash of the chip starts normally, a crash start reminder signal is generated based on the potential change of the IO pin; when the automatic crash of the chip ends normally, a crash end reminder signal is generated based on the potential change of the IO pin; when the automatic crash of the chip fails to start normally or is abnormally interrupted, a crash abnormal reminder signal is generated based on the potential change of the IO pin.

13. A chip testing method, characterized in that, include: Perform wafer-level testing on the wafer containing the chip, and after the wafer-level testing passes, configure the chip, including configurations for automatic collapse. The chip is packaged, and after the chip is packaged, the chip collapse test method as described in any one of claims 10-12 is used to trigger an automatic collapse after the chip is powered on, and after the automatic collapse of the chip is completed normally, the first flag bit stored inside the chip is rewritten accordingly to indicate that the collapse test of the chip is completed normally. Based on the first flag, mass production testing is performed on the chip that has successfully completed the collapse test.

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