Evaluation method of vertical cavity surface emitting laser
By employing template sampling testing and data fitting methods in VCSEL chip production, the problem of insufficient industrial temperature testing equipment was solved, enabling efficient and accurate optoelectronic performance testing while reducing time and costs.
Patent Information
- Application Number
- CN202511059622.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-07
- Publication Date
- 2025-10-28
AI Technical Summary
In existing VCSEL chip production, there is a lack of equipment capable of mass production testing at -40℃ and 125℃, which makes it difficult to obtain operating temperature test data and results in high testing time and cost.
The circuit pattern is transferred onto the wafer using a template, and sampling tests are performed to fit the optoelectronic performance data. The optoelectronic performance of all chips is restored by quadratic data fitting and least squares method. Combined with different oxide apertures and process area divisions, the testing efficiency and accuracy are improved.
It saves two-thirds of the testing time, reduces testing costs, solves the bottleneck of not being able to mass-produce test the working temperature data, and ensures the accuracy and representativeness of the test data.
Smart Images
Figure CN120847593A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of lasers, and in particular to an evaluation method for a vertical cavity surface-emitting laser. Background Technology
[0002] Driven by the rapid growth of 5G mobile networks and emerging technology markets such as artificial intelligence (AI), virtual / augmented reality (VR / AR), and the Internet of Things (IoT), data transmission traffic in data centers has surged. The mainstream optical modules for data center applications have evolved from 200 Gbit / s to the next generation of 800 Gbit / s. Currently, for short-distance transmission links of 100 Gbps per channel, the 850 nm wavelength Vertical-Cavity Surface-Emitting Laser (VCSEL) stands out among numerous semiconductor optical communication chips due to its advantages such as high speed, high reliability, easy coupling, low power consumption, and low cost, as well as its compatibility with existing multimode fiber (MMF) cabling systems. It has become the mainstream and preferred optical chip solution for data centers and short-distance optical communications.
[0003] With the ever-increasing market demand, the industry's demand for VCSEL optical chips is growing rapidly, and the production capacity of VCSEL optical chips is also facing new challenges. Due to the different application scenarios of VCSEL chips, some are used in commercial temperature environments (-10℃ ~ +85℃), while others are used in industrial temperature environments (-40℃ ~ +125℃). In order to ensure that the chips delivered to customers can 100% meet their performance requirements, VCSEL laser manufacturers generally conduct photoelectric performance tests on VCSEL chips at three temperatures: -10℃, 25℃, and 85℃. Only through test data at these three temperatures can qualified chips that meet customer performance requirements be screened out.
[0004] Taking a 6-inch VCSEL wafer as an example, one 6-inch VCSEL wafer contains approximately 240,000 VCSEL chips. The testing time for a single VCSEL chip at a single temperature is approximately 3 seconds, and the testing time for a single 6-inch VCSEL wafer is approximately 200 hours (8.3 days). The time for a single 6-inch VCSEL wafer to complete three-temperature testing is approximately 25 days.
[0005] In the manufacturing of VCSEL optical chips, the photoelectric characteristic (LIV) testing is the most time-consuming and costly step. Limited by existing testing equipment, there is currently no equipment in the industry capable of mass production testing at -40℃ and 125℃ (existing testing equipment can only perform full mass production testing from -10℃ to 85℃). This means that obtaining VCSEL chip operating temperature test data is a pressing problem that needs to be solved in the industry. Summary of the Invention
[0006] To improve testing efficiency, this application provides an evaluation method for vertical cavity surface-emitting lasers.
[0007] The evaluation method for a vertical-cavity surface-emitting laser provided in this application adopts the following technical solution: An evaluation method for a vertical-cavity surface-emitting laser includes, S1. The circuit pattern is transferred onto the wafer using a template. Several square detection areas are evenly arranged on the template, and each detection area contains several arrayed chips. S2. Sample the chips in all detection areas. The sampled chips include all chips that are linearly distributed in the middle of the detection area. S3. Perform photoelectric performance testing at 25℃ on all sampled chips and obtain test data T1; S4. Perform photoelectric performance testing on all chips at 25℃ and obtain test data T0; S5. Perform photoelectric performance testing at -10℃ on all sampled chips and obtain test data T2. S6. Perform photoelectric performance testing at 85℃ on all sampled chips and obtain test data T3; S7. Fit the test data T1, T2 and T3 with quadratic terms to obtain the fitting coefficients. Then, use the fitting coefficients and T0 to fit and restore the photoelectric performance data of all chips at different temperatures using the least squares method.
[0008] By adopting the above technical solution, the data obtained through fitting is basically consistent with the measured data. Using T0, T1, T2, and T3 data, the data for all chips can be 100% restored, saving two-thirds of the testing time and improving testing efficiency. The fitting coefficient can also be used to fit difficult-to-test operating temperature data, significantly reducing testing costs while also solving the bottleneck of not being able to mass-produce tests based on operating temperature data.
[0009] Preferably, the lower left corner of the detection area has a test structure for measuring the electrical parameters of the wafer. Above the test structure is a collection area, which is square in shape and consists of several collection chips distributed in an n*n pattern. The oxide holes of the collection chips are all different. In step S2, when performing sampling tests, the sampled chips also include all the collection chips.
[0010] By adopting the above technical solution, chips with different oxidation pore sizes are designed. The main purpose is to use them for the final data fitting calculation. By inputting the data of chips with different oxidation pore sizes into the fitting calculation, the obtained fitting coefficient will be more representative and accurate, and the test data error caused by the fluctuation of wet oxidation process can be reduced.
[0011] Preferably, the bottom row of the acquisition chip is the first layer, and the top row is the nth layer. The oxide pore size of the acquisition chip in odd-numbered layers increases from left to right, and the oxide pore size of the acquisition chip in even-numbered layers increases from right to left. The difference in oxide pore size between adjacent acquisition chips in the same layer is the same, which is D, and the difference between all layers is D. The oxide pore size of the rightmost acquisition chip in an odd-numbered layer is smaller than the oxide pore size of the acquisition chip above it, and the difference is D. The oxide pore size of the leftmost acquisition chip in an even-numbered layer is smaller than the oxide pore size of the acquisition chip above it, and the difference is D.
[0012] As a preferred option, n is 4, there are 16 acquisition chips in the acquisition area, D is 0.5um, and the oxide pore size is the smallest in the acquisition chip in the lower left corner of the acquisition area.
[0013] As a preferred option, all sampled chips represent 2% of the total number of chips.
[0014] Preferably, the chips on the wafer are divided into several process regions according to their distance from the center of the circle. The innermost process region is circular, and the remaining process regions are annular. In step S7, when performing fitting calculation, the chips on the wafer are divided by the process regions and then the fitting calculation is performed.
[0015] Preferably, the wafer is 6 inches in size, and there are four process areas, namely: Process Area 1: The distance between the chip and the center of the wafer in Process Area 1 is greater than 60,000 μm. Process Area 2: The distance between the chip and the center of the wafer in Process Area 2 is 40,000um-60,000um; Process Zone 3: The distance between the chip and the center of the wafer in Process Zone 3 is 20000um-40000um; Process Zone 4: The distance between the chip and the center of the wafer in Process Zone 4 is 0-20000um.
[0016] By adopting the above technical solution, due to process reasons (requiring both revolution and rotation) during the growth and deposition of the epitaxial wafer on the epitaxial equipment, there will be differences in the consistency of parameters such as thickness, composition, doping concentration, and crystal quality of the epitaxial layer in the inner and outer ring regions. Because the differences in the epitaxial layer will naturally result in performance differences in chips from different process regions after the laser fabrication process is completed, by combining the uniformity of the epitaxial process, areas with high consistency in the wafer epitaxial process are divided into a single process region. In this way, the accuracy of the fitting coefficient can be further improved, achieving 100% reproduction of the true performance of the laser.
[0017] In summary, this application includes at least one of the following beneficial technical effects: 1. While ensuring the accuracy of test data, it saves approximately 2 / 3 of the testing time and improves testing efficiency; 2. Solve the bottleneck problem of not being able to test industrial temperature data in mass production. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of the wafer structure after the template pattern is transferred in the embodiment; Figure 2 This is a schematic diagram of the detection area in the embodiment; Figure 3 This is a schematic diagram of the acquisition area in the embodiment; Figure 4 This is a schematic diagram of the structure of the process area in the embodiment; Figure 5-1 This is a voltage fitting coefficient curve diagram of process region one and process region two in the embodiment; Figure 5-2 This is a voltage fitting coefficient curve diagram of process area three and process area four in the embodiment; Figure 6-1 This is a power fitting coefficient curve diagram of process area one and process area two in the embodiment; Figure 6-2 This is a power fitting coefficient curve diagram of process area three and process area four in the embodiment; Figure 7-1 This is a graph showing the impedance fitting coefficients of process region one and process region two in the embodiment. Figure 7-2 This is a graph showing the impedance fitting coefficients of process zones three and four in the embodiment. Figure 8 This is a comparison chart of the measured data and the fitted data of the chip in the embodiment.
[0019] Explanation of reference numerals in the attached figures: 1. Wafer; 2. Detection area; 3. Acquisition area; 4. Process area one; 5. Process area two; 6. Process area three; 7. Process area four; 8. Test structure; 9. Sampling area. Detailed Implementation
[0020] The present application will be further described in detail below with reference to all the accompanying drawings.
[0021] Example
[0022] This application discloses an evaluation method for a vertical-cavity surface-emitting laser (VCSEL), using a 6-inch wafer as an example, including the following steps: S1. The circuit pattern is transferred to the wafer 1 shown in Figure 1 using a template. Several square detection areas 2 are uniformly arranged on the template, and each detection area 2 contains several arrayed chips.
[0023] Reference Figure 2 The lower left corner of the detection area 2 has a test structure 8 for measuring the electrical parameters of wafer 1, and a data acquisition area 3 is located above the test structure 8. The data acquisition area 3 is square and consists of several data acquisition chips arranged in a 4*4 pattern inside, with a total of 16 data acquisition chips in the data acquisition area 3.
[0024] Reference Figure 3 The oxide pore size of the 16 acquisition chips decreases sequentially in an S-shaped distribution. The bottom row of acquisition chips is the first layer, and the top row is the fourth layer. The oxide pore size of the acquisition chips in odd-numbered layers increases from left to right, while the oxide pore size of the acquisition chips in even-numbered layers increases from right to left. The difference in oxide pore size between adjacent acquisition chips within the same layer is 0.5 μm, and the difference between all layers is 0.5 μm.
[0025] Reference Figure 3 In odd-numbered layers, the oxide pore size of the rightmost acquisition chip is smaller than that of the adjacent acquisition chip above it, with a difference of 0.5 μm. In even-numbered layers, the oxide pore size of the leftmost acquisition chip is smaller than that of the adjacent acquisition chip above it, with a difference of 0.5 μm.
[0026] Reference Figure 3 The oxide pore size in the leftmost acquisition chip of the first layer is 3um, and the oxide pore size in the leftmost acquisition chip of the fourth layer is 10.5um.
[0027] S2. Sample the chips in all detection areas 2 for testing. The sampled chips account for 2% of the total number of chips.
[0028] Reference Figure 2 The sampled chips include sampling chips and all acquisition chips. The sampling chips are linearly distributed within the detection area 2 to form the sampling area 9, and the straight line where the sampling chips are distributed is horizontal and located in the middle of the detection area 2.
[0029] S3. Perform photoelectric performance testing at 25°C on all sampled chips to obtain test data T1.
[0030] S4. Perform full photoelectric performance testing of all chips on wafer 1 at room temperature (25°C) according to the test specifications, and obtain test data T0.
[0031] S5. Perform photoelectric performance testing at -10℃ on all sampled chips to obtain test data T2.
[0032] S6. Perform photoelectric performance testing at 85℃ on all sampled chips and obtain test data T3.
[0033] Reference Figure 4The chip on wafer 1 is divided into four process regions (ring regions) according to the distance from the center of the circle. The four process regions are process region 1 4 (ring=1), process region 2 5 (ring=2), process region 3 6 (ring=3) and process region 4 7 (ring=4).
[0034] Process area 1 (4) is ring-shaped, with a distance greater than 60,000 μm between the chip within process area 1 and the center of wafer 1. Process area 2 (5) is ring-shaped, with a distance of 40,000 μm-60,000 μm between the chip within process area 2 and the center of wafer 1. Process area 3 (6) is ring-shaped, with a distance of 20,000 μm-40,000 μm between the chip within process area 3 and the center of wafer 1. Process area 4 (7) is circular, with a distance of 0-20,000 μm between the chip within process area 4 and the center of wafer 1.
[0035] S7. Refer to the test data T1, T2, T3. Figures 5-1 to 7-2 Based on the location of wafer 1 and the process area, the fitting coefficients are obtained by fitting the data using quadratic terms. Then, the fitting coefficients and the full test data of T0 are used to fit and reconstruct the optoelectronic performance data of all chips that were not fully tested at different temperatures using the least squares method.
[0036] Reference Figure 8 By using T0, T1, T2, and T3 data, the temperature data of all chips can be reconstructed, saving 2 / 3 of the testing time. Fitting coefficients can also be used to fit difficult-to-test operating temperature data, significantly reducing testing costs while also solving the bottleneck of operating temperature data being unsuitable for mass production testing; the data obtained through fitting is basically consistent with the measured data.
[0037] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.
Claims
1. A method for evaluating a vertical-cavity surface-emitting laser, characterized in that: include, S1. The circuit pattern is transferred onto the wafer using a template. Several square detection areas are evenly arranged on the template, and each detection area contains several arrayed chips. S2. Sample the chips in all detection areas. The sampled chips include all chips that are linearly distributed in the middle of the detection area. S3. Perform photoelectric performance testing at 25℃ on all sampled chips and obtain test data T1; S4. Perform photoelectric performance testing on all chips at 25℃ and obtain test data T0; S5. Perform photoelectric performance testing at -10℃ on all sampled chips and obtain test data T2. S6. Perform photoelectric performance testing at 85℃ on all sampled chips and obtain test data T3; S7. Fit the test data T1, T2 and T3 with quadratic terms to obtain the fitting coefficients. Then, use the fitting coefficients and T0 to fit and restore the photoelectric performance data of all chips at different temperatures using the least squares method.
2. The evaluation method for a vertical-cavity surface-emitting laser according to claim 1, characterized in that: The lower left corner of the detection area has a test structure for measuring the electrical parameters of the wafer. Above the test structure is a collection area, which is square in shape and consists of several collection chips distributed in an n*n pattern. The oxide holes of the collection chips are all different. In step S2, when performing sampling tests, the sampled chips also include all the collection chips.
3. The evaluation method for a vertical-cavity surface-emitting laser according to claim 2, characterized in that: The bottom row of the acquisition chip is the first layer, and the top row is the nth layer. The oxide pore size of the acquisition chip in odd-numbered layers increases from left to right, and the oxide pore size of the acquisition chip in even-numbered layers increases from right to left. The difference in oxide pore size between adjacent acquisition chips in the same layer is the same, which is D, and the difference between all layers is D. The oxide pore size of the rightmost acquisition chip in an odd-numbered layer is smaller than the oxide pore size of the acquisition chip above it, and the difference is D. The oxide pore size of the leftmost acquisition chip in an even-numbered layer is smaller than the oxide pore size of the acquisition chip above it, and the difference is D.
4. The evaluation method for a vertical-cavity surface-emitting laser according to claim 3, characterized in that: n is 4, there are 16 acquisition chips in the acquisition area, D is 0.5um, and the oxide pore size is the smallest in the acquisition chip in the lower left corner of the acquisition area.
5. The evaluation method for a vertical-cavity surface-emitting laser according to claim 4, characterized in that: All sampled chips represent 2% of the total number of chips.
6. The evaluation method for a vertical-cavity surface-emitting laser according to claim 1, characterized in that: The chips on the wafer are divided into several process regions according to their distance from the center of the circle. The innermost process region is circular, and the remaining process regions are annular. In step S7, when performing fitting calculation, the chips on the wafer are divided by the process regions and then the fitting calculation is performed.
7. The evaluation method for a vertical-cavity surface-emitting laser according to claim 6, characterized in that: The wafer is 6 inches in size, and there are four process areas, namely: Process Area 1: The distance between the chip and the center of the wafer in Process Area 1 is greater than 60,000 μm. Process Area 2: The distance between the chip and the center of the wafer in Process Area 2 is 40,000um-60,000um; Process Zone 3: The distance between the chip and the center of the wafer in Process Zone 3 is 20000um-40000um; Process Zone 4: The distance between the chip and the center of the wafer in Process Zone 4 is 0-20000um.