Pattern offset monitoring structure

Abstract

The invention discloses a pattern offset monitoring structure. The pattern offset monitoring structure comprises a monitoring main body unit, the monitoring main body unit comprises first to third graphs which are arranged in parallel, the first graph is located on the first side of the second graph, and the third graph is located on the second side of the second graph. The second pattern is connected to the first test pad. The first pattern is connected to the second test pad. The third pattern is connected to the third test pad. And a first through hole is formed in the top or the bottom of the second pattern. The first test pad and the second test pad form a test group for testing offset windows of the first pattern and the second pattern; the first test pad and the third test pad form a test group for testing offset windows of the third pattern and the second pattern. The method can be used for monitoring the overlay error and the pattern offset outside the overlay error at the same time.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a pattern offset monitoring structure. Background Art

[0002] Due to the shrinking device size, the gate length and the half-pitch length of the back-end metal lines have decreased dramatically, undoubtedly posing a significant challenge to photolithography. The back-end metal interconnects, designed to connect to front-end devices, have relatively free routing within the layout, resulting in patterns that are more difficult to handle with photolithography. The reliance on optical proximity correction is particularly pronounced, but the reduced size and complex patterns also decrease the accuracy of the optical correction model, increasing correction errors due to the increased difficulty, leading to deviations between the actual photolithography exposure process and the layout. Differences introduced by photolithography can also cause further centerline shifts during etching. Furthermore, due to the difficulty in correcting some patterns, centerline shifts are used to increase the process window. All of these factors contribute to deviations between the actual arrangement of some patterns and the layout. If these deviations are not corrected, the short-circuit and open-circuit windows will shrink, affecting product yield.

[0003] like Figure 1 The diagram shows the layout graphic, the actual graphic, and the corresponding cross-sectional graphic corresponding to the graphic offset caused by the existing actual process. Figure 1 In the diagram, dashed box 101a shows the graphics in the design layout, which includes multiple graphics 103a; dashed box 101b shows the graphics in dashed box 101a after they have been transferred to the wafer, which also includes multiple graphics 103b. A comparison reveals that the multiple graphics 103b in dashed box 101b are offset relative to the bottom graphics 103a. For example, the individually marked graphics 103b1 are offset to the left by d1 relative to graphics 103a1, graphics 103b2 are offset to the right by d2 relative to graphics 103a2, and graphics 103b3 are offset to the right by d3 relative to graphics 103a3.

[0004] The dashed frame 102a corresponds to a cross-sectional view of the graphic in the dashed frame 101a, which also includes through holes 104a located at the bottom of each graphic 103a. It can be seen that there is a spacing d4 between the through holes 104a at the bottom of graphics 103a2 and 103a3.

[0005] The dashed frame 102b corresponds to a cross-sectional view of the graphic in the dashed frame 101b, which also includes through holes 104b located at the bottom of each graphic 103b. It can be seen that there is a spacing d5 between the through holes 104b at the bottom of graphics 103b2 and 103b3.

[0006] Since d5 is less than d4, this makes it easy for short circuits or open circuits, as indicated by mark 105, to occur in the dashed box 102b.

[0007] Existing pattern offset monitoring structures all employ electrical testing methods, primarily for monitoring overlay errors caused by multilayer lithography processes. However, they lack a monitoring method for offsets between the structure itself and the layout caused by non-overlay processes. Current approaches to fill this gap involve first obtaining the centerline spacing of the same layer using methods such as TEM / Prov, then comparing it with the layout to determine the offset, and subsequently correcting the vias. However, these methods require multiple samplings or destructive data acquisition, and are also susceptible to interference from overlay processes, making them unsuitable for widespread monitoring and accurate guidance for mask correction of vias.

[0008] like Figures 2A to 2C It is the layout graphic structure of the three monitoring substructures included in the existing graphic offset monitoring structure; Figure 2A The structure shown is an intrinsic migration monitoring structure. Figure 2B The structure shown is a positive offset monitoring structure. Figure 2C The three structures shown are identical, except for the offset setting of the through hole 203.

[0009] For example Figure 2A For this purpose, the monitoring structure includes a first pattern 201 and two second patterns 202 on both sides. The first pattern 201 is provided with a through hole 203.

[0010] The first pattern 201 is connected to the test pad 205.

[0011] The second pattern 202 is connected to the test pad 204.

[0012] This can be obtained by shifting the through hole 203 to the right. Figure 2B The structure shown can be obtained by shifting the through hole 203 to the left. Figure 2C The structure shown.

[0013] but Figures 2A to 2C The structure shown, when subjected to overlay error, cannot measure the actual pattern offset caused by the process beyond the overlay error. For example... Figure 3 As shown, is Figure 2A The corresponding layout's graphic structure after the actual manufacturing process is completed; it can be seen that... Figure 3 In the middle, the position of through hole 203 is relative to Figure 2A The through hole 203 is offset from its design position, and this offset prevents it from passing through. Figures 2A to 2C The structure shown was obtained through testing. Summary of the Invention

[0014] The technical problem to be solved by the present invention is to provide a pattern offset monitoring structure that can be used to simultaneously monitor overprinting error and pattern offset other than overprinting error.

[0015] To solve the above-mentioned technical problems, the graphic offset monitoring structure provided by the present invention includes a monitoring main unit.

[0016] The monitoring unit includes a first graphic, a second graphic, and a third graphic arranged in parallel, wherein the first graphic is located on the first side of the second graphic, and the third graphic is located on the second side of the second graphic.

[0017] The second pattern is connected to the first test pad.

[0018] The first pattern is connected to the second test pad.

[0019] The third pattern is connected to the third test pad.

[0020] A first through hole is provided at the top or bottom of the second pattern.

[0021] The first test pad and the second test pad form a test group for testing the offset windows of the first and second graphics; the first test pad and the third test pad form a test group for testing the offset windows of the third and second graphics.

[0022] A further improvement is that the monitoring structure includes multiple monitoring substructures.

[0023] Each of the monitoring substructures includes the corresponding monitoring main unit.

[0024] A further improvement is that each of the monitoring substructures comprises multiple monitoring main units, and each monitoring main unit is arranged repeatedly. Each monitoring main unit of the same monitoring substructure shares the same first test pad, the same second test pad, and the same third test pad.

[0025] A further improvement is that the monitoring substructure is divided into an intrinsic offset monitoring structure, a positive offset monitoring structure, and a negative offset monitoring structure.

[0026] The monitoring structure includes one intrinsic offset monitoring structure, multiple positive offset monitoring structures, and multiple negative offset monitoring structures.

[0027] On the layout, the intrinsic offset monitoring structure has an intrinsic initial offset, which indicates that there is no offset between the center line of the first through hole and the center line of the second pattern.

[0028] Each of the positive offset monitoring structures has a positive offset amount, which represents the offset of the center line of the first through hole towards the second side of the center line of the second pattern.

[0029] Each of the negative offset monitoring structures has a negative offset amount, which represents the offset of the center line of the first through hole towards the first side of the center line of the second pattern.

[0030] A further improvement is that the monitoring structure also includes a data processing module, which includes a first positive offset window and a first negative offset window for obtaining the first graph and the second graph.

[0031] The first positive offset window is the minimum positive offset of each of the positive offset monitoring structures when the first test pad and the second test pad are short-circuited.

[0032] The first negative offset window is the minimum negative offset of each of the negative offset monitoring structures when the first test pad and the second test pad are short-circuited.

[0033] A further improvement is that the data processing module includes a second positive offset window and a second negative offset window for obtaining the third graphic and the second graphic.

[0034] The second positive offset window is the minimum positive offset of each of the positive offset monitoring structures when the first test pad and the third test pad are short-circuited.

[0035] The second negative offset window is the minimum negative offset of each of the negative offset monitoring structures corresponding to the short circuit between the first test pad and the third test pad.

[0036] A further improvement is that the data processing module also includes a tool for obtaining the overlay error.

[0037] The overlay error is half the value of the first positive offset window minus the value of the first negative offset window; or, the overlay error is half the value of the second positive offset window minus the value of the second negative offset window.

[0038] A further improvement is that the data processing module also includes a method for obtaining intrinsic offsets.

[0039] The intrinsic offset is the second positive offset window minus the first positive offset window; or, the intrinsic offset is the second negative offset window minus the first negative offset window.

[0040] A further improvement is that, in each of the monitoring substructures, the first patterns of each of the monitoring main units are connected together to form a first pattern chain.

[0041] The second graphic of each of the monitoring main units is connected together to form a second graphic chain.

[0042] The third graphics of each of the monitoring main units are connected together to form a third graphic chain.

[0043] A further improvement is that the first pattern, the second pattern, and the third pattern are all metal lines.

[0044] A further improvement is that the spacing between the first, second, and third graphics of each monitoring main unit adopts the graphic spacing of the weakness pattern in the layout.

[0045] A further improvement is that the intrinsic offset includes pattern offsets generated in the lithography and etching processes due to OPC correction errors.

[0046] A further improvement is that the intrinsic offset is used to correct the first via in the layout so as to compensate for the intrinsic offset.

[0047] A further improvement is that, in each of the monitoring substructures, two adjacent monitoring main units are symmetrically arranged.

[0048] This invention connects the first to third patterns of the monitoring main unit to corresponding test pads, and forms corresponding test groups with the first and second test pads and the first and third test pads, respectively. In this way, the monitoring main unit can obtain two sets of offset windows. By combining the two sets of offset windows, not only the overlay error can be obtained, but also the pattern offset caused by process factors other than the overlay error, that is, the offset between the time pattern and the designed layout pattern. Therefore, this invention can be used to simultaneously monitor overlay error and pattern offsets other than the overlay error. In this way, the layout can be further corrected based on the obtained pattern offsets caused by process factors other than the overlay error, and finally the product yield can be improved.

[0049] Furthermore, compared to existing methods that require obtaining pattern offsets caused by process factors other than overlay errors through means such as TEM, the present invention can achieve this simply by measuring the monitoring structure, which can greatly improve efficiency and ultimately improve the efficiency of modifying the photomask layout. Attached Figure Description

[0050] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0051] Figure 1 It consists of the layout graphic, the actual graphic, and the corresponding cross-sectional graphic corresponding to the graphic offset caused by the existing actual process.

[0052] Figures 2A-2C It is the layout graphic structure of the three monitoring substructures included in the existing graphic offset monitoring structure;

[0053] Figure 3yes Figure 2A The graphic structure of the corresponding layout after the actual process is completed;

[0054] Figures 4A-4C This refers to the layout graphic structure of the three monitoring substructures included in the graphic offset monitoring structure of this embodiment of the invention;

[0055] Figure 5 yes Figure 4A The corresponding layout is the graphic structure after the actual process is completed. Detailed Implementation

[0056] like Figures 4A to 4C The diagram shows the layout graphic structure of the graphic offset monitoring structure of the embodiment of the present invention, which includes three monitoring substructures; the graphic offset monitoring structure of the embodiment of the present invention includes a monitoring main unit 401.

[0057] The monitoring main unit 401 includes: a first graphic 301, a second graphic 302 and a third graphic 303 arranged in parallel, wherein the first graphic 301 is located on the first side of the second graphic 302 and the third graphic 303 is located on the second side of the second graphic 302.

[0058] The second pattern 302 is connected to the first test pad 305.

[0059] The first pattern 301 is connected to the second test pad 306.

[0060] The third pattern 303 is connected to the third test pad 307.

[0061] A first through hole 304 is provided at the top or bottom of the second pattern 302.

[0062] The first test pad 305 and the second test pad 306 form a test group for testing the offset windows of the first pattern 301 and the second pattern 302; the first test pad 305 and the third test pad 307 form a test group for testing the offset windows of the third pattern 303 and the second pattern 302.

[0063] In this embodiment of the invention, the monitoring structure includes multiple monitoring substructures.

[0064] Each of the monitoring substructures includes the corresponding monitoring main unit 401.

[0065] Each monitoring substructure includes multiple monitoring main units 401, and each monitoring main unit 401 is arranged repeatedly. Each monitoring main unit 401 of the same monitoring substructure shares the same first test pad 305, the same second test pad 306, and the same third test pad 307.

[0066] In this embodiment of the invention, in each of the monitoring substructures, two adjacent monitoring main units 401 are symmetrically arranged. Figure 4A The CCP shows three monitoring main units 401, with the two monitoring main units 401 on the left having a symmetrical structure.

[0067] In this embodiment of the invention, the monitoring substructure is divided into an intrinsic offset monitoring structure, a positive offset monitoring structure, and a negative offset monitoring structure. Each monitoring structure includes one intrinsic offset monitoring structure, multiple positive offset monitoring structures, and multiple negative offset monitoring structures.

[0068] Figure 4A Corresponding to the intrinsic offset monitoring structure, Figure 4B Corresponding to one of the positive offset monitoring structures, Figure 4C This corresponds to one of the negative offset monitoring structures.

[0069] On the map, such as Figure 4A As shown, the intrinsic offset monitoring structure has an intrinsic initial offset, which indicates that there is no offset between the center line of the first through hole 304 and the center line of the second pattern 302.

[0070] like Figure 4B As shown, each of the positive offset monitoring structures has a positive offset amount, which represents the offset of the center line of the first through hole 304 to the second side of the center line of the second pattern 302. Figure 4B In the middle, the second side of the center line of the second graphic 302 is the right side.

[0071] like Figure 4C As shown, each of the negative offset monitoring structures has a negative offset, which represents the offset of the center line of the first through hole 304 towards the first side of the center line of the second pattern 302. Figure 4C In the second graphic 302, the first side of the center line is the left side.

[0072] In this embodiment of the invention, the monitoring structure further includes a data processing module, which includes a first positive offset window and a first negative offset window for obtaining the first graphic 301 and the second graphic 302.

[0073] The first positive offset window is the minimum positive offset of each of the positive offset monitoring structures corresponding to a short circuit between the first test pad 305 and the second test pad 306. In actual testing, a series of positive offsets with different values ​​can be obtained. Figure 4BThe positive offset monitoring structure shown is tested. As the positive offset increases, the first through hole 304 and the corresponding top first pattern 301 or second pattern 302 may short-circuit. The positive offset corresponding to the moment the short circuit occurs is the first positive offset window.

[0074] The first negative offset window is the minimum negative offset of each of the negative offset monitoring structures corresponding to the short circuit of the first test pad 305 and the second test pad 306.

[0075] In this embodiment of the invention, the data processing module includes a second positive offset window and a second negative offset window for obtaining the third graphic 303 and the second graphic 302.

[0076] The second positive offset window is the minimum positive offset of each of the positive offset monitoring structures when the first test pad 305 and the third test pad 307 are short-circuited.

[0077] The second negative offset window is the minimum negative offset of each of the negative offset monitoring structures corresponding to the short circuit of the first test pad 305 and the third test pad 307.

[0078] The data processing module also includes a tool for obtaining overlay error.

[0079] The overlay error is half the value of the first positive offset window minus the value of the first negative offset window. Alternatively, the overlay error is half the value of the second positive offset window minus the value of the second negative offset window.

[0080] The overlay error can be expressed by the formula:

[0081] OVL shift=(A+C) / 2=(D+B) / 2 (1).

[0082] Wherein, OVL shift represents the overlay error, A represents the first positive offset window, -C represents the first negative offset window, D represents the second positive offset window, and -B represents the second negative offset window.

[0083] The data processing module also includes a tool for obtaining intrinsic offsets.

[0084] The intrinsic offset is the second positive offset window minus the first positive offset window; the corresponding formula is:

[0085] delta = (DA) (2).

[0086] delta represents the intrinsic offset.

[0087] The intrinsic offset is the second negative offset window minus the first negative offset window. The corresponding formula is:

[0088] delta=(CB) (2).

[0089] like Figure 4A As shown, in each of the monitoring substructures, the first pattern 301 of each of the monitoring main units 401 are connected together to form a chain of first pattern 301.

[0090] The second pattern 302 of each of the monitoring main units 401 are connected together to form a chain of second pattern 302.

[0091] The third pattern 303 of each of the monitoring main units 401 are connected together to form a chain of third pattern 303.

[0092] The first graphic 301, the second graphic 302, and the third graphic 303 are all metal wires.

[0093] In this embodiment of the invention, the spacing between the first graphic 301, the second graphic 302 and the third graphic 303 of each monitoring subject unit 401 adopts the graphic spacing of the weak pattern in the layout.

[0094] In this embodiment of the invention, the intrinsic offset includes pattern offsets caused by OPC correction errors during the photolithography and etching processes. For example... Figure 5 As shown, is Figure 4A The corresponding layout in the actual completed process shows that the first through hole 304 and the second pattern 302 are not actually aligned, but rather offset. This offset is not caused by the layout design, but by the process.

[0095] The intrinsic offset is used to correct the first via 304 in the layout, thereby compensating for the intrinsic offset. Therefore, in this embodiment of the invention, after obtaining the intrinsic offset, the value of the intrinsic offset can be used to correct the layout, that is, the upper and lower via masks are pre-moved by delta in this graphic to maximize the window.

[0096] In this embodiment of the invention, the first to third patterns 303 of the monitoring main unit 401 are respectively connected to the corresponding test pads, and the first and second test pads 306 and the first and third test pads 307 respectively form corresponding test groups. In this way, the monitoring main unit 401 can obtain two sets of offset windows. By combining the two sets of offset windows, not only the overlay error can be obtained, but also the pattern offset caused by process factors other than the overlay error, that is, the offset between the time pattern and the designed layout pattern. Therefore, this embodiment of the invention can be used to simultaneously monitor the overlay error and the pattern offset other than the overlay error. In this way, the layout can be further corrected based on the obtained pattern offset caused by process factors other than the overlay error, and finally the product yield can be improved.

[0097] Furthermore, compared to existing methods that require obtaining pattern offsets caused by process factors other than overlay errors through means such as TEM, the embodiments of the present invention can achieve this by measuring the monitoring structure, which can greatly improve efficiency and ultimately improve the efficiency of modifying the photomask layout.

[0098] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A structure for monitoring graphic offset, characterized in that, Includes the main monitoring unit; The monitoring unit includes: a first graphic, a second graphic, and a third graphic arranged in parallel, wherein the first graphic is located on the first side of the second graphic, and the third graphic is located on the second side of the second graphic; The second pattern is connected to the first test pad; The first pattern is connected to the second test pad; The third pattern is connected to the third test pad; A first through hole is provided at the top or bottom of the second pattern; The first test pad and the second test pad form a test group for testing the offset windows of the first and second graphics; the first test pad and the third test pad form a test group for testing the offset windows of the third and second graphics.

2. The graphic offset monitoring structure as described in claim 1, characterized in that: The monitoring structure includes multiple monitoring substructures; Each of the monitoring substructures includes the corresponding monitoring main unit.

3. The graphic offset monitoring structure as described in claim 2, characterized in that: Each monitoring substructure includes multiple monitoring main units, and each monitoring main unit is arranged repeatedly. Each monitoring main unit of the same monitoring substructure shares the same first test pad, the same second test pad, and the same third test pad.

4. The graphic offset monitoring structure as described in claim 3, characterized in that: The monitoring substructure is divided into intrinsic offset monitoring structure, positive offset monitoring structure and negative offset monitoring structure; The monitoring structure includes one intrinsic offset monitoring structure, multiple positive offset monitoring structures, and multiple negative offset monitoring structures. On the layout, the intrinsic offset monitoring structure has an intrinsic initial offset, which indicates that there is no offset between the center line of the first through hole and the center line of the second pattern; Each of the aforementioned positive offset monitoring structures has a positive offset amount, which represents the offset of the center line of the first through hole towards the second side of the center line of the second pattern; Each of the negative offset monitoring structures has a negative offset amount, which represents the offset of the center line of the first through hole towards the first side of the center line of the second pattern.

5. The graphic offset monitoring structure as described in claim 4, characterized in that, The monitoring structure also includes a data processing module, which includes a first positive offset window and a first negative offset window for obtaining the first graph and the second graph. The first positive offset window is the minimum positive offset of each of the positive offset monitoring structures when the first test pad and the second test pad are short-circuited; The first negative offset window is the minimum negative offset of each of the negative offset monitoring structures when the first test pad and the second test pad are short-circuited.

6. The graphic offset monitoring structure as described in claim 5, characterized in that: The data processing module includes a second positive offset window and a second negative offset window for obtaining the third graphic and the second graphic; The second positive offset window is the minimum positive offset of each of the positive offset monitoring structures when the first test pad and the third test pad are short-circuited; The second negative offset window is the minimum negative offset of each of the negative offset monitoring structures corresponding to the short circuit between the first test pad and the third test pad.

7. The graphic offset monitoring structure as described in claim 6, characterized in that, The data processing module also includes a tool for obtaining overlay error; The overlay error is half the value of the first positive offset window minus the value of the first negative offset window; or, the overlay error is half the value of the second positive offset window minus the value of the second negative offset window.

8. The graphic offset monitoring structure as described in claim 7, characterized in that, The data processing module also includes a tool for obtaining intrinsic offset; The intrinsic offset is the second positive offset window minus the first positive offset window; or, the intrinsic offset is the second negative offset window minus the first negative offset window.

9. The graphic offset monitoring structure as described in claim 3, characterized in that: In each of the monitoring substructures, the first graphic of each of the monitoring main units is connected together to form a first graphic chain; The second graphics of each of the monitoring main units are connected together to form a second graphic chain; The third graphics of each of the monitoring main units are connected together to form a third graphic chain.

10. The graphic offset monitoring structure as described in claim 1, characterized in that: The first, second, and third patterns are all metal wires.

11. The graphic offset monitoring structure as described in claim 10, characterized in that: The spacing between the first, second, and third graphics of each monitoring unit adopts the graphic spacing of the weakness pattern in the layout.

12. The graphic offset monitoring structure as described in claim 8, characterized in that: The intrinsic offset includes pattern offsets generated in the lithography and etching processes due to OPC correction errors.

13. The graphic offset monitoring structure as described in claim 8, characterized in that: The intrinsic offset is used to correct the first via in the layout so as to compensate for the intrinsic offset.

14. The graphic offset monitoring structure as described in claim 3, characterized in that: In each of the monitoring substructures, two adjacent monitoring main units are symmetrical.

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