Quick response LDO (Low Dropout Regulator) with anti-phase small gain stage
By introducing an inverting small gain stage and a push-pull intermediate stage structure into the LDO, a local fast loop and push-pull structure are formed, which solves the overshoot and undershoot problems of traditional LDO when the load changes rapidly, and significantly improves its transient response performance.
Patent Information
- Application Number
- CN202511006263.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-22
- Publication Date
- 2025-10-28
Smart Images
Figure CN120848673A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power management in integrated circuits, and particularly relates to a fast-response LDO with an inverting low-gain stage. Background Technology
[0002] With the rapid advancement of technology, portable electronic devices are becoming increasingly important in our daily lives and work. This trend has not only driven the development of hardware technology but also set higher standards for power management technology. To meet the stable and reliable power requirements of various portable devices, numerous power solutions have emerged in the market, greatly enriching the ecosystem of electronic products. Low dropout regulators (LDOs), as efficient and widely used voltage regulation devices, are particularly popular in miniaturized electronic devices. Their excellent noise suppression capabilities, compact design, and ease of integration make them ideal for many applications. However, traditional LDO designs typically rely on large external capacitors to ensure output voltage stability, especially under rapidly changing load current conditions. This reliance on large external capacitors leads to larger space requirements, increased costs, and slower response times, posing a significant challenge to modern electronic devices that strive for slim and lightweight designs. To address these issues, on-chip integrated LDOs have been developed. By optimizing the circuit structure, on-chip integrated LDOs reduce the need for large external capacitors, achieving a more compact and economical design. Nevertheless, while on-chip integrated LDOs have made progress in improving component count, their poor transient response performance limits their application under high dynamic load conditions. Therefore, developing a low-dropout linear regulator that can both reduce power consumption and improve transient response performance has become a critical problem that urgently needs to be solved in the current technological field. Summary of the Invention
[0003] To address the problems existing in the background art, the present invention provides a fast-response LDO with an inverting low-gain stage, comprising: a bias module, a bandgap reference, a control voltage generator, a flip-flop voltage follower, an inverting low-gain stage, a push-pull intermediate stage, and a power transistor M. P ;
[0004] The bias module is used to provide bias voltage for the control voltage generator, the inverting low-gain stage, and the flip-flop voltage follower;
[0005] The bandgap reference is used to provide a reference voltage V for the flip voltage follower and the control voltage generator. REF ;
[0006] The control voltage generator is used to generate a reference voltage V. REFIt is compared with the internal self-feedback voltage, and the resulting error signal is amplified to provide a control signal for the flip voltage follower;
[0007] The flip-flop voltage follower is used to convert the control signal and the LDO output voltage V. OUT The error signal is compared and amplified. The output of the flip voltage follower is connected to the non-inverting input of the push-pull intermediate stage and the input of the inverting low-gain stage.
[0008] The inverting low-gain stage is used to invert the input signal and amplify it slightly. The output of the inverting low-gain stage is connected to the inverting input of the push-pull intermediate stage.
[0009] The output terminal of the push-pull intermediate stage is connected to the power transistor M. P The gate is used for the power transistor M P Provide adjustment signal to adjust power transistor M P ; output current;
[0010] The power transistor M P The source terminal is connected to the power supply terminal V. IN The power transistor M P The drain of the LDO is connected to its output terminal.
[0011] The present invention has at least the following beneficial effects
[0012] This invention forms a local fast loop and push-pull structure by setting up an inverting low-gain stage and a push-pull intermediate stage, which can effectively suppress overshoot and undershoot at the output when the load changes rapidly, and improve the transient response performance of the on-chip integrated LDO. For example, when the load current changes under certain conditions, it can significantly reduce undershoot and overshoot voltage and shorten the recovery time. Attached Figure Description
[0013] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:
[0014] Figure 1 This is a block diagram of an LDO according to an embodiment of the present invention;
[0015] Figure 2 This is a specific circuit structure diagram shown in an embodiment of the present invention;
[0016] Figure 3 This is a schematic diagram illustrating the transient response regulation mechanism in an embodiment of the present invention;
[0017] Figure 4 This is a transient response curve of the LDO shown in an embodiment of the present invention. Detailed Implementation
[0018] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0019] See also Figures 1-4 This invention provides a fast-response LDO with an inverting low-gain stage, comprising: a bias module, a bandgap reference, a control voltage generator, a flip-flop voltage follower, an inverting low-gain stage, a push-pull intermediate stage, and a power transistor M. P ;
[0020] The bias module is used to provide bias voltage for the control voltage generator, the inverting low-gain stage, and the flip-flop voltage follower;
[0021] The bandgap reference is used to provide a reference voltage V for the flip voltage follower and the control voltage generator. REF ;
[0022] The control voltage generator is used to generate a reference voltage V. REF It is compared with the internal self-feedback voltage, and the resulting error signal is amplified to provide a control signal for the flip voltage follower;
[0023] The flip-flop voltage follower is used to convert the control signal and the LDO output voltage V. OUT The error signal is compared and amplified. The output of the flip voltage follower is connected to the non-inverting input of the push-pull intermediate stage and the input of the inverting low-gain stage.
[0024] The inverting low-gain stage is used to invert the input signal and amplify it slightly. The output of the inverting low-gain stage is connected to the inverting input of the push-pull intermediate stage.
[0025] The output terminal of the push-pull intermediate stage is connected to the power transistor M. P The gate is used for the power transistor M P Provide adjustment signal to adjust power transistor M P ; output current;
[0026] The power transistor MP The source terminal is connected to the power supply terminal V. IN The power transistor M P The drain is connected to the output of the LDO.
[0027] Preferably, the fast-response LDO further includes a frequency compensation module, which is connected in parallel between the output of the flip-flop voltage follower and the output of the LDO to ensure the stability of the entire regulator circuit system.
[0028] Preferably, the frequency compensation module includes a capacitor C. m .
[0029] In this embodiment, by adding a frequency compensation module and connecting it in parallel between the output of the flip-flop voltage follower and the output of the LDO, the stability of the entire voltage regulator circuit system can be ensured, providing a stable circuit foundation for improving transient response performance.
[0030] Preferably, the bias module includes: a current source I bias Transistor M B1 Transistor M B2 and transistor M B3 The current source I bias The input terminal is connected to the power supply terminal V. IN The current source I bias Output terminal, transistor M B1 The drain of the transistor M B1 Gate and transistor M B2 The gate of the transistor is connected to the first bias voltage output terminal of the bias module; the first bias voltage output terminal of the bias module is used to provide bias voltage to the inverting low-gain stage, the flip voltage follower, and the control voltage generator; the transistor M B1 The source and transistor M B2 Source grounded to GND; transistor M B3 The source terminal is connected to the power supply terminal V. IN Transistor M B3 Gate, transistor M B3 The drain and transistor M B2 The drain of the bias module is connected to the second bias voltage output terminal of the bias module; the second bias voltage output terminal of the bias module is used to provide a bias voltage to the flip voltage follower.
[0031] In this embodiment, a bias module with a specific structure is used, namely, current source I. bias Composed of multiple transistors, it can provide a stable bias voltage for the control voltage generator, inverting low-gain stage and flip-flop voltage follower, ensuring the normal operation of each module circuit and laying the foundation for the stable operation and transient response performance improvement of the entire LDO system.
[0032] Preferably, the flip voltage follower includes a transistor M. 11 Transistor M 13 Transistor M 15 and transistor M 16 The transistor M 11 The gate of transistor M serves as the inverting input of the flip-flop voltage follower; 11 The source of transistor M serves as the non-inverting input of a flip-flop voltage follower, which is connected to the output of the LDO; 11 The drain of the transistor M 13 The drain and transistor M 15 Source connection; transistor M 13 The gate of transistor M is connected to the first bias voltage output terminal provided by the bias module, serving as the first bias voltage terminal of the flip voltage follower; 13 Source grounded to GND; transistor M 15 The gate is connected to the reference voltage V REF Transistor M 15 The drain and transistor M 16 The drain is connected to the output of the flip-flop voltage follower; transistor M 16 The source is connected to the power supply voltage V. IN Transistor M 16 The gate of the flip voltage follower is connected to the second bias voltage output provided by the bias module as the second bias voltage terminal.
[0033] In this embodiment, the flip voltage follower consists of transistor M 11 Transistor M 13 Transistor M 15 and transistor M 16 Composition, in which transistor M 11 The gate is used as the inverting input, the source as the non-inverting input and connected to the output of the LDO, and the drain is connected to transistor M. 13 The drain of the transistor M 15 The source of transistor M is connected to the source. 13 The gate of transistor M is connected to the first bias voltage output terminal of the bias module and its source is grounded. 15 The gate is connected to the reference voltage V REF Drain and transistor M 16 The drains of transistors M and M are connected together to the output of the flip-flop voltage follower. 16 The source is connected to the power supply voltage V. IN Furthermore, the gate is connected to the second bias voltage output terminal of the bias module. This flip-flop voltage follower can accurately convert the control signal and the LDO output voltage V OUTThe comparison is performed, and the resulting error signal is amplified. Its output is connected to the non-inverting input of the push-pull intermediate stage and the input of the inverting low-gain stage, providing an accurate and amplified signal for subsequent circuits. This helps the push-pull intermediate stage to more effectively control the power transistor M. P The gate is adjusted to further improve the transient response performance of the LDO in conjunction with the overall circuit structure.
[0034] Preferably, the control voltage generator includes transistors M1, M2, M3, M4, M5, M6, and M7. 12 and transistor M 14 The source of transistor M1, the source of transistor M2, and the drain of transistor M6 are connected; the gate of transistor M1, the drain of transistor M5, and the gate of transistor M6 are connected. 12 The source of transistor M1 is connected; the drain of transistor M1, the gate of transistor M4, the drain of transistor M3, and the gate of transistor M4 are connected; the drain of transistor M2, the gate of transistor M5, and the drain of transistor M4 are connected; the gate of transistor M2 is connected to the reference voltage V. REF The source of transistor M3, the source of transistor M4, the source of transistor M5, and the power supply terminal V. IN Connections; source of transistor M6 and transistor M 14 Source grounded to GND; transistor M 14 The gate of transistor M6 and the gate of transistor M7 serve as the bias voltage terminals of the control voltage generator to receive the bias voltage provided by the bias module; transistor M7... 14 The drain of the transistor M 12 The drain of the transistor M 12 The gate of the circuit is connected to the output of the control voltage generator, and the output of the control voltage generator is connected to the inverting input of the flip voltage follower.
[0035] In this embodiment, the control voltage generator consists of transistors M1, M2, M3, M4, M5, M6, and M7. 12 and transistor M 14 The structure consists of transistors M1 and M2, whose sources are connected to the drain of transistor M6, and transistors M1 and M5, whose gates are connected to the gate of transistor M6 and M7, respectively. 12 The source of transistor M1 is connected to the source, the drain of transistor M1, the gate of transistor M4, and the drain and gate of transistor M3 are connected to the source, the drain of transistor M2 and the gate of transistor M5 are connected to the drain of transistor M4, and the gate of transistor M2 is connected to the reference voltage V. REF The sources of transistors M3, M4, and M5 are connected to the power supply terminal V. IN Transistor M6 and transistor M 14The source is grounded, transistor M 14 The gate of transistor M6 receives the bias voltage of the bias module, and transistor M... 14 The drain of the transistor M 12 The drain and gate of the control voltage generator are connected to the output terminal, which is then connected to the inverting input of a flip-flop voltage follower. The control voltage generator uses a reference voltage V... REF By comparing and amplifying the error signal with the internal self-feedback voltage, a precise control signal can be provided for the flip-flop voltage follower, ensuring that the flip-flop voltage follower can effectively perform signal comparison and amplification, and thus cooperate with subsequent circuits to control the power transistor M. P Adjustments can be made to help improve the transient response performance of the LDO.
[0036] Preferably, the inverting low-gain stage includes transistor M. 31 Transistor M 32 and transistor M 33 The transistor M 31 The source and transistor M 32 The source terminal is connected to the power supply terminal V. IN Transistor M 31 The gate of transistor M is connected to the input of the inverting low-gain stage; 31 The drain of the transistor M 32 The drain of the transistor M 32 Gate, transistor M 33 The drain of transistor M is connected to the output of the inverting low-gain stage; 33 Source grounded to GND; transistor M 33 The gate is connected to the bias voltage terminal of the inverting low-gain stage to receive the bias voltage provided by the bias module.
[0037] In this embodiment, the inverting low-gain stage can invert the input signal and amplify it slightly. Its output is connected to the inverting input of the push-pull intermediate stage, and together with the signal output from the flip-flop voltage follower, it acts on the push-pull intermediate stage, enabling the push-pull intermediate stage to more quickly and effectively control the power transistor M. P The gate is adjusted to help improve the transient response performance of the LDO.
[0038] Preferably, the push-pull intermediate stage includes transistor M. 21 Transistor M 22 Transistor M 23 and transistor M 24 The transistor M 21 The source and transistor M 24 The source terminal is connected to the power supply terminal V. IN Transistor M 21 The gate of transistor M serves as the non-inverting input of the push-pull intermediate stage;21 The drain of the transistor M 22 The drain of the transistor M 22 Gate and transistor M 23 Gate connection; transistor M 22 The source and transistor M 23 Source grounded to GND; transistor M 23 The drain of the transistor M 24 The drain and the output of the push-pull intermediate stage are connected; transistor M 24 The gate is used as the inverting input of the push-pull intermediate stage.
[0039] In this embodiment, the push-pull intermediate stage receives the signal output from the flip voltage follower and the inverted small-amplitude amplified signal output from the inverting small-gain stage, and utilizes the push-pull structure to quickly power transistor M. P Adjust the gate and adjust the power transistor M in a timely manner. P The output current is adjusted to cope with rapid load changes, effectively suppressing overshoot and undershoot at the output terminal, thereby significantly improving the transient response performance of the LDO.
[0040] It should be noted that in this embodiment, based on the appendix Figures 1-4 It can be concluded that an NMOS transistor includes: transistor M B1 Transistor M B2 Transistor M 15 Transistor M 22 Transistor M 33 Transistor M 23 Transistor M 13 Transistors M1, M6, and M2; PMOS transistors include: transistor M... B3 Transistor M 16 Transistor M 21 Transistor M 31 Transistor M 32 Transistor M 24 Transistor M p Transistor M 11 Transistor M5, Transistor M 12 Transistor M 14 Transistor M3 and transistor M4.
[0041] like Figure 3 As shown, Figure 3 A schematic diagram of the transient response regulation mechanism of an LDO is shown. The local fast loop inside the LDO and the push-pull structure at the gate of the power transistor MP enable the LDO to effectively suppress overshoot and undershoot at the output through the red and blue paths, respectively, under rapid load changes, thus improving the transient response performance of the on-chip integrated LDO. Figure 4 As shown, Figure 4 The transient response curve of the LDO is shown. The transient response performance of the LDO is improved by rapidly pushing-pull the gate of the power transistor MP through a local loop and a push-pull intermediate stage; for example... Figure 4 As shown, under the conditions of an edge time of 100 ns and a load capacitance of 100 pF, when the load current jumps from 1 mA to 50 mA, the enhanced undershoot voltage drops from 302 mV to 57 mV, and the recovery time is shortened from 2 μs to within 0.2 μs. When the load current jumps from 50 mA to 1 mA, the enhanced overshoot voltage drops from 283 mV to 41 mV, and the recovery time is also shortened from 2 μs to within 0.3 μs. The overshoot and undershoot voltages are small, and the recovery time is extremely short, effectively improving the transient response speed.
[0042] In summary, this invention, by setting up an inverting low-gain stage and a push-pull intermediate stage, forms a local fast loop and a push-pull structure, which can effectively suppress overshoot and undershoot at the output terminal when the load changes rapidly, and improve the transient response performance of the on-chip integrated LDO. For example, under certain conditions when the load current changes rapidly, it can significantly reduce undershoot and overshoot voltage and shorten the recovery time.
[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A fast-response LDO with an inverting low-gain stage, characterized in that, include: Bias module, bandgap reference, control voltage generator, flip-flop voltage follower, inverting low-gain stage, push-pull intermediate stage, and power transistor M P ; The bias module is used to provide bias voltage for the control voltage generator, the inverting low-gain stage, and the flip-flop voltage follower; The bandgap reference is used to provide a reference voltage V for the flip voltage follower and the control voltage generator. REF ; The control voltage generator is used to generate a reference voltage V. REF It is compared with the internal self-feedback voltage, and the resulting error signal is amplified to provide a control signal for the flip voltage follower; The flip-flop voltage follower is used to convert the control signal and the LDO output voltage V. OUT The error signal is compared and amplified. The output of the flip voltage follower is connected to the non-inverting input of the push-pull intermediate stage and the input of the inverting low-gain stage. The inverting low-gain stage is used to invert the input signal and amplify it slightly. The output of the inverting low-gain stage is connected to the inverting input of the push-pull intermediate stage. The output terminal of the push-pull intermediate stage is connected to the power transistor M. P The gate is used for the power tube M P Provides adjustment signal to adjust the power tube M P ; output current; The power transistor M P The source is connected to the power supply terminal V IN , the power tube M P The drain of the LDO is connected to its output terminal.
2. The fast-response LDO with an inverting low-gain stage according to claim 1, characterized in that, The fast-response LDO also includes a frequency compensation module, which is connected in parallel between the output of the flip-flop voltage follower and the output of the LDO to ensure the stability of the entire regulator circuit system.
3. A fast-response LDO with an inverting low-gain stage according to claim 2, characterized in that, The frequency compensation module includes capacitor C. m .
4. A fast-response LDO with an inverting low-gain stage according to claim 1, characterized in that, The bias module includes: a current source I bias Transistor M B1 Transistor M B2 and transistor M B3 The current source I bias The input terminal is connected to the power supply terminal V. IN The current source I bias Output terminal, transistor M B1 The drain of the transistor M B1 Gate and transistor M B2 The gate of the transistor is connected to the first bias voltage output terminal of the bias module; the first bias voltage output terminal of the bias module is used to provide bias voltage to the inverting low-gain stage, the flip voltage follower, and the control voltage generator; the transistor M B1 The source and transistor M B2 Source grounded to GND; transistor M B3 The source is connected to the power supply terminal V IN Transistor M B3 Gate, transistor M B3 The drain and transistor M B2 The drain of the bias module is connected to the second bias voltage output terminal of the bias module; the second bias voltage output terminal of the bias module is used to provide a bias voltage to the flip voltage follower.
5. A fast-response LDO with an inverting low-gain stage according to claim 4, characterized in that, The flip voltage follower includes transistor M 11 Transistor M 13 Transistor M 15 and transistor M 16 The transistor M 11 The gate of transistor M serves as the inverting input of the flip-flop voltage follower; 11 The source of transistor M serves as the non-inverting input of a flip-flop voltage follower, which is connected to the output of the LDO; 11 The drain of the transistor M 13 The drain and transistor M 15 The source connection; Transistor M 13 The gate of the flip voltage follower is connected to the first bias voltage output terminal provided by the bias module as the first bias voltage terminal. Transistor M 13 The source is grounded to GND; Transistor M 15 The gate is connected to the reference voltage V REF ; Transistor M 15 The drain and transistor M 16 The drain is connected to the output of the flip-flop voltage follower; transistor M 16 The source is connected to the power supply voltage V. IN ; Transistor M 16 The gate of the flip voltage follower is connected to the second bias voltage output provided by the bias module as the second bias voltage terminal.
6. A fast-response LDO with an inverting low-gain stage according to claim 1, characterized in that, The control voltage generator includes transistors M1, M2, M3, M4, M5, M6, and M7. 12 and transistor M 14 The source of transistor M1, the source of transistor M2, and the drain of transistor M6 are connected. The gate of transistor M1, the drain of transistor M5, and transistor M 12 The source connection; The drain of transistor M1, the gate of transistor M4, the drain of transistor M3, and the gate of transistor M3 are connected; the drain of transistor M2, the gate of transistor M5, and the drain of transistor M4 are connected; the gate of transistor M2 is connected to the reference voltage V. REF The source of transistor M3, the source of transistor M4, the source of transistor M5, and the power supply terminal V. IN Connections; source of transistor M6 and transistor M 14 Source grounded to GND; transistor M 14 The gate of the transistor and the gate of transistor M6 serve as the bias voltage terminals of the control voltage generator to receive the bias voltage provided by the bias module. Transistor M 14 The drain of the transistor M 12 The drain of the transistor M 12 The gate of the circuit is connected to the output of the control voltage generator, and the output of the control voltage generator is connected to the inverting input of the flip voltage follower.
7. A fast-response LDO with an inverting low-gain stage according to claim 1, characterized in that, The inverting low-gain stage includes transistor M. 31 Transistor M 32 and transistor M 33 The transistor M 31 The source and transistor M 32 The source is connected to the power supply terminal V IN Transistor M 31 The gate of transistor M is connected to the input of the inverting low-gain stage; 31 The drain of the transistor M 32 The drain of the transistor M 32 Gate, transistor M 33 The drain of transistor M is connected to the output of the inverting low-gain stage; 33 The source is grounded to GND; Transistor M 33 The gate is connected to the bias voltage terminal of the inverting low-gain stage to receive the bias voltage provided by the bias module.
8. A fast-response LDO with an inverting low-gain stage according to claim 1, characterized in that, The push-pull intermediate stage includes transistor M. 21 Transistor M 22 Transistor M 23 and transistor M 24 The transistor M 21 The source and transistor M 24 The source is connected to the power supply terminal V IN Transistor M 21 The gate of transistor M serves as the non-inverting input of the push-pull intermediate stage; 21 The drain of the transistor M 22 The drain of the transistor M 22 Gate and transistor M 23 Gate connection; transistor M 22 The source and transistor M 23 Source grounded to GND; transistor M 23 The drain of the transistor M 24 The drain and the output of the push-pull intermediate stage are connected; transistor M 24 The gate is used as the inverting input of the push-pull intermediate stage.