Dual-core resolving scheduling module for periodic and non-periodic flight control models
By using a dual-core solution scheduling module, the core processing units CPU0 and CPU1 interact with each other through shared memory and timer interrupt service functions. This solves the problem that traditional single-core CPUs cannot meet the collaborative processing requirements of highly integrated flight control models, and achieves efficient dual-core collaborative processing of periodic and non-periodic flight control models.
Patent Information
- Application Number
- CN202510883011.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-28
- Publication Date
- 2025-10-28
AI Technical Summary
Traditional single-core CPUs cannot meet the requirements of solving complex flight control models with high integration and high performance. They cannot achieve collaborative processing and real-time scheduling of multi-task and multi-type flight control models in weapon systems. Furthermore, they suffer from problems such as asynchronous data interaction, uncertain dual-core scheduling latency, and data read/write omissions and conflicts.
A dual-core solution scheduling module using periodic and non-periodic flight control models is adopted. The core processing units CPU0 and CPU1 interact with each other through shared memory. Combined with timers and interrupt service functions, dual-core collaborative processing is achieved to avoid asynchronous data interaction and uncertain scheduling delays.
It solves the problems of asynchronous data interaction and uncertain latency in dual-core scheduling, avoids data read/write omissions and conflicts, and achieves efficient collaborative processing of periodic and non-periodic flight control models.
Smart Images
Figure CN120849039A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of flight control device software design technology, specifically relating to a dual-core solution and scheduling module for periodic and non-periodic flight control models. Background Technology
[0002] Flight control devices are a crucial component of weapon systems. With increasing payloads and functional complexity, traditional single-core CPU processing units can no longer meet the demands of highly integrated, high-performance, and complex flight control model solving. Furthermore, they cannot achieve collaborative processing and real-time scheduling of multiple flight control models across various tasks within the weapon system. For example, a certain type of flight control device needs to simultaneously handle periodic and aperiodic flight control model solving tasks, with stringent requirements for data interaction synchronization and dual-core scheduling latency between the two model solutions. To address this issue, a dual-core solution and scheduling module for periodic and aperiodic flight control models is proposed. This invention fills this gap and is of great significance. Summary of the Invention
[0003] (a) Technical problems to be solved
[0004] The technical problem to be solved by this invention is that a certain type of flight control device needs to complete the collaborative processing and real-time scheduling of periodic and non-periodic flight control models, while avoiding problems such as asynchronous data interaction, uncertain dual-core scheduling delay, data read / write omissions and conflicts.
[0005] (II) Technical Solution
[0006] To solve the above technical problems, the present invention provides a dual-core solution and scheduling module for periodic and non-periodic flight control models. The dual-core solution and scheduling module includes: a core processing unit CPU0, a core processing unit CPU1, and shared memory.
[0007] The core processing unit CPU0 is equipped with a timer 0, which contains an interrupt service function.
[0008] The core processing unit CPU1 is equipped with a timer 1, and the timer 1 is configured with an interrupt service function.
[0009] The core processing unit CPU0 is used to complete periodic model calculations, and the core processing unit CPU1 is used to complete non-periodic model calculations. The cores interact with each other through shared memory.
[0010] The periodic and aperiodic flight control model dual-core solution scheduling module includes the following steps during the periodic and aperiodic flight control model dual-core solution scheduling process:
[0011] Step 1: The main program of the core processing unit CPU0 performs periodic calculations. At the same time, after each periodic calculation, it determines whether to perform non-periodic calculations. If non-periodic calculations are required, the shared memory is accessed through the interrupt service function of Timer 0, thereby writing the periodic model calculation results and non-periodic calculation start flag to the core processing unit CPU1.
[0012] Step 2: The interrupt service function of Timer 1 of the core processing unit CPU1 reads the periodic model solution results and aperiodic solution start flag sent by the core processing unit CPU0 in a time-sharing manner. Then, the aperiodic model solution is performed in the main program of the core processing unit CPU. After the solution is completed, the shared memory is accessed through the interrupt service function of Timer 1, and then the aperiodic model solution results and completion flag are written to the core processing unit CPU0.
[0013] Step 3: The core processing unit CPU0 reads the aperiodic model solution results and completion flags sent by the core processing unit CPU1 from the shared memory through the interrupt service function of timer 0 in a time-sharing manner. In the main program of the core processing unit CPU0, the input parameters of the aperiodic solution results are processed, the periodic model solution is performed, and then it is determined again whether to perform aperiodic solution... This cycle is repeated to complete the dual-core solution scheduling of periodic and aperiodic flight control models.
[0014] The write address of the core processing unit CPU0 is allocated in the shared memory in the range of 0 to 5000, and the write address of the core processing unit CPU1 is allocated in the shared memory in the range of 10001 to 15000.
[0015] The core processing unit CPU0 has a periodic model solution cycle of 5ms and a timer 0 cycle of 0.5ms. The 5ms cycle is generated by the timer 0 loop counter flag_timer0.
[0016] The core processing unit CPU1 has a timer 1 period of 0.5ms, and a 5ms period is generated by the timer 1 loop count flag_timer1.
[0017] The timer 0's loop counter flag, flag_timer0, cycles from 0 to 9 in 0.5ms intervals, and is used to control the CPU0 main program of the core processing unit to perform periodic calculations, time-sharing readings, and writing to shared memory.
[0018] The timer 1's loop counter flag_timer1 cycles from 0 to 9 in 0.5ms intervals, and is used to control the CPU0 main program of the core processing unit to perform non-periodic calculations, time-sharing reading and writing to shared memory.
[0019] When flag_timer0 equals 0, the interrupt service function of timer 0 sends the periodic model solution result and the non-periodic solution start flag to the core processing unit CPU1 through shared memory.
[0020] When flag_timer1 equals 5, the interrupt service function of Timer 1 reads the periodic model solution results and non-periodic solution start flag sent by the core processing unit CPU0 in shared memory.
[0021] When flag_timer1 equals 6, the interrupt service function of Timer 1 sends the non-periodic model solution result and completion flag to the core processing unit CPU0 through shared memory.
[0022] When flag_timer0 equals 9, the interrupt service function of Timer 0 reads the non-periodic model solution result and completion flag sent by the core processing unit CPU1 in shared memory.
[0023] The processing platform of the dual-core solution scheduling module is implemented using a ZYNQ main control chip.
[0024] (III) Beneficial Effects
[0025] Compared with existing technologies, the dual-core solution and scheduling module for periodic and aperiodic flight control models of this invention has the greatest advantage of solving problems such as asynchronous data interaction and uncertain dual-core scheduling delay when periodic and aperiodic flight control models are solved simultaneously. Furthermore, it utilizes timers to achieve time-sharing data processing in shared memory between the two cores, avoiding data read / write omissions and conflicts. This module has already been successfully applied to flight control devices for various weapons. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of the dual-core solution scheduling module for periodic and non-periodic flight control models.
[0027] Figure 2 A schematic diagram of the design process for the dual-core solution scheduling module of periodic and non-periodic flight control models. Detailed Implementation
[0028] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0029] To solve the above technical problems, the present invention provides a dual-core solution and scheduling module for periodic and non-periodic flight control models. The dual-core solution and scheduling module includes: a core processing unit CPU0, a core processing unit CPU1, and shared memory.
[0030] The core processing unit CPU0 is equipped with a timer 0, which contains an interrupt service function.
[0031] The core processing unit CPU1 is equipped with a timer 1, and the timer 1 is configured with an interrupt service function.
[0032] The core processing unit CPU0 is used to complete periodic model calculations, and the core processing unit CPU1 is used to complete non-periodic model calculations. The cores interact with each other through shared memory.
[0033] The periodic and aperiodic flight control model dual-core solution scheduling module includes the following steps during the periodic and aperiodic flight control model dual-core solution scheduling process:
[0034] Step 1: The main program of the core processing unit CPU0 performs periodic calculations. At the same time, after each periodic calculation, it determines whether to perform non-periodic calculations. If non-periodic calculations are required, the shared memory is accessed through the interrupt service function of Timer 0, thereby writing the periodic model calculation results and non-periodic calculation start flag to the core processing unit CPU1.
[0035] Step 2: The interrupt service function of Timer 1 of the core processing unit CPU1 reads the periodic model solution results and aperiodic solution start flag sent by the core processing unit CPU0 in a time-sharing manner. Then, the aperiodic model solution is performed in the main program of the core processing unit CPU. After the solution is completed, the shared memory is accessed through the interrupt service function of Timer 1, and then the aperiodic model solution results and completion flag are written to the core processing unit CPU0.
[0036] Step 3: The core processing unit CPU0 reads the aperiodic model solution results and completion flags sent by the core processing unit CPU1 from the shared memory through the interrupt service function of timer 0 in a time-sharing manner. In the main program of the core processing unit CPU0, the input parameters of the aperiodic solution results are processed, the periodic model solution is performed, and then it is determined again whether to perform aperiodic solution... This cycle is repeated to complete the dual-core solution scheduling of periodic and aperiodic flight control models.
[0037] The write address of the core processing unit CPU0 is allocated in the shared memory in the range of 0 to 5000, and the write address of the core processing unit CPU1 is allocated in the shared memory in the range of 10001 to 15000.
[0038] The core processing unit CPU0 has a periodic model solution cycle of 5ms and a timer 0 cycle of 0.5ms. The 5ms cycle is generated by the timer 0 loop counter flag_timer0.
[0039] The core processing unit CPU1 has a timer 1 period of 0.5ms, and a 5ms period is generated by the timer 1 loop count flag_timer1.
[0040] The timer 0's loop counter flag, flag_timer0, cycles from 0 to 9 in 0.5ms intervals, and is used to control the CPU0 main program of the core processing unit to perform periodic calculations, time-sharing readings, and writing to shared memory.
[0041] The timer 1's loop counter flag_timer1 cycles from 0 to 9 in 0.5ms intervals, and is used to control the CPU0 main program of the core processing unit to perform non-periodic calculations, time-sharing reading and writing to shared memory.
[0042] When flag_timer0 equals 0, the interrupt service function of timer 0 sends the periodic model solution result and the non-periodic solution start flag to the core processing unit CPU1 through shared memory.
[0043] When flag_timer1 equals 5, the interrupt service function of Timer 1 reads the periodic model solution results and non-periodic solution start flag sent by the core processing unit CPU0 in shared memory.
[0044] When flag_timer1 equals 6, the interrupt service function of Timer 1 sends the non-periodic model solution result and completion flag to the core processing unit CPU0 through shared memory.
[0045] When flag_timer0 equals 9, the interrupt service function of Timer 0 reads the non-periodic model solution result and completion flag sent by the core processing unit CPU1 in shared memory.
[0046] The processing platform of the dual-core solution scheduling module is implemented using a ZYNQ main control chip.
[0047] Furthermore, the present invention also provides a dual-core solution scheduling method for periodic and aperiodic flight control models. The dual-core solution scheduling method for periodic and aperiodic flight control models is implemented based on a dual-core solution scheduling module, which includes: a core processing unit CPU0, a core processing unit CPU1, and shared memory.
[0048] The core processing unit CPU0 is equipped with a timer 0, which contains an interrupt service function.
[0049] The core processing unit CPU1 is equipped with a timer 1, and the timer 1 is configured with an interrupt service function.
[0050] The core processing unit CPU0 is used to complete periodic model calculations, and the core processing unit CPU1 is used to complete non-periodic model calculations. The cores interact with each other through shared memory.
[0051] The dual-core solution scheduling method for the periodic and aperiodic flight control model includes the following steps:
[0052] Step 1: The main program of the core processing unit CPU0 performs periodic calculations. At the same time, after each periodic calculation, it determines whether to perform non-periodic calculations. If non-periodic calculations are required, the shared memory is accessed through the interrupt service function of Timer 0, thereby writing the periodic model calculation results and non-periodic calculation start flag to the core processing unit CPU1.
[0053] Step 2: The interrupt service function of Timer 1 of the core processing unit CPU1 reads the periodic model solution results and aperiodic solution start flag sent by the core processing unit CPU0 in a time-sharing manner. Then, the aperiodic model solution is performed in the main program of the core processing unit CPU. After the solution is completed, the shared memory is accessed through the interrupt service function of Timer 1, and then the aperiodic model solution results and completion flag are written to the core processing unit CPU0.
[0054] Step 3: The core processing unit CPU0 reads the aperiodic model solution results and completion flags sent by the core processing unit CPU1 from the shared memory through the interrupt service function of timer 0 in a time-sharing manner. In the main program of the core processing unit CPU0, the input parameters of the aperiodic solution results are processed, the periodic model solution is performed, and then it is determined again whether to perform aperiodic solution... This cycle is repeated to complete the dual-core solution scheduling of periodic and aperiodic flight control models.
[0055] The write address of the core processing unit CPU0 is allocated in the shared memory in the range of 0 to 5000, and the write address of the core processing unit CPU1 is allocated in the shared memory in the range of 10001 to 15000.
[0056] The core processing unit CPU0 has a periodic model solution cycle of 5ms and a timer 0 cycle of 0.5ms. The 5ms cycle is generated by the timer 0 loop counter flag_timer0.
[0057] The core processing unit CPU1 has a timer 1 period of 0.5ms, and a 5ms period is generated by the timer 1 loop count flag_timer1.
[0058] The timer 0's loop counter flag, flag_timer0, cycles from 0 to 9 in 0.5ms intervals, and is used to control the CPU0 main program of the core processing unit to perform periodic calculations, time-sharing readings, and writing to shared memory.
[0059] The timer 1's loop counter flag_timer1 cycles from 0 to 9 in 0.5ms intervals, and is used to control the CPU0 main program of the core processing unit to perform non-periodic calculations, time-sharing reading and writing to shared memory.
[0060] When flag_timer0 equals 0, the interrupt service function of timer 0 sends the periodic model solution result and the non-periodic solution start flag to the core processing unit CPU1 through shared memory.
[0061] When flag_timer1 equals 5, the interrupt service function of Timer 1 reads the periodic model solution results and non-periodic solution start flag sent by the core processing unit CPU0 in shared memory.
[0062] When flag_timer1 equals 6, the interrupt service function of Timer 1 sends the non-periodic model solution result and completion flag to the core processing unit CPU0 through shared memory.
[0063] When flag_timer0 equals 9, the interrupt service function of Timer 0 reads the non-periodic model solution result and completion flag sent by the core processing unit CPU1 in shared memory.
[0064] The processing platform of the dual-core solution scheduling module is implemented using a ZYNQ main control chip.
[0065] Example 1
[0066] In this embodiment, firstly, the core processing unit CPU0 sets a 0.5ms timer 0. The timer 0 generates a 5ms cycle by cyclically counting the flag value (flag_timer0 counts from 0 to 9 in a 0.5ms cycle) to control the main program of the core processing unit CPU0 to perform periodic calculations. At the same time, after each periodic calculation, it is determined whether to perform non-periodic calculations. If the non-periodic calculation conditions are met, the interrupt service function of timer 0 sends the periodic model calculation results and the non-periodic calculation start flag to the core processing unit CPU1 through shared memory when flag_timer0 equals 0.
[0067] Secondly, the core processing unit CPU1 sets up a 0.5ms timer 1. The timer 1 generates a 5ms cycle by cyclically counting the flag value (flag_timer1 counts from 0 to 9 in 0.5ms intervals). This cycle is used to control the core processing unit CPU0 to read and write to shared memory in a time-sharing manner. When flag_timer1 equals 5, the interrupt service function of timer 1 reads the periodic model solution results and aperiodic solution start flag sent by the core processing unit CPU0 from the shared memory. At the same time, the main program of the core processing unit CPU1 performs aperiodic model solution. After the solution is completed, the interrupt service function of timer 1 sends the aperiodic model solution results and completion flag to the core processing unit CPU0 through shared memory when flag_timer1 equals 6.
[0068] Finally, the core processing unit CPU0 reads the aperiodic model solution results and completion flag sent by the core processing unit CPU1 from the shared memory when flag_timer0 equals 9 through the interrupt service function of timer 0. In the main program of the core processing unit CPU0, the input parameters of the aperiodic solution results are processed, the periodic model solution is performed, and then it is determined again whether to perform the aperiodic solution... This cycle is repeated to complete the dual-core solution scheduling of periodic and aperiodic flight control models.
[0069] Example 2
[0070] like Figure 2 As shown, this invention proposes a dual-core solution scheduling module for periodic and non-periodic flight control models, implemented on the ZYNQ platform. The module's workflow includes the following steps:
[0071] 1) The core processing unit CPU0 sets a 0.5ms timer 0, which generates a 5ms cycle by cyclically counting the flag value of timer 0 (flag_timer0 counts from 0 to 9 in a 0.5ms period) to control the main program to perform periodic calculations;
[0072] 2) The core processing unit CPU1 sets up a 0.5ms timer 1, which generates a 5ms cycle by cyclically counting the flag value of timer 1 (flag_timer1 counts from 0 to 9 in a 0.5ms cycle) to control the core processing unit CPU0 to read and write shared memory in a time-sharing manner.
[0073] 3) After the periodic calculation of the core processing unit CPU0 is completed, it is determined whether to perform non-periodic calculation. If the non-periodic calculation condition is met, the periodic model calculation result and the non-periodic calculation start flag are sent to the core processing unit CPU1 through shared memory when flag_timer0 equals 0 via the interrupt service function of Timer 0.
[0074] 4) When the interrupt service function of Timer 1 reads the periodic model solution results and non-periodic solution start flag sent by the core processing unit CPU0 in the shared memory when flag_timer1 equals 5;
[0075] 5) After receiving the non-periodic solution start flag, the main program of the core processing unit CPU1 performs non-periodic model solution in the main program. After the solution is completed, the non-periodic model solution result and completion flag are sent to the core processing unit CPU0 through shared memory via the interrupt service function of Timer 1 when flag_timer1 equals 6.
[0076] 6) The core processing unit CPU0 reads the non-periodic model solution result and completion flag sent by the core processing unit CPU1 in the shared memory when flag_timer0 equals 9 through the interrupt service function of timer 0. It then completes the input parameter processing of the non-periodic solution result in the main program and performs periodic model solution.
[0077] 7) Repeat steps 3) to 6) until n data interactions are completed. This cycle is used to complete the dual-core solution scheduling of the periodic and non-periodic flight control model.
[0078] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A dual-core solution and scheduling module for periodic and non-periodic flight control models, characterized in that, The dual-core computation and scheduling module includes: a core processing unit CPU0, a core processing unit CPU1, and shared memory; The core processing unit CPU0 is equipped with a timer 0, which contains an interrupt service function. The core processing unit CPU1 is equipped with a timer 1, and the timer 1 is configured with an interrupt service function. The core processing unit CPU0 is used to complete periodic model calculations, and the core processing unit CPU1 is used to complete non-periodic model calculations. The cores interact with each other through shared memory.
2. The dual-core solution and scheduling module for the periodic and non-periodic flight control model as described in claim 1, characterized in that, The dual-core solution and scheduling module for the periodic and aperiodic flight control model includes the following steps during the dual-core solution and scheduling process: Step 1: The main program of the core processing unit CPU0 performs periodic calculations. At the same time, after each periodic calculation, it determines whether to perform non-periodic calculations. If non-periodic calculations are required, the shared memory is accessed through the interrupt service function of Timer 0, thereby writing the periodic model calculation results and non-periodic calculation start flag to the core processing unit CPU1. Step 2: The interrupt service function of Timer 1 of the core processing unit CPU1 reads the periodic model solution results and aperiodic solution start flag sent by the core processing unit CPU0 in a time-sharing manner. Then, the aperiodic model solution is performed in the main program of the core processing unit CPU. After the solution is completed, the shared memory is accessed through the interrupt service function of Timer 1, and then the aperiodic model solution results and completion flag are written to the core processing unit CPU0. Step 3: The core processing unit CPU0 reads the aperiodic model solution results and completion flags sent by the core processing unit CPU1 from the shared memory through the interrupt service function of timer 0 in a time-sharing manner. In the main program of the core processing unit CPU0, the input parameters of the aperiodic solution results are processed, the periodic model solution is performed, and then it is determined again whether to perform aperiodic solution... This cycle is repeated to complete the dual-core solution scheduling of periodic and aperiodic flight control models.
3. The dual-core solution and scheduling module for the periodic and non-periodic flight control model as described in claim 1, characterized in that, The write address allocation range of the core processing unit CPU0 in the shared memory is 0 to 5000, and the write address allocation range of the core processing unit CPU1 in the shared memory is 10001 to 15000.
4. The dual-core solution and scheduling module for the periodic and non-periodic flight control model as described in claim 1, characterized in that, The core processing unit CPU0 has a periodic model solution period of 5ms and a timer 0 period of 0.5ms. The 5ms period is generated by the timer 0 loop counter flag_timer0. The core processing unit CPU1 has a timer 1 period of 0.5ms, and a 5ms period is generated by the timer 1 loop count flag_timer1.
5. The dual-core solution and scheduling module for the periodic and non-periodic flight control model as described in claim 4, characterized in that, The timer 0's loop counter flag, flag_timer0, counts from 0 to 9 in a 0.5ms cycle, and is used to control the CPU0 main program of the core processing unit to perform periodic calculations, time-sharing readings, and writing to shared memory.
6. The dual-core solution and scheduling module for periodic and non-periodic flight control models as described in claim 5, characterized in that, The timer 1's loop counter flag, flag_timer1, counts from 0 to 9 in a 0.5ms cycle, and is used to control the CPU0 main program of the core processing unit to perform non-periodic calculations, time-sharing reading, and writing to shared memory.
7. The dual-core solution and scheduling module for the periodic and non-periodic flight control model as described in claim 6, characterized in that, When flag_timer0 equals 0, the interrupt service function of Timer 0 sends the periodic model solution result and the non-periodic solution start flag to the core processing unit CPU1 through shared memory. When flag_timer1 equals 5, the interrupt service function of Timer 1 reads the periodic model solution results and non-periodic solution start flag sent by the core processing unit CPU0 in shared memory. When flag_timer1 equals 6, the interrupt service function of Timer 1 sends the non-periodic model solution result and completion flag to the core processing unit CPU0 through shared memory. When flag_timer0 equals 9, the interrupt service function of Timer 0 reads the non-periodic model solution result and completion flag sent by the core processing unit CPU1 in shared memory.
8. The dual-core solution and scheduling module for the periodic and non-periodic flight control model as described in claim 7, characterized in that, The processing platform of the dual-core solution scheduling module is implemented using a ZYNQ main control chip.
9. The dual-core solution and scheduling module for periodic and non-periodic flight control models as described in claim 7, characterized in that, The module addresses the issues of asynchronous data interaction and uncertain dual-core scheduling delays when periodic and non-periodic flight control models are solved simultaneously.
10. The dual-core solution and scheduling module for the periodic and non-periodic flight control model as described in claim 7, characterized in that, The module utilizes a timer to achieve time-sharing data processing in the dual-core shared memory, thus avoiding data read / write omissions and conflicts.