A chip, a data transmission method, and an electronic device

Abstract

This application provides a chip, a data transmission method, and an electronic device. The chip includes multiple chips, each chip comprising multiple functional nodes. The multiple chips are interconnected via a mesh structure, and the multiple functional nodes within each chip are interconnected via a bidirectional ring structure. A first data packet sent from a first chip to a second chip is transmitted in a first direction within the ring structure of the first chip, and then transmitted to the second chip via the mesh structure according to a dimensional order routing strategy. The first data packet is also transmitted in a second direction within the ring structure of the second chip, the second direction being the opposite of the first direction. This application avoids deadlock and has low implementation complexity and low operational overhead.

Description

Technical Field

[0001] This application relates to chip integration technology, and more particularly to a chip, a data transmission method, and an electronic device. Background Technology

[0002] Currently, integrated circuits are developing towards multi-die integration, which involves interconnecting and assembling multiple functionally distinct, verified, and unpackaged chip components, and then packaging them into a single chip within a single package, forming a multi-chip module. To fully leverage the role of each functional unit within this multi-chip module, it is crucial to construct a high-performance, integrated on-chip and inter-chip network to achieve efficient communication between multiple functional units and chips. In building large-scale homogeneous systems, Network-on-Chip (NoC) has replaced traditional bus-based architectures as an indispensable system component.

[0003] In on-chip networking (NoC) systems, deadlock is a critical issue, especially in multi-core systems, where packet transmission paths can form circular dependencies, preventing any packets from advancing. As network size and complexity increase, the frequency of deadlock increases. Deadlock-free operation is the most important problem in NoC design because it is a prerequisite for achieving efficient and reliable on-chip communication, determining the viability of NoC and even SoC. Existing deadlock resolution algorithms cannot handle multi-level network scenarios or may increase network burden, impacting latency and bandwidth, resulting in low direct benefits. Summary of the Invention

[0004] This application provides a chip, a data transmission method, and an electronic device that can avoid deadlock through a simple routing algorithm and a deadlock avoidance strategy.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] This application provides a chip comprising: a plurality of chips, each chip including a plurality of functional nodes, wherein:

[0007] The multiple core particles are interconnected by a grid structure, and the multiple functional nodes in each core particle are interconnected by a bidirectional ring structure.

[0008] The first data packet sent from the first core to the second core is transmitted in a first direction in the ring structure within the first core, and then transmitted to the second core through the mesh structure according to the dimensional order routing strategy. The first data packet is transmitted in a second direction in the ring structure within the second core, and the second direction is the opposite direction of the first direction.

[0009] This application provides a data transmission method, including:

[0010] Get the data packet to be sent;

[0011] When the data packet to be sent is a first data packet sent from the first chip to the second chip in the chip, the first data packet is transmitted in the first direction in the ring structure within the first chip.

[0012] The first data packet is transmitted to the second core particle through the mesh structure according to the dimensional order routing strategy.

[0013] The first data packet is transmitted in a second direction along the ring structure within the second core until it reaches the target functional node. The second direction is the opposite of the first direction.

[0014] In some embodiments, the method further includes:

[0015] When the data packet to be sent is a second data packet sent from a first functional node in the first core to a second functional node in the first core, the target direction is determined;

[0016] The second data packet is transmitted in a ring structure within the first core in a target direction until it reaches the second functional node, where the target direction is either a first direction or a second direction.

[0017] The embodiments of this application have the following beneficial effects:

[0018] The chip provided in this application embodiment includes multiple dies, each die containing multiple functional nodes. The dies are interconnected using a mesh structure, and the functional nodes within each die are interconnected using a bidirectional ring structure. The mesh topology allows parallel communication between multiple dies, avoiding bottlenecks caused by a single bus, thereby effectively improving data transmission efficiency and bandwidth. Furthermore, the mesh structure offers better scalability. For an independent die, its internal structure is relatively regular, and the number of cores may not be extremely large (e.g., 8-16 cores). Using a ring structure is simpler, more efficient, and has predictable latency. In this application embodiment, the die contains a bidirectional ring structure. A first data packet sent from the first die to the second die is transmitted in the first direction along the ring structure within the first die, and then transmitted to the second die through the mesh structure according to a dimensional order routing strategy. The first data packet is also transmitted in the second direction along the ring structure within the second die, where the second direction is the opposite of the first direction. In other words, the data packet is transmitted across dies. The data flow of the particles is transmitted in a ring structure in different directions at the sending end (first particle) and the receiving end (second particle). There is no circular dependency in the routing, so deadlock will not occur. Furthermore, data transmission is based on a dimensional order routing strategy in the mesh structure between particles. This not only reduces routing complexity and eliminates the need for continuous deadlock monitoring, resulting in low operating overhead, but also ensures the determinism of the routing path and avoids deadlock. In addition, in this embodiment, no retransmission mechanism is involved, making the control messages simpler and reducing the network bandwidth occupation of the control messages, thereby improving bandwidth utilization, reducing network latency, and ultimately improving the chip's utilization benefits. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the first structure of the chip provided in the embodiments of this application;

[0020] Figure 2 This is a schematic diagram of a second structure of the chip provided in an embodiment of this application;

[0021] Figure 3 This is a schematic diagram of the third structure of the chip provided in the embodiments of this application;

[0022] Figure 4 This is a schematic diagram of a bidirectional loop routing node architecture;

[0023] Figure 5 This is a schematic flowchart of a data transmission method provided in an embodiment of this application;

[0024] Figure 6 This is another flowchart illustrating the data transmission method provided in the embodiments of this application.

[0025] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0028] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0029] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0030] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0031] In the implementation of this application, the collection and processing of relevant data should strictly comply with the requirements of relevant laws and regulations, obtain the informed consent or separate consent of the personal information subject, and carry out subsequent data use and processing within the scope of laws and regulations and the authorization of the personal information subject.

[0032] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0033] 1) System on Chip (SoC) is a chip technology that integrates complete system functions. This technology integrates core components such as processor, memory, and peripheral interfaces into a single chip, supports software and hardware co-design, and is widely used in industrial control, consumer electronics, automotive electronics and the Internet of Things.

[0034] 2) Network on Chip (NoC) is a novel communication method for System-on-Chip (SoC). As a key component of multi-core technology, it achieves concurrent communication through distributed routing nodes and time-division multiplexing links, replacing the traditional bus architecture to solve scalability and performance bottlenecks. Its architecture is divided into Electronic Network on Chip (ENoC) based on electronic technology and Optical Network on Chip (ONoC) based on optical technology, employing a globally asynchronous and locally synchronous clock mechanism to reduce power consumption.

[0035] 3) A die is an independent bare chip separated from a silicon wafer through a dicing process. It serves as the physical carrier of semiconductor devices, carrying a complete integrated circuit structure. A die is an independent functional chip containing transistors and circuits manufactured using semiconductor processes.

[0036] 4) Mesh topology, a common NoC topology. Its router nodes are arranged in a two-dimensional array, with each node directly connected to adjacent nodes in the east, west, south, and north directions. The mesh structure is well-organized, with simple layout and wiring, strong scalability, and good path diversity.

[0037] 5) Universal Chip Interconnect Express (UCIe) is an open, standardized die-to-die interconnect protocol. It defines a complete set of standards for the physical layer, data link layer, and protocol stack. The UCIe standard includes the following core technical parameters: defining a complete physical layer specification, including electrical signal levels and clock synchronization mechanisms; specifying the minimum number of physical channels and channel bandwidth; supporting both organic substrates and silicon interposers as packaging media; and reserving space for expansion into stacked 3D packaging interfaces.

[0038] 6) A UCIe Bridge node is a dedicated hardware module integrated within the die, acting as a bridge between the on-chip network (such as Mesh / Ring) and the off-chip UCIe link; therefore, it can also be called a bridging node. The functions of a UCIe Bridge node include:

[0039] 1. Protocol Conversion: Convert the data packet format and protocol of the on-chip network to the format and protocol required by the UCIe standard, and vice versa.

[0040] 2. Routing and traffic splitting: Selecting which UCIe link to send the data packet out through based on its destination.

[0041] In this embodiment, route splitting refers to the process where broadcast data streams are divided into multiple data streams at the UCIe Bridge node based on different routes to different destinations. For example, traffic received by the UCIe Bridge node from the UCIe link is divided into traffic on the current die and traffic that goes to other dies via an internal bypass through another UCIe link.

[0042] 7) A UCIe link is a physical communication channel that conforms to the UCIe standard. It consists of multiple high-speed serial channels and includes specific implementations such as physical layer electrical characteristics, clock schemes, and encoding methods, used to actually transmit bit streams between two dies.

[0043] 8) Dimensional order routing strategy refers to the strategy of routing according to the coordinate dimension (X, Y), including XY routing strategy, YX routing strategy, XY-YX routing strategy, etc.

[0044] 9) The XY routing strategy refers to a routing strategy that first moves entirely along the X-axis (horizontal direction) and then entirely along the Y-axis (vertical direction). The entire path is unique and predetermined, therefore it is a deterministic route.

[0045] Assuming the network topology is a 4×4 grid with coordinates ranging from (0,0) to (3,3), and the source node has coordinates (1,1) and the destination node has coordinates (3,2), the path will be uniquely determined according to the XY routing strategy.

[0046] (1,1) → Compare X: 1≠3, need to go east → forward to East;

[0047] (2,1) → Compare X: 2≠3, need to go east → forward to East;

[0048] (3,1) → Compare X: 3=3, X coordinates match, now compare Y: 1≠2, need to forward to North;

[0049] (3,2) → Compare X: 3=3, compare Y: 2=2, reach the destination node.

[0050] The final path is: (1,1)→(2,1)→(3,1)→(3,2).

[0051] 10) The YX routing strategy is the complete opposite of the standard XY algorithm. It is a routing strategy in which data packets first move completely along the Y-axis (vertical direction) and then move completely along the X-axis (horizontal direction).

[0052] Using the above grid structure as an example, with the source node coordinates (1, 1) and the destination node coordinates (3, 2), according to the YX routing policy, the routing path is:

[0053] (1,1) → Compare Y: 1≠2, need to go north → forward to North;

[0054] (1,2) → Compare Y: 2=2, Y coordinates match, now compare X: 1≠3, need to forward to East;

[0055] (2,2) → Compare X: 2≠3, need to go east → forward to East;

[0056] (3,2) → Arrive at the destination.

[0057] That is, the final path is: (1,1)→(1,2)→(2,2)→(3,2).

[0058] 11) XY-YX routing strategy refers to a routing strategy that dynamically selects whether to execute XY rules or YX rules at the current hop based on network status or information about the data packet itself. Its primary goal is usually to achieve load balancing and avoid network hotspots.

[0059] To better understand the chip provided in the embodiments of this application, the deadlock handling strategies and their shortcomings in the related technologies will be explained first.

[0060] In System-on-Chip (SoC) and Network-on-Chip (NoC) design, deadlock preemption and deadlock avoidance are two mainstream deadlock handling strategies, each with its own characteristics and applicable to different scenarios.

[0061] Deadlock preemption allows deadlocks to occur, but detects and resolves them promptly through dynamic monitoring mechanisms. Typical techniques include: timeout detection and recovery, which sets timeout thresholds for transactions, automatically aborting and retrying after a timeout; and virtual channel preemption, which bypasses the deadlock chain through an escape channel. Deadlock preemption is complex to implement, has high runtime overhead (requiring continuous deadlock monitoring), and carries the risk of livelock (repeated retries may introduce new problems).

[0062] Deadlock avoidance eliminates the possibility of deadlock at the system architecture level by pre-designing constraints. For example, the XY deterministic routing algorithm, widely used in Network-on-Chip (NoC), is based on the idea of ​​transmitting data in a strict dimensional order (usually X dimension first, Y dimension later) to ensure path determinism and avoid deadlock.

[0063] While the XY routing algorithm performs well in single-core or 2D mesh structures, new deadlock problems may arise in multi-level networks, such as hierarchical networks with interconnected cores. For example, connecting multiple deadlock-free cores via the XY routing algorithm may create new deadlocks between cores. This is because routing paths in multi-level networks may involve NoC networks with multiple cores, and traditional deadlock resolution algorithms (such as virtual channel techniques) may not be effective in handling this situation. This deadlock problem is closely related to the complexity of the network topology, especially in multi-layered or asymmetric topologies.

[0064] Optimized message retransmission mechanisms for core-level networks can resolve network deadlock issues across cores. This already employs a layered, hybrid strategy of deadlock avoidance and deadlock preemption: the base layer uses deadlock avoidance (such as fixed XY routing), while the enhancement layer uses deadlock preemption (such as timeout retry mechanisms). However, retransmission mechanisms add control messages, increasing the network load and impacting network latency and bandwidth, resulting in low direct benefits.

[0065] Based on this, embodiments of this application provide a chip, a data transmission method, and an electronic device that can avoid deadlock through a simple routing algorithm and a deadlock avoidance strategy.

[0066] See Figure 1 , Figure 1 This is a schematic diagram of a first structure of a chip provided in an embodiment of this application. The chip includes: multiple chips, and each chip includes multiple functional nodes. Figure 1 The example shows four cores, namely core 101, core 102, core 103 and core 104, and in Figure 1 The example shows four functional nodes included in the core 101, namely node 1011, node 1022, node 1013 and node 1014.

[0067] A die, also known as a bare die, refers to a single, unpackaged silicon chip. It is typically a single chip unit obtained by cutting a silicon wafer containing multiple identical chips. A die is a fundamental product of semiconductor manufacturing. It is a small piece of semiconductor material (usually silicon) containing fully functional circuitry. CPUs, GPUs, and other chips are actually made by encapsulating one or more dies within a protective casing (package).

[0068] In the chip provided in this application embodiment, multiple chips are interconnected using a mesh structure, and multiple functional nodes in each chip are interconnected using a bidirectional ring structure, such as... Figure 1 As shown, the four functional nodes in the core 101 are interconnected using a clockwise ring structure 105 and a counterclockwise ring structure 106.

[0069] The cores are interconnected using a mesh structure, which can be a two-dimensional or multi-dimensional mesh. The mesh structure has a regular topology, and the cores, as nodes in the mesh, can flexibly expand the system scale through row and column links (e.g., increasing the number of cores only requires expanding the mesh dimension), adapting to the scalability requirements of multi-core integration. Furthermore, multiple physical paths exist between any two cores in the mesh (e.g., an XY route can be along the X-axis → Y-axis, and a YX route can be along the Y-axis → X-axis). Combined with routing algorithms, paths can be dynamically selected based on link load, avoiding congestion on a single link and improving the overall throughput of cross-core communication. In addition, cores are typically interconnected using high-speed interconnects (such as silicon interposers and bonding technologies). The row / column links of the mesh can be aligned with the physical wiring direction, reducing signal transmission distance and interference, and lowering physical layer loss in cross-core communication.

[0070] For an individual core, the functional nodes within the core are generally fixed, and the internal structure is relatively regular. Therefore, the functional nodes within the core can be connected in a ring structure. The number of links in a ring topology is proportional to the number of nodes. Compared to mesh or tree structures, it has lower hardware overhead (such as wiring resources and routing logic), making it suitable for the limited physical space and power constraints within the core. In a ring structure, functional nodes are directly connected via bidirectional links, eliminating the need for complex routing or intermediate node forwarding, resulting in extremely low local communication latency. Bidirectional links enable parallel bidirectional data transmission, improving bandwidth utilization within the core and reducing data transmission conflicts.

[0071] The first data packet sent from the first core to the second core is transmitted in the first direction in the ring structure within the first core, and then transmitted to the second core through the grid structure according to the dimensional order routing strategy. The first data packet is transmitted in the second direction in the ring structure within the second core, and the second direction is the opposite direction of the first direction.

[0072] In the embodiments of this application, the dimensional order routing strategy can be an XY routing strategy or an XY-YX routing strategy, which will be described below.

[0073] The XY routing strategy is a deterministic routing strategy. In its implementation, it first moves entirely along the X-axis (horizontal direction) and then entirely along the Y-axis (vertical direction) (or Y-axis first, then X, but X-axis first, then Y is the standard definition). The entire path is unique and pre-determined. The routing logic of the XY routing strategy is extremely simple, requiring very few hardware logic gates, resulting in low area and power consumption. Furthermore, because the strict order of X-axis first, then Y-axis (or Y-axis first, then X-axis) prevents cycles in the channel dependency graph. All data packets first request east / west channels, then north / south channels; the dependencies are strictly acyclic, thus preventing deadlocks. Since the path is deterministic, data packets will eventually reach their destination, preventing livelocks. Additionally, using the XY routing strategy, all data packets from the source to the destination follow the exact same path, ensuring that their arrival order matches their sending order, thus achieving data order preservation.

[0074] In some embodiments, to achieve load balancing and avoid network hotspots, an XY-YX routing strategy can be used. This strategy dynamically selects whether to execute the XY rule or the YX rule at the current hop based on network conditions or information about the data packet itself. XY-YX routing strategies typically have two implementation modes:

[0075] Mode 1: When a data packet is injected into the network, the source node decides whether the data packet should use XY routing or YX routing throughout the entire process based on a certain strategy (such as random selection, round-robin, or hashing based on the destination address).

[0076] In implementation, a very small flag bit can be added to the packet header (e.g., 1 bit: 0 represents XY, 1 represents YX). During routing, each node in the network reads this flag bit and uses it to determine whether to compare X first (if the flag is XY) or Y first (if the flag is YX).

[0077] Mode 2, Hop-by-Hop Adaptive, is implemented such that each intermediate core dynamically determines whether to proceed in the X or Y direction next, based on its local congestion information (e.g., the depth of the downstream output queue).

[0078] The XY-YX routing strategy can effectively reduce network hotspots and improve overall network throughput by distributing traffic across different paths. Furthermore, as long as the constraint that "once a movement in one dimension begins, that dimension must be completed first" is followed, it can ensure that no cycles are formed in the channel dependency graph, thereby avoiding deadlock.

[0079] In this embodiment of the application, the first direction and the second direction are opposite directions; for example, the first direction is counterclockwise and the second direction is clockwise. See also Figure 1 Taking core 101 as the first core and core 103 as the second core, with an XY routing strategy as the dimensional order routing strategy, this example illustrates the process. Assume the first data packet originates from node 1012 in core 101. The first data packet is transmitted counter-clockwise to the output port of core 101, then, according to the XY routing strategy, it is transmitted to core 102, and from core 102 to core 103. The first data packet then loops clockwise until it reaches the target functional node in core 103. In other words, cross-core traffic loops counter-clockwise at the data sending end (first core), outputting to the mesh structure, and then leaves the mesh structure clockwise at the data receiving end (second core), transmitting to the target functional node. This forms an "S"-shaped path, thus preventing closed loops in the entire system and eliminating deadlock.

[0080] In some embodiments, the chip further includes a bridging node, which is used to perform protocol conversion and traffic splitting on data packets transmitted to different chips; the bridging node corresponds to N bridging links, which are used to connect different chips and realize the physical channel and protocol interface for data communication; where N is the number of bridging links required for the mesh structure, that is, N is a positive integer greater than or equal to 1.

[0081] A bridging node is responsible for converting and transmitting data packet formats, timings, and protocols from on-chip networks (such as Ring network structures) to the formats and protocols required by the UCIe standard for inter-chip interconnection. In practical applications, a bridging node can be a UCIe Bridge node. Logically, a bridging node can be viewed as a gateway or port connecting on-chip and off-chip networks. A chip can include one bridging node, in which case its external connections must correspond to the row / column direction of the mesh structure (such as the four directions of up, down, left, and right). A single bridging node can integrate multiple bridging links, serving as a unified entry and exit point for the chip, simplifying the interface logic between the chip and the network structure. Furthermore, when there is only one bridging node, it can centrally handle all cross-chip traffic. Nodes within the chip (such as functional nodes in a ring structure) only need to send cross-chip data to this node without needing to be aware of the specific topology of the external mesh, thereby reducing the size of the routing table and decision logic within the chip.

[0082] In some embodiments, since a bridging node is connected to multiple bridging links, and different bridging links connect to different external cores, when the bridging node of the first core sends data, it needs to determine the destination address of the first data packet through traffic splitting and, based on the destination address, determine which specific bridging link the first data packet should be sent out through. In practical applications, a routing table can be stored in the bridging node. This routing table defines the mapping relationship between the destination address (or address range) and the corresponding output bridging link.

[0083] In some embodiments, the chip further includes multiple bridging nodes, which are used to perform protocol conversion and traffic splitting on data packets transmitted to different chips; each bridging node corresponds to one or more bridging links, which are physical channels connecting different bridging nodes.

[0084] In some embodiments, when a chip includes multiple bridging nodes, one chip may correspond to one bridging node, or one chip may correspond to two or more bridging nodes. See also Figure 2 Each core corresponds to one bridging node, and each bridging node corresponds to two bridging links. Specifically, core 101 corresponds to bridging node 201, core 102 corresponds to bridging node 202, core 103 corresponds to bridging node 203, and core 104 corresponds to bridging node 204. Bridging nodes 201 and 202 are interconnected via bridging links, bridging nodes 202 and 203 are interconnected via bridging links, bridging nodes 203 and 204 are interconnected via bridging links, and bridging nodes 201 and 204 are interconnected via bridging links.

[0085] For each core, when a core corresponds to a bridging node, the core and its corresponding bridging node are connected through at least two multiplexing / demultiplexing devices; the multiplexing / demultiplexing devices are used for path selection or path allocation; there is an internal bypass path between the two multiplexing / demultiplexing devices.

[0086] See Figure 2 Each chip is connected to its corresponding bridging node via two multiplexing / demultiplexing devices. The multiplexing device is used for path selection, i.e., selecting one output from multiple inputs, while the demultiplexing device is used for path allocation, i.e., assigning one input to one of the multiple outputs. Internal bypass paths exist between each pair of multiplexing / demultiplexing devices. These internal bypass paths are physical channels designed and laid out directly on the silicon wafer, providing a fast path for "through" traffic that does not enter the chip's internal core network.

[0087] In some embodiments, when a first data packet sent from the first core to the second core is transmitted to the third core, since the third core is not the target core, the first data packet is "passing" traffic for the third core. At this time, the first data packet is output to the second core or the fourth core through the internal bypass path of the third core.

[0088] See Figure 2Continuing with the example of chip 101 as the first chip and chip 103 as the second chip, based on the YX routing strategy, the first data packet sent from chip 101 to chip 103 is looped counterclockwise on chip 101, then looped off at bridging node 201, and transmitted to bridging node 204 via bridging link 401. Since chip 104 corresponding to bridging node 204 is not the target chip, the first data packet is transmitted to bridging link 403 via the internal bypass path 402 corresponding to chip 104. The first data packet reaches bridging node 203 via bridging link 403 and loops clockwise until it reaches the target functional node. Thus, since the internal bypass path is usually the shortest and most direct physical connection, with fewer hops and shorter clock cycles, data transmission latency is significantly reduced. Due to the reduced data transmission latency, the link can prepare to receive the next batch of data more quickly, improving interconnection efficiency and thereby enhancing the data throughput of the multi-die chip system as a whole. Furthermore, by using an internal bypass path to remove "passing" traffic from the on-chip main interconnect network, the NoC bandwidth can be fully used for communication between computing units within the chip, avoiding interference from external traffic on internal performance.

[0089] See Figure 3 Each core corresponds to two bridging nodes, and each bridging node corresponds to two bridging links. For each core, it is connected to each of its corresponding bridging nodes via at least two multiplexing / demultiplexing devices. These multiplexing / demultiplexing devices are also used for path selection or path allocation; the multiplexing devices are used for path selection, and the demultiplexing devices are used for path allocation. Internal bypass paths exist between the multiplexing / demultiplexing devices corresponding to different bridging nodes.

[0090] In this embodiment, the example of a third functional node of a first core sending a first data packet for data access to a second functional node of a second core is used for illustration. The first core corresponds to... Figure 3 Core 101, the second core corresponds to Figure 3 Core 103, such as Figure 3As shown, the first data packet loops counterclockwise on core 101. When the first data packet passes through bridging node 501, it exits the loop and reaches bridging node 501 via multiplexing / demultiplexing devices. Then, it reaches bridging node 503 corresponding to core 104 via bridging link 502. Since the target node is not in core 104, the first data packet is a transit traffic for core 104. At this time, the first data packet reaches bridging node 505 corresponding to core 104 via the internal bypass path 504 of core 104, and is transmitted from bridging node 505 to bridging node 507 corresponding to core 103 via bridging link 506. Since core 103 is the core where the target node is located, the first data packet enters the ring structure inside core 103 via bridging node 507 via multiplexing / demultiplexing devices, loops clockwise, and is transmitted to the target node (e.g., the fourth functional node).

[0091] In some embodiments, after receiving the first data packet, the fourth functional node can execute an access request and generate a response data packet, such as a third data packet. The third data packet needs to be routed to the third functional node in core 101. The third data packet is looped counterclockwise in core 103, exits the loop after passing through the bridging node 508 corresponding to core 103, and reaches the bridging node 510 corresponding to core 102 through bridging link 509. Since the target node corresponding to the third data packet is not inside core 102, the third data packet reaches the bridging node 512 corresponding to core 102 through the internal bypass path 511 corresponding to core 102, and is transmitted to core 101 via bridging link 513 and bridging node 514. Since the target node is inside 101, the third data packet is looped clockwise in core 101, exits the loop when it reaches the third functional node, and at this time, the response information is returned to the request initiating node.

[0092] In this embodiment of the application, cross-core traffic is sent at the sending end in a ring structure in the first direction and received at the destination end in a ring structure in the second direction. Since the first direction and the second direction are opposite directions, the receiving end can definitely exit the ring, and there is naturally no circular dependency of routing, so deadlock will not be formed.

[0093] In some embodiments, a second data packet sent from a first functional node in a first core to a second functional node in a first core is transmitted in a ring structure within the first core in a target direction, which is either a first direction or a second direction.

[0094] In some embodiments, the methods for determining the target direction include at least the following three:

[0095] The first method involves randomly determining the direction from either the first or the second direction.

[0096] The second method is based on determining the first and second distances.

[0097] Wherein, the first distance is the distance between the first functional node and the second functional node determined according to the first direction, the second distance is the distance between the first functional node and the second functional node determined according to the second direction, and when the first distance is less than the second distance, the target direction is the first direction, and when the first distance is greater than or equal to the second distance, the target direction is the second direction.

[0098] For example, if the first distance between the first functional node and the second functional node is determined to be 3 according to the first direction, and the second distance between the first functional node and the second functional node is determined to be 2 according to the second direction, then the second direction is determined as the target direction. This implementation method can be understood as selecting the ring-up direction based on the principle of proximity, which can minimize the number of hops that the data packet traverses on the ring, thereby reducing communication latency.

[0099] The third method is to determine the data type based on the second data packet.

[0100] The data type is either a request type or a response type, with the request type corresponding to a first direction and the response type corresponding to a second direction. That is, if the second data packet is a request type, the destination direction is the first direction; if the second data packet is a response type, the destination direction is the second direction. This protocol specifies that request and response data packets are allocated completely independent physical paths. Thus, even if the request path is completely blocked, the response path remains unobstructed, preventing circular dependencies and avoiding deadlocks in ring transmissions.

[0101] Routing on the ring structure within a kernel itself does not cause deadlock, but when combined with paths within the kernel node, it can lead to deadlock. For example, if a concentrated wave of accesses to a node occurs, the traffic (data packets) fills the ring structure and related paths within the node, and the responses from the accessing node still need to be routed back to the ring, a deadlock will form. This deadlock is caused by the ring structure and is essentially unrelated to cross-kernel traffic, making it much easier to analyze and resolve than deadlocks caused by cross-kernel traffic. This deadlock is caused by a ring dependency resulting from the ring path formed by the ring and the path within the node. When traffic is looping and waiting in the ring path, it cannot continue, thus causing a deadlock. In the embodiments of this application, this deadlock can be avoided by ensuring that access traffic cannot fill the ring and the path within the node. In practical applications, deadlock can be avoided in the following two ways:

[0102] The first method is to obtain a data volume threshold and a first number of data packets that have been sent before the first functional node sends the second data packet. When the first number is less than the data volume threshold, the first functional node sends the second data packet.

[0103] The data volume threshold can be set based on system performance requirements to limit the number of accesses each functional node can initiate. Therefore, the data volume threshold can be understood as defining and limiting the maximum theoretical traffic that may be generated based on the chip's target application scenario and performance indicators. The data volume thresholds for different functional nodes can be the same or different. Deadlock will not occur if the number of accesses initiated by a functional node is not less than the data volume threshold.

[0104] The second method: Before the first functional node sends the second data packet, the first functional node sends a space request message to the second functional node. When the second functional node returns a notification message that the space request was successful, the first functional node sends the second data packet.

[0105] The second implementation ensures that the buffer of the functional node is filled, because the sender will be prevented from sending before the buffer is full. This fundamentally breaks the chain of deadlock.

[0106] The following will describe an exemplary application of the embodiments of this application in a real-world application scenario.

[0107] This application provides a multi-die interconnected NoC structure and a corresponding simple routing algorithm, employing a deadlock avoidance strategy to prevent deadlock. The NoC topology is as follows: dies are interconnected using a mesh structure, each die containing multiple nodes, which are interconnected via a bidirectional ring structure.

[0108] Figure 4 This is a schematic diagram of a bidirectional ring routing node architecture, as shown below. Figure 4 As shown, the bidirectional ring routing node includes: a router 601, a multiplexer / demultiplexer 602, a network interface 603, and a node local module 604. The router 601 is used for route control, processing and forwarding data from different directions (including clockwise input and counter-clockwise output). The multiplexer / demultiplexer 602 performs data multiplexing and demultiplexing to ensure efficient data transmission between different paths. The network interface 603 connects the router 601 and the node local module 604, enabling communication between the node local module and the network. The node local module 604 is the node's local functional module, used for data processing and data interaction with the network.

[0109] Traffic within a die can choose its ring-up direction according to certain principles (such as proximity rules). Cross-die traffic sending and receiving uses different ring-up directions, combined with a routing strategy using the XY (or a variant of the XY algorithm, such as XY-YX) algorithm between dies. That is, cross-die traffic selects a counter-clockwise (or clockwise) ring-up direction at the source die, and a clockwise (or counter-clockwise) ring-up direction at the destination die. Because sending and receiving use different ring-up directions, traffic can definitely exit the ring at the receiving end, naturally eliminating circular dependencies in routing and preventing deadlocks.

[0110] In this embodiment, the UCIe Bridge node used for cross-die connections (corresponding to the bridging node in other embodiments) can logically be one (a UCIe Bridge node contains the number of UCIe links required by the mesh structure), or there can be several UCIe Bridge nodes, depending on the topology between dies. A UCIe Bridge node contains only one UCIe link. The UCIe Bridge node needs to distribute traffic destined for different dies.

[0111] Within the Die, UCIe links used for cross-Die connections require the use of internal bypasses. Internal bypasses are physical channels designed and laid out directly on the silicon die, specifically designed to directly connect the receiver of one UCIe Bridge node to the transmitter of another UCIe Bridge node, thereby providing a fast path for "passing" traffic that does not enter the Die's internal core network.

[0112] Routing within the ring structure of this die itself does not cause deadlock, but when combined with node paths within the same die, it can lead to deadlock. For example, if multiple accesses to a node occur, traffic fills the ring structure and related paths within the node, and the response from the accessed node still needs to be routed back up the ring, a deadlock will occur. This deadlock is caused by the ring structure and is essentially unrelated to cross-die traffic, making it much easier to analyze and resolve than deadlocks caused by cross-die traffic. This deadlock is caused by a ring dependency resulting from the ring structure and the ring paths within the nodes. When traffic is looping and waiting in the ring path, it cannot continue, thus causing a deadlock. In the embodiments of this application, this deadlock can be avoided by ensuring that access traffic does not fill the ring structure and the paths within the nodes:

[0113] First, limit the number of access requests.

[0114] In some embodiments, based on system performance requirements, the number of accesses that each node can initiate can be limited to a certain number, thus preventing deadlocks. Alternatively, this can be achieved through protocol design, such as requiring space to be allocated before sending requests.

[0115] Second, increase the internal cache space of the nodes.

[0116] Third, avoid it through system routing policies.

[0117] In some embodiments, system routing policies can be used to restrict request traffic and access traffic to use different bidirectional loop paths, that is, to allocate completely independent physical paths for request traffic and response traffic. Therefore, even if the request path is completely blocked, the response path remains unobstructed, and circular dependencies cannot be formed.

[0118] Each transaction (which can be a flow control unit (flit), packet, or message, depending on system requirements) contains bitmap routing information. This bitmap routing information is used to mark all target nodes, distinguishing whether a target node is located within the current die or in another die. When the target node is in another die, meaning the traffic originating from the current die is cross-die traffic, it can be routed from the UCIe Bridge node to the target node in another die via a UCIe link. If the target node is within the current die, the traffic simply passes through the UCIe Bridge node and continues routing within the ring structure. Due to broadcasting, the above situation may occur on the same flit, in which case one flit will be split into two flits (cross-die and intra-die). Traffic received by the UCIe Bridge node via the UCIe link is similarly divided into intra-die traffic and traffic that needs to be routed to other dies via another UCIe link. Thus, the UCIe Bridge node achieves traffic splitting.

[0119] The data transmission method provided in this application will be described in conjunction with exemplary applications and implementations of the chip provided in the embodiments of this application.

[0120] See Figure 5 , Figure 5 This is a flowchart illustrating a data transmission method provided in an embodiment of this application, which is applied to the chip provided in the foregoing embodiment. (The text will then be combined with...) Figure 5 The steps shown are explained.

[0121] In step S101, the data packet to be sent is obtained.

[0122] In some embodiments, the data packet to be sent can be a request data packet requesting access, or a response data packet obtained by executing the request access. The data packet to be sent can be a first data packet transmitted across cores, for example, a data packet sent from a third functional node of a first core to a fourth functional node of a second core; the data packet to be sent can also be a second data packet transmitted within a core, for example, a data packet sent from a first functional node of a first core to a second functional node of a first core.

[0123] In step S102, when the data packet to be sent is the first data packet sent from the first chip to the second chip, the first data packet is transmitted in the first direction along the ring structure within the first chip.

[0124] Here, the first direction can be either clockwise or counterclockwise. In this embodiment, a counterclockwise direction is used as an example. Multiple functional nodes within each chip are interconnected through a bidirectional ring structure. The number of links in the ring topology is proportional to the number of nodes. Compared to mesh or tree structures, it has lower hardware overhead (such as wiring resources and routing logic), making it suitable for the limited physical space and power constraints within the chip. In the ring structure, functional nodes are directly connected via bidirectional links, eliminating the need for complex routing or intermediate node forwarding, resulting in extremely low local communication latency. The bidirectional links enable parallel bidirectional data transmission, improving bandwidth utilization within the chip and reducing data transmission conflicts.

[0125] In step S103, the first data packet is transmitted to the second core according to the dimensional order routing strategy.

[0126] Here, the dimensional order routing strategy refers to a strategy that routes data according to the coordinate dimensions (X, Y), including XY routing strategy, YX routing strategy, XY-YX routing strategy, etc. In this embodiment, the chip includes multiple chips, and the multiple chips are interconnected through a mesh structure. In step S103, the first data packet is transmitted to the second chip through the mesh structure constructed by the multiple chips according to the dimensional order routing strategy.

[0127] In some embodiments, during the transmission of the first data packet to the second chip via a mesh structure constructed from multiple chips according to a dimensional order routing strategy, when the first data packet is transmitted to another chip (e.g., the third chip) where the target functional node is not located, the first data packet will not be transmitted on the ring structure inside the third chip. Instead, it will quickly pass through the third chip via the internal bypass path corresponding to the third chip and reach the next chip. The next chip is also not the chip where the target functional node is located, and it will also be transmitted via the internal bypass path corresponding to that chip. The internal bypass path is a physical channel directly designed and laid out on the silicon wafer, used to provide a fast channel for "passing" traffic that does not enter the core network inside the chip. The internal bypass path significantly reduces the data transmission latency. Due to the reduced data transmission latency, the link can be prepared to receive the next batch of data more quickly, improving interconnect efficiency and thus enhancing the data throughput of the multi-die chip as a whole system. Furthermore, by stripping the "passing" traffic from the on-chip main interconnect network through the internal bypass path, the NoC bandwidth can be fully used for communication between computing units inside the chip, avoiding interference from external traffic to internal performance. If the next core is the core containing the target functional node, then the first data packet will enter the ring structure inside that core for transmission.

[0128] In step S104, the first data packet is transmitted in the second direction along the ring structure within the second core until it reaches the target functional node.

[0129] The second direction is the opposite of the first direction. That is, if the first direction is clockwise, then the second direction is counterclockwise; if the first direction is counterclockwise, then the second direction is clockwise.

[0130] See Figure 1 Taking core 101 as the first core and core 103 as the second core, with an XY routing strategy as the dimensional order routing strategy, this example illustrates the process. Assume the first data packet originates from node 1012 in core 101. The first data packet is transmitted counter-clockwise to the output port of core 101, then, according to the XY routing strategy, it is transmitted to core 102, and from core 102 to core 103. The first data packet then loops clockwise until it reaches the target functional node in core 103. In other words, cross-core traffic loops counter-clockwise at the data sending end (first core), outputting to the mesh structure, and then leaves the mesh structure clockwise at the data receiving end (second core), transmitting to the target functional node. This forms an "S"-shaped path, thus preventing closed loops in the entire system and eliminating deadlock.

[0131] In the data transmission method provided in this application embodiment, after receiving the data packet to be sent, when the data packet to be sent is the first data packet sent from the first chip to the second chip, the first data packet is transmitted in the first chip's ring structure in the first direction, and then transmitted to the second chip according to the dimensional order routing strategy. The first data packet is then transmitted in the second chip's ring structure in the second direction until it reaches the target functional node. Since the first data packet is transmitted in different directions in the first chip (sender) and the second chip (receiver), there is no circular dependency in the routing, thus preventing deadlock. Furthermore, data transmission in the inter-chip mesh structure is based on the dimensional order routing strategy, resulting in low routing complexity, no need for continuous deadlock monitoring, low operating overhead, and ensuring the determinism of the routing path while avoiding deadlock. Additionally, in this application embodiment, no retransmission mechanism is involved, making the control messages simpler and reducing the network bandwidth usage of the control messages, thereby improving bandwidth utilization, reducing network latency, and ultimately increasing the chip's utilization benefits.

[0132] In some embodiments, see Figure 6 After step S101, the following steps may also be performed:

[0133] In step S001, it is determined whether the data packet to be sent is the second data packet transmitted within the core.

[0134] Specifically, when the data packet to be sent is a second data packet sent from the first functional node in the first core to the second functional node in the first core, step S002 is entered; when the data packet to be sent is not a second data packet, that is, when the data packet to be sent is a first data packet transmitted across cores, step S102 is entered.

[0135] In step S002, the target direction is determined.

[0136] The target direction is either a first direction or a second direction. In some embodiments, the method for determining the target direction includes at least the following three:

[0137] The first method involves randomly determining the direction from either the first or the second direction.

[0138] The second method is based on determining the first and second distances.

[0139] Wherein, the first distance is the distance between the first functional node and the second functional node determined according to the first direction, the second distance is the distance between the first functional node and the second functional node determined according to the second direction, and when the first distance is less than the second distance, the target direction is the first direction, and when the first distance is greater than or equal to the second distance, the target direction is the second direction.

[0140] For example, if the first distance between the first functional node and the second functional node is determined to be 3 according to the first direction, and the second distance between the first functional node and the second functional node is determined to be 2 according to the second direction, then the second direction is determined as the target direction. This implementation method can be understood as selecting the ring-up direction based on the principle of proximity, which can minimize the number of hops that the data packet traverses on the ring, thereby reducing communication latency.

[0141] The third method is to determine the data type based on the second data packet.

[0142] The data type is either a request type or a response type, with the request type corresponding to a first direction and the response type corresponding to a second direction. That is, if the second data packet is a request type, the destination direction is the first direction; if the second data packet is a response type, the destination direction is the second direction. This protocol specifies that request and response data packets are allocated completely independent physical paths. Thus, even if the request path is completely blocked, the response path remains unobstructed, preventing circular dependencies and avoiding deadlocks in ring transmissions.

[0143] In step S003, the second data packet is transmitted in the ring structure within the first core according to the target direction until it reaches the second functional node.

[0144] The target direction is either the first direction or the second direction.

[0145] In some embodiments, routing on the ring structure within a kernel does not inherently cause deadlock. However, when combined with intra-kernel node paths, deadlock can occur. For example, if a cluster of accesses to a node occurs, and traffic (data packets) fills the ring structure and related intra-kernel paths, and the responses from accessing nodes still need to be routed back to the ring, a deadlock will form. This deadlock is caused by the ring structure and is essentially unrelated to cross-kernel traffic, making it much easier to analyze and resolve than deadlocks caused by cross-kernel traffic. This deadlock is caused by a ring dependency resulting from the ring path formed by the ring and intra-kernel paths. When traffic is looping and waiting in the ring path, it cannot continue, leading to a deadlock. In the embodiments of this application, this deadlock can be avoided by ensuring that access traffic cannot fill the ring and intra-kernel paths. In practical applications, deadlock can be avoided in the following two ways:

[0146] The first method: Before step S003, obtain the data volume threshold and the first number of data packets that have been sent for the first functional node. When the first number is less than the data volume threshold, the first functional node sends the second data packet.

[0147] The data volume threshold can be set based on system performance requirements to limit the number of accesses each functional node can initiate. Therefore, the data volume threshold can be understood as defining and limiting the maximum theoretical traffic that may be generated based on the chip's target application scenario and performance indicators. The data volume thresholds for different functional nodes can be the same or different. Deadlock will not occur if the number of accesses initiated by a functional node is not less than the data volume threshold.

[0148] The second method: Before step S003, the first functional node sends a space request message to the second functional node. When the second functional node returns a notification message that the space request was successful, the first functional node sends the second data packet.

[0149] The second implementation method ensures that the buffer of the functional node is filled, because the sender will be prevented from sending before the buffer is full, thus fundamentally breaking the chain of deadlock and avoiding deadlock.

[0150] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A chip, characterized by The chip comprises a plurality of core particles, each of which comprises a plurality of functional nodes, wherein: The plurality of core particles are interconnected in a mesh structure, and the plurality of functional nodes in each of the core particles are interconnected in a bidirectional ring structure; A first data packet transmitted from a first core particle to a second core particle is transmitted in a first direction on the ring structure in the first core particle, and is transmitted to the second core particle through the mesh structure according to a dimensional order routing strategy, and is transmitted in a second direction on the ring structure in the second core particle, the second direction being the opposite direction of the first direction.

2. The chip according to claim 1, characterized in that, The chip further comprises a bridge node for performing protocol conversion and shunting processing on data packets transmitted to different core particles; The bridge node corresponds to N bridge links, the bridge links being used for connecting different core particles and realizing physical channels and protocol interfaces for data communication, wherein N is the number of bridge links required by the mesh structure.

3. The chip of claim 1, wherein, The chip further comprises a plurality of bridge nodes for performing protocol conversion and shunting processing on data packets transmitted to different core particles; Each of the bridge nodes corresponds to one or more bridge links, the bridge links being physical channels connecting different bridge nodes.

4. The chip of claim 3, wherein For each of the core particles, when the core particle corresponds to one bridge node, the core particle and the bridge node are connected through at least two multiplexing / demultiplexing devices; The multiplexing / demultiplexing devices are used for path selection or path allocation, and there is an internal bypass path between two of the multiplexing / demultiplexing devices.

5. The chip of claim 3, wherein For each of the core particles, when the core particle corresponds to at least two bridge nodes, the core particle and each of the bridge nodes are connected through at least two multiplexing / demultiplexing devices; The multiplexing / demultiplexing devices are used for path selection or path allocation, and there is an internal bypass path between the multiplexing / demultiplexing devices corresponding to different bridge nodes.

6. The chip according to claim 4 or 5, characterized in that When the first data packet is transmitted to a third core particle, the first data packet is output to the second core particle or a fourth core particle by the internal bypass path of the third core particle.

7. The chip according to any one of claims 1 to 5, characterized in that A second data packet transmitted from a first functional node in the first core particle to a second functional node in the first core particle is transmitted in a target direction on the ring structure in the first core particle, the target direction being the first direction or the second direction.

8. The chip of claim 7, wherein, The target direction is randomly determined from the first direction and the second direction; or The target direction is determined based on a first distance and a second distance, the first distance being a distance between the first functional node and the second functional node determined in the first direction, the second distance being a distance between the first functional node and the second functional node determined in the second direction, and when the first distance is less than the second distance, the target direction is the first direction, and when the first distance is greater than or equal to the second distance, the target direction is the second direction; or The target direction is determined based on a data type of the second data packet, the data type being a request type or a response type, and the request type corresponding to a first direction and the response type corresponding to a second direction.

9. The chip of claim 7, wherein, Before the first functional node sends the second data packet, a data amount threshold value and a first number of sent data packets are obtained, and when the first number is less than the data amount threshold value, the first functional node sends the second data packet.

10. The chip of claim 9, wherein, Before the first functional node sends the second data packet, the first functional node sends a space application message to the second functional node, and when the second functional node returns a space application success notification message, the first functional node sends the second data packet.

11. A data transmission method, characterized by, The method is applied to the chip provided in any one of claims 1 to 10, and the method comprises: obtaining a to-be-sent data packet; when the to-be-sent data packet is a first data packet sent from a first chiplet to a second chiplet in the chip, transmitting the first data packet on a ring structure in the first chiplet in a first direction; transmitting the first data packet to the second chiplet through the mesh structure according to a dimension order routing strategy; transmitting the first data packet on a ring structure in the second chiplet in a second direction until a target functional node is reached, the second direction being an opposite direction of the first direction.

12. The method of claim 11, wherein, The method further comprises: when the to-be-sent data packet is a second data packet sent from a first functional node in the first chiplet to a second functional node in the first chiplet, determining a target direction; transmitting the second data packet on a ring structure in the first chiplet in the target direction until the second functional node is reached, the target direction being the first direction or the second direction.

13. An electronic device, comprising: The electronic device comprises the chip according to any one of claims 1 to 10.

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