Low-cost soft error reinforcement method based on approximate triple modular redundancy unit

Abstract

The invention discloses a low-cost soft error reinforcement method based on an approximate triple modular redundancy unit. The method comprises the following steps: establishing an approximate library: establishing an approximate gate unit for a basic gate unit of a to-be-reinforced circuit, and integrally establishing an approximate gate unit library; software modeling: acquiring basic information of each standard gate unit in the circuit, and evaluating the performance of the circuit according to a soft error propagation physical model so as to perform software modeling; and approximate reinforcement: selecting a gate unit in a to-be-reinforced circuit in a semi-directional manner based on improved dynamic adjustment NSGA-II to replace the gate unit with an approximate gate unit in an approximate library, simulating circuit performance indexes through an estimator, performing multi-target optimization solution, obtaining an optimal compromise of area, power consumption and soft error rate through iteration, and giving an approximate reinforcement scheme. The method has high efficiency, practicability and universality, can be used for guiding low-cost soft-error-tolerant approximate reinforcement of various high-reliability structures such as triple modular redundancy (TMR) and the like, and can adapt to multi-scene and multi-requirement circuit reinforcement design.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor and integrated circuit technology, specifically relating to a low-cost soft error hardening method for integrated circuits based on approximate triple-modular redundancy units. Background Technology

[0002] In recent years, with the rapid development of the semiconductor industry, integrated circuit technology nodes have continued to evolve. The introduction of nanoscale processes has significantly reduced transistor size and lowered supply voltage, thereby increasing the operating frequency and integration density of integrated circuits, driving continuous improvement in chip performance, and supporting more complex and efficient system designs. However, this progress has also significantly increased the sensitivity of integrated circuits to external disturbances such as radiation, posing a severe challenge to circuit reliability design.

[0003] Traditional circuit-level hardening structures primarily utilize redundancy principles. For example, Triple Modular Redundancy (TMR) achieves error masking by replicating three circuits and adding a majority voter, and is widely used in high-reliability scenarios such as aerospace and automotive. However, its high area and power consumption costs make it difficult to deploy in resource-constrained scenarios such as today's popular commercial aerospace satellites.

[0004] In recent years, the Approximate TMR (ATMR) structure, based on the idea of ​​approximate computation, has been proposed. By replacing some redundant paths with approximate gates that have better area and energy consumption, resource overhead can be significantly reduced while ensuring a certain level of reliability. However, the combined effects of different gate-level replacements in ATMR design are highly nonlinear, and traditional exhaustive search or fixed-probability genetic optimization methods are difficult to quickly obtain the optimal solution. Therefore, designing a flexible and efficient approximate hardening method that compromises between indicators such as area, power consumption, and soft error rate to achieve efficient multi-objective optimization and provide a comprehensive optimal replacement hardening scheme has become a research focus. Summary of the Invention

[0005] The purpose of this invention is to provide a flexible and efficient circuit approximation hardening method that makes trade-offs between indicators such as area, power consumption, and soft error rate to adapt to diverse design conditions and provide designers with the optimal low-cost and high-reliability approximation hardening solution.

[0006] The approximate hardening process in this invention is based on an improved second-generation non-dominated sorting genetic algorithm (NSGA-II) that semi-directionally selects gate cells in the circuit to be hardened and replaces them with approximate gate cells from a pre-established approximation library. A customized software estimator simulates circuit performance indicators, and multi-objective optimization is performed iteratively to obtain the optimal trade-off between area, power consumption, and soft error rate, resulting in a final set of approximate hardening schemes. This invention's method is efficient, practical, and versatile, and can be used to guide low-cost, soft-error-tolerant approximate hardening of various high-reliability structures such as triple-modular redundancy (TMR). It is adaptable to circuit hardening designs with diverse requirements and scenarios. The technical solution of this invention is described in detail below.

[0007] A low-cost soft error hardening method based on approximate triple-modular redundancy units includes three processes:

[0008] Approximate library establishment, software modeling, and approximate hardening; among which:

[0009] Approximation library establishment process: Based on the Karnaugh map modification method, construct corresponding approximation gate units for the basic gate units of the circuit to be hardened, and establish an overall approximation gate unit library;

[0010] Software modeling process: Obtain basic information such as area and power consumption of each standard gate unit in the circuit. Based on the physical model of soft error propagation, use Python code to perform software modeling to evaluate the area, power consumption, and soft error rate of the circuit, and build an easy-to-interact and efficient circuit performance evaluator.

[0011] Approximate hardening process: Based on the improved NSGA-II semi-directional selection, the gate cells in the circuit to be hardened are replaced with approximate gate cells in the pre-established approximation library. The performance index of the approximate hardened circuit is simulated by a customized software estimator, and multi-objective optimization is performed. After iteration, the optimal trade-off between area, power consumption and soft error rate is obtained, and a final set of approximate hardening schemes is given, replacing the two redundant modules in the traditional triple-modular redundancy hardened circuit with low-cost and high-reliability approximate modules.

[0012] In this invention, the approximation library establishment process specifically includes the following steps:

[0013] (1) Based on the initial circuit netlist, the entire circuit is traversed and scanned to obtain the set of gate units in the circuit to be strengthened;

[0014] (2) By using Boolean decomposition, the downward approximation version and the upward approximation version of each gate unit in the gate unit set are obtained;

[0015] (3) The obtained approximate gate units are combined into a downward approximate gate unit library and an upward approximate gate unit library, and the downward approximate version and the upward approximate version of the approximate gate unit are obtained again by Boolean decomposition.

[0016] (4) By iterating in this way, a complete and closed-loop approximate gate unit library is obtained;

[0017] (5) The process of establishing the approximate library is complete.

[0018] In this invention, the approximate hardening structure obtained by multi-objective optimization is a circuit after approximately replacing the gate units of traditional triple-modular redundancy (TMR) structures for hardening the circuit to be hardened. This achieves the lowest possible hardware losses, such as area and power consumption, while ensuring high reliability hardening.

[0019] In this invention, the software modeling process performs logic synthesis on the circuit file, extracting the area and power consumption information of each standard gate unit. A physical propagation model of soft errors in the circuit is constructed, and a customized estimator written in Python simulates the area and power consumption of the overall circuit, estimating the soft error rate of each hardened circuit.

[0020] In this invention, the approximate hardening process treats the hardening circuit as a directed acyclic graph G =<V,E> In a directed graph G, vertices V contain the input and output terminals of the circuit and all logic gate units in the circuit, and directed edges E in the directed graph G contain all the connections in the circuit.

[0021] In this invention, the approximate hardening process uses the improved second-generation non-dominated sorting genetic algorithm NSGA-II as a multi-objective optimization algorithm, which interacts with the circuit performance evaluator modeled in software to perform multi-objective optimization on the area, power consumption, and soft error rate of the hardened circuit, obtaining a Pareto solution set, and selecting the optimal next-generation parent set from it; the actual multi-objective optimization problem is written as:

[0022]

[0023] Where G is the directed acyclic graph representation of the hardened circuit.

[0024] In this invention, during the approximate hardening process, the improved NSGA-II employs a polarity expansion mechanism before the mutation stage. By analyzing the polarity of each gate unit through reverse traversal circuitry, it identifies and replaces bidirectional gate units with corresponding unidirectional gate units in a pre-established approximation library, thereby expanding the optimizable space and reducing the risk of local convergence of NSGA-II.

[0025] In this invention, the approximate reinforcement process defines a bidirectional gate unit as a gate unit containing multiple paths of opposite polarity, which prevents its fan-in gate unit from approximating.

[0026] In this invention, the improved NSGA-II during the approximate hardening process employs a dynamic probability adjustment mechanism. Before creating offspring at a specified iteration cycle, the mutation probability of each circuit and gate unit is dynamically adjusted through testability analysis, improving the efficiency of multi-objective optimization. Approximately low testability gate units have a lower impact on circuit accuracy, i.e., soft error rate. Increasing their mutation probability helps promote multi-objective optimization methods to explore hardened circuits with lower hardware losses at the cost of minimal soft error rate sacrifice, thus optimizing the convergence efficiency and quality of NSGA-II. Specifically, the following steps are included:

[0027] (1) Perform a breadth-first search by traversing the directed acyclic graph of the circuit to be reinforced, starting from the input port and ending at the output port, to calculate the controllability of each gate unit, i.e., the probability that the output of the gate unit is a specified logic value, denoted as P. ctrl (g i =v i ), where P ctrl G represents the probability of controllability. i v represents the i-th logic gate unit. i Represents the specified logical value, either 0 or 1;

[0028] (2) Perform a breadth-first search by traversing the directed acyclic graph of the circuit to be reinforced in reverse order. Starting from the output port and ending at the input port, calculate the observability of each gate cell, i.e., the probability that the output of the gate cell can propagate to the main output port of the circuit, denoted as P. obv (g i ), where P obv G represents the observability probability. i This represents the i-th logic gate unit;

[0029] (3) Traverse the directed acyclic graph of the circuit to be hardened again, and estimate the testability probability of each gate unit by the product of the controllability probability and the observability probability under the signal independence assumption, denoted as P. test (g i =v i ):

[0030]

[0031] (4) Adjust the approximate mutation probability of each gate unit according to the measurability probability, denoted as

[0032]

[0033] in, This indicates that the i-th gate cell has a stuck-at-f fault, i.e., 0-blocking and 1-blocking, representing downward approximation and upward approximation, respectively; α is a very small constant to ensure that the denominator is not zero; β is a scaling factor to control the sensitivity of the mutation probability to the measurability probability;

[0034] (5) When generating offspring, the improved NSGA-II selects gate units for approximation based on the dynamically adjusted mutation probability and replaces them with approximation gate units in the pre-established approximation library.

[0035] Compared with existing circuit optimization and hardening technologies, the advantages of this invention are reflected in three aspects:

[0036] First, high efficiency. This invention performs fine-grained gate-level approximation replacement of circuits based on a pre-established approximation library, without operating on the entire circuit. Compared with existing approximation methods such as Boolean decomposition algorithm and Karnaugh map modification method, the computational complexity is reduced by orders of magnitude, and the solution process is more efficient and convenient. This makes this invention applicable to multi-objective optimization and soft error hardening design of large-scale circuits.

[0037] Second, practicality. This invention adopts an approximate hardening mode, and achieves a trade-off between hardening circuit area, power consumption and soft error rate through multi-objective optimization. Compared with traditional high-cost hardening structures such as triple-modular redundancy (TMR), this invention significantly reduces hardware losses while ensuring high reliability. It is suitable for cost-critical fields such as currently popular commercial aerospace satellites and intelligent driving.

[0038] Third, versatility. This invention can provide a flexible and universal approximate hardening scheme, which is not limited to the application of approximate basic hardening structures. It can be used to optimize the soft error-tolerant redundancy hardening of various high reliability structures such as triple modal redundancy (TMR). Compared with existing circuit optimization and hardening technologies, this invention can adapt to circuit designs with multiple scenarios and requirements. Attached Figure Description

[0039] Figure 1 This is a flowchart of the multi-objective optimization soft error hardening method based on an approximate gate unit library and dynamically adjusted NSGA-II as described in this invention.

[0040] Figure 2 A schematic diagram showing the structural and hardware loss optimization of TMR and ATMR.

[0041] Figure 3 This refers to the approximation library information obtained during the process of establishing an approximation library for the circuit to be hardened, using the C880 circuit as the reference.

[0042] Figure 4 This is an example of the operation of polar expansion during the approximate reinforcement process of the present invention.

[0043] Figure 5This is an example of the operation of dynamic probability adjustment during the approximate reinforcement process of the present invention.

[0044] Figure 6 This is a dynamic probability adjustment table using a three-gate circuit as an example.

[0045] Figure 7 This is the final Pareto hardening scheme output after the C880 circuit is approximated and hardened by this invention. Detailed Implementation

[0046] The present invention is described in further detail below with reference to the examples.

[0047] Example 1

[0048] A low-cost soft error hardening method based on approximate triple-modular redundancy units includes three processes, such as... Figure 1 As shown, these represent the approximate library creation process, the software modeling process, and the approximate hardening process, respectively.

[0049] In this embodiment, the multi-objective optimization method is implemented using Python. The circuit to be approximated and hardened is the c880 circuit in LGSynh93Benchmark. The basic hardening structure for approximation is selected as a highly reliable triple-modular redundancy hardening. Its circuit structure and approximation optimization are as follows: Figure 2 As shown. The basic information of the circuit was obtained based on a 28-nm CMOS bulk silicon process.

[0050] In this embodiment, the process of establishing the approximation library specifically includes the following steps:

[0051] (1) Based on the C880 circuit netlist, the entire circuit is traversed and scanned to obtain the set of gate units in the circuit to be reinforced, including one-input NOT gate, two-input AND gate, two-input OR gate, two-input NAND gate, two-input NOR gate, three-input AND gate, three-input NAND gate, four-input NAND gate, and buffer.

[0052] (2) By using Boolean decomposition, the downward approximation version and the upward approximation version of each gate unit in the gate unit set are obtained. The partial approximation library files for the C880 circuit are as follows: Figure 3 As shown;

[0053] (3) The obtained approximate gate units are combined into a downward approximate gate unit library and an upward approximate gate unit library, and the downward approximate version and upward approximate version of the approximate gate unit are obtained again by Boolean decomposition, and the approximate library is updated.

[0054] (4) By iterating in this way, a complete and closed-loop approximate gate unit library is obtained;

[0055] (5) The approximation library creation process is complete. This process uses the Boolean decomposition algorithm to create upward and downward approximation version libraries for each standard logic gate unit in the C880 circuit, which is beneficial for agile approximation hardening in the subsequent multi-objective optimization process.

[0056] In this embodiment, the software modeling process of the circuit is as follows:

[0057] (1) Information Acquisition. The basic information such as area and power consumption of all standard gate cells and approximate gate cells involved in the pre-established approximation library of the c880 circuit is obtained by using the Design Compiler tool.

[0058] (2) Hardware loss assessment algorithm simulation. Based on the gate cell area and power consumption information obtained during the information acquisition process, classes of gate cells, circuit modules, and triple redundancy architecture are constructed using Python. The total area and power consumption information of the input circuit netlist are estimated by summation, which can be approximated by the number of transistors.

[0059] (3) Simulation of the soft error physical propagation model algorithm. Python is used to construct the gate unit, circuit module, and triple-modular redundancy architecture classes and internal signal transmission models. By randomly flipping the output of any gate unit in any circuit module of the triple-modular redundancy architecture under a random input vector, the single-event transient soft error effect under a high-energy particle injection scenario is simulated. The soft error rate of the hardened architecture is estimated by using large-scale flip statistics determined by the number of input ports. In this example, the number of random input vectors for the C880 circuit is set to 2. 14 The number of flips for each input vector is set to 2. 6 .

[0060] (4) The software modeling process is completed. Based on the basic information such as the area and power consumption of each gate unit in the circuit to be hardened and the approximate gate units in the approximation library, this process constructs a hardware loss estimator and a soft error rate estimator based on the soft error physical propagation model through Python code. This is beneficial for the efficient evaluation of specific hardened individuals in the subsequent multi-objective optimization process and is easier to interact with compared to using tools such as Design Compiler.

[0061] In this embodiment, the approximate circuit hardening process specifically includes the following steps:

[0062] (1) Circuit diagram encoding. The circuit to be reinforced is encoded as a directed acyclic graph G =<V,E> In a directed graph G, vertices V contain the input and output terminals of the circuit and all logic gates. Directed edges E in G contain all connections in the circuit. The C880 circuit has 469 vertices and 357 directed edges.

[0063] (2) Population Initialization. This method employs an improved dynamic adjustment NSGA-II to achieve multi-objective optimization. First, based on the approximation library, the initial circuit undergoes random mutation and crossover to generate the initial population. In this embodiment, mutation refers to selecting approximate gate units from the pre-established approximation library for approximate replacement, and crossover refers to swapping the downward and upward approximation modules of two approximate triple-redundancy hardened circuits. In this embodiment, the initial population size is set to 200.

[0064] (3) Performance evaluation. The area, power consumption and soft error rate of each approximate triple-redundant hardened circuit are estimated using a Python simulator built based on the software modeling process, which is beneficial for subsequent multi-objective optimization.

[0065] (4) Multi-objective optimization solution. A multi-objective optimization algorithm is used to solve the above three performance indicators. In this embodiment, the actual multi-objective optimization problem can be written as:

[0066]

[0067] Wherein, G is the directed acyclic graph representation of each approximate triple-modular redundancy hardened circuit.

[0068] In this embodiment, the improved dynamic adjustment second-generation non-dominated sorting genetic algorithm (NSGA-II) is selected to perform multi-objective optimization for area, power consumption, and soft error rate, and obtain Pareto solution set. The next generation parent set is selected through elitist strategy.

[0069] (5) Polarity Expansion. The improved dynamically adjusted NSGA-II performs polarity analysis on the approximate triple-modular redundancy hardened circuit before the evolutionary operation, directionally detecting bidirectional gate units and replacing them with corresponding unidirectional gate units stored in a pre-established approximation library. In this embodiment, a bidirectional gate unit refers to a gate unit containing multiple opposite polarity paths internally, hindering its fan-in gate unit approximation. This process is called polarity expansion, and its schematic diagram is shown below. Figure 4 As shown, this helps to expand the multi-objective optimization space and reduce the risk of local convergence of NSGA-II due to the limited solution space.

[0070] (6) Dynamic probability adjustment.

[0071] The improved dynamically adjusted NSGA-II dynamically adjusts the mutation probability of each gate cell—namely, the upward approximation probability and the downward approximation probability—based on testability analysis before performing abrupt operations on the approximate triple modulo redundancy hardened circuit. Gate cells with lower testability result in a smaller decrease in accuracy of the circuit's main output during approximation; that is, while reducing hardware losses, they also minimize the increase in the soft error rate of the approximate triple modulo redundancy hardened circuit, making them more suitable for hardening. Therefore, gate cells with lower testability have a higher mutation probability. The specific calculation steps are as follows, illustrated in the diagram. Figure 5 As shown:

[0072] ① Perform a breadth-first search on the directed acyclic graph of the circuit to be reinforced, starting from the input port and ending at the output port, to calculate the controllability of each gate cell, i.e., the probability that the output of the gate cell is a specified logic value, denoted as P. ctrl (g i =v i ), where P ctrl G represents the probability of controllability. i v represents the i-th logic gate unit. i Represents the specified logical value, either 0 or 1;

[0073] ② Perform a breadth-first search on the directed acyclic graph of the circuit to be reinforced, starting from the output port and ending at the input port. Calculate the observability of each gate cell, i.e., the probability that the output of that gate cell can propagate to the main output port of the circuit, denoted as P. obv (g i ), where P obv G represents the observability probability. i This represents the i-th logic gate unit;

[0074] ③ Traverse the directed acyclic graph of the circuit to be hardened again, and estimate the testability probability of each gate unit by multiplying the controllability probability and the observability probability under the signal independence assumption. This probability is denoted as P. test (g i =v i ):

[0075]

[0076] ④ The dynamic adjustment formula for the approximate mutation probability of each gate unit is denoted as follows:

[0077]

[0078] in, The α represents a stuck-at-f fault in the i-th gate unit, i.e., 0-blocking and 1-blocking, representing downward approximation and upward approximation, respectively; α is a very small constant to ensure the denominator is not zero; β is a scaling factor to control the sensitivity of the mutation probability to the measurability probability; in this embodiment, β is set to 1 and α is set to 0.001. To illustrate the calculation process and results, a three-gate circuit and its dynamic probability adjustment table are shown below. Figure 6 As shown.

[0079] (8) The optimization and hardening process ends. The improved dynamic adjustment NSGA-II is iterated multiple times until the stopping condition is met, resulting in the final Pareto solution set. The output Pareto solution set is a directed acyclic graph representation of each approximate triple-modulus hardened circuit. After being converted into a Verilog netlist by software, the final approximate hardening scheme can be output. Designers can select the set of approximate hardening schemes that best suit the area, power consumption, and soft error rate indicators according to the actual needs of the circuit design, thereby optimizing the circuit hardening design. Figure 7 The document lists the Pareto solution set finally given by the c880 circuit in the embodiments of the present invention. Each solution set is an approximate triple modal redundancy hardening scheme. Figure 7 The Chinese Communist Party (CCP) lists 10 circuits, with the initial circuit being an unhardened C880 circuit, serving as a normalized standard value for area, power consumption, and soft error rate. ATMR1 to ATMR8 represent the Pareto solution set of approximately triple-modular redundancy (TMR) hardened circuits. For example, ATMR4 exhibits a 72.8% reduction in soft error rate compared to the unhardened circuit, while only increasing additional area and power consumption by 93.2% and 95.4%, respectively. This is half that of the traditional TMR, achieving low-cost, high-reliability hardening. Designers can select the most suitable replacement scheme based on their actual needs. Therefore, this invention can effectively guide designers in designing soft error-tolerant hardened circuits. Compared to existing circuit redundancy hardening methods, it can efficiently solve large-scale circuit hardening problems, is applicable to the approximate hardening of various high-reliability structures, and is more suitable for cost-critical applications such as commercial aerospace satellites and autonomous driving.

Claims

1. A low-cost soft error hardening method based on approximately triple-modular redundancy units, characterized in that, It includes three processes: Approximate library establishment, software modeling, and approximate hardening; among which: Approximation library establishment process: Based on the Karnaugh map modification method, construct corresponding approximation gate units for the basic gate units of the circuit to be hardened, and establish an overall approximation gate unit library; Software modeling process: Obtain basic information on the area and power consumption of each standard gate unit in the circuit, and perform software modeling to evaluate the area, power consumption, and soft error rate of the circuit based on the physical model of soft error propagation, and build an easy-to-interact circuit performance evaluator. Approximate hardening process: Based on the improved NSGA-II semi-directional selection, the gate cells in the circuit to be hardened are replaced with approximate gate cells in the pre-established approximation library. The performance index of the approximate hardened circuit is simulated by the circuit performance evaluator, and multi-objective optimization is performed. After iteration, the optimal trade-off between area, power consumption and soft error rate is obtained. Two redundant modules in the traditional triple-modular redundancy hardened circuit are replaced with approximate modules. The final set of approximate hardening schemes is given, which achieves the lowest possible area and power consumption hardware loss while ensuring high reliability hardening.

2. The low-cost soft error hardening method based on approximately triple-modular redundancy units according to claim 1, characterized in that, The approximation library creation process specifically includes the following steps: (1) Based on the initial circuit netlist, the entire circuit is traversed and scanned to obtain the set of gate units in the circuit to be strengthened; (2) By using Boolean decomposition, the downward approximation version and the upward approximation version of each gate unit in the gate unit set are obtained; (3) The obtained approximate gate units are combined into a downward approximate gate unit library and an upward approximate gate unit library, and the downward approximate version and the upward approximate version of the approximate gate unit are obtained again by Boolean decomposition. (4) By iterating in this way, a complete and closed-loop approximate gate unit library is obtained; (5) The process of establishing the approximate library is complete.

3. The low-cost soft error hardening method based on approximately triple-modular redundancy units according to claim 1, characterized in that, The software modeling process involves logically synthesizing the circuit file and extracting the area and power consumption information of each standard gate unit.

4. The low-cost soft error hardening method based on approximately triple-modular redundancy units according to claim 1, characterized in that, The software modeling process described above is based on the physical propagation model of soft errors in the circuit and the standard cell area and power consumption information extracted by logic synthesis. A customized estimator written in Python simulates the area and power consumption of the overall circuit and estimates the soft error rate of each hardened circuit.

5. The low-cost soft error hardening method based on approximately triple-modular redundancy units according to claim 1, characterized in that, The approximate hardening process described above treats the hardening circuit as a directed acyclic graph G =<V,E> In a directed graph G, vertices V contain the input and output terminals of the circuit and all logic gate units in the circuit, and directed edges E in the directed graph G contain all the connections in the circuit.

6. The low-cost soft error hardening method based on approximately triple-modular redundancy units according to claim 1, characterized in that, In the approximate hardening process, the improved second-generation non-dominated sorting genetic algorithm NSGA-II is used as a multi-objective optimization algorithm. It interacts with the circuit performance evaluator modeled in software to perform multi-objective optimization on the area, power, and soft error rate (SER) of the hardened circuit, obtaining a Pareto solution set, from which the optimal next-generation parent set is selected. The actual multi-objective optimization problem is written as: Where G is the directed acyclic graph representation of the hardened circuit.

7. The low-cost soft error hardening method based on approximately triple-modular redundancy units according to claim 1, characterized in that, The aforementioned approximate hardening process involves the improved NSGA-II employing a polarity expansion mechanism. This mechanism analyzes the polarity of each gate unit through a reverse traversal circuit, identifying and replacing bidirectional gate units with corresponding unidirectional gate units from a pre-established approximation library. This expands the optimizable space and reduces the risk of local convergence in NSGA-II.

8. The low-cost soft error hardening method based on approximately triple-modular redundancy units according to claim 1, characterized in that, In the aforementioned optimization and reinforcement process, a bidirectional gate unit is defined as a gate unit containing multiple paths of opposite polarity, which prevents it from approximating the gate unit.

9. The low-cost soft error hardening method based on approximately triple-modular redundancy units according to claim 1, characterized in that, The aforementioned approximate hardening process, the improved NSGA-II employs a dynamic probability adjustment mechanism. This mechanism estimates and dynamically adjusts the mutation probability of each gate element and each approximate version in the approximation library selected by NSGA-II based on measurability analysis; specifically, it includes the following steps: (1) Perform a breadth-first search by traversing the directed acyclic graph of the circuit to be reinforced, starting from the input port and ending at the output port, to calculate the controllability of each gate unit, i.e., the probability that the output of the gate unit is a specified logic value, denoted as P. ctrl (g i =v i ); where P ctrl G represents the probability of controllability. i v represents the i-th logic gate unit. i Represents the specified logical value, either 0 or 1; (2) Perform a breadth-first search by traversing the directed acyclic graph of the circuit to be reinforced in reverse order. Starting from the output port and ending at the input port, calculate the observability of each gate cell, i.e., the probability that the output of the gate cell can propagate to the main output port of the circuit, denoted as P. obv (g i ), where P obv G represents the observability probability. i This represents the i-th logic gate unit; (3) Traverse the directed acyclic graph of the circuit to be hardened again, and estimate the testability probability of each gate unit by the product of the controllability probability and the observability probability under the signal independence assumption, denoted as P. test (g i =v i ): (4) Adjust the approximate mutation probability of each gate unit according to the measurability probability, denoted as in, This indicates that the i-th gate cell has a stuck-at-f fault, i.e., 0-blocking and 1-blocking, representing downward approximation and upward approximation, respectively; α is a very small constant to ensure that the denominator is not zero; β is a scaling factor to control the sensitivity of the mutation probability to the measurability probability; (5) When generating offspring, the improved NSGA-II selects gate units for approximation based on the dynamically adjusted mutation probability and replaces them with approximation gate units in the pre-established approximation library.

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