Multi-chip parallel module packaging method based on multi-objective optimization

Abstract

The invention provides a multi-chip parallel module packaging method based on multi-objective optimization, and the method comprises the steps: constructing a multi-chip parallel module packaging structure, and extracting feature geometric parameters based on the packaging structure; constructing a multi-objective optimization function based on the characteristic geometric parameters and the corresponding performance parameters; and solving the multi-objective optimization function through an improved genetic algorithm, and obtaining a leading-edge solution. And finally, correcting the multi-chip parallel module packaging structure through a leading edge solution. According to the method, the multi-objective optimization function containing the characteristic geometric parameters and the corresponding performance parameters is constructed, the improved genetic algorithm is combined for solving, the leading-edge solution of the key parameters in the multi-chip parallel design is obtained, software does not need to be used for simulation fitting, parameterization simulation time is shortened, the overall efficiency is improved, and the method is suitable for large-scale popularization and application. And guidance can be provided for the packaging design of the multi-chip parallel power module.

Description

Technical Field

[0001] This invention relates to the field of electronic power device technology, and more specifically to a multi-chip parallel module packaging method based on multi-objective optimization. Background Technology

[0002] Silicon carbide (SiC) power modules have garnered significant attention and widespread application in fields such as electric vehicles and new energy power generation due to their fast switching performance, low on-resistance, and high stability. However, the manufacturing process for SiC power modules is still immature, resulting in a low yield rate for SiC wafers, which typically limits the rated current of SiC chips to less than 150A. Therefore, in current technologies, SiC power modules often employ a parallel connection of multiple chips to meet high current requirements. However, most current SiC power module packaging designs directly adopt silicon-based module packaging designs, failing to fully leverage the advantages of SiC devices, and the packaging design system for power modules remains imperfect.

[0003] Furthermore, in terms of power module packaging optimization design, existing research mainly focuses on reducing parasitic inductance, reducing thermal resistance, and increasing module power density. Reducing parasitic inductance can be approached from aspects such as bonding wires and loop layout: for example, replacing traditional aluminum wiring with copper electrical connectors can effectively eliminate significant parasitic inductance from the perspective of matching thermal expansion coefficients; in terms of loop optimization, optimizing the layout of direct copper-clad laminates to reduce loop area, utilizing the principle of magnetic circuit cancellation, and employing wide busbars can all reduce packaging parasitic parameters. Packaging thermal resistance is mainly determined by the heat conduction path. Since there are usually more than one chip inside the module, i.e., multiple heat sources, and these heat sources are all soldered on the same substrate, sharing thermal paths, thermal coupling issues must also be considered. Therefore, thermal resistance can be reduced by optimizing packaging materials and packaging structure. In the Cauer thermal network model, the thermal resistance of the solder layer, ceramic layer, and heat dissipation substrate layer accounts for a large proportion of the total thermal resistance. Therefore, high thermal conductivity ceramic materials, such as AlN or Si3N4, can be used to replace traditional Al2O3. Additionally, nano-silver sintering technology can be considered to replace traditional soldering. Improving power density mainly involves reducing module size. To comprehensively consider the interrelationships among these aspects, a multiphysics-based design of the power module is necessary.

[0004] In existing technologies, there are also power module packaging design methods based on intelligent algorithms. The objective function in these algorithms is generally obtained through simulation fitting. However, performing a large number of simulations consumes excessive resources, and the simulation time is long and the cost is high. In addition, some power module packaging designs only consider single-chip models and do not consider the parallel connection of multiple chips. Since the current carrying capacity of a single silicon carbide MOSFET chip is limited, the rated current is generally less than 150A. In order to meet the requirements of high current levels, multiple chips need to be connected in parallel. Therefore, the existing single-chip models cannot be used to guide the design of power modules.

[0005] In summary, a method is needed to quickly guide the design of packaging structures, thereby solving the multi-chip parallel multi-objective optimization problem, while reducing parametric simulation time and lowering overall costs. Summary of the Invention

[0006] This invention addresses the problems existing in the prior art by providing a multi-objective optimization packaging structure design method. By improving the genetic algorithm, the design parameters can be solved quickly, thereby achieving the goal of reducing costs and increasing efficiency.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] This invention provides a multi-chip parallel module packaging method based on multi-objective optimization, which includes the following steps:

[0009] Construct a multi-chip parallel module packaging structure;

[0010] Based on the multi-chip parallel module packaging structure, the characteristic geometric parameters of the packaging structure are extracted;

[0011] Based on the aforementioned feature geometric parameters and corresponding performance parameters, a multi-objective optimization function is constructed;

[0012] The multi-objective optimization function is solved by an improved genetic algorithm, and the frontier solution is obtained.

[0013] The multi-chip parallel module packaging structure is corrected by the aforementioned leading edge solution.

[0014] Optionally, the multi-chip parallel module packaging structure includes a chip, a substrate, electrical connectors, and a heat dissipation component;

[0015] The characteristic geometric parameters include chip geometric parameters, chip spacing, electrical connector geometric parameters, substrate geometric parameters, and heat dissipation component geometric parameters.

[0016] Optionally, the performance parameters include parasitic inductance parameters, thermal resistance parameters, and module area parameters;

[0017] The objective function corresponding to the parasitic inductance parameter is to minimize the parasitic inductance;

[0018] The objective function corresponding to the thermal resistance parameter is to minimize the total thermal resistance;

[0019] The objective function corresponding to the module area parameter is to minimize the total area of ​​the module.

[0020] Optionally, constructing the objective function corresponding to the parasitic inductance parameters includes the following steps:

[0021] Construct the expression for the parasitic inductance of the power source in each chip branch;

[0022] An initial objective function is established with the goal of minimizing the difference in parasitic inductance of the power source between different branches;

[0023] Based on the analysis of thin copper sheet inductance, the initial objective function is transformed into the objective function of parasitic inductance.

[0024] Optionally, constructing the objective function corresponding to the thermal resistance parameter includes the following steps:

[0025] Calculate the self-thermal resistance from the chip to the substrate, where the self-thermal resistance is the sum of the thermal conduction resistances of each layer, plus the convective heat transfer resistance.

[0026] The mutual thermal resistance between adjacent chips is calculated based on the coupling area between the chips, the effective convection heat transfer area, and the convection heat transfer thermal resistance.

[0027] The objective function of total thermal resistance is obtained by superimposing the self-thermal resistance and the mutual thermal resistance.

[0028] Optionally, constructing the objective function corresponding to the module area parameter includes the following steps:

[0029] Calculate the area of ​​each module partition separately; the area of ​​each module partition includes: the area occupied by the chip, the area occupied by the chip spacing, the area occupied by the electrical connection layout, and the area occupied by the heat dissipation components.

[0030] Based on the area of ​​the module partitions, the objective function for the total area of ​​the module is obtained by summation.

[0031] Optionally, in constructing the multi-objective optimization function, the feature geometric parameters are screened based on the multi-chip parallel module packaging structure and packaging process, and the function independent variables are obtained;

[0032] Set constraints or constraint ranges for each function's independent variable.

[0033] Optionally, the improved genetic algorithm is a fast non-dominated sorting genetic algorithm, and the front solution is a Pareto front solution;

[0034] The improved genetic algorithm for solving the multi-objective optimization function includes the following steps:

[0035] Based on the multi-objective optimization function, the improved genetic algorithm is initialized, and an initial population is obtained;

[0036] The objective optimization function of each individual in the initial population is evaluated to obtain the evaluation results;

[0037] Individuals are ranked according to Pareto based on the assessment results;

[0038] Individuals are subjected to recombination, crossover, and mutation operations to obtain a new population; the new population is iteratively calculated, and the frontier solution is obtained when the stopping condition is met.

[0039] Optionally, during the initialization of the improved genetic algorithm, the initial population size is 500, the maximum number of iterations is 5000, and the coefficient of the optimal frontier individual ranges from 0 to 1.

[0040] Optionally, the optimal frontier individual coefficient is 0.3.

[0041] Compared with the prior art, the present invention has the following beneficial effects:

[0042] This invention constructs a multi-objective optimization function containing characteristic geometric parameters and corresponding performance parameters, and solves it using an improved genetic algorithm to obtain the leading edge solution of key parameters in multi-chip parallel design. This eliminates the need for software simulation fitting, reduces parameterized simulation time, improves overall efficiency, and provides guidance for the packaging design of multi-chip parallel power modules. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a flowchart of the method in a specific embodiment of the present invention;

[0045] Figure 2 This is a flowchart of the improved genetic algorithm solution in a specific embodiment of the present invention;

[0046] Figure 3 This is a top view of the power module interior and a schematic diagram of the location of the parasitic inductor at the power source in a specific embodiment of the present invention;

[0047] Figure 4 This is a schematic diagram of the principle of the dual-pulse test circuit corresponding to the three parallel chips inside the power module in a specific embodiment of the present invention;

[0048] Figure 5 This is a simplified cross-sectional view of the power module in a specific embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram of the thermal resistance coupling area between adjacent chips in a specific embodiment of the present invention;

[0050] Figure 7 This is a schematic diagram of the area corresponding to the power density in a specific embodiment of the present invention;

[0051] Figure 8 This is a schematic diagram of multi-objective optimization independent variables in a specific embodiment of the present invention;

[0052] Figure 9 This is a three-dimensional diagram of the Pareto front solution for multi-objective optimization of the power module package in a specific embodiment of the present invention.

[0053] In the diagram: 1. Module DBC ceramic layer, 2. Module power source copper plating, 3. Module drain copper plating, 4. Module gate copper plating, 5. Module Kelvin source copper plating, 6. Silicon carbide MOSFET chip, 7. Gate resistor, 8. Module power source bonding wire, 9. Module Kelvin source bonding wire, 10. Module gate bonding wire, 11. Kelvin source terminal mounting position, 12. Gate terminal mounting position, 13. Drain power terminal mounting position, 14. Source power terminal mounting position, 15. Chip solder layer, 16. Module DBC undercopper layer, 17. Module DBC solder layer, 18. Module heat dissipation substrate. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0056] It is worth noting that, unless otherwise specified, the methods used in this invention are all conventional methods; and the raw materials and equipment used are all conventional commercially available products, and their sources are not specifically limited.

[0057] It should also be noted that, for ease of understanding, the method steps in the specific embodiments of the present invention are described in a certain order, but those skilled in the art can change the order of the steps according to actual needs, so this should not be used as a limiting condition; further, in the description of the following specific embodiments, the superscripts and subscripts of each parameter should be understood as distinguishing marks of similar identifiers in accordance with common interpretations, representing parameters of the related or corresponding devices, and should not be understood as specific models or special marks.

[0058] like Figure 1 As shown in the figure, this application provides a multi-chip parallel module packaging method based on multi-objective optimization, which mainly includes the following steps:

[0059] First, a multi-chip parallel module packaging structure is pre-constructed based on the work objectives and design specifications. This embodiment specifically uses... Figure 3 and Figure 5 The structure shown is illustrated as an example. Specifically, this structure includes multiple silicon carbide MOSFET chips 6, which serve as the core power devices, enabling efficient power conversion. The substrate 18 typically uses materials with good thermal conductivity and electrical insulation properties, such as a direct-bonded copper (DBC) substrate. A DBC substrate generally consists of a ceramic layer sandwiched between two copper layers. The upper copper layer is used for chip mounting and electrical connections, while the lower copper layer can be tightly bonded to the heat dissipation components for efficient heat dissipation. Electrical connectors include module power source bonding wires 8, module Kelvin source bonding wires 9, module gate bonding wires 10, etc., as well as drain power terminal mounting positions 13, source power terminal mounting positions 14, gate terminal mounting positions 12, and Kelvin source terminal mounting positions 11. Bonding wires typically use high-purity metal wires, such as gold wires, and employ processes like ultrasonic bonding to achieve electrical connections between chip electrodes and the substrate or pins. Terminals serve as interfaces connecting the module to external circuits; their materials are mostly metals with good conductivity and mechanical strength, such as copper alloys. The design must consider factors such as terminal spacing and shape to meet electrical performance and installation requirements. Heat dissipation components generally use heat sinks, water-cooled plates, etc., which, through close contact with the substrate, rapidly dissipate the heat generated by the chip, maintaining the module's normal operating temperature.

[0060] Therefore, based on the aforementioned pre-designed packaging structure, its characteristic geometric parameters are extracted. These parameters include chip geometry, chip spacing, electrical connector geometry, substrate geometry, and heat dissipation component geometry. Specifically, chip geometry encompasses the chip's length, width, and thickness, which determine its physical size and integration density. For example, common silicon carbide MOSFET chips may range in size from a few square millimeters to tens of square millimeters, with a thickness of several hundred micrometers. Chip spacing refers to the distance between adjacent chips, and its size affects electrical performance and module power density. It is generally determined based on chip heat generation and current conduction requirements, and may range from a few tenths of a millimeter to several millimeters. Regarding electrical connector geometry, the diameter and length of the bonding wires, and the length, diameter, and spacing of the terminals (pins) are all crucial.

[0061] Furthermore, a multi-objective optimization function is constructed based on the characteristic geometric parameters and their corresponding performance parameters. The performance parameters include parasitic inductance, thermal resistance, and module area. The objective function for the parasitic inductance parameter is to minimize the parasitic inductance; the objective function for the thermal resistance parameter is to minimize the total thermal resistance; and the objective function for the module area parameter is to minimize the total module area. Even further, during the construction of the multi-objective optimization function, the characteristic geometric parameters are screened based on the multi-chip parallel module packaging structure and packaging technology to obtain the function's independent variables. Therefore, the construction process of the multi-objective optimization function in this embodiment is as follows:

[0062] (1) Parasitic inductance parameters:

[0063] When constructing the objective function corresponding to the parasitic inductance parameters, the expression for the parasitic inductance of the power source of each chip branch is constructed, and the initial objective function is established with the goal of minimizing the difference in parasitic inductance of the power source between different branches; based on the analysis of thin copper sheet inductance, the initial objective function is transformed into the parasitic inductance objective function.

[0064] Therefore, the self-inductance of the connecting wires (such as bonding wires) between the parallel module chips must first be calculated. Specifically, in this embodiment... Figure 3 This is a top view of the power module and a schematic diagram of the location of the parasitic inductor at the power source. The top view of this module is an example, consisting of 6 silicon carbide MOSFET chips connected in parallel. Specific modules can be constructed using multiple chips connected in parallel depending on the actual current required. The layout is symmetrical from left to right; therefore, subsequent analysis will focus only on the left side. Figure 3 The positions of the parasitic inductors at the power sources on the left correspond one-to-one with the parasitic inductors of the same name. Points 1, 2, 3, and 0 are potential points. Since the parasitic inductance at the power sources has a significant impact on dynamic current imbalance, this embodiment uses minimizing the difference in parasitic inductance between different branches as the first objective function of multi-objective optimization. For example, Figure 4As shown, this is a schematic diagram of the parallel connection of three chips inside the power module corresponding to the dual-pulse test circuit in this embodiment. DC This is a DC voltage source used to power the power circuit of the power module; C DC The busbar capacitor is used to maintain DC voltage stability; L is the load inductance; D is the anti-parallel diode, which provides freewheeling when the silicon carbide MOSFET chip 6 is turned off; Q1 to Q3 are silicon carbide MOSFET chips 6; L g L is the gate stray inductance. d1 L is the stray inductance on the drain side between drain power terminal mounting position 13 and Q1. d2 L is the stray inductance between the drain-side branches of Q1 and Q2. d3 For the stray inductance between the drain-side branches of Q2 and Q3, L bs1 For the module power source bonding wire 8 stray inductor of Q1, L bs2 For the module power source bonding wire 8 stray inductor of Q2, L bs3 For the Q3 module power source bonding wire 8 stray inductor, L cs L is the source-side stray inductance between Q1 and source power terminal mounting position 14. cs1 For the stray inductance between the source-side branches of Q1 and Q2, L cs2 For the stray inductance between the source-side branches of Q2 and Q3, i d1 For the current flowing through Q1, i d2 For the current flowing through Q2, i d3 U represents the current flowing through Q3. drive R is the gate drive power supply used to power the drive circuit. g This is the gate drive resistor.

[0065] The specific solution process is as follows:

[0066] The drain current i flowing through Q1 to Q3 d It can be represented by the following expression:

[0067]

[0068] In the formula, g fs For the transconductance of a silicon carbide MOSFET, v gs V is the gate-source voltage. th Since the threshold voltage is taken into account, and the parameter differences between chips are not considered, it is assumed that the transconductance and threshold voltage of the chips are equal.

[0069] Furthermore, v gs It can be written as the following expression:

[0070]

[0071] In the formula, vg V is the gate voltage. 1O v 2O v 3O These are the power source voltages for branches Q1, Q2, and Q3, respectively, and the gate voltages of the chip are considered to be equal.

[0072] Among them, and v 1O v 2O v 3O The expression is as follows:

[0073]

[0074] In the formula, △L s1 The power source parasitic inductance of branch Q1 is denoted as ΔL. s2 The power source parasitic inductance of branch Q2 is denoted as ΔL. s3 This is denoted as the power source parasitic inductance of branch Q3. d1 / dt is i d1 The rate of change of dynamic current, di d2 / dt is i d2 The rate of change of dynamic current, di d3 / dt is i d3 The three dynamic current change rates are considered to be consistent in this embodiment. That is:

[0075]

[0076] Therefore, the objective function expression for minimizing the difference in parasitic inductance of power sources between different branches is:

[0077] min(|ΔL s1 -ΔL s2 |+|ΔL s2 -ΔL s3 |+|ΔL s3 -ΔL s1 |);

[0078] The parasitic inductance of the power source of the branch can be expressed as:

[0079]

[0080] Furthermore, since the stray inductance of the module's power source bonding wire can be considered uniform, i.e., L bs1 =L bs2 =L bs3 =L bs Therefore, the objective function can be further simplified, resulting in the following expression for the initial objective function:

[0081] min(2L cs1 +L cs2 );

[0082] Furthermore, in the analysis of thin copper sheet inductors, the analytical expression for the inductance is as follows:

[0083]

[0084] In the formula, μ0 is the free permeability, which has a value of 4π*10 -7 H / m, where l is the length of the thin copper sheet and w is the width of the thin copper sheet.

[0085] Therefore, in the multi-objective optimization of this embodiment, the initial objective function, after further analysis, yields the objective function for current balance, which is as follows:

[0086]

[0087] In the formula, l1, l2, and l3 are the copper pour lengths of different segments related to the source circuit in the module, and w1 is the width of the corresponding copper pour.

[0088] (2) Thermal resistance parameters:

[0089] In this embodiment, the total thermal resistance is divided into two parts: the self-thermal resistance from the chip to the substrate is calculated, which is the sum of the thermal conduction resistances of each layer, plus the convective heat transfer resistance; the mutual thermal resistance between adjacent chips is calculated, based on the coupling area between chips, the effective convective heat transfer area, and the convective heat transfer resistance. By superimposing the self-thermal resistance and the mutual thermal resistance, the objective function of the total thermal resistance can be obtained.

[0090] Specifically, in the self-heating resistance section, such as Figure 5 The simplified cross-sectional view of the power module shown indicates that the module can be approximately divided into 7 layers for analysis. From top to bottom, these layers are: silicon carbide MOSFET chip 6, chip solder layer 15, module drain copper plating 3, module DBC ceramic layer 1, module DBC lower copper layer 16, module DBC solder layer 17, and module heat dissipation substrate 18. Here, 5.37 mm is the length of the silicon carbide MOSFET chip 6, and h1, h2, h3, h4, h5, and h6 are the heights of the chip solder layer 15, module drain copper plating 3, module DBC ceramic layer 1, module DBC lower copper layer 16, module DBC solder layer 17, and module heat dissipation substrate 18, respectively. These parameters are preferably the independent variables of the objective function, and their upper and lower limits are shown in the layer thickness constraints in Table 1 below.

[0091] Table 1 Layer Thickness Constraints

[0092]

[0093] Therefore, considering the thermal expansion effect, the self-thermal resistance R of the power module self The expression is as follows:

[0094]

[0095] In the formula, λ i is the thermal conductivity of the i-th layer material; h is the convective heat transfer coefficient, which is taken as 6500 W / (m²) in this embodiment. 2 ·℃); S d For effective convective heat transfer area; S i R is the effective thermal conductivity area of ​​the i-th layer material; dl For convective heat transfer thermal resistance.

[0096] Among them, S i The expression is as follows:

[0097]

[0098] At the same time:

[0099] S d1 =S d2 =S d3 =S6;

[0100] In the formula, S d1 、S d2 、S d3 The effective convective heat transfer areas are Q1, Q2, and Q3, respectively.

[0101] Specifically, in the mutual thermal resistance section, such as Figure 6 The diagram shows the thermal resistance coupling area between adjacent chips. Because multiple chips are connected in parallel within the module, there are multiple heat sources, and the chips are close together, thermal coupling exists between them. Therefore, the mutual thermal resistance R... mutual This must also be considered. Therefore, in this embodiment, the sum of self-thermal resistance and mutual thermal resistance is used as the second objective function for multi-objective optimization.

[0102] The formula for calculating mutual thermal resistance is as follows:

[0103]

[0104] In the formula, S ij S is the overlapping area of ​​the effective convection heat transfer areas corresponding to chip i and chip j. dj R represents the effective convective heat transfer area corresponding to chip j. dlj Let J be the convective thermal resistance corresponding to chip j.

[0105] S ij The calculation formula is as follows:

[0106]

[0107] In the formula, D is the center distance between the two chips, such as... Figure 8As shown in a1; α is the angle corresponding to arc OAM, β is the angle corresponding to arc QAN; S OAM for Figure 6 The area of ​​the mid-circular arc OAM, S QAN for Figure 6 The area of ​​the middle circular arc QAN, S OAQ for Figure 6 The area of ​​triangle OAQ; r i 、r j The effective convective heat transfer area radius of the silicon carbide MOSFET chip 6 is calculated using the following formula:

[0108]

[0109] Therefore, in the multi-objective optimization function of this embodiment, the objective function regarding the thermal resistance parameter is:

[0110] min(R self +R mutual );

[0111] (3) Module area parameters:

[0112] Calculate the area of ​​each module partition; that is, divide the module into planar partitions, and the partition area includes: the area occupied by the chip, the area occupied by the chip spacing, the area occupied by the electrical connection layout, and the area occupied by the heat dissipation components. Based on the above module partition areas, obtain the total module area by summing.

[0113] Specifically, the module area can be understood as the power density requirement, and the specific expression for power density ρ is as follows:

[0114]

[0115] In the formula, P is power; V is volume; U is voltage; I is current; l length l width l high Let be the length, width, and height of the object being sought, respectively. Since the goal is to achieve efficient high-power output while miniaturizing the internal power converter, the power density should be as high as possible. According to the formula, the module volume should be as small as possible. Since the height of each layer of material in the module is small and doesn't vary much, the third objective function is to minimize the area. Here, the area is... Figure 7 The area enclosed in bold squares.

[0116] The formula is:

[0117] min(l length ×l width ) = min(l(w1+w2));

[0118] In the formula, l is the dimension of the module in the length direction, and w1 and w2 are the dimensions of different parts of the module in the width direction.

[0119] Among them, such as Figure 8 The constraints corresponding to the horizontal dimension independent variables a1~a4 and b1~b5 shown are listed in Table 2 below: Horizontal dimension constraints.

[0120] Table 2 Lateral Dimension Constraints

[0121]

[0122] In the objective function, the correspondence between variables and independent variables is as follows:

[0123]

[0124] In the formula, 4.46 mm is the width of the silicon carbide MOSFET chip 6.

[0125] Therefore, the above three objective functions are combined to form the multi-objective function to be solved in this embodiment, and the formula is:

[0126]

[0127] Based on this, this embodiment solves the multi-objective optimization function and obtains the frontier solution by improving the genetic algorithm. Specifically, the improved genetic algorithm selected in this embodiment is the Fast Non-dominated Sorting Genetic Algorithm (NSGA-II). This algorithm, when used in the scenario of this embodiment, reduces the complexity of non-dominated sorting genetic algorithms and has the advantages of fast running speed and good convergence of the solution set. The frontier solution is the Pareto front solution.

[0128] In the process of selecting the above independent variables, it is necessary to follow the requirements of the multi-chip parallel module packaging structure and the specifications and process standards of the specific packaging process, so as to screen the characteristic geometric parameters and select parameters that can be controlled to process, have a certain processing range, and can have a practical impact on the results as the independent variables of the function.

[0129] like Figure 2 As shown, the solution process includes:

[0130] A. Initialization: The improved genetic algorithm is initialized based on the multi-objective optimization function to obtain an initial population. The population size is set to 500 during initialization, which is determined after comprehensively considering the problem complexity and computing resources. This ensures the diversity of the population without causing excessive computation. The maximum number of iterations is 5000 to ensure that the algorithm has enough iterations to find a better solution. The coefficient of the optimal frontier individual ranges from 0 to 1, and in this embodiment, it is preferably 0.3. This coefficient is used to control the proportion of the optimal frontier individual in the population, which can better represent the multi-objective optimization frontier and balance the global search and local search capabilities.

[0131] B. Evaluation: The objective optimization function of individuals in the initial population is evaluated to obtain the evaluation results. That is, the objective function values ​​such as parasitic inductance, total thermal resistance and total module area are calculated based on the combination of characteristic geometric parameters corresponding to the individual.

[0132] C. Ranking: Based on the evaluation results, individuals are Pareto-ranked to obtain a ranking sequence, with non-dominant individuals placed at the top, providing a basis for subsequent selection and evolution;

[0133] D. Iteration: Individuals are subjected to recombination, crossover, and mutation operations to obtain a new population. Recombination involves rearranging the genes (corresponding geometric parameters) of individuals. Crossover operations can be performed using methods such as two-point crossover, randomly selecting two crossover points and exchanging gene segments between the corresponding crossover points of the two parent individuals to generate new offspring individuals, increasing population diversity. Mutation operations randomly change the genes of individuals with a certain probability. For example, the gene for bond line length can be randomly changed within its constraints, which helps to escape local optima. Iterative calculations are performed on the new population. When the stopping condition is met, a Pareto front solution is obtained. The stopping condition is reaching the maximum number of iterations of 5000 or the fitness value of the population (the degree of optimization of the objective function) reaches the expected value. The Pareto front solution obtained at this time represents a series of non-dominated solutions that have reached equilibrium between different objectives.

[0134] Finally, the multi-chip parallel module packaging structure is corrected using the Pareto front solution. Based on the specific application scenarios' emphasis on parasitic inductance, thermal resistance, and module area, a suitable solution is selected from the Pareto front solutions to adjust the characteristic geometric parameters of the packaging structure, such as chip spacing and bond wire length, thereby optimizing the multi-chip parallel module packaging structure. In one specific embodiment, the results yield a multi-objective optimization Pareto front solution for power module packaging that simultaneously considers electrical, thermal, and power density considerations, as shown below. Figure 9 As shown in the figure, the Pareto front solutions for the three objective functions are presented in a clear and intuitive 3D coordinate graph. The figure reveals trade-offs among the multiple optimization objectives; no single result can simultaneously optimize all objectives. Therefore, the solutions should be customized based on the load characteristics of the application scenario, and the corresponding results can be obtained from the graph.

[0135] Finally, it should be noted that the above content is only used to illustrate the technical solution of the present invention, and is not intended to limit the scope of protection of the present invention. Simple modifications or equivalent substitutions made by those skilled in the art to the technical solution of the present invention do not depart from the essence and scope of the technical solution of the present invention.

Claims

1. A multi-chip parallel module packaging method based on multi-objective optimization, characterized in that: The steps include: Construct a multi-chip parallel module packaging structure; Based on the multi-chip parallel module packaging structure, the characteristic geometric parameters of the packaging structure are extracted; Based on the aforementioned feature geometric parameters and corresponding performance parameters, a multi-objective optimization function is constructed; The multi-objective optimization function is solved by an improved genetic algorithm, and the frontier solution is obtained. The multi-chip parallel module packaging structure is corrected by the aforementioned leading edge solution.

2. The multi-chip parallel module packaging method based on multi-objective optimization according to claim 1, characterized in that: The multi-chip parallel module packaging structure includes a chip, a substrate, electrical connectors, and a heat dissipation component; The characteristic geometric parameters include chip geometric parameters, chip spacing, electrical connector geometric parameters, substrate geometric parameters, and heat dissipation component geometric parameters.

3. The multi-chip parallel module packaging method based on multi-objective optimization according to claim 2, characterized in that: The performance parameters include parasitic inductance parameters, thermal resistance parameters, and module area parameters; The objective function corresponding to the parasitic inductance parameter is to minimize the parasitic inductance; The objective function corresponding to the thermal resistance parameter is to minimize the total thermal resistance; The objective function corresponding to the module area parameter is to minimize the total area of ​​the module.

4. The multi-chip parallel module packaging method based on multi-objective optimization according to claim 3, characterized in that: Constructing the objective function corresponding to the parasitic inductance parameters includes the following steps: Construct the expression for the parasitic inductance of the power source in each chip branch; An initial objective function is established with the goal of minimizing the difference in parasitic inductance of the power source between different branches; Based on the analysis of thin copper sheet inductance, the initial objective function is transformed into the objective function of parasitic inductance.

5. The multi-chip parallel module packaging method based on multi-objective optimization according to claim 3, characterized in that: Constructing the objective function corresponding to the thermal resistance parameter includes the following steps: Calculate the self-thermal resistance from the chip to the substrate, where the self-thermal resistance is the sum of the thermal conduction resistances of each layer, plus the convective heat transfer resistance. The mutual thermal resistance between adjacent chips is calculated based on the coupling area between the chips, the effective convection heat transfer area, and the convection heat transfer thermal resistance. The objective function of total thermal resistance is obtained by superimposing the self-thermal resistance and the mutual thermal resistance.

6. The multi-chip parallel module packaging method based on multi-objective optimization according to claim 3, characterized in that: Constructing the objective function corresponding to the module area parameter includes the following steps: Calculate the area of ​​each module partition separately; The module partition area includes: the area occupied by the chip, the area occupied by the chip spacing, the area occupied by the electrical connection layout, and the area occupied by the heat dissipation components. Based on the area of ​​the module partitions, the objective function for the total area of ​​the module is obtained by summation.

7. The multi-chip parallel module packaging method based on multi-objective optimization according to any one of claims 1-6, characterized in that: In the construction of the multi-objective optimization function, the feature geometric parameters are screened based on the multi-chip parallel module packaging structure and packaging process, and the function independent variables are obtained. Set constraints or constraint ranges for each function's independent variable.

8. The multi-chip parallel module packaging method based on multi-objective optimization according to claim 1, characterized in that: The improved genetic algorithm is a fast non-dominated sorting genetic algorithm, and the front solution is a Pareto front solution; The improved genetic algorithm for solving the multi-objective optimization function includes the following steps: Based on the multi-objective optimization function, the improved genetic algorithm is initialized, and an initial population is obtained; The objective optimization function of each individual in the initial population is evaluated to obtain the evaluation results; Individuals are ranked according to Pareto based on the assessment results; Individuals are recombined, crossovered, and mutated to obtain a new population; The new population is iteratively calculated, and the frontier solution is obtained when the stopping condition is met.

9. The multi-chip parallel module packaging method based on multi-objective optimization according to claim 8, characterized in that: During the initialization of the improved genetic algorithm, the initial population size is 500, the maximum number of iterations is 5000, and the coefficient of the optimal frontier individual ranges from 0 to 1.

10. The multi-chip parallel module packaging method based on multi-objective optimization according to claim 9, characterized in that: The optimal frontier individual coefficient is 0.3.

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