A via cell automatic generation method, system, device, medium and product

Abstract

The present application relates to the field of integrated circuit computer-aided design, and particularly relates to a via cell automatic generation method, system, device, medium and product. The via cell automatic generation method comprises the following steps: inputting a design rule file, identifying and extracting constraint parameters of a via and metal interconnection, and dividing the constraint parameters into size type and surrounding amount type constraint rules; traversing and obtaining values of the surrounding amount constraint parameters of the surrounding amount type constraint rules in the design rule file, arranging and combining all the values, defining each combination generated as a candidate via cell configuration, and generating a via cell configuration list. The via cell configuration list is traversed, and it is judged whether the candidate via cell configuration conforms to the size type constraint rule. If not, it is modified or deleted. If the rule is met, a via cell library is output. The system, computer device, computer readable storage medium and computer program product of the present application have the same beneficial effects as the via cell automatic generation method.

Description

Technical Field

[0001] This invention relates to the field of computer-aided design of integrated circuits, and in particular to a method, system, device, medium, and product for automatically generating via cells. Background Technology

[0002] In the high-density routing design of modern integrated circuits, the standard via cells provided by process design kits at specific nodes, due to their fixed geometric templates, are difficult to adapt to the complex design constraints of advanced process nodes. Especially in areas with densely stacked metal interconnect layers, these static via cells have inherent conflicts with placement and routing rules: on the one hand, they cannot dynamically respond to topological changes in rules such as spacing and enclosure; on the other hand, they lack the ability to collaboratively optimize multiple rule combinations. This lack of rule adaptability directly leads to a large number of design rule violations during the routing stage, such as core issues like missing via enclosures, and triggers a chain reaction of increased routing congestion and decreased routeability.

[0003] Given the aforementioned problems, current solutions rely on manual intervention and post-implementation repairs, which are not only inefficient but also fail to fundamentally achieve dynamic adaptation between via structures and design rules. Enabling via cells to intelligently respond to changes in design rules has become a key challenge in overcoming the bottleneck of high-density cabling. Summary of the Invention

[0004] To address the technical problem that existing process design kits at specific nodes provide standard via cells that are difficult to respond to changes in design rules, easily leading to design rule violations, increased wiring congestion, and decreased routing success rate, this invention provides a method, system, device, medium, and product for automatically generating via cells.

[0005] The present invention provides a method for automatically generating via cells, comprising the following steps: inputting a design rule file; identifying and extracting all constraint parameters related to vias and metal interconnects in the design rule file, and classifying the constraint parameters into size-based constraint rules and enclosing quantity-based constraint rules; traversing the enclosing quantity constraint parameters of the enclosing quantity-based constraint rules to obtain the values ​​of the enclosing quantity constraint parameters in the design rule file; arranging and combining all values, defining each generated combination as a candidate via cell configuration, and generating a via cell configuration list; traversing the via cell configuration list, determining whether each candidate via cell configuration conforms to the size-based constraint rules, and correcting it if it does not; wherein, if the corrected candidate via cell conforms to the size-based constraint rules, the candidate via cell configuration is retained; if the candidate via cell cannot be corrected, the candidate via cell configuration is deleted; if the candidate via cell configuration conforms to the size-based constraint rules, the candidate via cell configuration conforming to the rules is stored, and an automatically generated via cell library is output based on the candidate via cell configuration conforming to the rules.

[0006] Preferably, the size constraint rules include the following size constraint parameters: the length and width of the via, the minimum line width of the metal layer, the list of legal widths of the metal layer, and the width of adjacent metal lines of the via under different enclosing amounts; wherein, the length and width of the via define the size of the via; the enclosing amount constraint rules include the following enclosing amount constraint parameters: the minimum enclosing amount of the upper metal layer on the via, and the minimum enclosing amount of the lower metal layer on the via.

[0007] Preferably, before determining whether a candidate via cell configuration conforms to size-based constraint rules, the method further includes the following step: deleting invalid candidate via cell configurations from the via cell configuration list based on routing optimization criteria; wherein, the routing optimization criteria include:

[0008] If the size of a candidate via unit configured in a non-preferred routing direction is greater than the routing channel resource threshold in that direction, the candidate via unit configuration is deemed invalid.

[0009] Preferably, the via cell configuration that does not conform to the size constraint rules is corrected by the following steps: calculating the minimum metal line width required by the candidate via cell configuration, which is defined as the via cell width; if the via cell width is less than the minimum metal line width, calculating the difference between the via cell width and the minimum metal line width; updating the enclosing amount of the via cell based on the difference.

[0010] If the via cell width is greater than the minimum linewidth of the metal layer and less than the maximum width in the list of legal widths of the metal layer, select the legal width in the list that is greater than the via cell width but has the smallest difference from the via cell width, calculate the difference between the via cell width and the legal width, and update the via cell bounding based on the difference;

[0011] If the width of a via cell is greater than the maximum width in the list of valid metal layers, the corresponding candidate via cell configuration cannot be modified, and the candidate via cell configuration is deleted.

[0012] Preferably, the formula for calculating the width of the via unit is:

[0013]

[0014] in, Width of the via unit The width of the via. This is the minimum enclosure size of the metal layer;

[0015] The formula for updating the encirclement is:

[0016]

[0017] in, For the new encirclement quantity, The original enclosed area of ​​the metal layer. Width of the via unit;

[0018] When the width of the via cell is less than the minimum linewidth of the metal layer This is the minimum linewidth of the metal layer; when the via cell width is greater than the minimum linewidth of the metal layer, but less than the maximum width in the list of valid widths for the metal layer, This is the legal width value in the list of legal widths for the metal layer that is greater than the width of the via cell but has the smallest difference between the two widths.

[0019] The present invention also provides a via cell generation system, the via cell generation system including a user terminal and a microservice terminal connected by communication; the microservice terminal receives a command to be processed input by the user terminal, and executes the steps of the above-described automatic via cell generation method according to the command to be processed.

[0020] The present invention also provides a computer device, including a storage device, a processor, and a computer program stored on the storage device, wherein the processor executes the computer program to implement the steps of the above-described automatic via cell generation method.

[0021] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-described automatic via cell generation method.

[0022] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described automatic via unit generation method.

[0023] Compared with the prior art, the automatic via unit generation method, system, equipment, medium and product provided by the present invention have the following advantages:

[0024] 1. This invention provides an automatic via cell generation method, overcoming the technical problems of existing standard via cells provided by process design kits at specific nodes, which are difficult to respond to changes in design rules, easily leading to design rule violations, increased routing congestion, and decreased routing success rate. Specifically, by directly extracting all constraint parameters related to vias and metal interconnects from the design rule file, and classifying the constraint parameters into size constraint rules and enclosing quantity constraint rules; by pre-extracting and classifying the design rule constraint parameters of vias and metal interconnects, and locking key parameters before generating candidate via cell configurations, a precise data foundation is laid for the subsequent automated generation process, ensuring the efficiency and rule compliance of via cell configuration generation, and preventing design rule violations from the source.

[0025] Furthermore, by arranging and combining the constraint parameters of the enclosing quantity constraint rules, all possible candidate via cell configurations are obtained, and a via candidate configuration list is generated; this avoids missing the optimal solution and improves the quality and efficiency of routing.

[0026] The system checks whether each candidate via configuration in the list conforms to dimensional constraints. If it does not conform, it corrects the configuration; if correction is not possible, the candidate via configuration is deleted. If it conforms, it is stored and the via configuration library is output. This judgment and correction mechanism ensures that the final output candidate via configurations meet the constraints of dimensional design rules, avoiding wiring congestion and design rule violations caused by insufficient or illegal metal wire width at via connections.

[0027] Automatically creating via cells that conform to design rule files can adapt to complex design rule constraints under advanced process nodes, improving the routing efficiency of integrated circuit physical design; it avoids routing quality problems caused by using standard via cells from traditional process design kits, which cannot adapt to topology changes in design rules.

[0028] 2. The via cell automatic generation method provided in this embodiment of the invention uses the via length and width, minimum line width of the metal layer, list of legal widths of the metal layer, and width of adjacent metal lines of the via under different enclosure amounts as size constraint parameters; it ensures that the line width of the metal lines connected in the candidate via cell configuration is too small or does not belong to the list of legal widths, which would result in a design rule violation, and constrains the width of adjacent metal lines of the via in the candidate via cell configuration under different enclosure amounts, avoiding routing congestion, and ensuring that the via cell will not short-circuit with other adjacent and parallel metal lines.

[0029] Using the minimum enclosure amount of the upper and lower metal layers as the enclosure amount constraint parameter, it ensures that the connection between the via and the upper and lower metal lines always meets the process reliability requirements, effectively preventing connection failure or reliability degradation caused by insufficient enclosure.

[0030] 3. The via cell automatic generation method provided in this embodiment of the invention will pre-evaluate and screen the candidate via cell configuration based on routing optimization criteria before determining whether the candidate via cell configuration meets the size constraint rules, and delete invalid candidate via cell configurations.

[0031] The above-mentioned pre-evaluation and screening mechanism can identify and eliminate invalid via cell configurations that would lead to a deterioration in routing results if actually created and adopted, retaining only effective configurations with high optimization potential; thereby reducing the search space and improving design efficiency and quality.

[0032] Regarding routing optimization criteria, by determining whether the size of the candidate via cell configured in a non-preferred routing direction is greater than the routing channel resource threshold in that direction, it is assessed whether the candidate via cell will occupy a large number of routing channels or block critical routing areas, thereby improving the routing feasibility of the integrated circuit physical design and avoiding the introduction of other design rule violations.

[0033] 4. The via cell automatic generation method provided in this embodiment of the invention, when correcting the configuration of candidate via cells when the width of the via cell is less than the minimum line width of the metal layer, updates the enclosing amount of the via cell by calculating the difference between the width of the via cell and the minimum line width of the metal layer, so as to avoid connection reliability problems, short circuit risks and other design rule violations that may be caused when using the via cell in actual routing.

[0034] When the via cell width is greater than the minimum linewidth of the metal layer but less than the maximum width in the valid metal layer list, the valid width value in the valid metal layer list that is greater than the via cell width but has the smallest difference between the two widths is selected. The via cell enclosure is then updated based on the difference between the valid width and the via cell width. This correction method updates the via cell width to the optimal valid value allowed by the process, ensuring compliance with design rules while maintaining routing resource density and avoiding unnecessary area overhead or routing congestion due to over-correction.

[0035] When the width of a via cell exceeds the maximum width of the valid metal layer list, the corresponding candidate via cell configuration cannot be corrected by updating the bounding amount, and the candidate via cell configuration will be directly deleted. This frees up space in the list, prevents redundant and invalid candidate via cell configurations from entering the via cell configuration list, and improves design efficiency and quality.

[0036] By automatically correcting or deleting candidate via cell configurations using the above method, the quality of the physical via cell library is improved, ensuring that the output results are compatible with the design rules. This eliminates the inefficiency caused by manual correction and the potential introduction of human factors from the source.

[0037] 5. The via unit automatic generation method provided in this embodiment of the invention calculates the updated values ​​of the via unit width and enclosure amount using mathematical formulas, ensuring the absolute compliance of the via unit in terms of size rules, enhancing connection reliability, and significantly improving design efficiency.

[0038] 6. This embodiment of the invention also provides a via cell generation system, the system including a user terminal and a microservice terminal connected by communication; the microservice terminal receives a command to be processed input by the user terminal, and executes the steps of the above-described automatic via cell generation method according to the command to be processed.

[0039] It should be noted that the via cell generation system provided by the present invention has the same beneficial effects as the above-described automatic via cell generation method, and will not be elaborated here.

[0040] 7. The present invention also provides a computer device, including a storage device, a processor, and a computer program stored in the storage device, wherein the processor executes the computer program to implement the steps of the above-described automatic via unit generation method.

[0041] It should be noted that the computer device provided by the present invention has the same beneficial effects as the above-described automatic via unit generation method, and will not be elaborated here.

[0042] 8. The present invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described automatic via unit generation method.

[0043] It should be noted that the computer-readable storage medium provided by the present invention has the same beneficial effects as the above-described automatic via cell generation method, which will not be elaborated here.

[0044] 9. The present invention also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the above-described automatic via unit generation method.

[0045] It should be noted that the computer program product provided by this invention has the same beneficial effects as the above-described automatic via cell generation method, and will not be elaborated here. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a flowchart illustrating steps S1 to S6 of an automatic via unit generation method provided in an embodiment of the present invention.

[0048] Figure 2 This is a flowchart illustrating steps S61 to S63 of an automatic via unit generation method provided in an embodiment of the present invention.

[0049] Figure 3 This is a flowchart illustrating step S4a in an automatic via unit generation method provided in an embodiment of the present invention.

[0050] Figure 4AThis is a schematic diagram illustrating a via unit automatic generation method provided in an embodiment of the present invention, wherein the via unit conforms to the wiring optimization standard.

[0051] Figure 4B This is one of the schematic diagrams illustrating an automatic via cell generation method provided by an embodiment of the present invention where the via cell does not conform to the wiring optimization standard.

[0052] Figure 4C This is the second schematic diagram of a via cell automatic generation method provided in an embodiment of the present invention, where the via cell does not conform to the wiring optimization standard.

[0053] Figure 5 This is a flowchart illustrating the process of determining whether a candidate via cell meets the routing optimization standard in an automatic via cell generation method according to an embodiment of the present invention.

[0054] Figure 6 This is a schematic diagram of the overall process of an automatic via unit generation method provided in an embodiment of the present invention.

[0055] Figure 7 This is a schematic diagram of the framework of a via unit generation system provided in an embodiment of the present invention.

[0056] Figure 8 This is a schematic diagram of the framework of a computer device provided in an embodiment of the present invention.

[0057] Figure 9 This is a schematic diagram of the framework of a computer-readable storage medium provided in an embodiment of the present invention.

[0058] Figure 10 This is a schematic diagram of the framework of a computer program product provided in an embodiment of the present invention.

[0059] Explanation of reference numerals in the attached diagram:

[0060] 1. Via cell generation system; 11. User terminal; 12. Microservice terminal;

[0061] 2. Computer equipment; 21. Storage device; 22. Processor;

[0062] 3. Computer-readable storage medium;

[0063] 4. Computer program products;

[0064] 100. Computer program;

[0065] V, Via; E, Enclosure; L1, Metal wire connecting one end of the via; L2, Metal wire connecting the other end of the via. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0067] In the embodiments provided by this invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0068] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to the invention.

[0069] In various embodiments of the present invention, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0070] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It is particularly important to note that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0071] In the high-density routing design of modern integrated circuits, the standard via cells provided by process design kits at specific nodes, due to their fixed geometric templates, are difficult to adapt to the complex design constraints of advanced process nodes. This lack of rule adaptability directly leads to a large number of design rule violations during the routing stage, such as core issues like missing via enclosures, and triggers a chain reaction of increased routing congestion and decreased routing success rate. Current solutions, based on these problems, rely on manual intervention and post-hoc remediation, which is not only inefficient but also fails to fundamentally achieve dynamic adaptation between via structures and design rules.

[0072] To address the technical problem that existing process design kits at specific nodes provide standard via cells that are difficult to respond to changes in design rules, easily leading to design rule violations, increased wiring congestion, and decreased routing success rate, this invention provides a method, system, device, medium, and product for automatically generating via cells.

[0073] First, please refer to Figure 1 This invention provides a method for automatically generating via cells, comprising the following steps:

[0074] S1: Input the design rule file, identify and extract all constraint parameters related to vias and metal interconnects in the design rule file;

[0075] S2: Classify constraint parameters into size constraint rules and enclosing quantity constraint rules;

[0076] S3: Traverse the bounding constraint parameters of the bounding constraint rules and obtain the values ​​of the bounding constraint parameters in the design rule file;

[0077] S4: Perform permutation and combination operations on all values, define each generated combination as a candidate via cell configuration, and integrate all candidate via cell configurations to generate a via candidate cell configuration list.

[0078] S5: Traverse the candidate via configurations in the via configuration list and determine whether each candidate via configuration conforms to the size constraint rules.

[0079] S6: If it does not meet the requirements, the corresponding via cell configuration is corrected; until all via cell configurations meet the rules, the via cell configurations are stored, via cells are generated based on the stored candidate via cell configurations, and the via cell library is output.

[0080] Understandably, this invention provides an automatic via cell generation method that overcomes the technical problems of existing standard via cells provided by process design kits at specific nodes, which are difficult to respond to changes in design rules and are prone to design rule violations, increased routing congestion, and decreased routing success rate. Specifically, by directly extracting all constraint parameters related to vias and metal interconnects from the design rule file and classifying the constraint parameters into size constraint rules and enclosing quantity constraint rules; by pre-extracting and classifying the design rule constraint parameters of vias and interconnects, and locking key parameters before generating candidate configurations, a data foundation is laid for the subsequent automated generation process, ensuring the efficiency and rule compliance of via cell configuration generation, and preventing design violations from the source.

[0081] Furthermore, by arranging and combining the constraint parameters of the enclosing quantity constraint rules, all possible candidate via cell configurations are obtained, and a via candidate configuration list is generated; this avoids missing the optimal solution and improves the quality and efficiency of routing.

[0082] The system also checks whether each candidate via configuration in the list conforms to dimensional constraints. If it does not, it corrects the configuration; otherwise, it stores the configuration and outputs it as the via library. This judgment and correction mechanism ensures that all candidate via configurations output in the final output meet the constraints of dimensional design rules, avoiding wiring congestion and design rule violations caused by insufficient or illegal metal wire width at via connections.

[0083] The automatically generated via cell library can adapt to the complex design rule constraints under advanced process nodes, improve the routing efficiency of integrated circuit physical design, and avoid routing quality problems caused by the inability of standard via cells from traditional process design kits to adapt to topology changes in design rules.

[0084] The following will explain the specific steps S1 to S6 of the automatic via unit generation method.

[0085] First, in step S1, the design rule file is input, and all constraint parameters related to vias and metal interconnects in the design rule file are identified and extracted by parsing the design rule file.

[0086] Understandably, in integrated circuit physical design, the wiring of an integrated circuit is divided into multiple parallel dielectric layers, i.e., metal layers. Vias are used to vertically penetrate multiple dielectric layers of the chip, providing a crucial structure for electrical connections and signal transmission between metal wiring layers. In the design rule documents for integrated circuit physical design, via-related parameters refer to the rules defining the via itself and the geometric relationships between the upper and lower metal layers directly connected to it; these are used to constrain the connection reliability of vias in the vertical direction.

[0087] In integrated circuit physical design, metal interconnects refer to the connection of internal components such as transistors, resistors, and capacitors within an integrated circuit chip using metal wires, forming a complete conductive path. In design rule documents, metal interconnect-related parameters refer to all rules defining the metal wires themselves and the horizontal geometric relationships between them; these rules constrain the feasibility and reliability of the metal wires themselves and the horizontal routing.

[0088] Identify and extract all parameters related to vias and metal interconnects from the design rule file to lay the data foundation for subsequent via element generation steps.

[0089] In step S2, the constraint parameters are classified into size constraint rules and enclosing quantity constraint rules.

[0090] Dimensional constraint rules include, but are not limited to, the following dimensional constraint parameters: via length and width, minimum linewidth for each metal layer, list of valid linewidths for each metal layer, and width of adjacent metal lines of the via under different enclosing amounts. Among these, the via length and width define the via's dimensions.

[0091] It's important to note that the width requirements for adjacent metal lines of vias under different enclosure amounts are not constraints on the dimensions of the via or the metal lines themselves, but rather an environmental constraint directly related to the layout environment in which the via exists. Specifically, when a via exists in an integrated circuit board layout and has a specific enclosure amount, the width of each of the metal lines parallel to and adjacent to the via must meet a preset minimum width value. The core constraint logic of this standard stems from the relative layout environment between the via and adjacent metal lines, rather than the independent dimensional attributes of the via or the metal lines.

[0092] By limiting the width of vias within a specific enclosure of adjacent metal traces, short circuits between vias and adjacent metal traces due to manufacturing variations are prevented. Furthermore, based on the width of the metal traces, wiring congestion can be predicted and prevented.

[0093] Enclosure constraint rules include, but are not limited to, the following enclosure constraint parameters: minimum enclosure amount of the upper metal layer to the via, and minimum enclosure amount of the lower metal layer to the via. By defining the minimum enclosure amount of the upper and lower metal layers of the via, it is ensured that the connection between the via and the upper and lower metal lines always meets the process reliability requirements, effectively preventing connection failures or reliability degradation caused by insufficient enclosure.

[0094] In step S3, the bounding constraint parameters of the bounding constraint rules are traversed to obtain the values ​​of the bounding constraint parameters in the design rule file.

[0095] Further, in step S4, all values ​​are permuted and combined; that is, by calculating the Cartesian product of the minimum enclosing amount of the upper metal and the minimum enclosing amount of the lower metal, and using a loop traversal algorithm to generate all possible ordered combinations. Each generated combination is defined as a candidate via cell configuration, ultimately resulting in multiple candidate via cell configurations that can characterize different via physical properties.

[0096] Understandably, assuming the minimum enclosure amount of the upper metal layer is 10nm and 12nm in the design rule file, and the enclosure amount of the lower metal layer is 8nm and 10nm, the permutation and combination operation is to traverse all possible combinations of these enclosure amount constraint parameters to generate four different candidate via cell configuration cells:

[0097] Configuration A: (Minimum encirclement of upper metal layer = 10nm, minimum encirclement of lower metal layer = 8nm).

[0098] Configuration B: (Minimum encirclement of upper metal layer = 10nm, minimum encirclement of lower metal layer = 10nm).

[0099] Configuration C: (Minimum encirclement of upper metal layer = 12nm, minimum encirclement of lower metal layer = 8nm).

[0100] Configuration D: (Minimum encirclement of upper metal layer = 12nm, minimum encirclement of lower metal layer = 10nm).

[0101] By performing permutation and combination calculations, it can be ensured that no via physical implementation method allowed by the design rules is missed, covering all possible candidate via cell configurations, avoiding missing the optimal solution, and improving the quality and efficiency of routing.

[0102] Generate and store all candidate via cell configurations to obtain a candidate via cell configuration list.

[0103] In step S5, the candidate via unit configuration list is traversed, and it is determined whether each candidate via unit configuration conforms to the size constraint rules.

[0104] In some embodiments, the method for determining whether a candidate via unit configuration conforms to size-based constraint rules is as follows: Calculate the width of the via unit generated by each candidate via unit configuration. If the width of the via unit is less than the minimum linewidth of the metal layer defined in the size-based constraint rules, the corresponding candidate via unit configuration is determined to be non-compliant with the size-based constraint rules. Furthermore, if the via unit width is greater than the minimum linewidth of the metal layer but less than the maximum width in the list of legal widths of the metal layer, the corresponding candidate via unit configuration is determined to be non-compliant with the size-based constraint rules.

[0105] A via cell includes the via itself, as well as upper and lower metal pads. The upper metal pad is the metal plate at the connection between the upper metal layer and the via, and its size is determined by the amount of upper metal surrounding it. The lower metal pad is the metal disk at the connection between the lower metal layer and the via, and its size is determined by the amount of lower metal surrounding it.

[0106] The formula for calculating the width of a via element is as follows:

[0107]

[0108] in, Width of the via unit The via width is obtained from the dimension class constraint rules; This represents the minimum enclosure size of the metal layer.

[0109] Understandably, in integrated circuit design, if the width of a via cell is less than the minimum linewidth of the metal layer, it can easily lead to defects such as open circuits or excessively high connection resistance due to process deviations during photolithography and etching, thus causing other design rule violations. Furthermore, via cells are critical nodes where vias converge; insufficient width will prevent them from providing adequate current carrying capacity, potentially causing reliability issues such as electromigration or overheating.

[0110] When the via width is greater than the minimum width of the metal layer but less than the maximum width in the list of valid metal layer widths, it can easily lead to deviations in linewidth control during photolithography and etching processes, causing reliability issues such as abnormal wire resistance and uneven current density.

[0111] By comparing the via cell width with the minimum linewidth of the metal layer and the list of legal widths of the metal layer, process reliability is ensured and design rule violations are avoided.

[0112] Furthermore, in step S6, if the candidate via unit configuration involved in step S5 does not conform to the size class constraint rules, the corresponding candidate via unit configuration is modified or deleted.

[0113] In some embodiments, for bounding parameters in candidate via cell configurations that do not conform to size-class constraint rules, they can be directly corrected to the minimum value allowed by the size constraint parameters involved in the size-class constraint rule. Alternatively, if the size-class constraint rule defines a list of legal values, the bounding parameter is corrected to a legal value in the list that is greater than the current value and closest to the current value. Alternatively, based on predefined routing optimization criteria, an optimal value is selected from the compliant value range of the size constraint parameter, and the bounding constraint parameter is modified to the optimal value.

[0114] In some embodiments, when the bounding parameter of a candidate via configuration is too large and cannot be corrected, the candidate via configuration will be directly deleted.

[0115] Understandably, the method of modifying the configuration of candidate via units is not limited to this, as long as it can be modified to conform to the size class constraint rules.

[0116] Until all candidate via cell configurations conform to the size class constraint rules, store all candidate via cell configurations, generate via cells based on the stored candidate via cell configurations, and output the via cell library.

[0117] Understandably, after executing steps S1-S6, a via cell library will be automatically generated. This via cell library is generated based on a design rule file. Unlike traditional static via cells, this embodiment of the invention can dynamically respond to topology changes in design rules during the generation of the via cell library. It also has collaborative optimization capabilities for multi-rule combination constraints, avoiding the introduction of design rule violations during actual routing.

[0118] The steps of the automatic via cell generation method provided in this embodiment of the invention solve the technical problem that the standard via cells provided by the existing process design kits at specific nodes are difficult to respond to changes in design rules, and are prone to design rule violations, increased wiring congestion, and decreased routing success rate.

[0119] Please see Figure 2 In some embodiments, the configuration of candidate via cells that does not conform to size class constraints is corrected, including the following steps:

[0120] S61: Calculate the candidate via cell configuration based on the metal line width defined by the minimum enclosure amount of the metal layer, and define it as the via cell width;

[0121] S62a: If the via cell width is less than the minimum linewidth of the metal layer, calculate the difference between the via cell width and the minimum linewidth of the metal layer.

[0122] S62b: If the via cell width is greater than the minimum linewidth of the metal layer and less than the maximum width in the list of legal widths of the metal layer, then calculate the difference between the via cell width and the legal width in the list of legal widths of the metal layer.

[0123] S62c: If the via cell width is greater than the maximum width in the valid list of metal layers, delete the candidate via cell configuration corresponding to the via cell width;

[0124] S63: Update the enclosure amount of the via cell based on the difference obtained in step S62a or step S62b.

[0125] The specific steps S61 to S63 of the via generation method will be explained below.

[0126] First, in step S61, the width of the metal line defined by the minimum enclosure amount of the metal layer is calculated for the candidate via cell configuration and defined as the via cell width.

[0127] In step S62a, if the width of the via cell is less than the minimum linewidth of the metal layer, the difference between the width of the via cell and the minimum linewidth of the metal layer is calculated; and in step S63, the enclosure amount of the via cell is updated based on the obtained difference.

[0128] In step S62b, if the via cell width is greater than the minimum line width of the metal layer and less than the maximum width in the list of legal widths of the metal layer, then the difference between the via cell width and the legal width in the list of legal widths of the metal layer is calculated.

[0129] In step S62b, the legal width value selected from the list of legal widths is greater than the width of the via unit, but has the smallest difference from the width of the via unit.

[0130] In step S63, the enclosure amount of the via unit is updated based on the obtained difference.

[0131] When correcting candidate via elements, the formula for updating the encirclement is:

[0132]

[0133] in, For the new encirclement quantity; This represents the original enclosed area of ​​the metal layer; This refers to the width of the via cell; when the width of the via cell is less than the minimum linewidth of the metal layer, This is the minimum linewidth of the metal layer; when the via cell width is greater than the minimum linewidth of the metal layer, but less than the maximum width in the list of valid widths for the metal layer, This is a valid value from the list of valid widths for the metal layer.

[0134] Understandably, assume there is a list of valid widths for the metal layer [W1, W2, Wi, Wj, ..., Wn], where 1 ≤ i ≤ n-1, j = i + 1; if Wi < Wvia_cell < Wj, then select... The value of is Wj.

[0135] When correcting candidate via configurations that do not conform to size constraints, the via enclosure is updated by calculating the difference between the via width and the minimum linewidth of the metal layer. This avoids design rule violations such as connection reliability issues and short-circuit risks that may occur when using the via in actual routing.

[0136] For via cell widths greater than the minimum trace width of the metal layer but less than the maximum width in the valid metal layer list, the valid width value in the valid metal layer list that is greater than the via cell width but has the smallest difference between the two widths is selected. The via cell enclosure is then updated based on the difference between the valid width and the via cell width. This correction method updates the via cell width to the optimal valid value allowed by the process, ensuring compliance with design rules while maintaining routing resource density and avoiding unnecessary area overhead or routing congestion due to over-correction.

[0137] The above method automatically corrects the configuration of candidate via cells, improving the quality of the physical via cell library, ensuring that the output results are compatible with the design rules, and eliminating the inefficiency caused by manual correction and the potential introduction of human factors from the source.

[0138] In step S62c, if the via cell width is greater than the maximum width in the valid list of metal layers, the candidate via cell configuration corresponding to the via cell width will be directly deleted.

[0139] Understandably, when the via cell width is too large, it exceeds the maximum allowable width of the metal line in the process, preventing the candidate via cell configuration from being directly corrected by updating the bounding amount. Therefore, the candidate via cell configuration will be directly deleted to free up space in the via cell configuration list, preventing redundant and invalid candidate via cell configurations from entering the via cell configuration list, thus improving design efficiency and quality.

[0140] Please see Figure 3 In some embodiments, after generating the candidate via unit configuration list in step S4, the following steps are also performed:

[0141] After step S4 is completed and a candidate via cell configuration list is generated, step S4a is executed: based on routing optimization criteria, the candidate via cell configurations in the candidate via cell configuration list are traversed, and the candidate via cell configurations are pre-evaluated and screened based on routing optimization criteria to identify and remove invalid candidate via cell configurations.

[0142] Step S5 will be executed only after step S4a is completed: determine whether the configuration of each candidate via unit conforms to the size constraint rules.

[0143] The following will explain step S4a in detail:

[0144] During the generation stage of candidate via cell configurations, a pre-evaluation and screening of the candidate via cell configurations obtained in step S3 is also required. That is, based on preset routing optimization criteria, invalid candidate via cell configurations that would lead to a deterioration in routing results if actually created and adopted are identified and eliminated, while valid candidate via cell configurations with high optimization potential are retained.

[0145] Understandably, routing optimization criteria refer to evaluation standards and screening rules established during the generation phase of candidate via cell configurations, based on the prediction of their potential negative impact on subsequent global and detailed routing results. These criteria aim to eliminate candidate via cell configurations that are theoretically feasible but practically hinder the routing tool from achieving high-quality routing. This narrows the search space of the candidate via cell list, improving routing design efficiency and quality.

[0146] These routing optimization criteria are not evaluated after actual routing, but rather based on pre-evaluation of common bottlenecks in circuit design rules, process characteristics, and routing algorithms.

[0147] In some embodiments, the routing optimization criterion is a routing feasibility criterion, which identifies and eliminates candidate via cell configurations that are too large and would occupy a large number of routing channels or block critical routing areas.

[0148] In other embodiments, the routing optimization criteria are design and process criteria, namely ensuring that the candidate via cell configuration is compatible with the expected routing direction.

[0149] Please see Figures 4A to 4C As an example, the via unit includes a via V and a via enclosure amount E; the left and right ends of the via unit are connected to metal line L1 and metal line L2, respectively.

[0150] in, Figure 4A The via unit is compatible with the routing directions of metal lines L1 and L2, and does not occupy a large number of additional routing channels or block critical routing areas. That is, the candidate via unit configuration corresponding to this via unit meets the routing optimization criteria and is a valid candidate via unit configuration, which is retained in step S4a.

[0151] and Figure 4B The via units in the diagram are incompatible with the routing directions of metal lines L1 and L2, occupying a large number of routing channels. Figure 4C Although the via units in the diagram are basically compatible with the routing directions of metal lines L1 and L2, they occupy too many routing channels. Therefore, Figure 4B and Figure 4C The candidate via configuration corresponding to the via unit does not meet the routing optimization criteria and is an invalid candidate via configuration, which should be eliminated in step S4a.

[0152] In some embodiments, where there are explicit metal layer linewidth constraints, size-based rules must be strictly followed, and configurations that are completely consistent with the metal layer linewidth constraints should be prioritized. However, where there are no explicit metal layer linewidth constraints, it is necessary to ensure that via units do not consume excessive routing resources to avoid causing localized congestion.

[0153] Furthermore, it should be noted that for some more complex process nodes, a universal screening mechanism cannot be fully applied, and some special flexibility is required. For example, on certain metal layers of some complex processes, if the size of a candidate via cell configured on a non-preferred routing surface is larger than the minimum linewidth of the metal layer in that direction, it is also allowed to be retained.

[0154] Please see Figure 5 In some embodiments, the routing optimization criteria specifically include:

[0155] If the size of a candidate via unit configured in a non-preferred routing direction is greater than the routing channel resource threshold in that direction, the candidate via unit configuration is deemed invalid.

[0156] The cabling channel resource threshold refers to the theoretical maximum space available for cabling in a specific cabling direction on a metal layer. Its value is determined by the cabling spacing of the metal layer and the expected occupancy rate of the cabling tracks. The cabling channel resource threshold can be set based on experience, for example, as N times the minimum spacing of the metal lines in the layer, where N is an integer greater than 1; alternatively, the threshold can be obtained by querying process documents or the design constraint files of cabling tools; or, the threshold can be dynamically adjusted based on the user-inputted expected cabling congestion target.

[0157] During the determination process based on routing channel resource thresholds, it is necessary to calculate the physical dimensions of the via units corresponding to the candidate via unit configurations in non-preferred routing directions; for example, on a horizontal routing metal layer, the encirclement amount of the metal layer in the vertical direction is obtained. This dimension is then compared with a predefined routing channel resource threshold. If the dimension exceeds the threshold, it is determined that if the via unit is adopted, it will block the entire routing channel in that direction. Therefore, the corresponding candidate via unit configuration is marked as invalid and removed from the candidate via unit configuration list, thereby ensuring the smooth flow of routing.

[0158] The above-mentioned pre-evaluation and screening mechanism can identify and eliminate invalid via cell configurations that would lead to a deterioration in routing results if actually created and adopted, retaining only effective configurations with high optimization potential; thereby reducing the search space and improving design efficiency and quality.

[0159] Please see Figure 6 The steps of the via cell automatic generation method provided in this embodiment of the invention solve the technical problem that the standard via cells provided by the existing process design kit at a specific node are difficult to respond to changes in design rules, and are prone to design rule violations, increased wiring congestion, and decreased routing success rate.

[0160] Using the aforementioned automatic via cell generation method, a design rule file is input, and dimensional constraint rules and enclosing quantity constraint rules are extracted. Candidate via cell configurations are obtained by arranging and combining the enclosing quantity constraint parameters based on the enclosing quantity constraint rules. In some embodiments, the obtained candidate via cell configurations are pre-evaluated and screened based on routing optimization criteria, eliminating invalid candidate via cell configurations. It is determined whether all valid candidate via cell configurations conform to the dimensional constraint rules; if not, they are corrected. If all candidate via cell configurations conform to the dimensional constraint rules, the corresponding via cells are generated, and a via cell library is output.

[0161] This automatic via cell generation method generates candidate via cell configurations by arranging and combining enclosing quantity constraints from a design rule file, and then uses size constraints to determine whether the candidate via cell configurations meet the constraints, dynamically generating a via cell library. Unlike traditional static via cells, which use fixed geometric templates and cannot dynamically respond to topology changes in design rules, the automatic via cell generation method provided in this invention can dynamically generate a via cell library based on the design rule file, intelligently responding to changes in design rules. This achieves the effects of reducing routing congestion, decreasing design rule violations, and improving routing success rate in integrated circuit design.

[0162] Please see Figure 7 This invention also provides a via cell generation system. The via cell generation system 1 includes a user terminal 11 and a microservice terminal 12 connected by communication. The microservice terminal 12 receives a pending command input by the user terminal 11 and executes the steps of the above-described automatic via cell generation method according to the pending command.

[0163] Understandably, the microservice 12 is responsible for executing the steps of the above-mentioned automatic via cell generation method. After executing the relevant steps, it outputs a preset command that uniquely matches the command to be processed to the user terminal 11. After receiving the preset command, the user terminal 11 submits it to the interpreter for verification and parsing, and finally it is executed by the EDA software.

[0164] It should be noted that the via unit automatic generation method provided in the aforementioned embodiments is implemented using a microservice-based via unit generation system 1. Specifically, microservices separate functionally single-function module units from the original, fully functional monolithic applications, making the original software architecture clearer and simpler, so as to facilitate the updating, maintenance, and further iterative improvement of the functions that a single module unit can achieve.

[0165] Specifically, the via cell generation system 1 of this invention separates the via cell generation function in the integrated circuit design software into a microservice 12. With this design, professionals in the art or users proficient in integrated circuit design software only need to deploy a via cell generation microservice in advance, and can request the microservice on different versions of integrated circuit design software within the local area network, thereby realizing via cell generation through the microservice 12, and reducing the occupation of memory resources.

[0166] Please see Figure 8 The present invention also provides a computer device 2, including a storage 21, a processor 22 and a computer program 100 stored on the storage 21, wherein the processor 22 executes the computer program 100 to implement the steps of the above-described automatic via unit generation method.

[0167] It is understood that when the computer device 2 provided in the embodiments of the present invention is running, the via cell automatic generation method described in the above embodiments can be implemented when the processor 22 executes the computer program 100. The computer device 2 provided in the embodiments of the present invention has the same beneficial effects as the via cell automatic generation method provided in the above embodiments.

[0168] In some embodiments, the computer device 2 is a computer device applied in the field of integrated circuit design technology, including but not limited to obtaining design rule files, extracting size-type constraint rules and enclosing quantity-type constraint rules, arranging and combining the enclosing quantity parameters of the enclosing quantity-type constraint rules to generate candidate via cell configurations, determining whether the candidate via cell configurations conform to size-type constraint rules, correcting candidate via cell configurations that do not conform to the rules, and performing pre-evaluation and screening of candidate via cell configurations, etc., which will not be elaborated here. Theoretically, the method steps involved in the technical solution of the present invention can all be implemented by the computer device 2, and the relevant parameters involved can also be adjusted by the computer device 2. Among them, the relevant parameters include but are not limited to preset command sets and preset option sets.

[0169] In some embodiments of the present invention, the processor 22 provided is a general-purpose processor, which is a microprocessor or any conventional processor, such as a central processing unit (CPU), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, which can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of this application.

[0170] In some embodiments, the method steps disclosed in this application may be executed by a hardware processor or by a combination of hardware and software modules in the processor 22.

[0171] Please see Figure 9 The present invention also provides a computer-readable storage medium 3, on which a computer program 100 is stored, which, when executed by a processor, implements the steps of the above-described automatic via unit generation method.

[0172] Understandably, the computer-readable storage medium 3 provided in the embodiments of the present invention stores a computer program 100, and the computer program 100 can be called by a processor to execute the via cell automatic generation method described in the above embodiments.

[0173] It should be noted that the computer-readable storage medium 3 provided in the embodiments of the present invention has the same beneficial effects as the via cell automatic generation method provided in the above embodiments, and will not be described in detail here.

[0174] Specifically, the computer-readable storage medium 3 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, disk, optical disk, etc.

[0175] In some embodiments, the computer-readable storage medium 3 includes a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs, and modules.

[0176] Specifically, the computer-readable storage medium 3 has storage space for a computer program 100 that performs any of the method steps of the above-described automatic via cell generation method, and these programs can be read from or written to one or more computer program products.

[0177] In some embodiments, the computer program 100 is capable of compression in an appropriate form.

[0178] Please see Figure 10 The present invention also provides a computer program product 4, including a computer program 100, which implements the steps of the above-described automatic via unit generation method when executed by a processor.

[0179] It is understood that the computer program product 4 provided in the embodiments of the present invention includes a computer program 100, and the computer program 100 can be called by a processor to execute the via cell automatic generation method described in the above embodiments, which will not be repeated here.

[0180] The above provides a detailed description of the automatic via cell generation method, via cell generation system, equipment, medium, and product disclosed in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention.

[0181] Furthermore, those skilled in the art will recognize that, based on the ideas of this invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this invention. Any modifications, equivalent substitutions, and improvements made within the principles of this invention should be included within the protection scope of this invention.

Claims

1. A method for automatically generating via cells, characterized in that, Includes the following steps: Input the design rule file, identify and extract all constraint parameters related to vias and metal interconnects in the design rule file, and classify the constraint parameters into size constraint rules and enclosing quantity constraint rules; Iterate through the bounding constraint parameters of the bounding constraint rules and obtain the values ​​of the bounding constraint parameters in the design rule file; perform permutation and combination operations on all values, define each generated combination as a candidate via element configuration, and integrate all candidate via element configurations to generate a via element configuration list. Iterate through the candidate via configurations in the via configuration list, and determine whether each candidate via configuration meets the size constraint rules. If it does not meet the rules, make corrections. If the corrected candidate via unit conforms to the size constraint rules, the candidate via unit configuration is retained; if the candidate via unit cannot be corrected, the candidate via unit configuration is deleted. If the candidate via cell configuration conforms to the size constraint rules, store the candidate via cell configuration that conforms to the rules, generate via cells based on the candidate via cell configuration, and output the via cell library.

2. The automatic via unit generation method as described in claim 1, characterized in that, The size constraint rules include the following size constraint parameters: The via length and width, minimum linewidth of the metal layer, list of legal widths of the metal layer, and width of adjacent metal lines of the via under different encirclement amounts; wherein, the length and width of the via define the size of the via; And / or, the enclosing quantity class constraint rule includes the following enclosing quantity constraint parameters: Minimum enclosure of the upper metal layer around the via; minimum enclosure of the lower metal layer around the via.

3. The automatic via unit generation method as described in claim 2, characterized in that, Before determining whether the candidate via unit configuration conforms to the size class constraint rules, the following steps are also included: Based on the routing optimization criteria, invalid candidate via configurations are removed from the via configuration list; The routing optimization criteria include: If the size of a candidate via unit configured in a non-preferred routing direction is greater than the routing channel resource threshold in that direction, the candidate via unit configuration is deemed invalid.

4. The automatic via unit generation method as described in claim 2, characterized in that, Correcting via configurations that do not conform to dimensional constraint rules includes the following steps: The candidate via cell configuration is calculated based on the metal line width defined by the minimum enclosure amount of the metal layer, and is defined as the via cell width. If the via cell width is less than the minimum linewidth of the metal layer, calculate the difference between the via cell width and the minimum linewidth of the metal layer; update the via cell bounding based on the difference. If the via cell width is greater than the minimum linewidth of the metal layer and less than the maximum width in the list of legal widths of the metal layer; select the legal width in the list of legal widths that is greater than the via cell width but has the smallest difference from the via cell width, calculate the difference between the via cell width and the legal width, and update the enclosing amount of the via cell based on the difference; If the width of a via cell is greater than the maximum width in the list of valid metal layers, the corresponding candidate via cell configuration cannot be modified, and the candidate via cell configuration is deleted.

5. The automatic via unit generation method as described in claim 4, characterized in that, The formula for calculating the width of a via element is: in, Width of the via unit The width of the via. This is the minimum enclosure size of the metal layer; The formula for updating the encirclement is: in, For the new encirclement quantity, The original enclosed area of ​​the metal layer. Width of the via unit; When the width of the via cell is less than the minimum linewidth of the metal layer This is the minimum linewidth of the metal layer; when the via cell width is greater than the minimum linewidth of the metal layer, but less than the maximum width in the list of valid widths for the metal layer, This is the legal width value in the list of legal widths for the metal layer that is greater than the width of the via cell but has the smallest difference between the two widths.

6. A via unit generation system, characterized in that: The via unit generation system includes a user terminal and a microservice terminal with communication connections; The microservice receives the pending command input from the user and executes the steps of the via cell automatic generation method according to any one of claims 1-5.

7. A computer device comprising a storage unit, a processor, and a computer program stored on the storage unit, characterized in that, The processor executes the computer program to implement the steps of the automatic via cell generation method according to any one of claims 1-5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the automatic via cell generation method according to any one of claims 1-5.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the automatic via cell generation method according to any one of claims 1-5.

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