Chip defect identification method and system

Abstract

The invention provides a chip defect identification method and system, and the method comprises the steps: carrying out the multi-level enhancement processing of an input chip packaging X-ray image according to the material density difference of different materials in chip packaging, and obtaining an enhanced X-ray image with optimized material characteristics; inputting the enhanced X-ray image into a pre-trained image segmentation network for packaging boundary identification and rotation correction to obtain a chip packaging area image; inputting the chip packaging area image into a pre-trained double-flow feature extraction network to perform extraction and fusion of defect morphological features and boundary features to obtain a fused multi-dimensional feature map; and inputting the fused multi-dimensional feature map into a pre-trained defect evaluation network for defect parameter calculation and reliability judgment to obtain a defect identification result. Through multi-level image enhancement and multi-network cooperative processing, various defect types in chip packaging can be accurately identified, and the accuracy and reliability of defect detection are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of defect detection technology, and in particular to a chip defect identification method and system. Background Technology

[0002] With the continuous miniaturization and increasing integration of electronic devices, the complexity of chip packaging processes is increasing, and various defects generated during the packaging process have a serious impact on chip performance and reliability. Traditional chip defect detection mainly relies on optical microscopes and manual visual inspection. However, due to the three-dimensional characteristics of chip packaging structures and the opacity of materials, optical inspection methods are difficult to accurately identify internal defects, resulting in significant deficiencies in both detection accuracy and efficiency.

[0003] X-ray nondestructive testing technology can penetrate packaging materials to observe internal structures, providing a new technical approach for chip defect detection. However, existing X-ray image analysis methods mainly employ traditional image processing algorithms and simple machine learning models. When dealing with complex packaging structures, these methods suffer from technical problems such as insufficient feature extraction, low defect identification accuracy, and inability to effectively distinguish between different types of defects, making it difficult to meet the actual needs of high-precision chip quality inspection. Summary of the Invention

[0004] The main objective of this invention is to solve the technical problems of insufficient feature extraction and low defect recognition accuracy in existing X-ray image defect detection methods. The first aspect of this invention provides a chip defect identification method, the chip defect identification method comprising: Based on the material density differences of different materials in the chip package, the input chip package X-ray image is enhanced in multiple layers to obtain an enhanced X-ray image with optimized material properties. An enhanced X-ray image is input into a pre-trained image segmentation network. The image segmentation network is used to perform packaging boundary recognition and rotation correction on the enhanced X-ray image to obtain the corresponding chip packaging region image. The chip packaging area image is input into a pre-trained dual-stream feature extraction network. The dual-stream feature extraction network extracts and fuses the defect morphology features and boundary features of the chip packaging area image to obtain the corresponding fused multidimensional feature map. The fused multidimensional feature map is input into a pre-trained defect evaluation network. The defect evaluation network calculates defect parameters and determines reliability of the fused multidimensional feature map to obtain the corresponding defect identification result.

[0005] Optionally, in a first implementation of the first aspect of the present invention, the step of performing multi-level enhancement processing on the input chip package X-ray image based on the material density differences of different materials in the chip package to obtain an enhanced X-ray image with optimized material properties includes: The preset X-ray attenuation coefficient lookup table for chip packaging materials is invoked, and material regions are identified for different grayscale value ranges of the input chip packaging X-ray image based on the differences in attenuation coefficients of different materials in the X-ray attenuation coefficient lookup table. The high-density metal region, medium-density ceramic region and low-density defect region identified in the X-ray image of the chip package are processed by corresponding enhancement strategies to obtain a layered enhanced image. The preset welding area recognition algorithm is used to calculate the density gradient vector field between the solder and the substrate material in the pixel neighborhood of the chip package X-ray image to locate the welding layer boundary and obtain the region of interest mask. The layered enhanced image is fused according to the region of interest mask to obtain an enhanced X-ray image with optimized material properties.

[0006] Optionally, in a second implementation of the first aspect of the present invention, the step of inputting the enhanced X-ray image into a pre-trained image segmentation network, and using the image segmentation network to perform encapsulation boundary recognition and rotation correction on the enhanced X-ray image to obtain a corresponding chip encapsulation region image includes: An enhanced X-ray image is input into a pre-trained image segmentation network, wherein the image segmentation network includes an encoder module, a rectangular spatial attention module, and a decoder module; The encoder module performs multi-layer convolution and downsampling processing on the enhanced X-ray image to extract multi-scale feature maps. The multi-scale feature map is input into the rectangular spatial attention module, and attention weights are calculated in the vertical and horizontal directions through 7×1 and 1×7 depth-separable strip convolutions to obtain a spatial attention weight map. The multi-scale feature map is weighted according to the spatial attention weight map, and then upsampled and fused through the decoder module to obtain the encapsulation boundary segmentation mask. The enhanced X-ray image is rotated and corrected according to the packaging boundary segmentation mask to obtain the corresponding chip packaging area image.

[0007] Optionally, in a third implementation of the first aspect of the present invention, the step of rotating and correcting the enhanced X-ray image according to the package boundary segmentation mask to obtain the corresponding chip package region image includes: Based on the encapsulation boundary segmentation mask, the encapsulation boundary contour line is extracted from the enhanced X-ray image to obtain the boundary contour coordinate set; The principal component analysis algorithm is used to calculate the angle between the principal direction vector of the encapsulated boundary contour line and the standard horizontal direction on the boundary contour coordinate set, thus obtaining the rotation angle parameter; A two-dimensional affine transformation matrix is ​​constructed based on the rotation angle parameters, and the enhanced X-ray image and the encapsulation boundary segmentation mask are simultaneously subjected to rotation transformation processing to obtain a corrected image and a corrected mask at a standard horizontal position. The bounding box of the correction mask is calculated using the minimum bounding rectangle algorithm. Based on the calculated rectangular region coordinates, the corresponding region is extracted from the correction image and its size is standardized to obtain the chip packaging region image.

[0008] Optionally, in a fourth implementation of the first aspect of the present invention, the step of inputting the chip packaging region image into a pre-trained dual-stream feature extraction network, and extracting and fusing defect morphology features and boundary features of the chip packaging region image through the dual-stream feature extraction network to obtain a corresponding fused multidimensional feature map includes: The chip packaging area image is input into a pre-trained dual-stream feature extraction network, which includes a defect segmentation stream, a boundary-aware stream, and a feature-related cross-gating module. The encoder in the defect segmentation stream performs global context analysis on the chip packaging area image using multiple preset scanning paths to extract multi-scale defect morphology features and obtain a defect morphology feature map. The boundary-aware flow is used to perform density jump detection processing on the chip packaging area image to extract density transition information between the solder layer and the substrate material, thereby obtaining a boundary feature map. The defect morphology feature map and boundary feature map are input into the feature correlation cross-gating module, and the correlation weight between the defect shape feature and the boundary feature intensity is calculated through the cross attention mechanism. The defect morphology feature map and boundary feature map are weighted and fused according to the correlation weight to obtain a fused multidimensional feature map.

[0009] Optionally, in a fifth implementation of the first aspect of the present invention, the step of performing global context analysis on the chip packaging region image through the encoder in the defect segmentation stream using multiple preset scanning paths to extract multi-scale defect morphology features and obtain a defect morphology feature map includes: The chip packaging area image is input into the encoder in the defect segmentation stream. The image pixels are serialized according to four preset scanning paths: top left to bottom right, top right to bottom left, bottom left to top right, and bottom right to top left, to obtain a multi-directional pixel sequence. The hidden state calculation and state transition processing of the multi-directional pixel sequence are performed by the state space modeling algorithm to establish long-distance dependencies between pixels and obtain a serialized feature representation containing global context information. The serialized feature representation is remapped into a two-dimensional feature map format, and features at different resolutions are extracted and fused using multi-scale convolutional kernels to obtain a multi-level defect morphology representation. The multi-level defect morphology representation is processed by feature mapping and channel adjustment using a convolutional neural network to obtain a defect morphology feature map.

[0010] Optionally, in a sixth implementation of the first aspect of the present invention, the step of inputting the fused multidimensional feature map into a pre-trained defect evaluation network, and using the defect evaluation network to calculate defect parameters and determine reliability of the fused multidimensional feature map to obtain the corresponding defect identification result includes: The fused multidimensional feature map is input into a pre-trained defect evaluation network. The defect evaluation network extracts the defect region from the fused multidimensional feature map and calculates the geometric parameters. The region type of the defect region is determined based on the defect location in the geometric parameters. The preset three-dimensional thermal conduction model of the chip package is invoked, and the area and location information of the defective region are input into the three-dimensional thermal conduction model to perform heat flow distribution simulation calculation, so as to obtain the contribution value of each defective region to the overall thermal resistance. The contribution values ​​are weighted according to the defect region type to calculate the overall reliability score. A judgment threshold is selected based on the chip application level to determine the pass / fail status and obtain the defect identification result.

[0011] A second aspect of the present invention provides a chip defect identification system, the chip defect identification system comprising: The image enhancement module is used to perform multi-level enhancement processing on the input chip package X-ray image based on the material density differences of different materials in the chip package, so as to obtain an enhanced X-ray image with optimized material properties. The boundary segmentation module is used to input the enhanced X-ray image into a pre-trained image segmentation network, and to perform encapsulation boundary recognition and rotation correction on the enhanced X-ray image through the image segmentation network to obtain the corresponding chip encapsulation region image; The feature extraction module is used to input the chip packaging area image into a pre-trained dual-stream feature extraction network, and to extract and fuse the defect morphology features and boundary features of the chip packaging area image through the dual-stream feature extraction network to obtain the corresponding fused multidimensional feature map. The defect assessment module is used to input the fused multidimensional feature map into a pre-trained defect assessment network, and to calculate the defect parameters and determine the reliability of the fused multidimensional feature map through the defect assessment network to obtain the corresponding defect identification result.

[0012] The aforementioned chip defect identification method and system perform multi-level enhancement processing on the input chip package X-ray image based on the material density differences of different materials in the chip package, obtaining an enhanced X-ray image with optimized material properties. The enhanced X-ray image is then input into a pre-trained image segmentation network for package boundary recognition and rotation correction, yielding a chip package region image. This image is then input into a pre-trained dual-stream feature extraction network for defect morphology and boundary feature extraction and fusion, resulting in a fused multi-dimensional feature map. Finally, the fused multi-dimensional feature map is input into a pre-trained defect evaluation network for defect parameter calculation and reliability determination, yielding the defect identification result. This invention, through multi-level image enhancement and multi-network collaborative processing, can accurately identify various defect types in chip packages, significantly improving the accuracy and reliability of defect detection.

[0013] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purposes and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0014] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the first embodiment of the chip defect identification method in this invention; Figure 2 This is a schematic diagram of one embodiment of the chip defect identification system in this invention. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] The terms "comprising" and "having," and any variations thereof, used in the embodiments of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0018] To facilitate understanding of this embodiment, a chip defect identification method disclosed in this invention will first be described in detail. For example... Figure 1 As shown, this method includes the following steps: 101. Based on the material density differences of different materials in the chip package, the input chip package X-ray image is subjected to multi-level enhancement processing to obtain an enhanced X-ray image with optimized material properties; In one embodiment of the present invention, the step of performing multi-level enhancement processing on the input chip package X-ray image based on the material density differences of different materials in the chip package to obtain an enhanced X-ray image with optimized material properties includes: calling a preset X-ray attenuation coefficient lookup table for chip package materials, and identifying material regions in different grayscale ranges of the input chip package X-ray image based on the attenuation coefficient differences of different materials in the X-ray attenuation coefficient lookup table; applying corresponding enhancement strategies to the high-density metal regions, medium-density ceramic regions, and low-density defect regions identified in the chip package X-ray image to obtain a layered enhanced image; running a preset welding region recognition algorithm to calculate the density gradient vector field between the solder and substrate materials in the pixel neighborhood of the chip package X-ray image to locate the welding layer boundary and obtain a region of interest mask; and performing fusion processing on the layered enhanced image based on the region of interest mask to obtain an enhanced X-ray image with optimized material properties.

[0019] Specifically, a pre-defined X-ray attenuation coefficient lookup table for chip packaging materials is used to identify material regions in the input image. This lookup table contains linear attenuation coefficient values ​​for common packaging materials such as silicon substrates, copper wires, aluminum pads, epoxy resin encapsulant, and ceramic substrates. These coefficients reflect the X-ray absorption capacity of different materials. The grayscale value of each pixel in the input X-ray image is read and matched against the attenuation coefficients in the lookup table. Specifically, a mapping relationship between grayscale values ​​and material density is established based on the Beer-Lambert law. By calculating the correlation between the pixel's grayscale value and the standard material attenuation coefficient, the material type corresponding to that pixel is determined. In this process, the grayscale value range of the entire image is divided into multiple intervals: high grayscale value intervals correspond to high-density metal materials such as copper wires and pads; medium grayscale value intervals correspond to medium-density materials such as ceramic substrates and silicon substrates; and low grayscale value intervals correspond to defective areas such as voids and cracks, or low-density packaging materials.

[0020] Specifically, after material region identification, corresponding enhancement strategies are applied to different identified material regions. For high-density metal regions, due to their strong X-ray absorption leading to low image contrast, a nonlinear grayscale transformation method is used to enhance detail information. The grayscale dynamic range of this region is expanded by adjusting the gamma correction parameters, and a local histogram equalization algorithm is applied to enhance the edge contours of metal wires. For medium-density ceramic and silicon substrate regions, an adaptive contrast-limited histogram equalization method is used, which can enhance contrast while avoiding excessive noise amplification. For low-density defect regions, high-pass filtering and edge enhancement algorithms are used to highlight the boundary features of defects. The second derivative of the image is calculated using the Laplacian operator to enhance edge information, and then the processing results are weighted and superimposed with the original image. Each enhancement strategy generates corresponding layered enhanced images. These images retain the spatial location information of the original image but have better visual effects and feature representation capabilities within their respective material regions.

[0021] Specifically, a pre-defined welding region recognition algorithm is used to accurately locate the weld layer boundary in the image. This algorithm is based on density gradient vector field analysis, which identifies the transition region between the solder and the substrate material by calculating the density change rate within the neighborhood of each pixel in the image. The algorithm first performs Gaussian filtering preprocessing on the input image to reduce noise interference, and then calculates the gradient components of the image in the horizontal and vertical directions, obtaining the gradient magnitude and direction information through the Sobel operator or Prevet operator. Further analysis of the distribution characteristics of the gradient vector field identifies regions with large gradient magnitudes and consistent directions as potential material interfaces. Since solder usually has high density characteristics while the substrate material has relatively low density, there is a significant density jump between the two, which manifests as a significant gray-level gradient in the X-ray image. The algorithm filters out pixels with gradient magnitudes exceeding a predetermined threshold by setting a threshold parameter, and applies connected component analysis to organize these pixels into continuous boundary line segments, ultimately generating a region of interest mask describing the location of the weld layer boundary.

[0022] Specifically, after obtaining the layered enhanced image and the region of interest (ROI) mask, a fusion process is performed to generate the final material property-optimized enhanced image. The fusion process employs a weighted, pixel-level fusion strategy, assigning different fusion weights to different regions based on their location information within the ROI mask. Higher weights are given to the edge-enhanced layered image near the weld area and material interface to highlight the detailed features of these key regions. In areas with uniform material, the layered enhanced image corresponding to the material type is primarily used as the main contributing source. The fusion algorithm calculates the final grayscale value of each pixel using a weighted averaging method, with the weight parameters dynamically determined based on the pixel's marker value in the ROI mask and the material type distribution in the surrounding neighborhood. Furthermore, boundary smoothing is applied to avoid noticeable boundary effects during the fusion of different regions. Gaussian weighted fusion and bilateral filtering techniques ensure that the fused image maintains good visual continuity while preserving detailed information, ultimately generating a material property-optimized enhanced X-ray image.

[0023] 102. Input the enhanced X-ray image into a pre-trained image segmentation network, and use the image segmentation network to perform packaging boundary recognition and rotation correction on the enhanced X-ray image to obtain the corresponding chip packaging region image; In one embodiment of the present invention, the step of inputting the enhanced X-ray image into a pre-trained image segmentation network, and performing encapsulation boundary recognition and rotation correction on the enhanced X-ray image through the image segmentation network to obtain a corresponding chip encapsulation region image includes: inputting the enhanced X-ray image into the pre-trained image segmentation network, wherein the image segmentation network includes an encoder module, a rectangular spatial attention module, and a decoder module; performing multi-layer convolution and downsampling processing on the enhanced X-ray image through the encoder module to extract multi-scale feature maps; inputting the multi-scale feature maps into the rectangular spatial attention module, and calculating attention weights in the vertical and horizontal directions through 7×1 and 1×7 depth-separable strip convolutions to obtain a spatial attention weight map; performing weighted processing on the multi-scale feature maps according to the spatial attention weight map, and performing upsampling and feature fusion through the decoder module to obtain an encapsulation boundary segmentation mask; and performing rotation correction on the enhanced X-ray image according to the encapsulation boundary segmentation mask to obtain a corresponding chip encapsulation region image.

[0024] Specifically, the image segmentation network adopts an encoder-decoder architecture, consisting of three core components: an encoder module, a rectangular spatial attention module, and a decoder module. The encoder module is responsible for extracting multi-level feature representations from the input image, the rectangular spatial attention module specifically handles the rectangular geometric characteristics of the chip package, and the decoder module reconstructs the extracted features into a segmentation mask. At the beginning of processing, the enhanced X-ray image first undergoes preprocessing steps, including size normalization and pixel value normalization, to ensure that the input data meets the input requirements of the pre-trained model. Subsequently, the image data is converted into tensor format and fed into the first convolutional layer of the encoder module to begin the feature extraction process.

[0025] Specifically, the encoder module performs deep feature extraction on enhanced X-ray images through multi-layer convolution and downsampling operations. This module contains five layers of feature extraction units, each consisting of multiple convolutional layers, batch normalization layers, and activation function layers. In the first layer, a 3x3 convolutional kernel is used to convolve the input image, extracting low-level features such as edges and textures. Then, a max-pooling layer is applied to halve the feature map size. In the second layer, the number of convolutional kernels is increased to extract more complex local patterns, while downsampling continues. As the network deepens, the third, fourth, and fifth layers progressively extract higher-level semantic features, with the receptive field of each layer continuously expanding to capture a wider range of contextual information. In each convolutional operation, padding preserves the spatial dimension of the feature map, and then downsampling is achieved through a 2-stride convolution or pooling operation. The entire encoding process generates five feature maps at different scales, corresponding to half, quarter, eighth, sixteenth, and thirty-second resolutions of the original image, respectively. These multi-scale feature maps contain rich information ranging from detailed textures to high-level semantics.

[0026] Specifically, the multi-scale feature map output by the encoder is then processed by the rectangular spatial attention module. This module is specifically designed to enhance the recognition capability of the rectangular boundaries of the chip package. It calculates attention weights in the vertical and horizontal directions using 7x1 and 1x7 depthwise separable stripe convolutions. The depthwise separable stripe convolution decomposes standard convolution into two steps: depthwise convolution and pointwise convolution. First, a 7x1 stripe convolution kernel is applied independently to each input channel to capture linear features in the vertical direction. Then, a 1x1 pointwise convolution fuses the information from different channels. Similarly, the 1x7 stripe convolution kernel specifically handles linear features in the horizontal direction. When calculating the attention weights, the module first groups the input multi-scale feature map by channel dimension, dividing the feature channels into a vertical perception group and a horizontal perception group. The vertical perception group calculates the importance weight of each spatial location in the vertical direction using a 7x1 stripe convolution, while the horizontal perception group calculates the weight in the horizontal direction using a 1x7 stripe convolution. Subsequently, the weights in the two directions are fused using element-wise multiplication to generate a comprehensive spatial attention weight map. The weight map highlights the chip package boundary region, especially the four edges of the rectangular outline, while suppressing background noise and the response of irrelevant regions.

[0027] Specifically, the attention weight map output by the rectangular spatial attention module is weighted and fused with the multi-scale feature map, and then input into the decoder module for upsampling and feature reconstruction. The decoder module adopts a symmetrical upsampling architecture, containing five levels of feature reconstruction units, each responsible for restoring the low-resolution feature map to a higher resolution. During the upsampling process, the feature map size is first doubled using transposed convolution or bilinear interpolation, and then fused with the feature map of the corresponding level in the encoder via skip connections. This skip connection mechanism can pass detailed information from the encoder to the decoder, avoiding the irrecoverability of spatial details lost during downsampling. In each decoding level, multiple convolutional layers further process the fused features, gradually refining the segmentation results. The final decoder output layer uses a 1x1 convolution to convert the multi-channel feature map into a single-channel probability map, and uses a sigmoid activation function to map pixel values ​​to a probability range of zero to one, generating a package boundary segmentation mask. The high-probability regions in this mask correspond to the boundary positions of the chip package, and the low-probability regions correspond to the background regions.

[0028] Specifically, after obtaining the package boundary segmentation mask, a rotation correction operation is performed to adjust the chip package to a standard horizontal position. The rotation correction process first binarizes the segmentation mask by setting a threshold to convert the probability map into a binary mask, and then applies morphological operations to remove noise and fill holes. Next, a contour extraction algorithm extracts the contour lines of the package boundary from the binary mask and calculates the directed bounding box of the contour. The directed bounding box algorithm determines the main orientation of the package by finding the smallest rectangle that tightly encloses the contour; the direction of the long side of this rectangle is the main orientation of the package. The angle parameter to be rotated is determined by calculating the angle between the long side of the bounding box and the horizontal axis. Subsequently, a two-dimensional rotation transformation matrix is ​​constructed, and an affine transformation operation is performed on the enhanced X-ray image. During the rotation, bilinear interpolation is used to calculate the grayscale value of the new pixel position to ensure the smoothness of the rotated image. After rotation, the rectangular range of the region of interest is determined based on the corrected package boundary position. The region containing the complete chip package is cropped from the rotated image and its size is normalized, finally generating a normalized chip package region image.

[0029] Furthermore, the step of rotating and correcting the enhanced X-ray image based on the package boundary segmentation mask to obtain the corresponding chip package area image includes: extracting the package boundary contour line from the enhanced X-ray image based on the package boundary segmentation mask to obtain a set of boundary contour coordinates; calculating the angle between the principal direction vector of the package boundary contour line and the standard horizontal direction using a principal component analysis algorithm to obtain a rotation angle parameter; constructing a two-dimensional affine transformation matrix based on the rotation angle parameter, and simultaneously performing rotation transformation processing on the enhanced X-ray image and the package boundary segmentation mask to obtain a corrected image and a corrected mask at a standard horizontal position; calculating the bounding box of the corrected mask using a minimum bounding rectangle algorithm, extracting the corresponding region from the corrected image based on the calculated rectangular region coordinates, and performing size standardization processing to obtain the chip package area image.

[0030] Specifically, the encapsulation boundary contours are extracted from the enhanced X-ray image based on the encapsulation boundary segmentation mask. This process begins with binarizing the segmentation mask, converting continuous probability values ​​into discrete binary labels by setting a threshold. Pixels above the threshold are labeled as foreground, and pixels below the threshold are labeled as background. Morphological opening and closing operations are then applied to post-process the binarized mask. The opening operation removes small noise points and burrs through erosion followed by dilation, while the closing operation fills small holes within the contour through dilation followed by erosion. Next, an edge detection algorithm is used to extract the contours from the processed binary mask. Specifically, a gradient-based contour tracking method is employed, starting from the boundary pixels of the mask and sequentially visiting adjacent boundary pixels in a clockwise or counterclockwise direction until returning to the starting point to form a closed contour. During contour extraction, the pixel coordinates of each contour point are recorded, including the x and y coordinates. Simultaneously, the perimeter and area parameters of the contour are calculated. A threshold is used to filter out the main encapsulation boundary contours, excluding small contours caused by noise. Finally, a sequence of coordinate points describing the shape of the encapsulation boundary is obtained, forming a boundary contour coordinate set.

[0031] Specifically, after obtaining the boundary contour coordinate set, the principal component analysis (PCA) algorithm is used to calculate the principal direction vector of the package boundary contour line. The PCA algorithm first centers the contour coordinate set, calculates the centroid coordinates of all contour points, and then subtracts the centroid coordinates from the coordinates of each contour point to obtain the offset coordinates relative to the centroid. Next, a covariance matrix is ​​constructed, which describes the distribution characteristics of contour points in different directions. The covariance matrix is ​​a 2x2 symmetric matrix, where the diagonal elements represent the variance of contour points in the horizontal and vertical coordinate directions, and the off-diagonal elements represent the covariance between the two coordinate directions. Then, eigenvalue decomposition is performed on the covariance matrix, calculating its eigenvalues ​​and corresponding eigenvectors. The eigenvector corresponding to the larger eigenvalue represents the principal direction of the contour point distribution, and the eigenvector corresponding to the smaller eigenvalue represents the secondary direction. Since chip packages typically have a rectangular or approximately rectangular shape, the principal direction vector points towards the long side of the package. The rotation angle parameter is obtained by calculating the angle between the principal direction vector and the standard horizontal direction (positive horizontal axis). Specifically, the arctangent function is used to calculate the direction angle of the principal direction vector, and then compared with zero degrees to obtain the required rotation angle value.

[0032] Specifically, based on the calculated rotation angle parameters, a two-dimensional affine transformation matrix is ​​constructed to synchronously rotate the enhanced X-ray image and the package boundary segmentation mask. The two-dimensional affine transformation matrix is ​​a 3x3 matrix containing cosine and sine components of the rotation transformation, capable of mapping each pixel coordinate in the image to its new coordinate position after rotation. During the rotation transformation, the rotation center point is first determined, typically chosen as the geometric center of the image to maintain the package's centered position within the image. For the rotation processing of the enhanced X-ray image, bilinear interpolation is used to calculate the grayscale value of each pixel position after rotation. This method estimates the pixel value at the target position by weighted averaging of the four nearest neighbor pixels in the source image, with the weights determined based on the inverse relationship between the target position and the four neighboring pixels. For the rotation processing of the package boundary segmentation mask, since the mask is a binary image, nearest neighbor interpolation is used to avoid intermediate grayscale values ​​generated during interpolation, ensuring that the rotated mask retains its clear binary characteristics. After the rotation transformation is completed, a corrected image and a corrected mask at a standard horizontal position are obtained, where the main boundaries of the chip package are aligned with the horizontal and vertical directions of the image.

[0033] Specifically, after rotation correction, the bounding box of the correction mask is calculated using the minimum bounding rectangle algorithm to determine the precise range of the chip package area. The minimum bounding rectangle algorithm first extracts all boundary points of the package outline from the correction mask, and then calculates the minimum rectangular region that can completely enclose these boundary points. The algorithm iterates through the coordinates of all boundary points, finding the minimum and maximum values ​​of the x-coordinate and y-coordinate; these four extreme values ​​determine the boundary position of the bounding rectangle. Since the package boundary after rotation correction is aligned with the coordinate axes, and the sides of the minimum bounding rectangle are parallel to the coordinate axes, the calculation process is simplified. Based on the calculated rectangular region coordinates, including the coordinates of the top-left corner, the rectangle width, and the height parameters, the corresponding rectangular region is extracted from the correction image. During region extraction, to avoid boundary effects and ensure complete package information is included, appropriate margins are added outside the rectangular boundaries to expand the range of the extracted region. After extraction, the chip packaging area image is standardized by adjusting it to a predetermined standard size using bilinear interpolation. This ensures that the packaging area images of different chip samples have uniform resolution and aspect ratio, ultimately generating a standardized chip packaging area image for subsequent feature extraction and defect identification.

[0034] 103. Input the chip packaging area image into a pre-trained dual-stream feature extraction network, and extract and fuse the defect morphology features and boundary features of the chip packaging area image through the dual-stream feature extraction network to obtain the corresponding fused multidimensional feature map; In one embodiment of the present invention, the step of inputting the chip packaging region image into a pre-trained dual-stream feature extraction network, and extracting and fusing defect morphology features and boundary features of the chip packaging region image through the dual-stream feature extraction network to obtain a corresponding fused multidimensional feature map includes: inputting the chip packaging region image into a pre-trained dual-stream feature extraction network, the dual-stream feature extraction network including a defect segmentation stream, a boundary awareness stream, and a feature-related cross-gating module; performing global context analysis on the chip packaging region image through the encoder in the defect segmentation stream using multiple preset scanning paths to extract multi-scale defect morphology features to obtain a defect morphology feature map; performing density jump detection processing on the chip packaging region image through the boundary awareness stream to extract density transition information between the solder layer and the substrate material to obtain a boundary feature map; inputting the defect morphology feature map and the boundary feature map into the feature-related cross-gating module, calculating the correlation weight between the defect shape feature and the boundary feature intensity through a cross-attention mechanism; and performing weighted fusion processing on the defect morphology feature map and the boundary feature map according to the correlation weight to obtain a fused multidimensional feature map.

[0035] Specifically, standardized chip packaging region images are input into a pre-trained dual-stream feature extraction network for processing. This network employs a parallel dual-stream architecture, comprising three main components: a defect segmentation stream, a boundary-aware stream, and a feature-related cross-gating module. The defect segmentation stream is specifically responsible for identifying and segmenting various types of packaging defects, the boundary-aware stream focuses on detecting density variation features at material interfaces, and the feature-related cross-gating module is responsible for intelligently fusing the features from the two streams. At the start of processing, the chip packaging region image undergoes preprocessing operations, including pixel value normalization and data format conversion, to ensure that the input data meets the requirements of the pre-trained model. Subsequently, the image data is simultaneously distributed to the two parallel branches, the defect segmentation stream and the boundary-aware stream, for independent feature extraction processing.

[0036] Specifically, the defect segmentation stream employs a Vision State Space-based encoder architecture to perform global context analysis and multi-scale feature extraction on the chip packaging region image. The encoder first serializes the input image pixel by pixel along four preset scanning paths: diagonal scanning from top left to bottom right, anti-diagonal scanning from top right to bottom left, horizontal scanning from left to right, and vertical scanning from top to bottom. During pixel serialization, each scanning path converts the two-dimensional image into a one-dimensional pixel sequence, preserving the spatial adjacency between pixels. Next, a state-space modeling algorithm processes each pixel sequence, establishing long-distance dependencies between pixels through a recursive state update mechanism. The state-space model includes a state transition matrix and an observation matrix. The state transition matrix describes the correlation strength between adjacent pixels, while the observation matrix maps the hidden states to the feature representation space. During state updates, the hidden state of the current pixel depends not only on its own pixel value but also on the cumulative influence of preceding pixels along the scanning path, thus capturing global context information. By fusing the state sequences from the four scanning paths, a feature representation containing global spatial relationships is obtained. Subsequently, the fused feature representations are remapped into a two-dimensional feature map format and further processed by a multi-scale convolution module to generate multi-scale feature maps containing defect morphology information at different levels, and finally output the defect morphology feature map.

[0037] Specifically, the boundary-aware flow is designed for density transition detection at material interfaces in chip packaging. This flow first performs multi-directional gradient calculations on the input chip packaging region image, using the Sobel, Prevet, and Laplacian operators to calculate the gradient responses in the horizontal, vertical, and diagonal directions, respectively. The Sobel operator calculates the weighted gradient of the pixel neighborhood using a 3x3 convolution kernel, effectively detecting edge information and suppressing noise interference. After gradient calculation, potential material interface locations are identified through gradient magnitude and direction analysis, with particular attention to the density transition region between the solder layer and the substrate material. Next, a non-maximum suppression algorithm is applied to refine the gradient response. This algorithm searches for local maxima along the gradient direction and suppresses responses in non-edge directions, resulting in more accurate boundary localization. Subsequently, a dual-threshold edge connection method is used to convert the gradient response into continuous boundary segments. A high threshold is used to identify strong edge points, and a low threshold is used to connect weak edge points, forming a complete boundary contour. During density transition information extraction, the density change rate and direction at each boundary point are calculated, and the degree of density transition is quantified by analyzing the grayscale differences between adjacent pixels. Finally, all boundary information is integrated into a boundary feature map, which highlights the interface position and density transition characteristics between different components such as solder layers, metal wires, and substrate materials.

[0038] Specifically, the feature-related cross-gating module receives feature maps from the defect segmentation stream and the boundary-aware stream, and calculates the correlation weights between the two types of features through a cross-attention mechanism. This module first performs dimensional alignment on the input defect morphology feature map and boundary feature map to ensure that the two feature maps have the same spatial resolution and number of channels. Next, it calculates the correlation matrix between features through a query-key-value attention mechanism, where the defect morphology feature serves as the query vector, and the boundary features serve as the key and value vectors. During the attention calculation process, the feature map is first transformed into three representation spaces—query, key, and value—through a linear transformation. Then, the dot product similarity between the query vector and the key vector is calculated to obtain the attention score matrix. This matrix describes the correlation strength between each defect morphology feature and the boundary feature; high-correlation regions correspond to locations where the defect overlaps with or is adjacent to the material interface. Subsequently, the attention score is normalized by mapping the score to a probability range of zero to one using a softmax function, forming a correlation weight distribution. Based on the calculated correlation weights, the module performs weighted fusion processing on the defect morphology feature map and the boundary feature map, employing a combination of channel-level and spatial-level attention mechanisms. Channel-level attention calculates the importance weight of each feature channel through global average pooling and fully connected layers, while spatial-level attention calculates the weight distribution at each spatial location. Finally, a weighted summation operation merges the two feature maps into a unified multidimensional feature representation. This fused feature map simultaneously contains morphological information of defects and boundary information of material interfaces, providing rich feature inputs for subsequent defect assessment and reliability determination.

[0039] Furthermore, the step of performing global context analysis on the chip packaging area image using the encoder in the defect segmentation stream along multiple preset scanning paths to extract multi-scale defect morphology features and obtain a defect morphology feature map includes: inputting the chip packaging area image into the encoder in the defect segmentation stream, and serializing the image pixels according to four preset scanning paths: top left to bottom right, top right to bottom left, bottom left to top right, and bottom right to top left, to obtain a multi-directional pixel sequence; performing hidden state calculation and state transition processing on the multi-directional pixel sequence using a state space modeling algorithm to establish long-distance dependencies between pixels, and obtaining a serialized feature representation containing global context information; remapping the serialized feature representation into a two-dimensional feature map format, and performing feature extraction and fusion processing at different resolutions using multi-scale convolutional kernels to obtain a multi-level defect morphology representation; and performing feature mapping and channel adjustment processing on the multi-level defect morphology representation using a convolutional neural network to obtain a defect morphology feature map.

[0040] Specifically, in the encoder processing stage of the defect segmentation stream, the chip packaging area image is first input into an encoder based on the Vision State Space architecture for global context analysis. This encoder employs a multi-directional scanning strategy to serialize the two-dimensional image, converting spatially distributed pixel information into temporal sequence data. The specific scanning path includes four preset directions: top-left to bottom-right main diagonal scanning, top-right to bottom-left anti-diagonal scanning, bottom-left to top-right reverse main diagonal scanning, and bottom-right to top-left reverse anti-diagonal scanning. During the top-left to bottom-right scanning process, starting from the top-left pixel of the image, each pixel is traversed sequentially along the diagonal direction. The single pixel on the first diagonal is processed first, then the two pixels on the second diagonal, and so on until the center diagonal, gradually decreasing to the single pixel at the bottom-right corner. The top-right to bottom-left scanning uses the opposite diagonal direction, traversing pixels along the anti-diagonal direction starting from the top-right corner. The bottom-left to top-right and bottom-right to top-left scanning use opposite starting positions and scanning directions, forming four complementary scanning modes. Each scan path converts a two-dimensional image into a one-dimensional pixel sequence while preserving the relative positional relationships and adjacency information between pixels, thus providing multi-angle spatial information input for subsequent sequence modeling.

[0041] Specifically, after pixel serialization, a state-space modeling algorithm is used to calculate hidden states and process state transitions in the pixel sequences of four directions. The state-space model adopts the mathematical framework of linear time-invariant systems, containing four core parameters: the state transition matrix, the input matrix, the output matrix, and the feedforward matrix. During the hidden state calculation, the hidden state of each pixel position depends not only on the current pixel's observation value but also on the cumulative influence of the states of previous pixels in the scan sequence. The state transition matrix describes the state transfer rules between adjacent pixels; this matrix is ​​learned and trained, and can adaptively adjust the correlation strength between different pixels. The input matrix maps the pixel's grayscale value to the hidden state space, while the output matrix converts the hidden state into a feature representation. In the recursive calculation of state updates, the hidden state at the current time step is calculated by combining the hidden state at the previous time step with the input value of the current pixel through matrix multiplication. Due to the parallel computing characteristics of the state-space model, the sequence processing in the four scan directions is performed simultaneously, with each direction generating an independent hidden state sequence. Subsequently, an attention fusion mechanism is used to integrate the hidden state sequences of the four directions, calculate the importance weights between different directions, and obtain a comprehensive serialized feature representation through weighted averaging. This feature representation contains global contextual information obtained from multiple spatial directions, enabling it to capture long-distance dependencies and complex spatial patterns between pixels.

[0042] Specifically, after obtaining the serialized feature representation, it needs to be remapped into a two-dimensional feature map format for subsequent convolutional processing. The mapping process employs a learnable reshaping transformation, converting the one-dimensional sequential features back to a two-dimensional spatial layout through a linear projection layer. During reshaping, the spatial dimensional relationships of the original image are preserved, ensuring that the feature information at each pixel location correctly corresponds to the corresponding position in the two-dimensional feature map. After reshaping, a multi-scale convolutional module further extracts and fuses features from the two-dimensional feature map. The multi-scale convolutional module contains three parallel convolutional branches, using 3x3, 5x5, and 7x7 convolutional kernels respectively. These different kernel sizes capture feature patterns within different receptive fields. The 3x3 kernel primarily extracts local detail features, such as the edges and texture information of small defects. The 5x5 kernel captures medium-range feature patterns, suitable for detecting medium-sized defect regions. The 7x7 kernel focuses on a larger range of contextual information, helping to identify large defects and complex spatial patterns. Each convolutional branch contains multiple convolutional layers, progressively extracting higher-level semantic information through layer-by-layer feature abstraction. In the feature fusion stage, the outputs of the three branches are combined through channel concatenation, and then dimension adjustment and feature integration are performed through one-to-one convolution to obtain a unified multi-level defect morphology representation.

[0043] Specifically, the final stage uses a specially designed convolutional neural network to perform feature mapping and channel adjustment processing on the multi-level defect morphology representation. This network contains multiple residual connection blocks and channel attention modules. The residual connection blocks avoid the gradient vanishing problem of deep networks through a skip connection mechanism, while preserving multi-scale information of the features. Each residual block contains two 3x3 convolutional layers, with batch normalization and ReLU activation functions inserted in between, and finally, the input is directly added to the output through residual connections. The channel attention module calculates the importance weight of each feature channel through global average pooling and fully connected layers. This module first performs global average pooling on each channel to obtain a channel-level global feature descriptor, and then calculates the attention weights through two fully connected layers. The first layer performs dimensionality reduction to reduce computational complexity, and the second layer restores the original number of channels and outputs weight values ​​between zero and one through a sigmoid activation function. The calculated channel weights are then multiplied element-wise with the original feature map to highlight the feature responses of important channels and suppress noise interference from irrelevant channels. Through the cascaded processing of multiple residual blocks and channel attention modules, the network gradually refines the feature representation and enhances the expressive power of defect-related features. Finally, a 1x1 convolutional layer is used to adjust the number of channels, standardizing the channel dimension of the feature map to the preset output size, generating the final defect morphology feature map, which contains rich multi-scale defect morphology information and global contextual relationships.

[0044] 104. Input the fused multidimensional feature map into the pre-trained defect evaluation network, and use the defect evaluation network to calculate defect parameters and determine reliability of the fused multidimensional feature map to obtain the corresponding defect identification result.

[0045] In one embodiment of the present invention, the step of inputting the fused multidimensional feature map into a pre-trained defect evaluation network, and using the defect evaluation network to calculate defect parameters and determine reliability of the fused multidimensional feature map to obtain the corresponding defect identification result includes: inputting the fused multidimensional feature map into the pre-trained defect evaluation network, extracting defect regions from the fused multidimensional feature map and calculating geometric parameters through the defect evaluation network, determining the region type of the defect region based on the defect location in the geometric parameters; calling a preset chip package three-dimensional thermal conduction model, inputting the area and location information of the defect region into the three-dimensional thermal conduction model to perform heat flow distribution simulation calculation, and obtaining the contribution value of each defect region to the overall thermal resistance; weighting the contribution value according to the defect region type, calculating the overall reliability score, and selecting a judgment threshold according to the chip application level to determine the pass / fail status, thereby obtaining the defect identification result.

[0046] Specifically, the fused multi-dimensional feature map is input into a pre-trained defect assessment network for comprehensive analysis and reliability determination. This network employs a multi-branch architecture, comprising three main components: a defect segmentation branch, a geometric parameter calculation branch, and a region classification branch. The defect segmentation branch first performs semantic segmentation on the fused feature map, generating a pixel-level defect probability map through multi-layer convolution and upsampling operations. The value of each pixel in this probability map represents the probability that the location belongs to a defect region. Next, the probability map is converted into a binary mask through threshold segmentation, with a probability threshold set to 0.5. Pixels above this threshold are marked as defect regions, and pixels below the threshold are marked as normal regions. Subsequently, a connected component analysis algorithm is applied to post-process the binary mask, identifying independent defect regions and assigning them unique identifiers. The geometric parameter calculation branch performs detailed geometric analysis on each identified defect region, calculating multiple geometric parameters including area, perimeter, major axis length, minor axis length, eccentricity, circularity, and convex hull area. Area is calculated by counting the number of pixels within the defect region and multiplying it by the physical size of each pixel. Perimeter is calculated using a boundary tracking algorithm, measuring along the contour of the defect region. The lengths of the major and minor axes are calculated using principal component analysis to determine the projected lengths of the defect region in the primary and secondary directions. The eccentricity is reflected by the ratio of the major and minor axes to indicate the slenderness of the defect shape.

[0047] Specifically, the region classification branch determines the type of defect region based on the defect location information in the calculated geometric parameters. This branch first establishes a functional area division map of the chip package, dividing the package space into three levels: critical areas, important areas, and general areas. Critical areas include the core functional units, main signal transmission paths, and power distribution networks—the parts that have the greatest impact on chip performance. Important areas include secondary signal lines, auxiliary functional modules, and heat dissipation channels—areas that significantly affect chip functionality. General areas include package edges, non-functional fill areas, and mechanical support structures—the parts that have a relatively smaller impact on chip performance. The classification process uses a spatial location matching algorithm to compare the centroid coordinates of each defect region with the functional area division map to determine the functional area type of the defect. For large defects spanning multiple functional areas, an area weighting method is used to calculate the area proportion of the defect in different functional areas, assigning the defect to the functional area type with the largest proportion. The classification results, together with the defect's geometric parameters, constitute complete defect description information, providing basic data for subsequent thermal conductivity analysis and reliability assessment.

[0048] Specifically, after extracting and classifying defect areas, a pre-defined 3D thermal conductivity model of the chip package is used to simulate heat flow distribution. This model is built based on the finite element method and includes the 3D geometry of the chip package, material thermal properties, and boundary condition settings. The 3D geometry accurately describes the spatial distribution and dimensional parameters of various components such as the chip die, solder layer, substrate, and heat sink. The material thermal properties include key parameters such as thermal conductivity, specific heat capacity, and density of various materials. The boundary condition settings include necessary conditions for heat conduction analysis such as heat source power distribution, ambient temperature, and convective heat transfer coefficient. During the simulation calculation, the identified defect area information is first imported into the 3D model, including the spatial location, area size, and shape parameters of the defects. For void defects, the thermal conductivity of the corresponding area is set to a value close to zero in the model to simulate the situation where heat flow cannot pass through the area. For crack defects, thermal resistance values ​​are set on the crack path to simulate the blocking effect of heat flow transmission. For material delamination defects, the contact thermal resistance parameters of the corresponding area are adjusted to reflect the decrease in thermal conductivity. Subsequently, a finite element method (FEM) was run to perform steady-state thermal conduction analysis, calculating the temperature distribution and heat flux density distribution of the entire package structure. By comparing the thermal conduction analysis results with and without defects, the contribution of each defect region to the overall thermal resistance was calculated, reflecting the degree of impact of defects on the chip's thermal management performance.

[0049] Specifically, in the final stage, the thermal resistance contribution values ​​are weighted according to the defect region type to calculate the overall reliability score and perform a pass / fail determination. The weighting process considers the differences in the impact of defects in different functional regions on chip reliability. The contribution value of defects in critical regions is multiplied by a weighting coefficient of 1.0 to maintain the original level of influence; the contribution value of defects in important regions is multiplied by a weighting coefficient of 0.7 to moderately reduce their influence weight; and the contribution value of defects in general regions is multiplied by a weighting coefficient of 0.3 to significantly reduce their influence weight. After the weighted calculation is completed, the weighted contribution values ​​of all defects are summed to obtain the overall thermal resistance increment value, which reflects the comprehensive impact of all defects on the overall thermal management performance of the chip. Next, the thermal resistance increment value is converted into a reliability score from zero to one hundred using a reliability scoring algorithm. A higher score indicates better thermal reliability of the chip. The conversion process uses a nonlinear mapping function, considering the nonlinear relationship between thermal resistance increment and reliability degradation. The appropriate threshold is selected based on the chip's application level for qualification assessment. High-end application chips, such as server processors and graphics processors, require a reliability score of no less than 90; mid-range application chips, such as those in consumer electronics, require no less than 80; and low-end application chips, such as simple controllers, require no less than 70. By comparing the calculated reliability score with the corresponding qualification threshold, the final defect identification result is output, including complete information such as the number of defects, their location distribution, severity, and qualification status.

[0050] In this embodiment, the input chip package X-ray image is enhanced using multi-level enhancement processing based on the material density differences of different materials in the chip package, resulting in an enhanced X-ray image with optimized material properties. The enhanced X-ray image is then input into a pre-trained image segmentation network for package boundary recognition and rotation correction, yielding a chip package region image. This image is then input into a pre-trained dual-stream feature extraction network for defect morphology and boundary feature extraction and fusion, resulting in a fused multi-dimensional feature map. Finally, the fused multi-dimensional feature map is input into a pre-trained defect evaluation network for defect parameter calculation and reliability determination, yielding the defect identification result. This invention, through multi-level image enhancement and multi-network collaborative processing, can accurately identify various defect types in chip packages, significantly improving the accuracy and reliability of defect detection.

[0051] The chip defect identification method in the embodiments of the present invention has been described above. The chip defect identification system in the embodiments of the present invention is described below. Please refer to [link / reference]. Figure 2 One embodiment of the chip defect identification system in this invention includes: Image enhancement module 201 is used to perform multi-level enhancement processing on the input chip package X-ray image based on the material density difference of different materials in the chip package, so as to obtain an enhanced X-ray image with optimized material properties; The boundary segmentation module 202 is used to input the enhanced X-ray image into a pre-trained image segmentation network, and to perform encapsulation boundary recognition and rotation correction on the enhanced X-ray image through the image segmentation network to obtain the corresponding chip encapsulation region image; The feature extraction module 203 is used to input the chip packaging area image into a pre-trained dual-stream feature extraction network, and to extract and fuse the defect morphology features and boundary features of the chip packaging area image through the dual-stream feature extraction network to obtain the corresponding fused multidimensional feature map. The defect evaluation module 204 is used to input the fused multidimensional feature map into a pre-trained defect evaluation network, and to calculate the defect parameters and determine the reliability of the fused multidimensional feature map through the defect evaluation network to obtain the corresponding defect identification result.

[0052] In this embodiment of the invention, the chip defect identification system operates the aforementioned chip defect identification method. The system performs multi-level enhancement processing on the input chip package X-ray image based on the material density differences of different materials within the chip package, obtaining an enhanced X-ray image with optimized material properties. The enhanced X-ray image is then input into a pre-trained image segmentation network for package boundary recognition and rotation correction, yielding a chip package region image. This image is then input into a pre-trained dual-stream feature extraction network for defect morphology and boundary feature extraction and fusion, resulting in a fused multi-dimensional feature map. Finally, the fused multi-dimensional feature map is input into a pre-trained defect evaluation network for defect parameter calculation and reliability determination, yielding the defect identification result. This invention, through multi-level image enhancement and multi-network collaborative processing, can accurately identify various defect types in chip packages, significantly improving the accuracy and reliability of defect detection.

[0053] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0054] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0055] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip defect identification method, characterized in that, The chip defect identification method includes: Based on the material density differences of different materials in the chip package, the input chip package X-ray image is enhanced in multiple layers to obtain an enhanced X-ray image with optimized material properties. An enhanced X-ray image is input into a pre-trained image segmentation network. The image segmentation network is used to perform packaging boundary recognition and rotation correction on the enhanced X-ray image to obtain the corresponding chip packaging region image. The chip packaging area image is input into a pre-trained dual-stream feature extraction network. The dual-stream feature extraction network extracts and fuses the defect morphology features and boundary features of the chip packaging area image to obtain the corresponding fused multidimensional feature map. The fused multidimensional feature map is input into a pre-trained defect evaluation network. The defect evaluation network calculates defect parameters and determines reliability of the fused multidimensional feature map to obtain the corresponding defect identification result.

2. The chip defect identification method according to claim 1, characterized in that, The process of performing multi-level enhancement processing on the input chip package X-ray image based on the material density differences of different materials in the chip package to obtain an enhanced X-ray image with optimized material properties includes: The preset X-ray attenuation coefficient lookup table for chip packaging materials is invoked, and material regions are identified for different grayscale value ranges of the input chip packaging X-ray image based on the differences in attenuation coefficients of different materials in the X-ray attenuation coefficient lookup table. The high-density metal region, medium-density ceramic region and low-density defect region identified in the X-ray image of the chip package are processed by corresponding enhancement strategies to obtain a layered enhanced image. The preset welding area recognition algorithm is used to calculate the density gradient vector field between the solder and the substrate material in the pixel neighborhood of the chip package X-ray image to locate the welding layer boundary and obtain the region of interest mask. The layered enhanced image is fused according to the region of interest mask to obtain an enhanced X-ray image with optimized material properties.

3. The chip defect identification method according to claim 1, characterized in that, The step of inputting the enhanced X-ray image into a pre-trained image segmentation network, and then using the image segmentation network to perform packaging boundary recognition and rotation correction on the enhanced X-ray image to obtain the corresponding chip packaging region image includes: An enhanced X-ray image is input into a pre-trained image segmentation network, wherein the image segmentation network includes an encoder module, a rectangular spatial attention module, and a decoder module; The encoder module performs multi-layer convolution and downsampling processing on the enhanced X-ray image to extract multi-scale feature maps. The multi-scale feature map is input into the rectangular spatial attention module, and attention weights are calculated in the vertical and horizontal directions through 7×1 and 1×7 depth-separable strip convolutions to obtain a spatial attention weight map. The multi-scale feature map is weighted according to the spatial attention weight map, and then upsampled and fused through the decoder module to obtain the encapsulation boundary segmentation mask. The enhanced X-ray image is rotated and corrected according to the packaging boundary segmentation mask to obtain the corresponding chip packaging area image.

4. The chip defect identification method according to claim 3, characterized in that, The step of rotating and correcting the enhanced X-ray image based on the package boundary segmentation mask to obtain the corresponding chip package region image includes: Based on the encapsulation boundary segmentation mask, the encapsulation boundary contour line is extracted from the enhanced X-ray image to obtain the boundary contour coordinate set; The principal component analysis algorithm is used to calculate the angle between the principal direction vector of the encapsulated boundary contour line and the standard horizontal direction on the boundary contour coordinate set, thus obtaining the rotation angle parameter; A two-dimensional affine transformation matrix is ​​constructed based on the rotation angle parameters, and the enhanced X-ray image and the encapsulation boundary segmentation mask are simultaneously subjected to rotation transformation processing to obtain a corrected image and a corrected mask at a standard horizontal position. The bounding box of the correction mask is calculated using the minimum bounding rectangle algorithm. Based on the calculated rectangular region coordinates, the corresponding region is extracted from the correction image and its size is standardized to obtain the chip packaging region image.

5. The chip defect identification method according to claim 1, characterized in that, The step involves inputting the chip packaging region image into a pre-trained dual-stream feature extraction network. The dual-stream feature extraction network then extracts and fuses defect morphology features and boundary features from the chip packaging region image to obtain a corresponding fused multidimensional feature map, including: The chip packaging area image is input into a pre-trained dual-stream feature extraction network, which includes a defect segmentation stream, a boundary-aware stream, and a feature-related cross-gating module. The encoder in the defect segmentation stream performs global context analysis on the chip packaging area image using multiple preset scanning paths to extract multi-scale defect morphology features and obtain a defect morphology feature map. The boundary-aware flow is used to perform density jump detection processing on the chip packaging area image to extract density transition information between the solder layer and the substrate material, thereby obtaining a boundary feature map. The defect morphology feature map and boundary feature map are input into the feature correlation cross-gating module, and the correlation weight between the defect shape feature and the boundary feature intensity is calculated through the cross attention mechanism. The defect morphology feature map and boundary feature map are weighted and fused according to the correlation weight to obtain a fused multidimensional feature map.

6. The chip defect identification method according to claim 5, characterized in that, The step of performing global context analysis on the chip packaging region image using the encoder in the defect segmentation stream along multiple preset scanning paths to extract multi-scale defect morphology features and obtain a defect morphology feature map includes: The chip packaging area image is input into the encoder in the defect segmentation stream. The image pixels are serialized according to four preset scanning paths: top left to bottom right, top right to bottom left, bottom left to top right, and bottom right to top left, to obtain a multi-directional pixel sequence. The hidden state calculation and state transition processing of the multi-directional pixel sequence are performed by the state space modeling algorithm to establish long-distance dependencies between pixels and obtain a serialized feature representation containing global context information. The serialized feature representation is remapped into a two-dimensional feature map format, and features at different resolutions are extracted and fused using multi-scale convolutional kernels to obtain a multi-level defect morphology representation. The multi-level defect morphology representation is processed by feature mapping and channel adjustment using a convolutional neural network to obtain a defect morphology feature map.

7. The chip defect identification method according to claim 1, characterized in that, The step of inputting the fused multidimensional feature map into a pre-trained defect evaluation network, and using the defect evaluation network to calculate defect parameters and determine reliability of the fused multidimensional feature map to obtain the corresponding defect identification result includes: The fused multidimensional feature map is input into a pre-trained defect evaluation network. The defect evaluation network extracts the defect region from the fused multidimensional feature map and calculates the geometric parameters. The region type of the defect region is determined based on the defect location in the geometric parameters. The preset three-dimensional thermal conduction model of the chip package is invoked, and the area and location information of the defective region are input into the three-dimensional thermal conduction model to perform heat flow distribution simulation calculation, so as to obtain the contribution value of each defective region to the overall thermal resistance. The contribution values ​​are weighted according to the defect region type to calculate the overall reliability score. A judgment threshold is selected based on the chip application level to determine the pass / fail status and obtain the defect identification result.

8. A chip defect identification system, characterized in that, The chip defect identification system includes: The image enhancement module is used to perform multi-level enhancement processing on the input chip package X-ray image based on the material density differences of different materials in the chip package, so as to obtain an enhanced X-ray image with optimized material properties. The boundary segmentation module is used to input the enhanced X-ray image into a pre-trained image segmentation network, and to perform encapsulation boundary recognition and rotation correction on the enhanced X-ray image through the image segmentation network to obtain the corresponding chip encapsulation region image; The feature extraction module is used to input the chip packaging area image into a pre-trained dual-stream feature extraction network, and to extract and fuse the defect morphology features and boundary features of the chip packaging area image through the dual-stream feature extraction network to obtain the corresponding fused multidimensional feature map. The defect assessment module is used to input the fused multidimensional feature map into a pre-trained defect assessment network, and to calculate the defect parameters and determine the reliability of the fused multidimensional feature map through the defect assessment network to obtain the corresponding defect identification result.

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