Dual-port random access memory

Abstract

The invention relates to the technical field of integrated circuits, and discloses a dual-port random access memory. The dual-port random access memory comprises a first clock signal end, a second clock signal end, a first access end, a second access end, a first output end, a second output end, a control selection unit, a single-port random access memory and a latch holding unit. The control selection unit is connected with the first clock signal end, the second clock signal end, the first access end, the second access end and the single-port random access memory, and selectively outputs a signal of the first access end or a signal of the second access end to the single-port random access memory according to the first clock signal and the second clock signal; the second clock signal is synchronized with the first clock signal, and a frequency of the second clock signal is twice a frequency of the first clock signal. The two ports of the dual-port RAM can be operated completely independently without mutual restriction, and the dual-port RAM is small in area, low in cost and wider in application range.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a dual-port random access memory. Background Technology

[0002] Dual-port Random Access Memory (RAM) is frequently used in integrated circuit design due to functional requirements. Dual-port RAM, with its two independent and parallel read / write ports, plays a crucial role in multiprocessor systems, real-time control, and high-speed data acquisition and exchange. Dual-port RAM allows two independent devices or modules to access it simultaneously, improving data throughput and reducing communication latency. It is widely used, especially in embedded systems, industrial control, and communication equipment requiring parallel processing and real-time response. Compared to single-port RAM, dual-port RAM achieves true parallel operation through independent address, data, and control lines, avoiding read / write conflicts and overcoming the performance bottleneck of single-port RAM under time-sharing. However, traditionally, the chip area of ​​dual-port RAM with the same storage capacity is often twice that of single-port RAM, or even more.

[0003] In one related technical solution, a pseudo-dual-port RAM is implemented using a single-port RAM. Specifically, a single-port RAM is used, and the read and write data are buffered through the read FIFO module and write First In First Out (FIFO) module of a Field Programmable Gate Array (FPGA) chip. An arbitration mechanism is added to realize a pseudo-dual-port RAM. However, this technical solution has significant limitations. It can only realize continuous read and write, and cannot realize random read and write of dual-port RAM.

[0004] In another related technical solution, a mapping logic circuit module including a general synchronous single-port static random access memory and multiple input multiple output terminals is designed. The signal ports of the synchronous dual-port SRAM are connected to the corresponding functional ports of the synchronous single-port static random access memory (SRAM) through the logic circuit, thereby realizing the mapping of signal ports. In other words, the function of synchronous dual-port SRAM is realized based on single-port SRAM. However, the two ports in this technical solution cannot operate completely independently and will restrict each other, so it cannot realize a true dual-port RAM. Summary of the Invention

[0005] This application provides a dual-port random access memory. The technical solution of this application can implement the random read / write function of a dual-port RAM using a single-port RAM. Furthermore, the two ports of the dual-port RAM implemented in this application can operate completely independently without any mutual constraint. Moreover, the dual-port RAM implemented in this application has a small area, low cost, and a wider range of applications.

[0006] In a first aspect, this application provides a dual-port random access memory, comprising: The system includes a first clock signal terminal, a second clock signal terminal, a first access terminal, a second access terminal, a first output terminal, a second output terminal, a control selection unit, a single-port random access memory, and a latch and hold unit. The control selection unit is connected to the first clock signal terminal, the second clock signal terminal, the first access terminal, the second access terminal, and the single-port random access memory. The control selection unit is used to select whether to output the signal of the first access terminal or the signal of the second access terminal to the single-port random access memory according to the first clock signal of the first clock signal terminal and the second clock signal of the second clock signal terminal. The second clock signal is synchronized with the first clock signal, and the frequency of the second clock signal is twice the frequency of the first clock signal. The single-port random access memory is connected between the control selection unit and the latch holding unit. The single-port random access memory is used to output the data to be read by the first access terminal and the second access terminal, or to write the data to be written by the first access terminal and the second access terminal within the same first clock cycle. The first clock cycle is the clock cycle of the first clock signal. The clock signal of the single-port random access memory adopts the same timing characteristics as the second clock signal. The latch and hold unit is connected to the single-port random access memory, the control selection unit, the first output terminal, and the second output terminal. The latch and hold unit is used to latch and hold the data from the first access terminal and the data from the second access terminal output by the single-port random access memory in the same first clock cycle, and then output them through the first output terminal and the second output terminal respectively.

[0007] In one possible implementation of the first aspect, the control selection unit includes a control signal generator and a signal selector. The control signal generator is connected to the first clock signal terminal, the second clock signal terminal, the signal selector, and the latch-and-hold unit. The control signal generator is used to generate a selection signal based on the first clock signal of the first clock signal terminal and the second clock signal of the second clock signal terminal, and output the selection signal to the signal selector and the latch-and-hold unit. This allows the signal selector to select either the signal of the first access terminal or the signal of the second access terminal to be output to the single-port random access memory (SRAM) based on the selection signal. The latch-and-hold unit also uses the selection signal to latch and hold the data from the first access terminal and the data from the second access terminal output by the SRAM within the same first clock cycle.

[0008] In one possible implementation of the first aspect, the control signal generator includes a first D flip-flop, a second D flip-flop, a first inverter, and an XOR gate. The clock input of the first D flip-flop is connected to the first clock signal terminal, the data input of the first D flip-flop is connected to the output of the first inverter, the output of the first D flip-flop is connected to the input of the first inverter, the data input of the second D flip-flop, and one of the inputs of the XOR gate, the clock input of the second D flip-flop is connected to the second clock signal terminal, and the output of the second D flip-flop is connected to the other input of the XOR gate, so that the output of the XOR gate outputs the selection signal. The selection signal is a pre-high-level symmetrical square wave, and the clock period of the selection signal is the same as the clock period of the first clock signal.

[0009] In one possible implementation of the first aspect, the first access terminal includes a first enable terminal, and the second access terminal includes a second enable terminal. The signal selector includes a second inverter, a first AND gate, a second AND gate, and an OR gate. The input of the second inverter is connected to the output of the control signal generator, the output of the second inverter is connected to one input of the first AND gate, the other input of the first AND gate is connected to the second enable terminal, and the output of the first AND gate is connected to one input of the OR gate. One input of the second AND gate is connected to the output of the control signal generator, the other input of the second AND gate is connected to the first enable terminal, and the output of the second AND gate is connected to the other input of the OR gate, so that the output of the OR gate outputs an enable signal.

[0010] In one possible implementation of the first aspect, the latch-and-hold unit includes a third D flip-flop, a first latch, and a second latch. The third D flip-flop is connected between the control signal generator, the first latch, and the second latch. The third D flip-flop delays the selection signal by a second clock cycle to obtain a latch control signal. The latch control signal controls the first latch to latch and hold the data at the first access terminal of the single-port random access memory, and controls the second latch to latch and hold the data at the second access terminal of the single-port random access memory. The second clock cycle is the clock cycle of the second clock signal. The input terminals of the first latch and the second latch are both connected to the output terminal of the third D flip-flop, the output terminal of the single-port random access memory, and the second clock signal terminal. The output terminal of the first latch is connected to the first output terminal, and the output terminal of the second latch is connected to the second output terminal. The first latch is used to output the data of the first access terminal output by the single-port random access memory within the same first clock cycle through the first output terminal. The second latch is used to output the data of the second access terminal output by the single-port random access memory within the same first clock cycle through the second output terminal.

[0011] In one possible implementation of the first aspect, the clock input of the third D flip-flop is connected to the output of the control signal generator, the output of the third D flip-flop is connected to the first input of the first latch and the first input of the second latch; the second input of the first latch and the second input of the second latch are both connected to the output of the single-port random access memory, and the third input of the first latch and the third input of the second latch are both connected to the second clock signal terminal.

[0012] In one possible implementation of the first aspect, the first latch includes a first selector and a fourth D flip-flop, wherein the latch control terminal of the first selector is connected to the output terminal of the third D flip-flop, one input terminal of the first selector is connected to the output terminal of the single-port random access memory, the other input terminal of the first selector is connected to the first output terminal, the output terminal of the first selector is connected to the data input terminal of the fourth D flip-flop, the clock input terminal of the fourth D flip-flop is connected to the second clock signal terminal, and the output terminal of the fourth D flip-flop is connected to the first output terminal.

[0013] In one possible implementation of the first aspect, the data output by the first latch is delayed by one second clock cycle relative to the data output by the single-port random access memory, and the data output by the first latch remains unchanged within one first clock cycle.

[0014] In one possible implementation of the first aspect, the second latch includes a third inverter, a second selector, and a fifth D flip-flop. The input of the third inverter is connected to the output of the third D flip-flop, and the output of the third inverter is connected to the latch control terminal of the second selector. One input of the second selector is connected to the output of the single-port random access memory, and the other input of the second selector is connected to the second output. The output of the second selector is connected to the data input of the fifth D flip-flop, the clock input of the fifth D flip-flop is connected to the second clock signal terminal, and the output of the fifth D flip-flop is connected to the second output.

[0015] In one possible implementation of the first aspect, the data output by the second latch is synchronized with the data output by the single-port random access memory, and the data output by the second latch remains unchanged within one first clock cycle.

[0016] Compared with the prior art, the beneficial effects of this application are as follows: The control selection unit in the dual-port random access memory provided by this application is used to select whether to output the signal of the first access terminal or the signal of the second access terminal to the single-port random access memory according to the first clock signal of the first clock signal terminal and the second clock signal of the second clock signal terminal. The second clock signal is synchronized with the first clock signal, and the frequency of the second clock signal is twice the frequency of the first clock signal. That is to say, the second clock signal is a multiplier clock signal of the first clock signal. Thus, the gating control of the first access terminal and the second access segment can be realized using a simple clock signal. The control logic is simple and easy to implement, and it can facilitate the constraint design and timing convergence of the chip back end. This synchronization relationship between clock signals makes clock management and signal synchronization simpler and more reliable, which helps to improve the stability and reliability of dual-port RAM.

[0017] The single-port random access memory (SRAM) in this application is connected between the control selection unit and the latching unit. The SRAM is used to output data to be read from the first access terminal and the second access terminal, or to write data to be written to the first access terminal and the second access terminal, within the same first clock cycle. The first clock cycle is the clock cycle of the first clock signal, and the clock signal of the SRAM adopts the same timing characteristics as the second clock signal. The latching unit is connected to the SRAM, the control selection unit, and the first and second output terminals. The latching unit is used to latch and hold the data from the first access terminal and the data from the second access terminal output by the SRAM within the same first clock cycle, and then output them through the first and second output terminals respectively. In other words, the data output from the output terminal of the single-port random access memory is latched and held by the latch-and-hold unit and then output through the two output terminals respectively. Thus, the first access terminal and the second access terminal can perform read or write operations on the single-port random access memory within a first clock cycle. The dual-port RAM implemented in this application completely simulates the interface timing of conventional dual-port RAM. The two ports can be accessed simultaneously using random addresses independently without any mutual constraints.

[0018] The technical solution of this application can realize the function of dual-port RAM by using only a single-port RAM, a control selection unit, a latch and hold unit, and two synchronous clock signals. Compared with the existing dual-port RAM, the dual-port RAM provided by this application is smaller in size, lower in cost, and has a wider range of applications. Attached Figure Description

[0019] Figure 1 According to some embodiments of this application, a circuit diagram of a dual-port RAM is shown; Figure 2 According to some embodiments of this application, a circuit diagram of a control signal generator is shown; Figure 3 According to some embodiments of this application, a circuit diagram of a signal selector is shown; Figure 4 According to some embodiments of this application, a circuit diagram of a first latch is shown; Figure 5 According to some embodiments of this application, a circuit diagram of a second latch is shown; Figure 6 According to some embodiments of this application, a method is shown. Figure 1 The circuit timing diagram shown illustrates how the two ports of a dual-port RAM can independently perform data reading operations. Figure 7 According to some embodiments of this application, a method is shown. Figure 1The circuit timing diagram shown illustrates how the two ports of a dual-port RAM can perform data writing operations independently. Figure 8 According to some embodiments of this application, a method is shown. Figure 1 The diagram shows the timing of a dual-port RAM circuit where data is written to one port and read from the other. Detailed Implementation

[0020] The illustrative embodiments of this application include, but are not limited to, a dual-port random access memory.

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0022] Figure 1 According to some embodiments of this application, a circuit diagram of a dual-port RAM 100 is shown. Figure 1 As shown, the dual-port RAM 100 provided in this application includes: a first clock signal terminal 11, a second clock signal terminal 12, a first access terminal 13, a second access terminal 14, a first output terminal 15, a second output terminal 16, a control selection unit 20, a single-port random access memory 30, and a latch and hold unit 40.

[0023] The control selection unit 20 is connected to the first clock signal terminal 11, the second clock signal terminal 12, the first access terminal 13, the second access terminal 14, and the single-port random access memory 30. The control selection unit 20 is used to select whether to output the signal from the first access terminal 13 or the signal from the second access terminal 14 to the single-port random access memory 30 based on the first clock signal from the first clock signal terminal 11 and the second clock signal from the second clock signal terminal 12. The second clock signal is synchronized with the first clock signal, and the frequency of the second clock signal is twice the frequency of the first clock signal. In other words, the second clock signal is a multiplier of the first clock signal. Therefore, the selection control of the first access terminal 13 and the second access terminal 14 can be achieved using a simple clock signal. The control logic is simple and easy to implement, and it facilitates the constraint design and timing convergence of the chip backend. This synchronization relationship between clock signals makes clock management and signal synchronization simpler and more reliable, helping to improve the stability and reliability of the dual-port RAM 100.

[0024] refer to Figure 1The single-port random access memory 30 is connected between the control selection unit 20 and the latch and hold unit 40. The single-port random access memory 30 is used to output data to be read from the first access terminal 13 and the second access terminal 14, or to write data to be written to the first access terminal 13 and the second access terminal 14, within the same first clock cycle. The first clock cycle is the clock cycle of the first clock signal. The clock signal of the single-port random access memory 30 adopts the same timing characteristics as the second clock signal; in other words, the clock signal used by the single-port random access memory 30 is the second clock signal.

[0025] In some embodiments, within the same first clock cycle, the first access terminal 13 and the second access terminal 14 can write data to the single-port random access memory 30. In some embodiments, within the same first clock cycle, the first access terminal 13 can write data to the single-port random access memory 30, while the second access terminal 14 reads data from the single-port random access memory 30. In some embodiments, within the same first clock cycle, the first access terminal 13 can read data from the single-port random access memory 30, while the second access terminal 14 writes data to the single-port random access memory 30. In other embodiments, within the same first clock cycle, both the first access terminal 13 and the second access terminal 14 can read data from the single-port random access memory 30, thereby completely simulating the interface timing of a conventional dual-port RAM. The two ports can independently access each other simultaneously using random addresses without any mutual constraint.

[0026] Within the same first clock cycle, the control selection unit 20 can select the first access terminal 13 and the second access terminal 14 respectively. In some embodiments, the control selection unit 20 can select the first access terminal 13 first and then the second access terminal 14; in other embodiments, the control selection unit 20 can select the second access terminal 14 first and then the first access terminal 13. In other words, within the same first clock cycle, the control selection unit 20 can select the first access terminal 13 and the second access terminal 14 alternately. The clock signal used by the first access terminal 13 and the second access terminal 14 is the first clock signal.

[0027] In some embodiments, after the first access terminal 13 is selected, it can write or read data to the single-port random access memory 30 according to the write enable signal WENA of the first access terminal 13. For example, when the write enable signal of the first access terminal 13 is low, a write operation of the first access terminal 13 is triggered, thereby writing the data on the data bus of the first access terminal 13 into the memory cell of the single-port random access memory 30 specified by the address bus ADDRA of the first access terminal 13; when the write enable signal of the first access terminal 13 is high, a read operation of the first access terminal 13 is triggered, thereby reading data from the memory cell of the single-port random access memory 30 specified by the address bus ADDRA of the first access terminal 13.

[0028] In some embodiments, after the second access terminal 14 is selected, it can write or read data to the single-port random access memory 30 according to the write enable signal WENB of the second access terminal 14. For example, when the write enable signal of the second access terminal 14 is low, a write operation of the second access terminal 14 is triggered, thereby writing the data on the data bus of the second access terminal 14 to the memory cell of the single-port random access memory 30 specified by the address bus ADDRB of the second access terminal 14; when the write enable signal of the second access terminal 14 is high, a read operation of the second access terminal 14 is triggered, thereby reading data from the memory cell of the single-port random access memory 30 specified by the address bus ADDRB of the second access terminal 14.

[0029] Continue to refer to Figure 1 The latch and hold unit 40 is connected to the single-port random access memory 30, the control selection unit 20, the first output terminal 15, and the second output terminal 16. The latch and hold unit 40 is used to latch and hold the data of the first access terminal 13 and the data of the second access terminal 14 output by the single-port random access memory 30 in the same first clock cycle, and then output them through the first output terminal 15 and the second output terminal 16 respectively.

[0030] The control selection unit 20 includes a control signal generator 21 and a signal selector 22. The control signal generator 21 is connected to a first clock signal terminal 11, a second clock signal terminal 12, the signal selector 22, and a latch-and-hold unit 40. The control signal generator 21 generates a selection signal based on the first clock signal of the first clock signal terminal 11 and the second clock signal of the second clock signal terminal 12, and outputs the selection signal to the signal selector 22 and the latch-and-hold unit 40. This allows the signal selector 22 to select the signal of the first access terminal 13 or the signal of the second access terminal 14 to be output to the single-port random access memory 30 based on the selection signal. It also allows the latch-and-hold unit 40 to latch and hold the data of the first access terminal 13 and the data of the second access terminal 14 output by the single-port random access memory 30 within the same first clock cycle using the selection signal.

[0031] exist Figure 1 In the embodiment shown, the first access terminal 13 includes a first enable terminal 131, a first chip select terminal 132, a first address terminal 133, and a first data terminal 134; the second access terminal 14 includes a second enable terminal 141, a second chip select terminal 142, a second address terminal 143, and a second data terminal 144.

[0032] exist Figure 1 In the embodiment shown, the latch holding unit 40 includes a third D flip-flop 41, a first latch 42, and a second latch 43.

[0033] The third D flip-flop 41 is connected between the control signal generator 21, the first latch 42, and the second latch 43. The third D flip-flop 41 is used to delay the selection signal by a second clock cycle to obtain a latch control signal. The latch control signal is used to control the first latch 42 to latch and hold the data output from the first access terminal 13 of the single-port random access memory 30, and the latch control signal is used to control the second latch 43 to latch and hold the data output from the second access terminal 14 of the single-port random access memory 30. The second clock cycle is the clock cycle of the second clock signal.

[0034] The input terminals 421 of the first latch 42 and 431 of the second latch 43 are both connected to the output terminal 411 of the third D flip-flop 41, the output terminal 31 of the single-port random access memory 30, and the second clock signal terminal 12. The output terminal 422 of the first latch 42 is connected to the first output terminal 15, and the output terminal 432 of the second latch 43 is connected to the second output terminal 16. The first latch 42 is used to output the data of the first access terminal 13 of the single-port random access memory 30 within the same first clock cycle through the first output terminal 15. The second latch 43 is used to output the data of the second access terminal 14 of the single-port random access memory 30 within the same first clock cycle through the second output terminal 16.

[0035] The clock input terminal 412 of the third D flip-flop 41 is connected to the output terminal 215 of the control signal generator 21. The output terminal 411 of the third D flip-flop 41 is connected to the first input terminal 4211 of the first latch 42 and the first input terminal 4311 of the second latch 43. The second input terminal 4212 of the first latch 42 and the second input terminal 4312 of the second latch 43 are both connected to the output terminal 31 of the single-port random access memory 30. The third input terminal 4213 of the first latch 42 and the third input terminal 4313 of the second latch 43 are both connected to the second clock signal terminal 12.

[0036] Figure 2 According to some embodiments of this application, a circuit diagram of a control signal generator 21 is shown, with reference to... Figure 2The control signal generator 21 includes a first D flip-flop 211, a second D flip-flop 212, a first inverter 213, and an XOR gate 214. The clock input terminal 2111 of the first D flip-flop 211 is connected to the first clock signal terminal 11. The data input terminal 2112 of the first D flip-flop 211 is connected to the output terminal 2132 of the first inverter 213. The output terminal 2113 of the first D flip-flop 211 is connected to the input terminal 2131 of the first inverter 213, the data input terminal 2121 of the second D flip-flop 212, and one of the input terminals 2141 of the XOR gate 214. The clock input terminal 2122 of the second D flip-flop 212 is connected to the second clock signal terminal 12. The output terminal 2123 of the second D flip-flop 212 is connected to the other input terminal 2142 of the XOR gate 214, so that the output terminal 2143 of the XOR gate 214 outputs a selection signal. The selection signal is a symmetrical square wave with a high level preceding it, and the clock period of the selection signal is the same as the clock period of the first clock signal.

[0037] Figure 2 The first inverter 213 and the first D flip-flop 211 generate a signal that continuously flips with the first clock signal. The second D flip-flop 212 and the XOR gate 214 detect the transition edges of this continuously flipping signal, so that there is a completely fixed correspondence between the selection signal SEL output by the control signal generator 21 and the first and second clock signals. Specifically, the selection signal SEL has a high level and a low level in each first clock cycle, and the high level and the low level each last for one second clock cycle, and the high level always comes first and the low level comes last. This allows the first input terminal and the second input terminal to be selected alternately in each first clock cycle, so that the first input terminal and the second input terminal can independently write data to or read data from the single-port random access memory 30 in each first clock cycle.

[0038] Figure 3 According to some embodiments of this application, a circuit diagram of a signal selector 22 is shown, with reference to... Figure 3 The signal selector 22 includes a second inverter 221, a first AND gate 222, a second AND gate 223, and an OR gate 224.

[0039] In this configuration, the input terminal 2211 of the second inverter 221 is connected to the output terminal 215 of the control signal generator 21; the output terminal 2212 of the second inverter 221 is connected to one input terminal 2221 of the first AND gate 222; the other input terminal 2222 of the first AND gate 222 is connected to the second enable terminal 141; and the output terminal 2223 of the first AND gate 222 is connected to one input terminal 2241 of the OR gate 224. Similarly, one input terminal 2231 of the second AND gate 223 is connected to the output terminal 215 of the control signal generator 21; the other input terminal 2232 of the second AND gate 223 is connected to the first enable terminal 131; and the output terminal 2233 of the second AND gate 223 is connected to the other input terminal 2242 of the OR gate 224, so that the output terminal 2243 of the OR gate 224 outputs an enable signal. When the selection signal SEL is high, the signal selector 22 outputs the enable signal CENA of the first access terminal 13 to the single-port random access memory 30. When the selection signal SEL is low, the signal selector 22 outputs the enable signal CENB of the second access terminal 14 to the single-port random access memory 30.

[0040] Similarly, when the selection signal SEL is high, the signal selector 22 outputs the write enable signal WENA of the first access terminal 13 to the single-port random access memory 30. When the selection signal SEL is low, the signal selector 22 outputs the write enable signal WENB of the second access terminal 14 to the single-port random access memory 30.

[0041] When the selection signal SEL is high, the signal selector 22 outputs the address signal ADDRA of the first access terminal 13 to the single-port random access memory 30. When the selection signal SEL is low, the signal selector 22 outputs the address signal ADDRB of the second access terminal 14 to the single-port random access memory 30.

[0042] When the selection signal SEL is high, the signal selector 22 outputs the data DA on the data bus of the first access terminal 13 to the single-port random access memory 30. When the selection signal SEL is low, the signal selector 22 outputs the data DB on the data bus of the second access terminal 14 to the single-port random access memory 30.

[0043] The signal selector 22 described above enables the first access terminal 13 and the second access terminal 14 to be selected in turn during each first clock cycle, so that both the first access terminal 13 and the second access terminal 14 can access the single-port random access memory 30 during each first clock cycle.

[0044] Figure 4 According to some embodiments of this application, a circuit diagram of a first latch 42 is shown. (See reference...) Figure 4The first latch 42 includes a first selector 423 and a fourth D flip-flop 424. The latch control terminal 4231 of the first selector 423 is connected to the output terminal 411 of the third D flip-flop 41. One input terminal 4232 of the first selector 423 is connected to the output terminal 31 of the single-port random access memory 30. The other input terminal 4233 of the first selector 423 is connected to the first output terminal 15. The output terminal 4234 of the first selector 423 is connected to the data input terminal 4241 of the fourth D flip-flop 424. The clock input terminal 4242 of the fourth D flip-flop 424 is connected to the second clock signal terminal 12. The output terminal 4243 of the fourth D flip-flop 424 is connected to the first output terminal 15. The data output by the first latch 42 is delayed by one second clock cycle relative to the data output by the single-port random access memory 30, and the data output by the first latch 42 remains unchanged within one first clock cycle, thereby satisfying the timing requirements of the first access terminal 13 and simulating the interface timing of randomly accessing one port of a conventional dual-port RAM using a random address.

[0045] Figure 5 According to some embodiments of this application, a circuit diagram of a second latch 43 is shown. (See reference...) Figure 5 The second latch 43 includes a third inverter 431, a second selector 432, and a fifth D flip-flop 433. The input 4311 of the third inverter 431 is connected to the output 411 of the third D flip-flop 41, and the output 4312 of the third inverter 431 is connected to the latch control terminal 4321 of the second selector 432. One input 4322 of the second selector 432 is connected to the output 31 of the single-port random access memory 30, and the other input 4323 of the second selector 432 is connected to the second output terminal 16. The output 4324 of the second selector 432 is connected to the data input 4331 of the fifth D flip-flop 433. The clock input 4332 of the fifth D flip-flop 433 is connected to the second clock signal terminal 12, and the output 4333 of the fifth D flip-flop 433 is connected to the second output terminal 16. The data output by the second latch 43 is synchronized with the data output by the single-port random access memory 30, and the data output by the second latch 43 remains unchanged within a first clock cycle. This satisfies the timing requirements of the second access port 14 and simulates the interface timing of randomly accessing another port of a conventional dual-port RAM using a random address.

[0046] The technical solution of this application can realize the dual-port RAM function using only a single-port RAM, a control selection unit 20, a latch and hold unit 40, and two synchronous clock signals. Compared with the existing dual-port RAM, the dual-port RAM provided by this application is smaller in size, lower in cost, and has a wider range of applications.

[0047] To more clearly illustrate the technical effects of the technical solution of this application, the following will describe them in sequence. Figures 6 to 8 The timing diagram.

[0048] Figure 6 According to some embodiments of this application, a method is shown. Figure 1 The circuit timing diagram shown illustrates how the two ports of a dual-port RAM can independently perform data reading operations.

[0049] Wherein, CLK refers to the first clock signal mentioned above; ADDRA is the address bus of the first access terminal 13; ADDRB is the address bus of the second access terminal 14; CLK2X refers to the second clock signal mentioned above, which is the multiplier clock signal of CLK; SEL refers to the selection signal mentioned above; AA0, AA1, AA2, and AA3 are the four address inputs of the first input terminal, and QA0, QA1, QA2, and QA3 are the storage data read values ​​corresponding to these four addresses; AB0, AB1, AB2, and AB3 are the four address inputs of the second input terminal, and QB0, QB1, and QB2 are the storage data read values ​​corresponding to AB0, AB1, and AB2; single-port RAM input A refers to the address input to the single-port RAM by the first and second input terminals, and single-port RAM output Q refers to the data output by the single-port RAM; latch output QA refers to the data output by the first output terminal 15, and latch output QB refers to the data output by the second output terminal 16.

[0050] from Figure 6 As can be seen intuitively, the clock period of the first clock signal CLK is twice that of the second clock signal CLK2X. The clock periods of the first and second input terminals are the same as those of the first clock signal CLK. The clock period of the selection signal SEL is twice that of the second clock signal CLK2X. When the selection signal SEL is high, the first input terminal is selected; when the selection signal SEL is low, the second input terminal is selected. The single-port RAM uses the second clock signal, and the output of the single-port RAM is delayed by one second clock cycle relative to the single-port RAM input A. The latched output QA is delayed by one second clock cycle relative to the output of the single-port RAM and remains for one first clock cycle. The latched output QB has no delay relative to the output of the single-port RAM and also remains for one first clock cycle. Figure 6 The timing diagram shown reflects that the two ports of the dual-port RAM provided in this application can independently and randomly read data from each other.

[0051] Figure 7 According to some embodiments of this application, a method is shown. Figure 1 The circuit timing diagram shown illustrates how the two ports of a dual-port RAM can perform data writing operations independently. Figure 7 Chinese nouns and Figure 6 The same applies, and will not be explained separately here; the following only refers to... Figure 7 Explain the meaning of the nouns that appear alone in the text.

[0052] like Figure 7 As shown, DA refers to the first input data bus. DA0, DA1, DA2, and DA3 are the data to be written to the single-port RAM corresponding to addresses AA0, AA1, AA2, and AA3, respectively. DB0, DB1, DB2, and DB3 are the data to be written to the single-port RAM corresponding to addresses AB0, AB1, AB2, and AB3, respectively. The single-port RAM input D points to the data being written to the single-port RAM.

[0053] from Figure 7 As can be seen intuitively, within the same first clock cycle, when the selection signal SEL is high, the first input terminal is activated, and the first input terminal writes data DA0, DA1, DA2, and DA3 to the addresses AA0, AA1, AA2, and AA3 of the single-port RAM, respectively; when the selection signal SEL is low, the second input terminal is activated, and the second input terminal writes data DB0, DB1, DB2, and DB3 to the addresses AB0, AB1, AB2, and AB3 of the single-port RAM, respectively. Figure 7 The timing diagram shown reflects that the two ports of the dual-port RAM provided in this application can be independently and randomly written to.

[0054] Figure 8 According to some embodiments of this application, a method is shown. Figure 1 The diagram shows the timing of a dual-port RAM circuit where data is written to one port and read from the other. Figure 8 Chinese nouns and Figure 6 or Figure 7 The same applies, and will not be explained separately here; the following only refers to... Figure 8 Explain the meaning of nouns that appear alone in the text. For example... Figure 8 As shown, the WEN input of the single-port RAM refers to the write enable signal of the single-port RAM.

[0055] from Figure 8 As can be seen intuitively, when the selection signal SEL is high, the first input terminal is enabled, and the single-port RAM input WEN is low, allowing data DA0 to be written to address AA0 in the single-port RAM; when the selection signal SEL is low, the second input terminal is enabled, and the single-port RAM input WEN is high, disabling data writing to the single-port RAM. The single-port RAM input A is AB0, meaning that the second input terminal reads the data corresponding to address AB0 from the single-port RAM. After one second clock cycle, the single-port RAM output Q is QBO, which means the single-port RAM outputs data QB0. Then, QB0 is latched by the second latch 43 and output through the second output terminal 16. Figure 8The timing diagram shown illustrates that the reading of data from one port and the writing of data from the other port of the dual-port RAM provided in this application do not affect each other.

[0056] The dual-port RAM implemented in this application completely simulates the interface timing of a conventional dual-port RAM. The two ports can be accessed simultaneously using random addresses independently, without any constraints between them.

[0057] Taking 28nm process as an example, for a traditional dual-port random access memory with an address depth of 512 and a bit width of 32 bits, its physical dimensions are 230.54um in length, 47.955um in width, and an area of ​​11056um. 2 The single-port random access memory 30, with the same address depth and bit width, has a physical size of 93.19µm in length, 36.77µm in width, and an area of ​​3427µm. 2 The area of ​​a single-port random access memory (RAM) 30 is 30.99% of the area of ​​a dual-port RAM. The dual-port RAM provided in this application adds 171 μm of logic circuit area compared to the single-port RAM. 2 That is, the total area of ​​the dual-port RAM provided in this application is only 32.54% of the area of ​​the traditional dual-port random access memory, which can significantly reduce the chip area occupied.

[0058] Various embodiments of the mechanisms disclosed in this invention can be implemented in hardware, software, firmware, or combinations of these implementations. Embodiments of this invention can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memories and / or storage elements), at least one input device, and at least one output device.

[0059] It should be noted that the units / modules mentioned in the various device embodiments of the present invention are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problem proposed by the present invention. Furthermore, to highlight the innovative aspects of the present invention, the above-described device embodiments of the present invention have not introduced units / modules that are not closely related to solving the technical problem proposed by the present invention. This does not mean that the above-described device embodiments do not contain other units / modules.

[0060] It should be noted that in the examples and description of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0061] Although the invention has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

1. A dual-port random access memory, characterized in that, include: The system includes a first clock signal terminal, a second clock signal terminal, a first access terminal, a second access terminal, a first output terminal, a second output terminal, a control selection unit, a single-port random access memory, and a latch and hold unit. The control selection unit is connected to the first clock signal terminal, the second clock signal terminal, the first access terminal, the second access terminal, and the single-port random access memory. The control selection unit is used to select whether to output the signal of the first access terminal or the signal of the second access terminal to the single-port random access memory according to the first clock signal of the first clock signal terminal and the second clock signal of the second clock signal terminal. The second clock signal is synchronized with the first clock signal, and the frequency of the second clock signal is twice the frequency of the first clock signal. The single-port random access memory is connected between the control selection unit and the latch holding unit. The single-port random access memory is used to output the data to be read by the first access terminal and the second access terminal, or to write the data to be written by the first access terminal and the second access terminal within the same first clock cycle. The first clock cycle is the clock cycle of the first clock signal. The clock signal of the single-port random access memory adopts the same timing characteristics as the second clock signal. The latch and hold unit is connected to the single-port random access memory, the control selection unit, the first output terminal, and the second output terminal. The latch and hold unit is used to latch and hold the data from the first access terminal and the data from the second access terminal output by the single-port random access memory in the same first clock cycle, and then output them through the first output terminal and the second output terminal respectively.

2. The dual-port random access memory according to claim 1, characterized in that, The control selection unit includes a control signal generator and a signal selector. The control signal generator is connected to the first clock signal terminal, the second clock signal terminal, the signal selector, and the latch-and-hold unit. The control signal generator is used to generate a selection signal based on the first clock signal of the first clock signal terminal and the second clock signal of the second clock signal terminal, and output the selection signal to the signal selector and the latch-and-hold unit. This allows the signal selector to select either the signal of the first access terminal or the signal of the second access terminal to be output to the single-port random access memory (SRAM) based on the selection signal. The latch-and-hold unit also uses the selection signal to latch and hold the data from the first access terminal and the data from the second access terminal output by the SRAM within the same first clock cycle.

3. The dual-port random access memory according to claim 2, characterized in that, The control signal generator includes a first D flip-flop, a second D flip-flop, a first inverter, and an XOR gate. The clock input of the first D flip-flop is connected to the first clock signal terminal, and the data input of the first D flip-flop is connected to the output of the first inverter. The output of the first D flip-flop is connected to the input of the first inverter, the data input of the second D flip-flop, and one of the inputs of the XOR gate. The clock input of the second D flip-flop is connected to the second clock signal terminal, and the output of the second D flip-flop is connected to the other input of the XOR gate, so that the output of the XOR gate outputs the selection signal. The selection signal is a symmetrical square wave with a high preceding level, and the clock period of the selection signal is the same as the clock period of the first clock signal.

4. The dual-port random access memory according to claim 3, characterized in that, The first access terminal includes a first enable terminal, and the second access terminal includes a second enable terminal. The signal selector includes a second inverter, a first AND gate, a second AND gate, and an OR gate. The input of the second inverter is connected to the output of the control signal generator, the output of the second inverter is connected to one input of the first AND gate, the other input of the first AND gate is connected to the second enable terminal, and the output of the first AND gate is connected to one input of the OR gate. One input of the second AND gate is connected to the output of the control signal generator, the other input of the second AND gate is connected to the first enable terminal, and the output of the second AND gate is connected to the other input of the OR gate, so that the output of the OR gate outputs an enable signal.

5. The dual-port random access memory according to claim 4, characterized in that, The latch and hold unit includes a third D flip-flop, a first latch, and a second latch. The third D flip-flop is connected between the control signal generator, the first latch, and the second latch. The third D flip-flop delays the selection signal by a second clock cycle to obtain a latch control signal. The latch control signal controls the first latch to latch and hold the data at the first access terminal of the single-port random access memory, and controls the second latch to latch and hold the data at the second access terminal of the single-port random access memory. The second clock cycle is the clock cycle of the second clock signal. The input terminals of the first latch and the second latch are both connected to the output terminal of the third D flip-flop, the output terminal of the single-port random access memory, and the second clock signal terminal. The output terminal of the first latch is connected to the first output terminal, and the output terminal of the second latch is connected to the second output terminal. The first latch is used to output the data of the first access terminal output by the single-port random access memory within the same first clock cycle through the first output terminal. The second latch is used to output the data of the second access terminal output by the single-port random access memory within the same first clock cycle through the second output terminal.

6. The dual-port random access memory according to claim 5, characterized in that, The clock input of the third D flip-flop is connected to the output of the control signal generator, and the output of the third D flip-flop is connected to the first input of the first latch and the first input of the second latch. The second input of the first latch and the second input of the second latch are both connected to the output of the single-port random access memory, and the third input of the first latch and the third input of the second latch are both connected to the second clock signal terminal.

7. The dual-port random access memory according to claim 5, characterized in that, The first latch includes a first selector and a fourth D flip-flop, wherein the latch control terminal of the first selector is connected to the output terminal of the third D flip-flop, one input terminal of the first selector is connected to the output terminal of the single-port random access memory, the other input terminal of the first selector is connected to the first output terminal, the output terminal of the first selector is connected to the data input terminal of the fourth D flip-flop, the clock input terminal of the fourth D flip-flop is connected to the second clock signal terminal, and the output terminal of the fourth D flip-flop is connected to the first output terminal.

8. The dual-port random access memory according to claim 5, characterized in that, The data output by the first latch is delayed by one second clock cycle relative to the data output by the single-port random access memory, and the data output by the first latch remains unchanged within one first clock cycle.

9. The dual-port random access memory according to claim 5, characterized in that, The second latch includes a third inverter, a second selector, and a fifth D flip-flop. The input of the third inverter is connected to the output of the third D flip-flop, and the output of the third inverter is connected to the latch control terminal of the second selector. One input of the second selector is connected to the output of the single-port random access memory, and the other input of the second selector is connected to the second output. The output of the second selector is connected to the data input of the fifth D flip-flop, the clock input of the fifth D flip-flop is connected to the second clock signal terminal, and the output of the fifth D flip-flop is connected to the second output.

10. The dual-port random access memory according to claim 5, characterized in that, The data output by the second latch is synchronized with the data output by the single-port random access memory, and the data output by the second latch remains unchanged within one first clock cycle.

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