Memory control method and storage device

Abstract

The invention provides a memory control method and a storage device. The method comprises the following steps: applying a multi-section nonlinear erasure voltage to a target entity unit in the memory module, wherein the erasure voltage is adjusted in sections according to a pre-charging stage, a main erasure stage and a stable compensation stage; and according to the word line layer corresponding to the target entity unit, referring to a group of interlayer compensation parameters, carrying out layer-dependent voltage offset setting on the erasing voltage so as to compensate the interlayer channel resistance difference in the target entity unit. Therefore, the operation efficiency and the stability of the storage device can be improved.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a memory control method and storage device. Background Technology

[0002] Non-volatile memory is widely used in various electronic devices. Among them, NAND Flash memory has advantages such as fast read speed and shock resistance. NAND Flash memory is programmed by applying a high voltage to a floating gate, causing electrons to tunnel through the oxide layer into the floating gate via quantum tunneling, thereby changing the threshold voltage of the memory cell to store data. The erase operation removes the electrons from the floating gate, lowering the threshold voltage to return the cell to the erased state.

[0003] With the continuous development of NAND flash memory technology, solid-state drives (SSDs) have made significant progress in storage density and read / write performance. Among the physical characteristics of flash memory, the erase operation is a key factor affecting the durability and operational efficiency of storage cells. Traditional erase voltage control methods mainly employ a fixed voltage mode.

[0004] In particular, as 3D NAND technology advances to higher stacking layers, the differences in process variations and charge retention capabilities between memory cells are becoming increasingly significant. Existing voltage control schemes are prone to problems such as prolonged erase operation times or excessive oxide layer damage when dealing with practical issues such as inherent differences in characteristics between memory blocks and changes in data retention decay gradients. This directly affects the reliability and lifespan of SSD products, becoming a major bottleneck restricting the development of high-density flash memory technology. Summary of the Invention

[0005] The present invention provides a memory control method and a storage device that can improve the above-mentioned problems, thereby improving the operating efficiency and stability of the storage device including a three-dimensional stacked memory module.

[0006] This invention provides a memory control method for a storage device, the storage device including a three-dimensional stacked memory module, and the memory control method comprising: applying a multi-segment nonlinear erase voltage to a target physical cell in the memory module, wherein the erase voltage is adjusted in segments according to a pre-charge stage, a main erase stage, and a stabilization compensation stage; and setting a layer-dependent voltage offset for the erase voltage according to the word line layer corresponding to the target physical cell and with reference to a set of inter-layer compensation parameters to compensate for the difference in inter-layer channel resistance in the target physical cell.

[0007] This invention also provides a storage device, including a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory module includes a three-dimensional stacked memory module. The memory controller is connected to the connection interface and the memory module. The memory controller is used to: apply a multi-segment nonlinear erase voltage to a target physical cell in the memory module, wherein the erase voltage is adjusted segmentally according to a pre-charge phase, a main erase phase, and a stabilization compensation phase; and set a layer-dependent voltage offset for the erase voltage based on the word line layer corresponding to the target physical cell and referring to a set of inter-layer compensation parameters to compensate for the inter-layer channel resistance differences in the target physical cell. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0011] Figure 4 This is a schematic diagram of the word line layer stacking structure shown in an embodiment of the present invention;

[0012] Figure 5 This is a schematic diagram of the operation timing of the triple erase verification operation according to an embodiment of the present invention;

[0013] Figure 6 This is a schematic diagram illustrating the configuration of decoding table storage areas for multiple entity units according to an embodiment of the present invention;

[0014] Figure 7 This is a schematic diagram of an erase voltage compensation circuit according to an embodiment of the present invention;

[0015] Figure 8 This is a flowchart illustrating a memory control method according to an embodiment of the present invention;

[0016] Figure 9 This is a flowchart illustrating a memory control method according to an embodiment of the present invention;

[0017] Figure 10 This is a flowchart illustrating a memory control method according to an embodiment of the present invention. Detailed Implementation

[0018] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0019] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0020] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 via connection interface 121 (e.g., exchange signals, instructions, and / or data).

[0021] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0022] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include flash memory controller.

[0023] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0024] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0025] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0026] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0027] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuits), which are not limited by the present invention.

[0028] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1) to 301(B). Each physical unit includes multiple storage units for non-volatile storage of data.

[0029] In one embodiment, an entity unit may include one or more entity erase units. For example, an entity erase unit may refer to an entity block. An entity erase unit may include multiple entity programmable units. For example, an entity programmable unit may refer to an entity page.

[0030] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0031] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0032] In one embodiment, multiple programmed units in a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to multiple programmed units in this physical erase unit to change the threshold voltage of at least some of the memory cells in these programmed units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased.

[0033] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1) to 301(A) and 301(A+1) to 301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1) to 301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1) to 301(B) in the idle area 32 do not store any data (e.g., valid data).

[0034] In one embodiment, if a physical unit does not store valid data, this physical unit can be associated with the free area 32. Furthermore, physical units in the free area 32 can be erased to clear the data within them. In one embodiment, physical units in the free area 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as the free pool.

[0035] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0036] In one embodiment, the memory control circuit 23 may be configured with a plurality of logic units 302(1) to 302(C) to map physical units (i.e., physical units 301(1) to 301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0037] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0038] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logic-to-physical mapping table).

[0039] In one embodiment, memory module 122 includes a three-dimensional (3D) stacked memory module. For example, memory module 122 may include a word line layer stack structure with 128, 256, 512 layers, or other numbers of layers. Each word line layer stack structure includes multiple stacked word line layers. The memory cells in each word line layer may form one or more physical programmable units. Furthermore, each physical unit may include multiple word line layers in one or more word line layer stack structures.

[0040] In traditional 3D NAND flash memory technology, as the number of vertically stacked layers exceeds 200, channel resistance differences, erase consistency, and charge pump ripple issues pose significant challenges to reliability. Generally, although erase control can be performed using linear step voltages, which is simple to operate, it is difficult to effectively compensate for non-ideal electric field distributions between layers, leading to uneven erase depth and increased bit error rate.

[0041] Therefore, embodiments of the present invention provide an erase control method with segmented nonlinear erase voltage control, layer dependency compensation mechanism, triple verification mechanism and multi-block collaborative scheduling design, which is suitable for multi-channel, high-density stacked three-dimensional NAND storage devices.

[0042] In one embodiment, when an erase operation is to be performed on a specific physical cell (also referred to as a target physical cell) in the memory module 122, the memory control circuit 23 may apply a multi-segment nonlinear erase voltage to the target physical cell. Specifically, the memory control circuit 23 may sequentially adjust the erase voltage applied to the target physical cell in segments during the pre-charge phase, the main erase phase, and the stabilization compensation phase. This will be described in detail below.

[0043] (1) Pre-charging stage

[0044] The main objective of this stage is to gradually raise the floating gate potential of each memory cell within the target physical cell to an initial voltage environment suitable for primary erasure. Specifically, during the pre-charge stage, the erase voltage applied to the target physical cell increases linearly.

[0045] In one embodiment, the memory control circuit 23 may control or adjust the erase voltage applied to the target physical cell during the precharge phase according to the following formula (1).

[0046] V(t)=V0+K1×t (1)

[0047] In formula (1), V(t) represents the erase voltage at time t, V0 is the initial erase voltage (e.g., 0V or floating state), and K1 is the linear gain coefficient (e.g., 0.12V / μs). For example, in the pre-charge phase, the aforementioned erase voltage is applied for approximately 0.5ms, and the final voltage can be approximately 15V to avoid excessive instantaneous voltage difference leading to oxide layer breakdown. It should be noted that formula (1) and all the parameters mentioned above can be adjusted according to practical needs.

[0048] (2) Main erasure phase

[0049] This stage is the main voltage ramp-up stage of the erase operation. In particular, during the main erase stage, the erase voltage applied to the target physical cell increases exponentially.

[0050] In one embodiment, the memory control circuit 23 may control or adjust the erase voltage applied to the target physical cell during the main erase phase according to the following formula (2).

[0051] V(t)=V0+K2×(1-exp(-t / τ)) (2)

[0052] In formula (2), V(t) represents the erase voltage at time t, V0 is the initial erase voltage, K2 is the voltage gain coefficient, and τ is the time constant. For example, in the main erase phase, τ can be set to 1.28 ms, K2 can be set to 7V, and therefore, the aforementioned erase voltage can be gradually increased from 15V to approximately 22V. It should be noted that in the main erase phase, adjusting the aforementioned erase voltage using formula (2) can prevent excessive voltage increase and ensure that the charge pump output current remains below 5mA. Furthermore, formula (2) and all the parameters mentioned above can be adjusted according to practical needs.

[0053] (3) Stable compensation phase

[0054] During this phase, to prevent excessive ionization of the float gate due to erase voltage overshoot, a logarithmic decay mechanism is introduced to stabilize the voltage as the erase process nears completion. Specifically, during the stabilization compensation phase, the erase voltage applied to the target physical unit decreases logarithmically.

[0055] In one embodiment, the memory control circuit 23 may control or adjust the erase voltage applied to the target physical cell during the stabilization compensation phase according to the following formula (3).

[0056] V(t)=Vmax-K3×·ln(t) (3)

[0057] In formula (3), V(t) represents the erase voltage at time t, Vmax is the maximum erase voltage (e.g., the peak erase voltage at the end of the previous stage), and K3 is the logarithmic decay coefficient (e.g., 0.8V / ms). It should be noted that this stage helps control the critical voltage distribution of each memory cell in the target physical cell at the end of the erase operation, avoiding tail broadening of the critical voltage distribution.

[0058] In one embodiment, during the erase operation targeting a target physical cell, the memory control circuit 23 can set a layer-dependent voltage offset for the erase voltage based on the multiple word line layers corresponding to the target physical cell and referring to a set of inter-layer compensation parameters. This effectively compensates for the inconsistent erase depth caused by differences in inter-layer channel resistance in the word line layer stacking structure during the erase operation targeting the target physical cell.

[0059] In one embodiment, the memory control circuit 23 can divide a word line layer stack structure in the memory module 122 into three layer groups. Then, the memory control circuit 23 can incorporate an inter-layer compensation parameter for at least one of these three layer groups into the erase voltage control for the target physical cell. Thus, by introducing a layer-dependent voltage compensation mechanism, the problem of uneven erasure caused by the vertical channel resistance of the word line layer stack structure in different parts of the stack structure can be improved.

[0060] Figure 4 This is a schematic diagram of the word line layer stacking structure according to an embodiment of the present invention. Please refer to... Figure 4 In one embodiment, it is assumed that the memory module 122 includes a word line layer stack structure 41. The word line layer stack structure 41 includes a plurality of stacked word line layers 401(1) to 401(F).

[0061] In one embodiment, in the word line layer stack structure 41, the memory control circuit 23 can divide word line layers 401(1) to 401(D) into top word line layers, word line layers 401(D+1) to 401(E) into middle word line layers, and word line layers 401(E+1) to 401(F) into bottom word line layers. Taking a 256-layer word line layer stack structure 41 as an example, word line layers 401(1) to 401(D) belonging to the top word line layers can be layers 0 to 63, word line layers 401(D+1) to 401(E) belonging to the middle word line layers can be layers 64 to 191, and word line layers 401(E+1) to 401(F) belonging to the bottom word line layers can be layers 192 to 255. However, the division method of the layer groups can also be adjusted according to practical needs.

[0062] In one embodiment, the memory control circuit 23 can determine the aforementioned interlayer compensation parameters based on the individual electrical characteristics of the three layer groups (i.e., the top word line layer, the middle word line layer, and the bottom word line layer). For example, the aforementioned interlayer compensation parameters may include an offset voltage corresponding to the top word line layer (also referred to as the first offset voltage), an offset voltage corresponding to the bottom word line layer (also referred to as the second offset voltage), and an offset voltage corresponding to the middle word line layer (also referred to as the third offset voltage). The first offset voltage, the second offset voltage, and the third offset voltage may be different from each other.

[0063] In one embodiment, in the top word line layer, every 8 layers (or other layers), the memory control circuit 23 may increase the erase voltage by a positive offset of 0.1V (i.e., using a first offset voltage that increases with the number of layers) (e.g., up to +0.7V). In the bottom word line layer, every 1 layer (or other layers), the memory control circuit 23 may increase the erase voltage by a negative offset of -0.05V (i.e., using a second offset voltage that decreases with the number of layers) (e.g., up to -3.2V). In the middle word line layer, the memory control circuit 23 may also fine-tune or temporarily omit the corresponding offset voltage (i.e., a third offset voltage) in a similar manner. It should be noted that the above-described method for setting inter-layer compensation parameters is merely an example and can be adjusted according to practical needs.

[0064] In one embodiment, the step size of the aforementioned erase voltage can be dynamically adjusted according to which layer group the word line layer in the target physical cell is located in. For example, the top word line layer can use a larger step value (e.g., 0.3V / step) to accelerate the erasure of the high-resistivity layer, while the middle word line layer and the bottom word line layer can use relatively smaller step values ​​(e.g., 0.2V / step and 0.15VStep) to compensate for the difference in electric field strength in the vertical channel.

[0065] In one embodiment, the memory control circuit 23 can set the aforementioned inter-layer compensation parameters in the voltage offset registers corresponding to each word line layer in the word line layer stack structure via register groups. For example, the memory control circuit 23 can write the setting information (e.g., the first voltage compensation value) corresponding to the aforementioned first offset voltage to the voltage offset registers corresponding to each word line layer 401(1) to 401(D) in the top word line layer, write the setting information (e.g., the second voltage compensation value) corresponding to the aforementioned second offset voltage to the voltage offset registers corresponding to each word line layer 401(E+1) to 401(F) in the bottom word line layer, and write the setting information (e.g., the third voltage compensation value) corresponding to the aforementioned third offset voltage to the voltage offset registers corresponding to each word line layer 401(D+1) to 401(E) in the middle word line layer.

[0066] Subsequently, during the erase operation targeting the target physical cell, the corresponding offset voltage (or voltage compensation value) can be read from the voltage offset register corresponding to each word line layer, based on which of the three layer groups the word line layer in the target physical cell belongs to, and used to adjust or compensate the erase voltage used. This helps to achieve uniformity in the erase depth of each memory cell within the same physical cell and facilitates the convergence of the critical voltage distribution of each memory cell.

[0067] In one embodiment, during the erase operation targeting the physical unit, the memory control circuit 23 may employ a triple erase verification operation to improve erase efficiency and enhance the accuracy of the assessment of the erase status.

[0068] In one embodiment, the aforementioned triple erase verification operation includes a pre-erasure verification operation, a mid-erasure verification operation, and a final erase verification operation. The pre-erasure verification operation, the mid-erasure verification operation, and the final erase verification operation can be executed sequentially on the erased target entity unit.

[0069] Figure 5 This is a schematic diagram illustrating the timing of the triple erase verification operation according to an embodiment of the present invention. Please refer to... Figure 5 Assume that an erase operation on the target physical unit is triggered at time point T(1). After the erase operation on the target physical unit begins (i.e., time point T(1)), between time points T(1) and T(2), the memory control circuit 23 can perform a pre-erasure verification operation on the target physical unit. Then, between time points T(2) and T(3), the memory control circuit 23 can perform an intermediate erase verification operation on the target physical unit. Subsequently, between time points T(3) and T(4), the memory control circuit 23 can perform a final erase verification operation on the target physical unit.

[0070] The pre-erase verification operation is used to preliminarily determine the reference erase depth of each memory cell in the target physical cell. For example, in the pre-erase verification operation, the memory control circuit 23 can use a verification voltage with a relatively coarse resolution (e.g., 0.5V) to quickly scan each memory cell in the target physical cell to roughly determine the reference erase depth of the current target physical cell.

[0071] The intermediate erase verification operation dynamically adjusts the reference voltage based on a temperature compensation mechanism. For example, in the intermediate erase verification operation, the memory control circuit 23 can dynamically adjust the reference voltage generated based on the currently detected temperature (or temperature change) of the memory device 12. This reference voltage is used to generate the aforementioned erase voltage. For example, for every 10 degrees Celsius increase in the temperature of the memory device 12, the memory control circuit 23 can reduce this reference voltage by 0.03V. This strengthens the compensation for thermal drift in the critical voltage distribution of each memory cell in the target memory cell.

[0072] The final erase verification operation is used to check using an asymmetric parity check matrix of low-density parity-check codes (LDPC). For example, in the final erase verification operation, the memory control circuit 23 can read data from the erased target physical cell, and the decoding circuit 25 can decode this data based on the LDPC asymmetric matrix to finally verify the erase integrity of the target physical cell.

[0073] In one embodiment, the asymmetric parity-check matrix used in the aforementioned final erase verification operation may have a lateral density parameter that dynamically changes based on the entity cell number. This allows for a dynamic row weight configuration with density gradients for different entity cells.

[0074] Traditionally, the parity-check matrix H used in LDPC encoding is designed with an evenly distributed distribution, meaning that each row in the parity-check matrix H has a fixed number of non-zero elements (i.e., row weight), such as 4 or 6. However, for 3D NAND storage devices, erase operations performed on different blocks may face complex situations such as different inter-layer interferences, different voltage fluctuations, and different degrees of data degradation. Therefore, using the aforementioned even or fixed row weight design is no longer sufficient to balance reliability and resource efficiency.

[0075] In one embodiment, in the aforementioned final erasure verification operation, an LDPC asymmetric matrix (i.e., verification matrix H) with a row weight gradient configuration is used for data decoding and verification, which can further improve the efficiency and reliability of data verification after erasure.

[0076] Taking the 8-channel access mechanism as an example, in the aforementioned horizontal density gradient configuration, as the entity unit numbers of different entity units increase, the row weights (i.e., parity check matrix H) of the asymmetric matrix used by these entity units decrease in a decreasing distribution. For example, after every 4 entity units, the row weight (i.e., the number of non-zero elements) of the asymmetric matrix (i.e., parity check matrix H) used by the next entity unit decreases by 1. This can optimize the encoding / decoding performance for specific applications. It should be noted that how the aforementioned entity units are adjusted after each few entity units can also be set or adjusted according to practical needs.

[0077] The above gradient configuration strategy has the following technical effects and significance:

[0078] Strengthen verification of key blocks: In collaborative erasure operations involving multiple entity units, some entity units may be located in high-risk areas (such as underlying channels). For such entity units, setting a higher row weight can increase interleaving and fault tolerance.

[0079] Save decoding resources: For multi-entity units with lower row weights, the corresponding decoding complexity is also reduced, thereby improving the decoding efficiency when multiple channels are running simultaneously.

[0080] Dynamic fault tolerance adjustment: The memory control circuit 23 can dynamically adjust the previous dynamic gradient configuration based on the historical error rate. For example, for entity cells with a high historical error rate, the corresponding row weight can be increased.

[0081] Reduce data interference coupling: A high-density (high row weight) LDPC asymmetric matrix is ​​allocated to the region where erase errors frequently occur, which can detect erase failures in advance and avoid data pollution caused by subsequent writes.

[0082] In one embodiment, the memory control circuit 23 may also configure a decoding table storage area for each entity unit in the memory module 122 to store the dynamic row weight configuration (i.e., the number of non-zero elements) and other useful encoding / decoding information for each entity unit.

[0083] Figure 6 This is a schematic diagram illustrating the configuration of decoding table storage areas for multiple entity units according to an embodiment of the present invention. Please refer to... Figure 6In one embodiment, the memory control circuit 23 may define a storage region 60 in the memory module 122 and divide the storage region 60 into multiple storage areas (i.e., decoding table storage areas) 61(1) to 61(G). Then, the memory control circuit 23 may store the decoding tables 610(1) to 610(G) in the storage areas 61(1) to 61(G) respectively. The decoding tables 610(1) to 610(G) correspond to the entity units 601(1) to 601(G) respectively. For example, the decoding table 601(i) may be used to record the aforementioned dynamic row weight configuration information and other types of encoding / decoding information for the entity unit 601(i), such as log-likelihood ratio (LLR) information.

[0084] In one embodiment, by storing the decoding table corresponding to each entity unit, the management and usage flexibility of the decoding table can be effectively improved, and it can be ensured that the decoding tables used for different entity units will not overwrite each other.

[0085] In one embodiment, in a multi-channel environment, the memory control circuit 23 can also dynamically calculate and adjust the erase priority of the target entity cell (and other entities to be erased simultaneously) based on the word line layer resistance factor and latency of the target entity cell. Then, the memory control circuit 23 can allocate resources of the charge pump related to the aforementioned erase voltage and schedule the erase for entities to be erased simultaneously based on the determined erase priority.

[0086] In one embodiment, the memory control circuit 23 can calculate the erase priority of the target physical cell according to the following formula (4):

[0087] PR=α×R_layer+β×(t_wait / t_max) (4),

[0088] In formula (4), PR represents the erase priority of the target entity cell, R_layer is the word line layer resistance factor of the target entity cell, t_wait is the waiting time of the target entity cell (e.g., the cumulative time of the target entity cell in the erase waiting queue), t_max is the upper limit of the waiting time, α and β are weighting coefficients, and satisfy α+β=1. For example, α and β can be 0.6 and 0.4 respectively, and can be adjusted according to practical needs. Through formula (4), both resistance distribution and time fairness can be taken into account, a relatively appropriate erase priority can be determined for the target entity cell, and an appropriate erase schedule can be performed for multiple entities to be erased simultaneously. It should be noted that formula (4) can also be adjusted according to practical needs.

[0089] In one embodiment, the memory control circuit 23 may control, adjust, and / or compensate the aforementioned erase voltage via an erase voltage compensation circuit. For example, this erase voltage compensation circuit may be included within the memory control circuit 23 or within the memory controller 123.

[0090] Figure 7 This is a schematic diagram of an erase voltage compensation circuit according to an embodiment of the present invention. Please refer to... Figure 7 The erase voltage compensation circuit 70 may include a reference voltage generator 71, a charge pump 72, and a control circuit 73.

[0091] A reference voltage generator 71 provides a reference voltage Vref. A charge pump 72 is connected to the reference voltage generator 71. The charge pump 72 receives the reference voltage Vref and generates an erase voltage Verase based on the reference voltage Vref. A control circuit 73 is connected to the charge pump 72 and controls, adjusts, and / or compensates the erase voltage Verase output by the charge pump 72. Furthermore, the control circuit 73 may include an integrated capacitor 731. The integrated capacitor 731 contains multiple capacitor cells and is connected to the output of the charge pump 72. For example, the integrated capacitor 731 can operate in BOOST mode (also known as active mode) or NORMAL mode (also known as normal mode).

[0092] In one embodiment, during the erasure of a target physical unit, the control circuit 73 can detect the output voltage ripple of the charge pump 72 (i.e., the voltage ripple of the erase voltage Verase). In response to the instantaneous current of this output voltage ripple exceeding a predetermined threshold, the control circuit 73 can provide an instantaneous compensation current via an integrated capacitor 731. For example, the integrated capacitor 731 may have a capacitance of 10 μF to provide the corresponding instantaneous compensation current. This instantaneous compensation current can suppress the ripple to remain below 300 mV. Furthermore, if the peak output current exceeds 5 mA, the integrated capacitor 731 can be automatically triggered to provide BOOST compensation in BOOST mode. Thus, during peak erase current, problems such as sudden output voltage drops, power overload, and / or damage to the charge pump 72 can be prevented, thereby improving the stability and reliability of the system.

[0093] In one embodiment, during the erasure process of a target physical cell (or multiple physical cells), the memory control circuit 23 can dynamically switch the power mode of the charge pump 72 and / or the integrated capacitor 731 (e.g., switching between 3.3V / 1.8V / 0.8V) based on the load and voltage stability of the charge pump 72 and / or the integrated capacitor 731. This achieves energy savings and improves system stability.

[0094] In one embodiment, when synchronously erasing multiple physical units, to avoid voltage drop caused by the superposition of instantaneous currents, during the aforementioned pre-charging phase, the control circuit 73 can control the charge pump 72 to adopt an interleaved start-up mode with an interval of 200μs to improve operational stability. Secondly, during the main erase phase, the control circuit 73 (or memory control circuit 23) can dynamically adjust the τ value in formula (2) according to the overall load to avoid excessive superposition of peak currents. Finally, during the stabilization compensation phase, the overall system operation is monitored in a low-power mode.

[0095] In one embodiment, after the erase operation on the target physical cell is completed, the memory control circuit 23 may apply a reset pulse to the target physical cell to suppress threshold voltage rebound (i.e., recovery) of each memory cell in the target physical cell. For example, after the erase operation on the target physical cell is completed, the control circuit 73 may control the charge pump 72 to output a reset pulse Vpulse (e.g., 1.8V / 50ns) to the control gate of each memory cell. This can suppress or mitigate threshold rebound caused by charge redistribution.

[0096] Figure 8 This is a flowchart illustrating a memory control method according to an embodiment of the present invention. Please refer to... Figure 8 In step S801, a multi-segment nonlinear erase voltage is applied to the target physical cell in the memory module, wherein the erase voltage is adjusted in segments according to the pre-charge stage, the main erase stage, and the stabilization compensation stage. In step S802, based on the word line layer corresponding to the target physical cell and referring to a set of inter-layer compensation parameters, a layer-dependent voltage offset setting is performed on the erase voltage to compensate for the inter-layer channel resistance differences in the target physical cell.

[0097] Figure 9 This is a flowchart illustrating a memory control method according to an embodiment of the present invention. Please refer to... Figure 9 In step S901, a target entity cell is determined. In step S902, it is determined whether the target entity cell contains a top word line layer. If yes, in step S903, a first offset voltage is written as an interlayer compensation parameter to the voltage offset register corresponding to the word line layer belonging to the top word line layer in the target entity cell. If no, in step S904, it is determined whether the target entity cell contains a bottom word line layer. If yes, in step S905, a second offset voltage is written as an interlayer compensation parameter to the voltage offset register corresponding to the word line layer belonging to the bottom word line layer in the target entity cell. If no, in step S906, a third offset voltage is written as an interlayer compensation parameter to the voltage offset register corresponding to the word line layer belonging to the middle word line layer in the target entity cell.

[0098] Figure 10This is a flowchart illustrating a memory control method according to an embodiment of the present invention. Please refer to... Figure 10 In step S1001, the TIM2 interrupt trigger of charge pump 72 is detected. In step S1002, the current output current of charge pump 72 is read. In step S1003, it is determined whether this current current is greater than 5.0A (which can be adjusted according to practical needs). If so (i.e., the current current is greater than 5.0A), in step S1004, the overcurrent counter is updated, for example, by incrementing the overcurrent counter by 1. In step S1005, it is determined whether the overcurrent counter is greater than the threshold and whether integrated capacitor 731 is not in BOOST mode. If so (i.e., the overcurrent counter is greater than the threshold and integrated capacitor 731 is not in BOOST mode), in step S1006, integrated capacitor 731 is switched to BOOST mode. In step S1007, the event EVEN-POWER_OVERLOAD is recorded in the event log for subsequent analysis. In step S1008, the start time of BOOST mode is recorded.

[0099] After switching integrated capacitor 731 to BOOST mode, in step S1009, it is determined whether a timeout has occurred. If so (i.e., BOOST mode timeout), in step S1010, integrated capacitor 731 is switched back to NORMAL mode. Then, in step S1011, EVENT_BOOST_TIMEOUT is recorded in the event log for subsequent analysis.

[0100] On the other hand, if the judgment result of step S1003 is negative (i.e., the current current is not greater than 5.0A), the overcurrent counter is cleared in step S1012. In step S1013, it is determined whether the integrated capacitor 731 is in BOOST mode and whether the current current is less than 4.5A (adjustable). If yes (i.e., the integrated capacitor 731 is in BOOST mode and the current current is less than 4.5A), the integrated capacitor 731 is switched back to NORMAL mode in step S1014. In step S1015, the event EVENT_POWER_RECOVERED is recorded in the event log for subsequent analysis.

[0101] However, Figures 8 to 10 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figures 8 to 10 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figures 8 to 10 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0102] In summary, the memory control method and memory device proposed in this embodiment of the invention have the following technical advantages: (1) By controlling the segmented nonlinear erase voltage, the critical voltage distribution broadening and over-erasure phenomenon of memory cells can be effectively reduced; (2) By using layer-dependent voltage compensation, the erase inconsistency caused by the difference in channel resistance can be effectively balanced; (3) By using a triple verification mechanism, the probability of incompletely erased physical cells entering subsequent programs can be effectively reduced; (4) By using a collaborative scheduling and load balancing strategy for multiple physical cells, the erase throughput can be improved and power ripple can be suppressed; (5) By integrating the LDPC decoding information configuration and the hardware compensation design of the power output terminal, the system performance and operational stability can be improved.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory control method, characterized in that, For a storage device, wherein the storage device includes a three-dimensional stacked memory module, and the memory control method includes: A multi-segment nonlinear erase voltage is applied to the target physical cell in the memory module, wherein the erase voltage is adjusted in segments according to the pre-charge phase, the main erase phase, and the stabilization compensation phase; and Based on the word line layer corresponding to the target entity cell, and referring to a set of interlayer compensation parameters, the erase voltage is set with a layer-dependent voltage offset to compensate for the interlayer channel resistance difference in the target entity cell.

2. The memory control method according to claim 1, wherein during the pre-charge phase, the erase voltage increases linearly. During the main erase phase, the erase voltage increases exponentially, and During the stabilization compensation phase, the erase voltage decreases logarithmically.

3. The memory control method according to claim 1, wherein the inter-layer compensation parameters include a first offset voltage corresponding to the top word line layer, a second offset voltage corresponding to the bottom word line layer, and a third offset voltage corresponding to the middle word line layer. The first offset voltage, the second offset voltage, and the third offset voltage are all different from each other.

4. The memory control method according to claim 1 further includes: The interlayer compensation parameters are set in the voltage offset registers corresponding to each word line layer through the register group.

5. The memory control method according to claim 1, further comprising: During the erasure of the target entity unit, three erasure verification operations are performed, including: The pre-erasure verification operation is used to initially determine the baseline erase depth of each storage cell in the target entity cell; The intermediate erase verification operation dynamically adjusts the reference voltage based on a temperature compensation mechanism; and The final erase verification operation uses an asymmetric parity check matrix of a low-density parity check code for inspection.

6. The memory control method according to claim 5, wherein the asymmetric parity check matrix used in the final erase verification operation has a lateral density parameter that varies according to the entity cell number to form a dynamic row weight configuration with a density gradient.

7. The memory control method according to claim 6 further includes: Each entity unit in the memory module is configured with a decoding table storage area to store the dynamic row weight configuration for each entity unit.

8. The memory control method according to claim 1, further comprising: In a multi-channel environment, the erase priority of the target entity cell is dynamically calculated and adjusted based on the word line layer resistance factor and latency of the target entity cell. as well as Based on the erase priority, charge pump resources are allocated in relation to the erase voltage.

9. The memory control method according to claim 1, further comprising: During the erasure of the target physical unit, the output voltage ripple of the charge pump is detected; as well as In response to the instantaneous current of the output voltage ripple exceeding a predetermined threshold, an instantaneous compensation current is provided through an integrated capacitor.

10. The memory control method according to claim 1, further comprising: After the erase operation on the target physical unit is completed, a reset pulse is applied to the target physical unit to suppress the threshold voltage bounce of each memory cell in the target physical unit.

11. A storage device, characterized in that, include: A connection interface used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory module includes a three-dimensional stacked memory module, and the memory controller is used to: A multi-segment nonlinear erase voltage is applied to the target entity cell in the memory module, wherein the erase voltage is adjusted in segments according to the pre-charge stage, the main erase stage and the stabilization compensation stage; as well as Based on the word line layer corresponding to the target entity cell, and referring to a set of interlayer compensation parameters, the erase voltage is set with a layer-dependent voltage offset to compensate for the interlayer channel resistance difference in the target entity cell.

12. The storage device of claim 11, wherein during the pre-charge phase, the erase voltage increases linearly. During the main erase phase, the erase voltage increases exponentially, and During the stabilization compensation phase, the erase voltage decreases logarithmically.

13. The storage device of claim 11, wherein the interlayer compensation parameters include a first offset voltage corresponding to the top word line layer, a second offset voltage corresponding to the bottom word line layer, and a third offset voltage corresponding to the middle word line layer. The first offset voltage, the second offset voltage, and the third offset voltage are all different from each other.

14. The storage device according to claim 11, wherein the memory controller is further configured to: The interlayer compensation parameters are set in the voltage offset registers corresponding to each word line layer through the register group.

15. The storage device according to claim 11, wherein the memory controller is further configured to: During the erasure of the target entity unit, three erasure verification operations are performed, including: The pre-erasure verification operation is used to initially determine the baseline erase depth of each storage cell in the target entity cell; During the intermediate erase verification operation, the reference voltage is dynamically adjusted based on the temperature compensation mechanism. as well as The final erase verification operation uses an asymmetric parity check matrix of a low-density parity check code for inspection.

16. The storage device of claim 15, wherein the asymmetric parity check matrix used in the final erase verification operation has a lateral density parameter that varies according to the entity cell number to form a dynamic row weight configuration with a density gradient.

17. The storage device according to claim 16, wherein the memory controller is further configured to: Each entity unit in the memory module is configured with a decoding table storage area to store the dynamic row weight configuration for each entity unit.

18. The storage device according to claim 11, wherein the memory controller is further configured to: In a multi-channel environment, the erase priority of the target entity cell is dynamically calculated and adjusted based on its word line layer resistance factor and latency; and Based on the erase priority, charge pump resources are allocated in relation to the erase voltage.

19. The storage device according to claim 11, wherein the memory controller is further configured to: During the erasure of the target physical unit, the output voltage ripple of the charge pump is detected; and In response to the instantaneous current of the output voltage ripple exceeding a predetermined threshold, an instantaneous compensation current is provided through an integrated capacitor.

20. The storage device according to claim 11, wherein the memory controller is further configured to: After the erase operation on the target physical unit is completed, a reset pulse is applied to the target physical unit to suppress the threshold voltage bounce of each memory cell in the target physical unit.

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