Efuse control switching method and FPGA (Field Programmable Gate Array)

Abstract

The invention discloses an efuse control switching method and an FPGA, and belongs to the technical field of integrated circuits, and the method comprises the steps: obtaining a first efuse control signal and the model of a target efuse storage module; under the condition that the model of the target efuse storage module is not matched with the first efuse control signal, target operation is determined according to the first efuse control signal, and the target operation is programming operation or reading operation; obtaining a preset model matched with the first efuse control signal and a multiple relation between the line width of the target efuse storage module and the line width of the efuse storage module of the preset model, and determining a second operation address according to the target operation, the multiple relation between the line width of the target efuse storage module and the line width of the efuse storage module of the preset model and the first operation address; and determining a second efuse control signal based on the first efuse control signal and the second operation address, wherein the second efuse control signal is used for executing the target operation on the target efuse storage module. And the development workload and the development period of the upgrade chip are reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to an efuse control switching method and an FPGA. Background Technology

[0002] Electronic fuse (EFUSE) memory is a non-volatile, one-time memory, also known as efuse memory. Each bit of efuse memory can only be programmed once. EFUSE memory is widely used in Field Programmable Gate Array (FPGA) devices to store important information such as device identifiers and decryption keys. Typically, FPGAs interact with the efuse memory through an efuse controller to control its programming and readback. The efuse controller needs to be designed according to the efuse memory model to adapt to its operating timing. When the efuse memory model changes due to process upgrades, the efuse controller needs to be redesigned, which is a significant undertaking. Summary of the Invention

[0003] This application proposes an efuse control switching method and an FPGA to improve the above-mentioned defects.

[0004] Firstly, this application provides an efuse control switching method applied to an efuse control switching module in an FPGA. The FPGA includes a target efuse storage module and an efuse control module. The efuse control module generates a first efuse control signal. The method includes: obtaining the first efuse control signal and the model number of the target efuse storage module, wherein the first efuse control signal includes a first operation address; if the model number of the target efuse storage module does not match the first efuse control signal, determining a target operation based on the first efuse control signal, wherein the target operation is a programming operation or a read operation; obtaining... A preset model matching the first efuse control signal is selected, along with a multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module. The capacity of the target efuse storage module is the same as the capacity of the preset model efuse storage module. A second operation address is determined based on the target operation, the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, and the first operation address. A second efuse control signal is determined based on the first efuse control signal and the second operation address. The second efuse control signal is used to perform the target operation on the target efuse storage module.

[0005] Optionally, in one possible implementation, the method further includes: if the model of the target efuse storage module matches the first efuse control signal, transmitting the first efuse control signal to the target efuse storage module, wherein the first efuse control signal is used to perform a target operation on the target efuse storage module, the target operation being a programming operation or a read operation.

[0006] Optionally, in one possible implementation, the target operation is a programming operation. Determining the second operation address based on the target operation, the multiple relationship between the row width of the target efuse storage module and the row width of a preset model efuse storage module, and the first operation address includes: determining a first row and column position based on the first operation address and the preset model, where the first row and column position represents the row and column addresses in the preset model efuse storage module corresponding to the first operation address; converting the first row and column position to a second row and column position based on the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, where the second row and column position represents the row and column addresses in the target efuse storage module; and determining the second operation address based on the second row and column position and the model of the target efuse storage module.

[0007] Optionally, in one possible implementation, the first efuse control signal further includes a first enable signal and a second enable signal. The first enable signal indicates that the power supply for programming operations is turned on, and the second enable signal indicates that programming operations have started. The step of determining the second efuse control signal based on the first efuse control signal and the second operation address includes: modifying the first interval duration between the first enable signal and the second enable signal in the first efuse control signal to a second interval duration according to the model of the target efuse storage module; modifying the first operation address in the first efuse control signal to a second operation address; and using the modified first efuse control signal as the second efuse control signal.

[0008] Optionally, in one possible implementation, the target operation is a read operation. Determining the second operation address based on the target operation, the multiple relationship between the row width of the target efuse storage module and the row width of a preset model efuse storage module, and the first operation address includes: determining a first row position based on the first operation address and the preset model, where the first row position represents the row address in the preset model efuse storage module corresponding to the first operation address; converting the first row position to a second row position based on the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, where the second row position represents the row address in the target efuse storage module; and determining the second operation address based on the second row position and the model of the target efuse storage module.

[0009] Optionally, in one possible implementation, after determining the second efuse control signal based on the first efuse control signal and the second operation address, the method further includes: transmitting the second efuse control signal to the target efuse storage module; responding to the first data transmitted by the target efuse storage module, determining second data based on the first data, the multiple relationship between the row width of the target efuse storage module and the row width of a preset model efuse storage module, and outputting the second data in parallel to the efuse control module, wherein the bit width of the second data is the same as the row width of the preset model efuse storage module.

[0010] Optionally, in one possible implementation, the step of determining second data based on the first data, the row width of the target efuse storage module, and the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, and outputting the second data in parallel to the efuse control module, includes: in response to the first data transmitted by the target efuse storage module, when the row width of the preset model efuse storage module is N times the row width of the target efuse storage module, merging N consecutively acquired first data to obtain second data, and outputting the second data in parallel to the efuse control module, where N is an integer greater than 1.

[0011] Optionally, in one possible implementation, the first efuse control signal further includes an address enable signal. The step of determining the second operation address based on the target operation, the multiple relationship between the row width of the target efuse storage module and the row width of a preset model efuse storage module, and the first operation address includes: modifying the first enable duration of the address enable signal in the acquired first efuse control signal to a second enable duration based on the model of the target efuse storage module; modifying the first operation address in the first efuse control signal to the second operation address; and using the modified first efuse control signal as the second efuse control signal.

[0012] Secondly, this application also provides an FPGA, including: an efuse control adapter module; a target efuse storage module; and an efuse control module, wherein the efuse control module is connected to the efuse control adapter module, and the efuse control adapter module is connected to the target efuse storage module. The efuse control module is used to send a first efuse control signal to the efuse control adapter module. The efuse control adapter module is used to: obtain the model of the first efuse control signal and the target efuse storage module, wherein the first efuse control signal includes a first operation address; and, in the case that the model of the target efuse storage module does not match the first efuse control signal, adjust the efuse control signal according to the first efuse control module. The SE control signal determines the target operation, which is either a programming operation or a read operation; it acquires a preset model matching the first efuse control signal, the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, and the capacity of the target efuse storage module is the same as the capacity of the preset model efuse storage module; based on the target operation, the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, and the first operation address, it determines a second operation address; based on the first efuse control signal and the second operation address, it determines a second efuse control signal, which is used to perform the target operation on the target efuse storage module.

[0013] Optionally, in one possible implementation, the target operation is a programming operation. When determining the second operation address based on the target operation, the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, and the first operation address, the efuse control switching module is further configured to: determine a first row and column position based on the first operation address and the preset model, wherein the first row and column position represents the row address and column address corresponding to the first operation address in the preset model efuse storage module; convert the first row and column position to a second row and column position based on the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, wherein the second row and column position represents the row address and column address in the target efuse storage module; and determine the second operation address based on the second row and column position and the model of the target efuse storage module.

[0014] The solution provided in this application converts the first efuse control signal into a second efuse control signal when the model of the target efuse storage module does not match the first efuse control signal. The second efuse control signal is used to perform the target operation on the target efuse storage module. On the one hand, compared to redesigning the efuse control module, the workload of designing the efuse control switching method in this application is smaller. On the other hand, designing different efuse control modules for different models of storage modules is labor-intensive, while the efuse control switching method of this application, after completing the design once, only requires modifying one parameter (the model of the target efuse storage module) to complete the design of the remaining efuse control switching modules, greatly improving the development efficiency of non-first-time efuse control switching modules and reducing the development cycle of upgrade chips.

[0015] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A flowchart of the efuse control switching method provided in an embodiment of this application is shown; Figure 2 A flowchart of an efuse control switching method according to another embodiment of this application is shown; Figure 3 A schematic diagram illustrating address translation provided in an embodiment of this application is shown; Figure 4 A flowchart of an efuse control switching method according to another embodiment of this application is shown; Figure 5 A flowchart of an efuse control switching method according to another embodiment of this application is shown; Figure 6 This paper shows a block diagram of the FPGA structure provided in an embodiment of the present application; Figure 7 This application also provides a block diagram of the structure of an FPGA according to another embodiment; Figure 8 This paper shows a structural block diagram of the control conversion module provided in an embodiment of the present application; Figure 9 This paper shows a structural block diagram of the data integration module provided in an embodiment of this application; Figure 10 A flowchart of an efuse control switching method according to another embodiment of this application is shown. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. The components of the embodiments of the present application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without inventive effort are within the scope of protection of the present application.

[0019] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0020] Electrical fuse (EFUSE) memory is a non-volatile, one-time memory, also known as efuse memory. Each bit of efuse memory can only be programmed once. EFUSE memory is widely used in Field Programmable Gate Array (FPGA) devices to store important information such as device identifiers and decryption keys. Typically, the FPGA needs to interact with the efuse memory through an efuse controller to control its programming and readback. The efuse controller needs to be designed according to the efuse memory model to adapt to its operating timing.

[0021] For example, if the efuse memory in the FPGA is of type 1, then the efuse controller is designed based on the type 1 efuse memory. When the FPGA chip is upgraded in the future, the efuse memory that can be selected must also be of type 1. If it is to be replaced with type 2 efuse memory, the efuse controller needs to be redesigned. Redesigning the efuse controller not only involves a large workload, but also has a long development cycle.

[0022] Therefore, in this application embodiment, an efuse control switching method and FPGA are provided to solve or partially solve the above problems.

[0023] Please see Figure 1 The document illustrates a flowchart of an efuse control switching method provided in an embodiment of this application. This method is applied to an efuse control switching module in an FPGA. The FPGA includes a target efuse storage module and an efuse control module. The efuse control module is used to generate a first efuse control signal, specifically including steps S101 to S105.

[0024] It should be noted that the FPGA includes a Configuration and Control System (CCS). The CCS is the core management module of the FPGA, mainly used for configuration loading, dynamic reconfiguration, hardware resource control, and status monitoring to ensure that the FPGA achieves the expected functions according to the user's design. The CCS configuration system includes a target efuse storage module, an efuse control transfer module, and an efuse control module. The efuse control module is connected to the efuse control transfer module, and the efuse control transfer module is connected to the target efuse storage module. The efuse control module is used to send a first efuse control signal to the efuse control transfer module. The efuse control transfer module is used to perform programming or read operations on the target efuse storage module based on the first efuse control signal. Please refer to the subsequent description for details.

[0025] Step S101: Obtain the first efuse control signal and the model of the target efuse storage module. The first efuse control signal includes a first operation address.

[0026] It should be noted that the first efuse control signal is used to control the programming data or read data of the target efuse storage module. The target efuse storage module refers to the storage module in the FPGA chip that works in conjunction with the efuse control module. The first operation address is used to characterize the address of the read operation or programming operation corresponding to the first efuse control signal.

[0027] The model of the target efuse storage module in the chip can be determined by the chip model, and the first efuse control signal transmitted by the efuse control module can be received.

[0028] For example, the first efuse control signal includes, but is not limited to, a chip select signal, a first enable signal, a second enable signal, a programming enable signal, a read enable signal, an address enable signal, and a first operation address. The first enable signal is used to indicate that the power supply for programming operation is turned on, the second enable signal is used to indicate that programming operation is started, and the first operation address represents the address corresponding to the programming operation or the read operation.

[0029] Step S102: If the model of the target efuse storage module does not match the first efuse control signal, determine the target operation based on the first efuse control signal. The target operation is either a programming operation or a read operation.

[0030] It should be noted that the efuse control module of the FPGA chip is designed based on the model of the efuse memory module. After the efuse control module is designed, the first efuse control signal generated by the efuse control module is also fixed. Therefore, when the FPGA chip process is upgraded, the model of the efuse memory module may change. In this case, the first efuse control signal does not match the model of the target efuse memory module, and it is impossible to directly control the efuse memory module to program or read data through the first efuse control signal issued by the efuse control module.

[0031] Therefore, when the model of the target EFS storage module does not match the first EFS control signal, the first EFS control signal needs to be converted to obtain a second EFS control signal. Programming or reading operations on the target EFS storage module are then performed based on the second EFS control signal. Conversely, when the target EFS storage module matches the first EFS control signal, programming or reading operations are performed directly based on the first EFS control signal. Thus, when the model of the target EFS storage module does not match the first EFS control signal, the target operation is determined based on the first EFS control signal, facilitating the execution of subsequent operation steps based on the target operation.

[0032] As can be seen from the foregoing, when the first efuse control signal includes a read enable signal, the target operation is determined to be a read operation; when the first efuse control signal includes a programming enable signal, the target operation is determined to be a programming operation.

[0033] Step S103: Obtain the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module that matches the first efuse control signal, wherein the capacity of the target efuse storage module is the same as the capacity of the preset model efuse storage module.

[0034] It should be noted that the preset model refers to the model of the efuse storage module. The preset model can be determined based on the model of the efuse control module. The preset model matches the first efuse control signal, which means that the preset model storage module can be directly controlled to perform programming or read operations based on the first efuse control signal. The preset model can be determined based on the first efuse control signal. Furthermore, based on the storage array of the preset model efuse storage module and the storage array of the target efuse storage module, it can be determined that the row width of the target efuse storage module is a multiple of the row width of the preset model efuse storage module.

[0035] In one example, the default EFS storage module has a capacity of 2KB, a storage array of 64*32, and a row width of 32 bits. The target EFS storage module has a capacity of 2KB, a storage array of 256*8, and a row width of 8 bits.

[0036] In one example, the default EFS storage module has a capacity of 2KB, a storage array of 128*16, and a row width of 16 bits. The target EFS storage module has a capacity of 2KB, a storage array of 64*32, and a row width of 32 bits.

[0037] Step S104: Determine the second operation address based on the target operation, the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, and the first operation address.

[0038] It should be noted that the second operation address represents the operation address that matches the target efuse storage module. The second operation address is used to characterize the row address and column address in the target efuse storage module.

[0039] In one optional embodiment, if the target operation is a programming operation, a first row and column position is determined based on the first operation address and the preset model number. The first row and column position represents the row address and column address corresponding to the first operation address in the preset model efuse storage module. Based on the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, the first row and column position is converted into a second row and column position. The second row and column position represents the row address and column address in the target efuse storage module. A second operation address is determined based on the second row and column position and the model number of the target efuse storage module. For details, please refer to the following embodiments.

[0040] In one optional embodiment, if the target operation is a read operation, a first row position is determined based on the first operation address and the preset model, where the first row position represents the row address corresponding to the first operation address in the preset model efuse storage module; the first row position is converted into a second row position based on the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, where the second row position represents the row address in the target efuse storage module; a second operation address is determined based on the second row position and the model of the target efuse storage module. For details, please refer to subsequent embodiments.

[0041] Step S105: Determine a second efuse control signal based on the first efuse control signal and the second operation address. The second efuse control signal is used to perform a target operation on the target efuse storage module.

[0042] It should be noted that the first operation address in the first efuse control signal is modified to the second operation address, and the modified first efuse control signal is used as the second efuse control signal.

[0043] In one implementation scenario, the original efuse control module and storage module in the FPGA chip are matched. After a chip upgrade, the capacity of the storage module remains unchanged, but the storage array of the storage module changes; that is, the model of the target efuse storage module does not match the first efuse control signal. To address this, this application designs an efuse control switching method to convert the first efuse control signal into a second efuse control signal when the model of the target efuse storage module does not match the first efuse control signal. The second efuse control signal is then transmitted to the target efuse storage module, allowing it to perform the target operation. Compared to redesigning the efuse control module, this application's efuse control switching module requires less design work, thus reducing the workload for developers.

[0044] In one implementation scenario, designing multiple efuse control modules for multiple different models of storage arrays (without changing the capacity of the storage arrays) would be labor-intensive. However, this application designs an efuse control adapter module for one model of efuse control module. Then, for other models of storage modules, only one parameter of the efuse control adapter module (the model of the target efuse storage module) needs to be modified to complete the design of the efuse control adapter module. This greatly improves the development efficiency of the efuse control adapter module for non-first-time applications and also reduces the development cycle of the upgraded chip.

[0045] In this embodiment, firstly, a first efuse control signal and the model of the target efuse storage module are obtained, the first efuse control signal including a first operation address; secondly, if the model of the target efuse storage module does not match the first efuse control signal, a target operation is determined based on the first efuse control signal, the target operation being a programming operation or a read operation; then, a preset model matching the first efuse control signal, a multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module are obtained, the capacity of the target efuse storage module being the same as the capacity of the preset model efuse storage module; a second operation address is determined based on the target operation, the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, and the first operation address; finally, a second efuse control signal is determined based on the first efuse control signal and the second operation address, the second efuse control signal being used to perform the target operation on the target efuse storage module.

[0046] When the model of the target efuse storage module does not match the first efuse control signal, the first efuse control signal is converted into a second efuse control signal, which is used to perform the target operation on the target efuse storage module. On one hand, compared to redesigning the efuse control module, the workload of designing the efuse control switching method in this application is less. On the other hand, designing different efuse control modules for different models of storage modules is labor-intensive, while the efuse control switching method of this application, after completing one design, only requires modifying one parameter (the model of the target efuse storage module) to complete the design of the remaining efuse control switching modules, greatly improving the development efficiency of non-first-time efuse control switching modules and reducing the development cycle of upgraded chips.

[0047] In an optional embodiment, the method further includes: if the model of the target efuse storage module matches the first efuse control signal, transmitting the first efuse control signal to the target efuse storage module, wherein the first efuse control signal is used to perform a target operation on the target efuse storage module, and the target operation is a programming operation or a read operation.

[0048] When the model of the target efuse storage module matches the model of the first control module, it means that the target efuse storage module can be directly controlled to perform the target operation based on the model of the first control module, and the first efuse control signal is transmitted to the target efuse storage module.

[0049] Please see Figure 2 The document illustrates a flowchart of an efuse control switching method provided in an embodiment of this application. This method is applied to an efuse control switching module in an FPGA. The FPGA includes a target efuse storage module and an efuse control module. The efuse control module is used to generate a first efuse control signal. The target operation is a programming operation, specifically including steps S201 to S207.

[0050] Step S201: Obtain the first efuse control signal and the model of the target efuse storage module. The first efuse control signal includes a first operation address.

[0051] Step S202: If the model of the target efuse storage module does not match the first efuse control signal, determine the target operation based on the first efuse control signal. The target operation is either a programming operation or a read operation.

[0052] Step S203: Obtain the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module that matches the first efuse control signal, wherein the capacity of the target efuse storage module is the same as the capacity of the preset model efuse storage module.

[0053] Steps S201 to S203 have been described in detail in the foregoing embodiments and will not be repeated here.

[0054] Step S204: Determine the first row and column positions based on the first operation address and the preset model. The first row and column positions represent the row address and column address corresponding to the first operation address in the preset model efuse storage module.

[0055] It should be noted that when performing programming operations on the target efuse storage module, one bit of data is programmed for each programming operation. The first operation address indicates the operation address where the target operation needs to be performed, and the first row and column position can be determined based on the first operation address and the preset model.

[0056] For example, the target operation is a programming operation. The storage array of the preset model efuse storage module is 64*32, and the row width of the preset model efuse storage module is 32 bits. The first operation address is 00000100000. The lower 6 bits of the first operation address are the row address of the preset model efuse storage module, and the higher 5 bits of the first operation address are the column address of the preset model efuse storage module. Therefore, the first operation address 00000100001 corresponds to the position of row 1 and column 0 in the preset storage module.

[0057] Step S205: Based on the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, convert the first row and column positions into second row and column positions, where the second row and column positions represent the row address and column address in the target efuse storage module.

[0058] It should be noted that the target efuse storage module has the same capacity as the preset model efuse storage module. Therefore, the first row and column position can be converted to the second row and column position based on the relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module.

[0059] For example, the preset efuse storage module has a storage array of 64*32 and a row width of 32 bits. The target efuse storage module has a storage array of 256*8 and a row width of 8 bits. If the first row and column position is the 1st row and 0th column position (arranged at the 33rd position) in the preset storage module, then the second row and column position can be determined to be the 4th row and 0th column position (arranged at the 33rd position).

[0060] Step S206: Determine the second operation address based on the second row and column position and the model of the target efuse storage module.

[0061] Since the second row and column positions represent the row and column addresses in the target efuse storage module, the second operation address can be determined based on the second row and column positions and the model of the target efuse storage module.

[0062] In one example, the preset model of the efuse storage module has a storage array of 64*32 and a row width of 32 bits. The target efuse storage module has a storage array of 256*8 and a row width of 8 bits. The first operation address is 00000100000, where the lower 6 bits of the first operation address are the row address of the preset model of the efuse storage module, and the higher 5 bits are the column address. Based on the first operation address 00000100000, the first row and column position is determined to be the position of row 1, column 0 in the preset model of the efuse storage module. Converting the first row and column position to the second row and column position, we can obtain the second row and column position as the position of row 4, column 0 in the target efuse storage module. Based on the second row and column position and the model of the target efuse storage module, the second operation address is determined to be 0000100000, where the lower 8 bits of the second operation address are the row address, and the higher 3 bits are the column address.

[0063] For an example, please refer to Figure 3 This diagram illustrates the transformation from the first row and column position to the second row and column position. The target operation is a programming operation. Type 1EFUSE represents the preset EFUSE storage module, and Type 2EFUSE represents the target EFUSE storage module. The preset EFUSE storage module has a storage array of 64*32 and a row width of 32 bits. The target EFUSE storage module has a storage array of 256*8 and a row width of 8 bits. Figure 3 It can be seen that the boxes containing data7~data0 in the row with row address 0 in type 1 EFUSE point to the row with row address 0 in type 2 EFUSE, indicating that the position with row address 0 and column addresses 0 to 7 in type 1 EFUSE is converted to the position with row address 0 and column addresses 0 to 7 in type 2 EFUSE. Similarly, the target EFUSE storage module has a storage array of 256*8 and a row width of 8 bits. From Figure 3 It can be seen that the boxes containing data15~data8 in the row with row address 0 in type 1 EFUSE point to the row with row address 1 in type 2 EFUSE, indicating that the position with row address 0 and column addresses 8 to 15 in type 1 EFUSE is transformed into the position with row address 1 and column addresses 0 to 7 in type 2 EFUSE.

[0064] Step S207: Determine a second efuse control signal based on the first efuse control signal and the second operation address. The second efuse control signal is used to perform a target operation on the target efuse storage module.

[0065] Step S207 has been described in detail in the foregoing embodiments and will not be repeated here.

[0066] In one optional embodiment, step S207 specifically includes steps S2071 to S2072.

[0067] Step S2071: Modify the first interval duration between the first enable signal and the second enable signal in the first efuse control signal to the second interval duration according to the model of the target efuse storage module.

[0068] It should be noted that the first enable signal is used to indicate that the power supply for programming operation is turned on, and the second enable signal is used to indicate that the programming operation has started. During the programming operation, the power supply required for the programming operation is turned on first, and after waiting for a period of time, the programming operation begins. The purpose is to ensure that the power supply is fully turned on during the programming operation. According to the technical manual, the time interval between the first enable signal and the second enable signal is different for different models of the target efuse storage module. Therefore, it is necessary to modify the first time interval between the first enable signal and the second enable signal in the first efuse control signal to the second time interval.

[0069] Step S2072: Modify the first operation address in the first efuse control signal to the second operation address, and use the modified first efuse control signal as the second efuse control signal.

[0070] The first operation address represents the row and column position in the preset model efuse storage module, and the second operation address represents the row and column position in the target efuse storage module. The first operation address corresponding to the preset model efuse storage module and the second operation address of the target efuse storage module are equivalent. Therefore, according to the model of the target efuse storage module, the first interval duration between the first enable signal and the second enable signal in the first efuse control signal is modified to the second interval duration, and the first modified address in the first efuse control signal is modified to the second operation address to obtain the second efuse control signal.

[0071] In this embodiment, when the target operation is a programming operation, if the model of the target efuse storage module does not match the first efuse control signal, the first efuse control signal is converted into a second efuse control signal. The target efuse storage module can be controlled to perform the target operation based on the second efuse control signal. Compared with redesigning the efuse control module, the workload of designing the efuse control switching method in this application is smaller.

[0072] Please see Figure 4 The document illustrates a flowchart of an efuse control switching method provided in an embodiment of this application. This method is applied to an efuse control switching module in an FPGA. The FPGA includes a target efuse storage module and an efuse control module. The efuse control module is used to generate a first efuse control signal. The target operation is a read operation, specifically including steps S301 to S307.

[0073] Step S301: Obtain the first efuse control signal and the model of the target efuse storage module. The first efuse control signal includes a first operation address.

[0074] Step S302: If the model of the target efuse storage module does not match the first efuse control signal, determine the target operation based on the first efuse control signal. The target operation is either a programming operation or a read operation.

[0075] Step S303: Obtain the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module that matches the first efuse control signal, wherein the capacity of the target efuse storage module is the same as the capacity of the preset model efuse storage module.

[0076] Steps S301 to S303 have been described in detail in the foregoing embodiments and will not be repeated here.

[0077] Step S304: Determine the first row position based on the first operation address and the preset model. The first row position represents the row address in the preset model efuse storage module that corresponds to the first operation address.

[0078] It should be noted that when performing a read operation on the target efuse storage module, one line of data is read at a time. The first operation address indicates the address where the target operation needs to be performed. The position of the first line can be determined based on the first operation address and the preset model.

[0079] Step S305: Based on the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, convert the first row position into a second row position, where the second row position represents the row address in the target efuse storage module.

[0080] It should be noted that the target efuse storage module has the same capacity as the preset model efuse storage module. Therefore, the first row position can be converted to the second row position based on the relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module.

[0081] Step S306: Determine the second operation address based on the position of the second row and the model of the target efuse storage module.

[0082] Since the second row position represents the row address in the target efuse storage module, the second operation address can be determined based on the second row position and the target efuse storage module.

[0083] In one example, the target operation is a read operation. The preset model of the Efuse storage module has a storage column width of 64*32 and a row width of 32 bits. The first operation address is 00000100000. The lower 6 bits of the first operation address are the row address of the preset model of the Efuse storage module, and the higher 5 bits are the column address of the preset model of the Efuse storage module. Therefore, the first operation address 00000100000 corresponds to the first row in the preset model of the Efuse storage module. The first row position is determined to be the first row of the preset model of the Efuse storage module, and the second row position is the fourth row of the target Efuse storage module. Based on the second row position and the model of the target Efuse storage module, the second operation address is determined to be 0000100000. The lower 8 bits of the second operation address are the row address, and the higher 3 bits are the column address.

[0084] Step S307: Determine a second efuse control signal based on the first efuse control signal and the second operation address. The second efuse control signal is used to perform a target operation on the target efuse storage module.

[0085] Step S307 has been described in detail in the foregoing embodiments and will not be repeated here.

[0086] In one alternative embodiment, after step S307, steps S3071 to S3072 are also included.

[0087] Step S3071: Transmit the second efuse control signal to the target efuse storage module.

[0088] Understandably, the second efuse control signal can directly control the target efuse storage module to perform the target operation. Therefore, when the target operation is a read operation, the second efuse control signal is transmitted to the target efuse storage module to read data. After receiving the second efuse control signal, the target efuse storage module performs the read operation and transmits the first data corresponding to the second operation address to the efuse control transfer module.

[0089] Step S3072: In response to the first data transmitted by the target efuse storage module, determine the second data based on the first data, the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, and output the second data in parallel to the efuse control module. The bit width of the second data is the same as the row width of the preset model efuse storage module.

[0090] After receiving the first data transmitted by the target efuse storage module, the second data is determined based on the relationship between the first data, the row width of the target efuse storage module, and the row width of the preset model efuse storage module. The second data is then transmitted to the efuse control module. The second data has the same row width as the preset model efuse storage module, indicating that the second data matches the first efuse control signal.

[0091] In one optional embodiment, in response to the first data transmitted by the target efuse storage module, if the row width of the preset model efuse storage module is N times the row width of the target efuse storage module, the N consecutively acquired first data are merged to obtain second data, and the second data is output in parallel to the efuse control module, where N is an integer greater than 1.

[0092] For example, the row width of the preset model efuse storage module is 32 bits, the row width of the target efuse storage module is 8 bits, and the row width of the first data is 8 bits. Then, the four consecutively received first data are merged to obtain the second data with a width of 32 bits, and the second data is transmitted to the efuse control module, thus realizing the read operation of the efuse control module on the target efuse storage module.

[0093] In one optional embodiment, in response to the first data transmitted by the target efuse storage module, if the row width of the target efuse storage module is M times the row width of the preset model efuse storage module, the acquired first data is divided into M second data in equal proportions, and each second data is output to the efuse control module in parallel in sequence, where M is an integer greater than 1.

[0094] For example, if the row width of the target efuse storage module is 32 bits, the row width of the preset model efuse storage module is 8 bits, and the row width of the first data is 32 bits, then the received first data is split into 4 second data in equal parts, and each second data is transmitted to the efuse control module in parallel, thus realizing the read operation of the efuse control module on the target efuse storage module.

[0095] Please see Figure 5 The document illustrates a flowchart of an efuse control switching method provided in an embodiment of this application. This method is applied to an efuse control switching module in an FPGA. The FPGA includes a target efuse storage module and an efuse control module. The efuse control module is used to generate a first efuse control signal, specifically including steps S401 to S406.

[0096] Step S401: Obtain the first efuse control signal and the model of the target efuse storage module. The first efuse control signal includes the first operation address.

[0097] Step S402: If the model of the target efuse storage module does not match the first efuse control signal, determine the target operation based on the first efuse control signal. The target operation is either a programming operation or a read operation.

[0098] Step S403: Obtain the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module that matches the first efuse control signal, wherein the capacity of the target efuse storage module is the same as the capacity of the preset model efuse storage module.

[0099] Step S404: Determine the second operation address based on the target operation, the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, and the first operation address.

[0100] Steps S401 to S404 have been described in detail in the foregoing embodiments and will not be repeated here.

[0101] Step S405: Based on the model of the target efuse storage module, modify the first enable duration of the address enable signal in the first efuse control signal to the second enable duration.

[0102] It should be noted that, according to the technical manual, the address enable signal has a different duration depending on the model of the target efuse storage module. Therefore, the first enable duration of the address enable signal in the first efuse control signal needs to be modified to the second enable duration.

[0103] Step S406: Modify the first operation address in the first efuse control signal to the second operation address, and use the modified first efuse control signal as the second efuse control signal.

[0104] When the first enable duration of the address enable signal in the first efuse control signal is modified to the second enable duration, the first operation address in the first efuse control signal is modified to the second operation address, and the modified first efuse control signal is used as the second efuse control signal.

[0105] Please see Figure 6 It illustrates a block diagram of an FPGA structure provided in an embodiment of this application, including: efuse control adapter module 610.

[0106] The target is the efuse storage module 620.

[0107] An efuse control module 630 is provided, which is connected to the efuse control transfer module 610 and the target efuse storage module 620. The efuse control module 630 is used to send a first efuse control signal to the efuse control transfer module 610.

[0108] The efuse control transfer module 610 is used to: acquire a first efuse control signal and the model of a target efuse storage module, wherein the first efuse control signal includes a first operation address; if the model of the target efuse storage module does not match the first efuse control signal, determine a target operation based on the first efuse control signal, wherein the target operation is a programming operation or a read operation; acquire a preset model that matches the first efuse control signal, and the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, wherein the capacity of the target efuse storage module is the same as the capacity of the preset model efuse storage module; determine a second operation address based on the target operation, the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, and the first operation address; and determine a second efuse control signal based on the first efuse control signal and the second operation address, wherein the second efuse control signal is used to perform the target operation on the target efuse storage module.

[0109] In an optional embodiment, the efuse control transfer module 610 can also be used to: transmit the first efuse control signal to the target efuse storage module when the model of the target efuse storage module matches the first efuse control signal. The first efuse control signal is used to perform a target operation on the target efuse storage module, wherein the target operation is a programming operation or a read operation.

[0110] In one optional embodiment, the efuse control switching module 610 can also be used to: determine a first row and column position based on the first operation address and the preset model, wherein the first row and column position represents the row address and column address corresponding to the first operation address in the preset model efuse storage module; convert the first row and column position into a second row and column position based on the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, wherein the second row and column position represents the row address and column address in the target efuse storage module; and determine a second operation address based on the second row and column position and the model of the target efuse storage module.

[0111] In one optional embodiment, the efuse control switching module 610 can also be used to: convert the first row position into a second row position according to the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, wherein the second row position represents the row address in the target efuse storage module; and determine a second operation address based on the second row position and the model of the target efuse storage module.

[0112] In one optional embodiment, the efuse control transfer module 610 can also be used to: transmit the second efuse control signal to the target efuse storage module; in response to the first data transmitted by the target efuse storage module, determine the second data based on the first data, the multiple relationship between the row bit width of the target efuse storage module and the row bit width of the preset model efuse storage module, and output the second data in parallel to the efuse control module, wherein the bit width of the second data is the same as the row bit width of the preset model efuse storage module.

[0113] In one optional embodiment, the efuse control switching module 610 can also be used to: determine a first row position based on the first operation address and the preset model, wherein the first row position represents the row address corresponding to the first operation address in the preset model efuse storage module; convert the first row position into a second row position based on the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, wherein the second row position represents the row address in the target efuse storage module; and determine a second operation address based on the second row position and the model of the target efuse storage module.

[0114] In one optional embodiment, the efuse control transfer module 610 can also be used to: transmit the second efuse control signal to the target efuse storage module; in response to the first data transmitted by the target efuse storage module, determine the second data based on the first data, the multiple relationship between the row bit width of the target efuse storage module and the row bit width of the preset model efuse storage module, and output the second data in parallel to the efuse control module, wherein the bit width of the second data is the same as the row bit width of the preset model efuse storage module.

[0115] In one optional embodiment, the efuse control transfer module 610 can also be used to: in response to the first data transmitted by the target efuse storage module, when the row width of the preset model efuse storage module is N times the row width of the target efuse storage module, merge the N consecutively acquired first data to obtain second data, and output the second data in parallel to the efuse control module, where N is an integer greater than 1.

[0116] In one optional embodiment, the efuse control transfer module 610 can also be used to: modify the first enable duration of the address enable signal in the first efuse control signal to a second enable duration according to the model of the target efuse storage module; modify the first operation address in the first efuse control signal to a second operation address; and use the modified first efuse control signal as the second efuse control signal.

[0117] Please see Figure 7 This illustration shows a structural block diagram of an FPGA provided in an embodiment of this application. The FPGA includes a CCS configuration system, which includes: efuse control adapter module 610.

[0118] The target is the efuse storage module 620.

[0119] efuse control module 630.

[0120] The efuse control transfer module 610 includes a controller module 611, a control conversion module 612, an address conversion module 613, and a data integration module 614. The controller module 611 is connected to the control conversion module 612, the address conversion module 613, and the data integration module 614, respectively.

[0121] For example, the controller module 611 is a state machine used to transmit the acquired first efuse control signal to the control conversion module 612, the address conversion module 613 and the data integration module 614, and to transmit the data processed by the control conversion module 612, the address conversion module 613 and the data integration module 614 to the target efuse storage module 620.

[0122] For example, Type 1 efuse represents a preset model efuse storage module, and Type 2 efuse represents a target efuse storage module. The preset model efuse storage module has a storage array of 64*32 and a row width of 32 bits. The target efuse storage module has a storage array of 256*8 and a row width of 8 bits.

[0123] Please see Figure 8 The control conversion module 612 includes a control signal detection module 6121, a counting and waiting module 6122, and a control signal conversion output module 6123.

[0124] The control conversion module 612 receives control signals for type 1 efuse (first efuse control signals), including a programming power enable signal, a chip select signal, a programming enable signal, a read enable signal, and an address enable signal. The control signal detection module 6121 detects the enable status of the type 1 efuse control signals, and the counting and waiting module 6122 starts counting after detecting the control enable. After counting is complete, the control signal conversion output module 6123 converts the type 1 efuse control signals into type 2 efuse control signals, which include a programming power enable signal, a programming enable signal, an address enable signal, and a read enable signal. After the above operations, the timing of the type 2 efuse control signals output by the control conversion module 612 meets the timing requirements of type 2 efuse.

[0125] Address translation module 613 includes a first address decoding unit, an address mapping unit, and a second address decoding unit.

[0126] The first address decoding unit is used to convert the first operation address in the type 1 efuse control signal into the row and column address in the preset model efuse storage module. The address mapping unit is used to map the row and column address in the preset model efuse storage module to the row and column address in the target efuse storage module. The second address decoding unit is used to convert the row and column address of the target efuse storage module into the second operation address.

[0127] Please see Figure 9The data integration module 614 includes a data sampling module 6141, a data sampling counting module 6142, and a data integration output module 6143.

[0128] The data integration module 614 is used to integrate the readback data of Type 2 efuse. efuse read operations are performed in row address units, reading back one row of data at a time. Type 1 efuse readback returns 32 bits of stored data, while Type 2 efuse readback returns 8 bits of stored data. When reading back from Type 2 efuse, the data sampling module 6141 samples 8 bits of readback data each time, and the data sampling counting module 6142 counts the number of data samples. After four counts, the data integration output module 6143 outputs a set of 32 bits of readback data and transmits it to the 32-bit efuse readback data bus.

[0129] For example, please refer to Figure 10 This document illustrates a flowchart of an efuse control switching method provided in an embodiment of this application. Type 1 efuse represents a preset model efuse storage module, and Type 2 efuse represents a target efuse storage module. The preset model efuse storage module has a storage array of 64*32 and a row width of 32 bits. The target efuse storage module has a storage array of 256*8 and a row width of 8 bits. The method includes the following steps.

[0130] Step S0: Enable control check.

[0131] It should be noted that, according to Figure 7 It can be seen that the efuse control module 630 sends an enable control signal to the efuse control transfer module 610. The enable control signal transmitted by the efuse control module 630 can be used to determine whether it is enabled. If the enable control is enabled, it means that the first efuse control signal needs to be converted. If the enable control signal is disabled, it means that the first efuse control signal does not need to be converted.

[0132] Step S40: If the efuse control conversion module is not enabled, no conversion processing is performed on the type 1 efuse control signal (first efuse control signal), address, and readback data.

[0133] Step S10: Should EFUSE be performed?

[0134] It should be noted that if the EFUSE control adapter module is enabled, it determines whether to operate EFUSE. The EFUSE control adapter module will only perform read or programming operations after receiving the chip select signal; receiving the chip select signal indicates that EFUSE needs to be operated. Step S20: Read EFUSE.

[0135] To perform an EFUSE operation, it is necessary to determine whether the current operation is a read EFUSE operation. Based on the aforementioned information, the determination of whether the current operation is a read EFUSE operation can be made based on the first EFUSE control signal, which will not be elaborated upon here.

[0136] Step S21: Control the conversion of row addresses.

[0137] If the current operation is a read EFUSE, the control conversion module 612 converts the type 1 EFUSE control signal, the address conversion module 613 converts the row address, and the readback does not require conversion of the column address. The controller module 611 accesses the target EFUSE storage module 610 through the converted type 2 EFUSE control signal (the second EFUSE control signal) and the address.

[0138] Step S22: Read 4 address data and output 32-bit EFUSE data.

[0139] The data integration module 614 begins receiving EFUSE readback data, reading back 8 bits of data each time. After reading the data 4 times, the readback data is integrated into 32 bits of data and transmitted to the 32-bit EFUSE readback data bus.

[0140] Step S23: Should we continue reading the next address?

[0141] Determine whether to continue reading EFUSE data at the next address. If to continue reading, return to step S20 and its subsequent steps.

[0142] Step S30: Enable programming power control conversion of row and column address conversion.

[0143] If the current operation is a programming EFUSE operation, the control conversion module 612 converts the type 1 EFUSE control signal and turns on the EFUSE programming power. Since the power establishment time of the two types of EFUSE is different, the control conversion module 612 will adjust the interval between the programming power enable and the programming enable to ensure that the type 2 EFUSE has enough time to switch to the programming power voltage. The address conversion module 613 converts the row and column addresses, and the controller module 611 operates the type 2 EFUSE through the converted type 2 EFUSE control signal and address.

[0144] Step S31, program EFUSE to turn off the programming power.

[0145] The control conversion module 612 detects the received Type 1 efuse address enable signal and outputs a Type 2 efuse address enable signal. Since the enable time of the Type 1 efuse address enable signal is flexibly adjustable, only the enable time length needs to be adjusted to meet the enable time requirement of the Type 2 efuse address enable signal. After the control conversion module 612 detects that the address enable signal is turned off, it sequentially turns off the programming enable signal and the programming power enable signal, and controls the time interval between the turn-off of the two signals to ensure the hold time requirement between the programming enable and the programming power.

[0146] Step S32: Should we continue programming the next address?

[0147] Determine whether to continue programming EFUSE. If to continue programming, return to step S30 and its subsequent steps.

[0148] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described device and module can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0149] In the several embodiments provided in this application, the coupling between modules can be electrical, mechanical, or other forms of coupling.

[0150] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An efuse control switching method, characterized in that, An efuse control switching module applied in an FPGA, wherein the FPGA includes a target efuse storage module and an efuse control module, the efuse control module being used to generate a first efuse control signal, the method comprising: Obtain the first efuse control signal and the model of the target efuse storage module, wherein the first efuse control signal includes a first operation address; If the model of the target efuse storage module does not match the first efuse control signal, the target operation is determined according to the first efuse control signal, and the target operation is a programming operation or a read operation. Obtain the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module that matches the first efuse control signal, and the capacity of the target efuse storage module is the same as the capacity of the preset model efuse storage module; The second operation address is determined based on the target operation, the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, and the first operation address; A second efuse control signal is determined based on the first efuse control signal and the second operation address. The second efuse control signal is used to perform a target operation on the target efuse storage module.

2. The method according to claim 1, characterized in that, Also includes: When the model of the target efuse storage module matches the first efuse control signal, the first efuse control signal is transmitted to the target efuse storage module. The first efuse control signal is used to perform a target operation on the target efuse storage module, which is a programming operation or a read operation.

3. The method according to claim 1, characterized in that, The target operation is a programming operation. Determining the second operation address based on the target operation, the multiple relationship between the row width of the target EFUSE storage module and the row width of a preset EFUSE storage module, and the first operation address includes: The first row and column positions are determined based on the first operation address and the preset model. The first row and column positions represent the row address and column address corresponding to the first operation address in the preset model efuse storage module. Based on the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, the first row and column positions are converted into second row and column positions, where the second row and column positions represent the row address and column address in the target efuse storage module; The second operation address is determined based on the second row and column position and the model of the target efuse storage module.

4. The method according to claim 3, characterized in that, The first efuse control signal further includes a first enable signal and a second enable signal. The first enable signal indicates that the power supply for programming operations is turned on, and the second enable signal indicates that programming operations have started. Determining the second efuse control signal based on the first efuse control signal and the second operation address includes: Based on the model of the target efuse storage module, the first interval duration between the first enable signal and the second enable signal in the first efuse control signal is modified to the second interval duration; In the first efuse control signal, the first operation address is modified to the second operation address, and the modified first efuse control signal is used as the second efuse control signal.

5. The method according to claim 1, characterized in that, The target operation is a read operation. The step of determining the second operation address based on the target operation, the multiple relationship between the row width of the target EFUSE storage module and the row width of a preset EFUSE storage module, and the first operation address includes: The first row position is determined based on the first operation address and the preset model, where the first row position represents the row address corresponding to the first operation address in the preset model efuse storage module. Based on the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, the first row position is converted into the second row position, where the second row position represents the row address in the target efuse storage module; The second operation address is determined based on the position of the second row and the model of the target efuse storage module.

6. The method according to claim 5, characterized in that, After determining the second efuse control signal based on the first efuse control signal and the second operation address, the method further includes: The second efuse control signal is transmitted to the target efuse storage module; In response to the first data transmitted by the target efuse storage module, a second data is determined based on the first data, the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, and the second data is output in parallel to the efuse control module. The bit width of the second data is the same as the row width of the preset model efuse storage module.

7. The method according to claim 6, characterized in that, The process of responding to the first data transmitted by the target efuse storage module, determining second data based on the first data and the multiple relationship between the row width of the target efuse storage module and the row width of a preset model efuse storage module, and outputting the second data in parallel to the efuse control module includes: In response to the first data transmitted by the target efuse storage module, if the row width of the preset model efuse storage module is N times the row width of the target efuse storage module, the N consecutively acquired first data are merged to obtain the second data, and the second data is output in parallel to the efuse control module, where N is an integer greater than 1.

8. The method according to claim 1, characterized in that, The first efuse control signal also includes an address enable signal. The step of determining the second operation address based on the target operation, the multiple relationship between the row width of the target efuse storage module and the row width of a preset model efuse storage module, and the first operation address includes: Based on the model of the target efuse storage module, the first enable duration of the address enable signal in the first efuse control signal is modified to the second enable duration. In the first efuse control signal, the first operation address is modified to the second operation address, and the modified first efuse control signal is used as the second efuse control signal.

9. An FPGA, characterized in that, include: efuse control adapter module; Target: efuse storage module; An efuse control module is connected to the efuse control transfer module, and the efuse control transfer module is connected to the target efuse storage module. The efuse control module is used to send a first efuse control signal to the efuse control transfer module. The efuse control adapter module is used for: Obtain the first efuse control signal and the model of the target efuse storage module, wherein the first efuse control signal includes a first operation address; If the model of the target efuse storage module does not match the first efuse control signal, the target operation is determined according to the first efuse control signal, and the target operation is a programming operation or a read operation. Obtain the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module that matches the first efuse control signal, and the capacity of the target efuse storage module is the same as the capacity of the preset model efuse storage module; The second operation address is determined based on the target operation, the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, and the first operation address; A second efuse control signal is determined based on the first efuse control signal and the second operation address. The second efuse control signal is used to perform a target operation on the target efuse storage module.

10. The FPGA according to claim 9, characterized in that, The target operation is a programming operation. When determining the second operation address based on the target operation, the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, and the first operation address, the efuse control switching module is further used for: The first row and column positions are determined based on the first operation address and the preset model. The first row and column positions represent the row address and column address corresponding to the first operation address in the preset model efuse storage module. Based on the multiple relationship between the row width of the target efuse storage module and the row width of the preset model efuse storage module, the first row and column positions are converted into second row and column positions, where the second row and column positions represent the row address and column address in the target efuse storage module; The second operation address is determined based on the second row and column position and the model of the target efuse storage module.

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