Package and method of forming same

Abstract

The embodiment of the invention discloses a package and a method of forming the same. A method of forming a package includes forming a first photoresist layer on a dielectric layer; performing a first exposure process on the first photoresist layer using a first lithography mask, during which a first region of the first photoresist layer is blocked from being exposed, a second region of the first photoresist layer is exposed, and a third region of the first photoresist layer is exposed, the second region surrounding the first region, and the third region surrounding the second region; the third area surrounds the second area; performing a second exposure process on the first photoresist layer using a second lithography mask, in which a first region of the first photoresist layer is exposed, a second region of the first photoresist layer is exposed, and a third region of the first photoresist layer is blocked from being exposed; and developing the first photoresist layer.

Description

Technical Field

[0001] Embodiments of this application relate to packages and methods of forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, this increase in integration density is due to iterative reductions in the smallest component size, allowing more components to be integrated into a given area. As the demand for miniaturized electronics grows, so too does the need for smaller, more innovative semiconductor die-packaging technologies. One example is the chip-on-wafer (CoWoS) structure, where one or more semiconductor devices are connected to an interposer, which is then connected to a packaging substrate (e.g., a printed circuit board). Summary of the Invention

[0003] According to one aspect of the embodiments of this application, a method for forming a package is provided, comprising: forming a first photoresist layer on a dielectric layer; performing a first exposure process on the first photoresist layer using a first photomask, wherein during the first exposure process, a first region of the first photoresist layer is blocked from being exposed, a second region of the first photoresist layer is exposed, and a third region of the first photoresist layer is exposed, wherein the second region surrounds the first region, and the third region surrounds the second region; performing a second exposure process on the first photoresist layer using a second photomask, wherein in the second exposure process, the first region of the first photoresist layer is exposed, the second region of the first photoresist layer is exposed, and the third region of the first photoresist layer is blocked from being exposed; and developing the first photoresist layer.

[0004] According to another aspect of the embodiments of this application, a method for forming a package is provided, comprising: exposing a first pattern in a first pattern region of a first photoresist layer, wherein the first pattern has a first linewidth; exposing a second pattern in a second pattern region of the first photoresist layer, wherein the second pattern has a second linewidth smaller than the first linewidth, wherein the first pattern region laterally surrounds the second pattern region; performing a first development process on the first pattern region and the second pattern region of the first photoresist layer to form a pattern in the first photoresist layer; and depositing a conductive material in the pattern of the first photoresist layer.

[0005] According to another aspect of the embodiments of this application, a package is provided, comprising: a redistribution interposer including a plurality of redistribution layers among a plurality of dielectric layers, wherein each of the plurality of redistribution layers has a first region surrounding the second region, the first region having a first pitch, the second region having a second pitch, wherein the second pitch is smaller than the first pitch, wherein the first region is adjacent to each sidewall of the redistribution interposer; a semiconductor die bonded to a first side of the redistribution interposer; and a package substrate bonded to a second side of the redistribution interposer. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1 to 16 A cross-sectional view is shown of an intermediate step in the process of forming a redistributed intermediary layer according to some embodiments.

[0008] Figure 17 A cross-sectional view is shown of the intermediate steps in forming the redistribution intermediary layer according to some embodiments.

[0009] Figure 18 and Figure 19 A plan view is shown of the intermediate steps in forming a redistribution intermediary layer according to some embodiments.

[0010] Figures 20 to 31 A plan view is shown of the intermediate steps in forming a redistribution intermediary layer according to some embodiments.

[0011] Figures 32 to 44 A cross-sectional view is shown of an intermediate step in the process of forming a redistributed intermediary layer according to some embodiments.

[0012] Figures 45 to 47 A cross-sectional view is shown of an intermediate step in the process of forming a packaged component according to some embodiments.

[0013] Figure 48 A cross-sectional view is shown of an intermediate step in the formation of a package according to some embodiments. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0016] According to some embodiments, a redistributable interposer layer is formed for a packaged component. Each redistributable interposer layer is formed using a double-exposure lithography technique, which uses multiple exposures of overlapping patterned regions. In some embodiments, a first patterned region surrounds a second patterned region, and the first and second patterned regions are exposed in different exposure steps using different lithographic masks. This allows for the formation of a larger redistributable interposer layer with finer redistributive layers, which can improve the functionality of larger redistributable interposers. The techniques described herein can allow for larger redistributable interposers, thereby improving routing and reducing costs.

[0017] Figures 1 to 16 Cross-sectional and plan views of intermediate steps in forming a redistributed intermediary layer according to some embodiments are shown. Figures 1-16 The process steps shown may be related to the formation of the redistribution interposer 240 (see...). Figure 44 The process steps are similar, and will be described in more detail below.

[0018] exist Figure 1 In some embodiments, a carrier substrate 10 is provided. The carrier substrate 10 may be a glass carrier substrate, a ceramic carrier substrate, a die-attachment film (DAF), etc. The carrier substrate 10 may be a wafer, etc., thereby allowing multiple packages to be formed simultaneously on the carrier substrate 10.

[0019] In some embodiments, a release layer (not shown) is formed on the carrier substrate 10. The release layer may be formed of a polymer-based material, which may be removed along with the carrier substrate 10 from the overlay structure to be formed in subsequent steps. In some embodiments, the release layer is an epoxy-based thermal release material that loses its adhesiveness upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, the release layer may be a UV adhesive that loses its adhesiveness upon exposure to UV light. The release layer may be dispensed and cured as a liquid, may be a laminated film laminated onto the carrier substrate 10, or may be the like. The top surface of the release layer may be flat and may have a high degree of flatness.

[0020] The carrier substrate 10 includes a first patterned region 100A, a second patterned region 100B, and an overlapping region 100AB. The first patterned region 100A and the second patterned region 100B are regions of the carrier substrate 10 where photolithography processes are performed in separate steps. For example, the first patterned region 100A of a photosensitive layer (e.g., a photoresist layer, a photomask, etc.) may be exposed to light in a first exposure process, and the second patterned region 100B of the photosensitive layer may be exposed to light in a second exposure process. The overlapping region 100AB is a region exposed to light in both the first exposure process (together with the first patterned region 100A) and the second exposure process (together with the second patterned region 100B). In this way, the overlapping region 100AB can be considered as part of the first patterned region 100A and the second patterned region 100B, and can be considered as a "stitched region," etc. In some embodiments, the first patterned region 100A may surround the second patterned region 100B, as will be described in more detail below. In this way, the size (e.g., area or dimension) of the first patterned region 100A can be larger than the size of the second patterned region 100B. In some embodiments, multiple second patterned regions 100B may exist, with a corresponding overlapping region 100AB between the first patterned region 100A and each second patterned region 100B. In some embodiments, the width W1 of the overlapping region 100AB can be in the range of about 1 μm to about 50 μm, but other widths are also possible.

[0021] Still referencing Figure 1According to some embodiments, a dielectric layer 20 is formed on a carrier substrate 10. If a release layer is present, the dielectric layer 20 may be formed on the release layer. The bottom surface of the dielectric layer 20 may contact the top surface of the carrier substrate 10 or the top surface of the release layer. In some embodiments, the dielectric layer 20 is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the dielectric layer 20 is formed of materials such as nitrides, such as silicon nitride; oxides, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; or similar materials. In other embodiments, the dielectric layer 20 may be a molding compound, epoxy resin, or any other suitable material. The dielectric layer 20 may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, etc., or combinations thereof. In some cases, the dielectric layer 20 may be considered as a passivation layer, an insulating layer, and / or an isolation layer. In other embodiments, metallization patterns or other conductive components (not shown) may first be formed on the carrier substrate 10 and then covered by the dielectric layer 20.

[0022] exist Figure 2 In some embodiments, a first photoresist layer 21 is formed on the dielectric layer 20. The first photoresist layer 21 can be, for example, a single-layer photoresist, a double-layer photoresist, a triple-layer photoresist, a multilayer of different materials, a photoresist structure, etc. Furthermore, in the embodiments discussed below, it is assumed that the first photoresist layer 21 is a positive photoresist, wherein the exposed portion is removed, and the unexposed portion is retained after the exposure process and subsequent development process. According to alternative embodiments, the first photoresist layer 21 comprises a negative photoresist, wherein the unexposed portion is removed, and the exposed portion is retained after the exposure process and subsequent development process. The first photoresist layer 21 can be formed using suitable techniques, such as spin coating, CVD, lamination, etc., or combinations thereof. In other embodiments where the dielectric layer 20 is a photosensitive material that can be patterned using photolithography, the first photoresist layer 21 may not be formed. In such embodiments, the dielectric layer 20 can be a photosensitive material, such as PBO, polyimide, BCB, etc.

[0023] exist Figure 3 In some embodiments, a first exposure process is performed to expose a portion of the first photoresist layer 21 in the first patterned region 100A and the overlapping region 100AB. The first exposure process may include positioning a first photomask 50A (e.g., a mask, photomask, etc.) on the first photoresist layer 21 and exposing the first photomask 50A to light (e.g., light source light). Figure 3(As indicated by the arrow in the image). The first photomask 50A includes an opaque region that blocks light and a transparent region that allows light to pass through the first photomask 50A to the first photoresist layer 21. The transparent region of the first photomask 50A corresponds to the pattern of the portion of the first photoresist layer 21 exposed to light and subsequently removed. An example exposed portion of the first photoresist layer 21 in the first patterned region 100A is shown in... Figure 3 The portion shown in the image is 21A'. Although Figure 3 Only the exposed portion of the first photoresist layer 21 in the first patterned region 100A is shown, but a portion of the first photoresist layer 21 in the overlapping region 100AB may also be exposed.

[0024] It is worth noting that the first photomask 50A exposes only a portion of the first photoresist layer 21 in the first patterned region 100A and the overlapping region 100AB. For example, the first photomask 50A may include a large opaque region continuously extending over the second patterned region 100B. Therefore, during the first exposure process, the second patterned region 100B of the first photoresist layer 21 is not exposed. The size (e.g., area) of the first photomask 50A may be large enough to cover the entire redistributed interposer subsequently formed. In some embodiments, the opaque region of the first photomask 50A corresponding to the second patterned region 100B may be surrounded (e.g., laterally surrounded) by the transparent patterned region of the first photomask 50A corresponding to the first patterned region 100A and the overlapping region 100AB.

[0025] exist Figure 4 In some embodiments, a second exposure process is performed to expose a portion of the first photoresist layer 21 in the second patterned region 100B and the overlapping region 100AB. The second exposure process may include positioning a second photomask 50B (e.g., a mask, photomask, etc.) on the first photoresist layer 21 and exposing the second mask 50B to light (e.g., light source light). Figure 4 (As indicated by the arrow in the image). The second photomask 50B includes an opaque region that blocks light and a transparent region that allows light to pass through the second photomask 50B to the first photoresist layer 21. The transparent region of the second photomask 50B corresponds to the pattern of the portion of the first photoresist layer 21 that is exposed and subsequently removed. An example exposed portion of the first photoresist layer 21 in the second patterned region 100B is shown in... Figure 4 The portion shown in the middle is designated as 21B'. Although Figure 4 Only the exposed portion of the first photoresist layer 21 in the second patterned region 100B is shown, but a portion of the first photoresist layer 21 in the overlapping region 100AB may also be exposed.

[0026] It is worth noting that the second photomask 50B exposes only a portion of the first photoresist layer 21 within the second patterned region 100B and the overlapping region 100AB. For example, the second photomask 50B may include an opaque region continuously extending around the second patterned region 100B and the overlapping region 100AB. Therefore, during the second exposure process, the first patterned region 100A of the first photoresist layer 21 is not exposed. In some embodiments, when multiple second patterned regions 100B exist, the same second photomask 50B can be used to expose multiple third patterned regions 100B. For example, the second photomask 50B can expose the first and second patterned regions 100B, reposition itself on the second patterned regions 100B, and then be used to expose the second patterned regions 100B in a separate exposure process. In some embodiments, because the size of the first patterned region 100A is larger than the size of the second patterned region 100B, the size of the transparent region of the first photomask 50A can be larger than the size of the transparent region of the second photomask 50B. In some cases, the size of the first photomask 50A may be larger than the size of the second photomask 50B. In some embodiments, the component dimensions (e.g., linewidth, pitch, spacing, etc.) of the pattern on the second photomask 50B are smaller than the component dimensions of the pattern on the first photomask 50A. For example, in some embodiments, the linewidth of the components on the first photomask 50A may be approximately 5 μm, and the linewidth of the components on the second photomask 50B may be approximately 2 μm. Other linewidths are also possible. Figures 3-4 A first exposure process using a first photomask 50A and a second exposure process using a second photomask 50B are shown. However, in other embodiments, the first exposure process may use the second photomask 50B and the second exposure process may use the first photomask 50A.

[0027] exist Figure 5 In some embodiments, the first photoresist layer 21 is developed to form openings 22A, 22B. In some embodiments, openings 22A, 22B expose the underlying dielectric layer 20. The first photoresist layer 21 can be developed using a suitable photolithography technique that removes the exposed portions of the first photoresist layer 21. For example, the exposed portion 21A' is removed to form opening 22A, and the exposed portion 21B' is removed to form hole 22B. In this way, the first photoresist layer 21 can be patterned using a first exposure process and a second exposure process.

[0028] exist Figure 6In some embodiments, an etching process is performed to extend openings 22A, 22B through dielectric layer 20. In this way, the patterned first photoresist layer 21 can be used as an etching mask. The etching process may include a wet etching process and / or a dry etching process, which may be anisotropic etching. In some embodiments, openings 22A, 22B in dielectric layer 20 correspond to a subsequently formed redistribution layer (e.g., Figure 14 The via portions of the redistribution layer 30). In embodiments where a metallization pattern is first formed on the carrier substrate 10, openings 22A and 22B in the dielectric layer 20 can expose the metallization pattern. After etching the dielectric layer 20, the first photoresist layer 21 can be removed, such as... Figure 7 As shown. The first photoresist layer 21 can be removed using an acceptable ashing or stripping process (e.g., using oxygen plasma).

[0029] exist Figure 8 In some embodiments, a seed layer 24 is deposited on the dielectric layer 20 and extends into openings 22A and 22B. In some embodiments, the seed layer 24 is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer 24 comprises a titanium layer and a copper layer on the titanium layer. The seed layer 24 can be formed using, for example, physical vapor deposition (PVD). In some cases, the deposition of the seed layer 24 may be conformal.

[0030] exist Figure 9 In some embodiments, a second photoresist layer 23 is formed on the seed layer 24. In some cases, the second photoresist layer 23 may be similar to the first photoresist layer 21. For example, the second photoresist layer 23 may be a single-layer photoresist, a double-layer photoresist, a triple-layer photoresist, a multilayer of different materials, a photoresist structure, etc. Furthermore, in the embodiments discussed below, it is assumed that the second photoresist layer 23 is a positive photoresist, wherein after the exposure process and subsequent development process, the exposed portion is removed, and the unexposed portion is retained. According to alternative embodiments, the second photoresist layer 23 comprises a negative photoresist, wherein after the exposure process and subsequent development process, the unexposed portion is removed, and the exposed portion is retained. The second photoresist layer 23 may be formed using suitable techniques, such as spin coating, CVD, lamination, etc., or combinations thereof.

[0031] exist Figure 10 In some embodiments, a first exposure process is performed to expose a portion of the second photoresist layer 23 in the first patterned region 100A and the overlapping region 100AB. The first exposure process may include positioning a first photomask 60A (e.g., a mask, photomask, etc.) on the second photoresist layer 23 and exposing the first photomask 60A to light (e.g., light source light). Figure 10(As indicated by the arrows in the diagram). The first photomask 60A differs from the first photomask 50A used for patterning the first photoresist layer 21, but it may have some similarities. For example, the transparent areas of the first photomask 60A correspond to the patterned portions of the second photoresist layer 23 that are exposed and subsequently removed. Example exposed portions of the second photoresist layer 23 in the first patterned region 100A and the overlapping region 100AB are shown in... Figure 10 The part in the middle is represented as 23A'.

[0032] It is worth noting that the first photomask 60A exposes only a portion of the second photoresist layer 23 in the first patterned region 100A and the overlapping region 100AB. For example, the first photomask 60A may include a large opaque region extending continuously over the second patterned region 100B. Therefore, during the first exposure process, the second patterned region 100B of the second photoresist layer 23 is not exposed. The size (e.g., area) of the first photomask 60A may be large enough to cover the entire redistributed interposer subsequently formed. In some embodiments, the opaque region of the first photomask 60A corresponding to the second patterned region 100B may be surrounded (e.g., laterally surrounded) by the transparent patterned region of the first photomask 60A corresponding to the first patterned region 100A and the overlapping region 100AB.

[0033] exist Figure 11 In some embodiments, a second exposure process is performed to expose portions of the second photoresist layer 23 in the second patterned region 100B and the overlapping region 100AB. The second exposure process may include positioning a second photomask 60B (e.g., a mask, photomask, etc.) on the second photoresist layer 23 and exposing the second photomask 60B to light (e.g., light source light). Figure 11 (As indicated by the arrow in the image). The second photomask 60B includes an opaque region that blocks light and a transparent region that allows light to pass through the second photomask 60B to the second photoresist layer 23. The transparent region of the second photomask 60B corresponds to the pattern of the exposed and subsequently removed portion of the second photoresist layer 23.

[0034] An example exposure portion of the second photoresist layer 23 in the second pattern region 100B is shown in... Figure 11 This is represented as exposure portion 23B'. Furthermore, during the first exposure process, a portion of the second photoresist layer 23 in the previously exposed overlapping region 100AB can be re-exposed during the second exposure process. An example of a "double exposure" portion of the second photoresist layer 23 is shown in... Figure 11 This is represented as double exposure portion 23AB'. It should be noted that double exposure portion 23AB' includes a portion of the exposure portion 23A' within the overlapping region 100AB. For example... Figure 11As shown, the second photoresist layer 23 may have an exposure portion that extends continuously from the first patterned region 100A through the overlapping region 100AB and into the second patterned region 100B. In this way, the exposure portions of the first patterned region 100A and the second patterned region 100B can be "stitched" together by the double exposure portion of the overlapping region 100AB. In some cases, during the first exposure process or the second exposure process, a portion of the second photoresist layer 23 in the overlapping region 100AB may be exposed only once.

[0035] It is worth noting that the second photomask 60B exposes only a portion of the second photoresist layer 23 in the second patterned region 100B and the overlapping region 100AB. For example, the second photomask 60B may include an opaque region extending continuously around the second patterned region 100B and the overlapping region 100AB. Therefore, during the second exposure process, the first patterned region 100A of the second photoresist layer 23 is not exposed to light. In some embodiments, when multiple second patterned regions 100B exist, the same second photomask 60B can be used to expose multiple second patterned regions 100B. For example, the second photomask 60B can expose the second patterned region 100B, reposition it on the second patterned region 100B, and then be used to expose the second patterned region 100B in a separate exposure process. In some embodiments, because the size of the first patterned region 100A is larger than the size of the second patterned region 100B, the size of the transparent region of the first photomask 60A can be larger than the size of the transparent region of the second photomask 60B. In some cases, the size of the first photomask 60A may be larger than the size of the second photomask 60B. In some embodiments, the component dimensions (e.g., linewidth, pitch, etc.) of the pattern on the second photomask 60B are smaller than the component dimensions of the pattern on the first photomask 60A. For example, in some embodiments, the linewidth of the components on the first photomask 60A may be approximately 5 μm, and the linewidth of the components on the second photomask 60B may be approximately 2 μm. Other linewidths are also possible. Figures 10-11 A first exposure process using a first photomask 60A and a second exposure process using a second photomask 60B are shown, but in other embodiments, the first exposure process may use the second photomask 60B and the second exposure process may use the first photomask 60A.

[0036] exist Figure 12In some embodiments, the second photoresist layer 23 is developed to form an opening 26. The opening 26 exposes the seed layer 24 and includes previously formed openings 22A, 22B. The opening 26 extends from the first patterned region 100A through the overlapping region 100AB and into the second patterned region 100B. In other embodiments, openings similar to the opening 26 may exist in the first patterned region 100A, the overlapping region 100AB, or the second patterned region 100B, or extend between or through one or more of these regions. The second photoresist layer 23 can be developed using a suitable photolithography technique that removes exposed portions of the second photoresist layer 23. For example, exposed portions 23A', 23AB', and 23B' are all removed to form the opening 26. In this way, the second photoresist layer 23 can be patterned using a first exposure process and a second exposure process, and may include double exposure of some portions of the second photoresist layer 23.

[0037] exist Figure 13 In this process, conductive material 28 is formed on the exposed portion of the seed layer 24 within the opening 26 of the second photoresist layer 23. The conductive material 28 can be formed by CVD, physical vapor deposition (PVD), plating (e.g., electroplating or electroless plating), etc. The conductive material 28 may include metals such as copper, titanium, tungsten, aluminum, ruthenium, cobalt, etc., or combinations thereof. Other materials are also possible. In some embodiments, the thickness of the conductive material 28 may be less than the thickness of the second photoresist layer 23.

[0038] exist Figure 14 In some embodiments, a portion of the second photoresist layer 23 and the underlying seed layer 24 is removed to form a redistribution layer 30. The second photoresist layer 23 can be removed using an acceptable ashing or stripping process (e.g., using oxygen plasma). Once the second photoresist layer 23 is removed, the exposed portion of the seed layer 24 is removed using, for example, an acceptable wet or dry etching process. The remaining portions of the seed layer 24 and the conductive material 28 form the redistribution layer 30. In some embodiments, the redistribution layer 30 includes conductive via portions extending through the dielectric layer 20 and conductive portions extending along the top surface of the dielectric layer 20. In some cases, the redistribution layer 30 can be considered as redistribution lines, metallization patterns, wiring layers, etc.

[0039] exist Figure 15In some embodiments, dielectric layer 32 is formed on redistribution layer 30 and dielectric layer 20. Dielectric layer 32 can be a material similar to or different from dielectric layer 20. For example, in some embodiments, dielectric layer 32 is formed of a polymer, such as PBO, polyimide, BCB, etc. In other embodiments, dielectric layer 32 is formed of materials such as nitrides, such as silicon nitride; oxides, such as silicon oxide, PSG, BSG, BPSG, etc.; molding materials; or similar materials. In some embodiments, dielectric layer 32 is a photosensitive material, such as PBO, polyimide, BCB, etc., which can be patterned using a photomask. Dielectric layer 32 can be formed by spin coating, lamination, CVD, etc., or combinations thereof.

[0040] Figure 15 A single redistribution layer 30 is shown, but in some embodiments, a process similar to that used to form redistribution layer 30 can be performed to form additional redistribution layers as part of a redistribution interposer, etc. In this way, the redistribution interposer can include any number of dielectric layers and redistribution layers. If more dielectric layers and redistribution layers are to be formed, steps and processes similar to those described above can be repeated. For example, in some embodiments, the redistribution interposer can include a stack of six or more redistribution layers, but more or fewer redistribution layers are also possible.

[0041] As an example, Figure 16 An additional redistribution layer 34 formed on redistribution layer 30 according to some embodiments is shown. Redistribution layer 34 extends through a first patterned region 100A, an overlap region 100AB, and a second patterned region 100B. Via portions of redistribution layer 34 extend through dielectric layer 32 to physically and electrically connect redistribution layer 30. Like redistribution layer 30, redistribution layer 34 is an illustrative example; other arrangements or configurations are possible. Redistribution layer 34 can be formed using steps similar to those described for redistribution layer 30. For example, a first photoresist layer can be formed on dielectric layer 32 and patterned using two exposure processes. The patterned first photoresist layer can be used as an etching mask to form an opening through dielectric layer 32 that exposes redistribution layer 30. A seed layer can then be deposited on dielectric layer 32 and in the opening. A second photoresist layer can then be formed on the seed layer and patterned using two exposure processes. A conductive material can be deposited on the exposed portions of the seed layer. The second photoresist layer and a portion of the seed layer beneath it can then be removed, leaving the conductive material and the remaining portion of the seed layer to form a redistribution layer 34. Furthermore, an additional dielectric layer, similar to dielectric layer 20 or dielectric layer 32, can be formed on the redistribution layer 34 and the dielectric layer 32. Depending on the functional and structural requirements of the redistribution interposer, additional redistribution layers and / or dielectric layers can be similarly formed.

[0042] In some cases, portions of the dielectric layer region that undergoes double exposure during patterning (e.g., exposure during a first and second exposure process) may form bumps (e.g., bumps, protrusions, ridges, etc.). These "bumped portions" of the dielectric layer may be located beneath portions of the photoresist that are exposed to light in both exposure processes (e.g., similar to...). Figure 11 (Double exposure portion 23AB'). In some cases, the raised portion of the dielectric layer can be a portion of the dielectric layer with a relatively large thickness. In some cases, the raised portion of the dielectric layer can be a portion of the dielectric layer extending over the raised portion of the underlying dielectric layer. In some cases, the redistribution layer extending over the raised portion of the dielectric layer can have a corresponding raised portion. The width of the raised portion of the dielectric layer or redistribution layer can be greater than, less than, or approximately equal to the width W1 of the overlapping region 100AB.

[0043] For example, Figure 17 The intermediate steps for forming a redistributed interposer with raised portions of a dielectric layer according to some embodiments are shown. Figure 17 The structure is similar to Figure 16 The structure, except that the via portions of the redistribution layer 30 are in physical and electrical contact with the underlying conductive component 40, is as follows: The conductive component 40 can be, for example, a metallized pattern formed on the carrier substrate 10, or a previously formed redistribution layer, etc. For simplicity, Figure 17 Zhongyu Figure 15 Features with similar characteristics were assigned the same reference numbers.

[0044] like Figure 17 As shown, dielectric layer 20 includes a raised portion 20' in the overlapping region 100AB where double exposure occurs. The raised portion 20' is higher than the non-raised portion by a height H1 ranging from about 0.1 μm to about 1 μm, but other heights are also possible. For example, a portion of dielectric layer 20 in the overlapping region 100AB may protrude by a height H1 from the top surface of a portion of the dielectric region in the first patterned region 100A and / or the second patterned region 100B. The redistribution layer 30 above the raised portion 20' may have a substantially constant thickness, so a portion of the redistribution layer 30 above the raised portion 20' may protrude by a height H2 from the adjacent top surface of the redistribution layer, with a height H2 ranging from about 0.1 μm to about 1 μm. The dielectric layer 32 above dielectric layer 20 may have a raised portion 32' due to its location above the raised portion 20', and / or may have a raised portion 32' due to the increased thickness caused by double exposure. The protrusion 32' may protrude to a height H1 similar to that of the protrusion 20'. Similarly, the redistribution layer 34 may protrude to a distance H2 similar to that of the redistribution layer 30. These are examples; other protrusions in the redistribution layer and / or dielectric layer are also possible.

[0045] Figure 18 and Figure 19 A plan view showing the intermediate steps of forming the redistribution intermediary layer according to some embodiments is shown. Figure 18 It showed something similar to Figure 11 A plan view of the structure of the process steps shown. Figure 19 It showed something similar to Figure 14 The diagram shows a top view of the structure of the process step. For simplicity, Figure 18 and Figure 19 Zhongyu Figure 11 and Figure 19 Features with similar characteristics were assigned similar reference numbers. However, Figures 18-19 The structure shown is an illustrative example that can be applied to other process steps, such as those performed to form an additional redistribution layer.

[0046] In some embodiments, the pattern in the overlapping region 100AB exposed by the first exposure process matches or overlaps with the corresponding pattern in the overlapping region 1000AB exposed by the second exposure process. However, referring to Figure 18 In some cases, the exposed portions 23A' and 23B' of the second photoresist layer 23 may not overlap precisely within the overlapping region 100AB. Figure 18 An example is shown where the exposed portion 23A' is laterally offset by a distance D1 from the corresponding exposed portion 23B'. The offset of the exposed portions can be in any lateral direction. In some cases, the offset of the exposed portions may be due to inaccurate stitching alignment between the first and second photolithographic masks. In some cases, the lateral offset between exposed portions 23A' and 23B' can form a single-exposure portion within the overlapping region 100AB. For example, Figure 18 The lateral offset causes the exposed portions 23A' and 23B' to extend in the overlapping area 100AB, excluding the double-exposed portion 23AB'.

[0047] refer to Figure 19 The lateral offset between the exposed portion 23A' and the exposed portion 23B' can then form a redistribution layer 30 with a corresponding offset region. Figure 19 An example is shown in the image, where, due to Figure 18The lateral offset D1, the redistribution layer 30 in the overlapping region 100AB includes kinked regions 30', whose linewidth L1 is greater than the linewidth L2 outside the overlapping region 100AB. The width W2 of these kinked regions 30' can be greater than, less than, or approximately equal to the width W1 of the overlapping region 100AB. In some cases, the kinked regions 30' can have a lateral offset D2 greater than, less than, or approximately equal to the lateral offset D1. In some cases, the linewidth L1 can be greater than the sum of the linewidth L2 and the lateral offset D2. In other words, the protrusion of the kinked regions 30' may be greater than... Figure 19 More shown, or the line width may be greater than Figure 19 The one shown is larger. Figure 19 The knotted area 30' shown is an example; other arrangements, configurations, or shapes are also possible.

[0048] Figures 20 to 31 Plan views are shown showing different configurations of a first patterned region 100A, a second patterned region 100B, and an overlapping region 100AB according to some embodiments. Figures 20-31 This is an illustrative example; other arrangements or configurations are possible. Figures 20-31 The exposed areas of the photoresist layer during the formation of the redistribution interposer are shown according to some embodiments. The photoresist layer may be similar to the first photoresist layer 21 or the second photoresist layer 23 previously described for forming the redistribution layer 30; for simplicity, in Figures 20-31 The middle label is marked as photoresist layer 23. However, it should be noted that... Figures 20-31 The photoresist layer 23 may be similar to other photoresist layers used to form other redistribution layers during the formation of the redistribution interposer.

[0049] Figures 20-31 It also shows patterned areas that can be exposed in either the first or second exposure process. For example, in Figures 20-31 In this process, a photolithographic mask similar to the previously described first photolithographic mask 50A or first photolithographic mask 60A can be used to expose the first patterned region 100A and the overlapping region 100AB in one exposure process, and a photolithographic mask similar to the previously described second photolithographic mask 50B or second photolithographic mask 60B can be used to expose the second patterned region 100B and the overlapping region 100AB in a separate exposure process. Therefore, the first patterned region 100A, the second patterned region 100B, and the overlapping region 100AB can be similar to those previously described for... Figures 1-19 Those mentioned above. In some embodiments, multiple second pattern regions 100B may exist, which will be described in more detail below.

[0050] Figure 20 and Figure 21Intermediate steps in the exposure process of the first patterned region 100A, the second patterned region 100B, and the overlapping region 100AB of the photoresist layer 23 according to some embodiments are shown. Figure 20 The diagram shows the first patterned region 100A and the overlapping region 100AB after performing the first exposure process. For example, the first patterned region 100A and the overlapping region 100AB can be exposed using a photomask, similar to using... Figure 3 Exposure or use of the first photolithography mask 50A Figure 10 Exposure of the first photomask 60A. The first patterned region 100A and the overlapping region 100AB may have patterns of exposed portions corresponding to the pattern of the photomask; for example, the pattern may include exposed portions similar to exposed portions 21A' or 23A'. Figure 20 As shown, in the first exposure process, the second pattern area 100B is not exposed. Figure 20 As shown, the area of ​​the first patterned region 100A is smaller than the area of ​​the photoresist layer 23. However, in other embodiments, the first patterned region 100A completely covers the photoresist layer 23 and may be approximately the same size as or larger than the photoresist layer 23.

[0051] like Figure 20 As shown, in some embodiments, the first patterned region 100A has an annular shape surrounding the second patterned region 100B, so that after the first exposure process, the exposed portion of the photoresist layer 23 surrounds the unexposed portion. The overlapping region 100AB is located between the first patterned region 100A and the second patterned region 100B and also has an annular shape. In some embodiments, the first patterned region 100A may have a size approximately the same as or larger than the size of the redistribution interposer. In some cases, using an annular first patterned region 100A allows for the use of a larger corresponding photomask, which may allow for the formation of a larger redistribution interposer.

[0052] Figure 21 It shows in Figure 20 The first patterned region 100A and the overlapping region 100AB are shown after a second exposure process following the first exposure process. For example, a photomask can be used to expose the second patterned region 100B and the overlapping region 100AB, similar to using a photomask. Figure 4 Exposure or use of the second photolithography mask 50B Figure 11 The second mask 60B is exposed. The patterns of the second patterned region 100B and the overlapping region 100AB may have exposure portions corresponding to the patterns of the photomask, for example, including exposure portions similar to exposure portions 21B', 23B', or 23AB'. During the second exposure process, the first patterned region 100A is not exposed. The overlapping region 100AB is doubly exposed.

[0053] like Figure 21 As shown, in some embodiments, the second patterned region 100B is surrounded by the first patterned region 100A and the overlapping region 100AB. In some embodiments, the pattern of the second patterned region 100B has a smaller component size than the pattern of the first patterned region 100A. The smaller size of the second patterned region 100B allows for a smaller photomask size to be used when forming a larger redistribution interposer layer, resulting in a smaller pattern component size. By using a first exposure process to form a larger component size in the first patterned region 100A and a second exposure process to form a smaller component size in the second patterned region 100B, a large redistribution interposer layer including flexible and efficient conductive wiring can be formed. In this way, a redistribution layer with a smaller linewidth can be formed in the second patterned region 100B, and a redistribution layer with a larger linewidth can be formed in the first patterned region 100A, with the redistribution layer in the overlapping region 100AB “stitching” the redistribution layer in the first patterned region 100A to the redistribution layer in the second patterned region 100B.

[0054] Although Figures 20-21 This illustration shows that the first patterned region 100A is exposed in the first exposure process before the second patterned region 100B is exposed in the second exposure process. However, in other embodiments, the second patterned region 100B may be exposed before the first patterned region 100B is exposed. For example, Figures 22-23 A first exposure process for exposing a second patterned region 100B according to some embodiments is shown, followed by a second exposure process for exposing a first patterned region 100A. Figure 22 In the first exposure process, a photolithographic mask is used to prevent the first patterned region 100A from being exposed, and to expose the patterns in the second patterned region 100B and the overlapping region 100AB. This forms the exposed second patterned region 100B surrounded by the unexposed first patterned region 100A. Figure 23 In the second exposure process, a photomask is used to block the exposure of the second patterned region 100B, while exposing the patterns in the first patterned region 100A and the overlapping region 100AB. In this way, the photoresist layer 23 can be exposed in individual areas of the photoresist layer 23 through multiple exposure processes.

[0055] In some embodiments, the photoresist layer 23 has a plurality of second patterned regions 100B, and each second patterned region 100B is sequentially exposed in a plurality of corresponding exposure processes using the same photomask. Figures 24-26The illustration shows intermediate steps in the exposure of a first patterned region 100A, a first second patterned region 100B-1, a first overlapping region 100AB-1, a second second patterned region 100B-2, and a second overlapping region 100AB-2. The first overlapping region 100AB-1 is located between the first second patterned region 100B-1 and the first patterned region 100A, and the second overlapping region 100AB-2 is located between the second second patterned region 100B-2 and the first patterned region 100A. Figures 24-26 An example with two second patterned regions 100B is shown, but in other embodiments, three or more second patterned regions 100B may exist. Adjacent second patterned regions 100B may be separated by a first patterned region 100A. The second patterned regions 100B may have the same size, and therefore can be exposed using the same photomask. The second patterned regions 100B may have the same dimensions as... Figures 24-26 The different arrangements or configurations shown.

[0056] exist Figure 24 In this process, a first exposure process is performed using a first photolithographic mask to expose a first pattern region 100A, a first overlapping region 100AB-1, and a second overlapping region 100AB-2. The first exposure process does not expose either the first or second pattern region 100B-1 or the second pattern region 100B-2. Therefore, the first and second pattern regions 100B-1 and 100B-2 are unexposed regions surrounded by the first pattern region 100A.

[0057] exist Figure 25 In this embodiment, a second exposure process is performed using a second photolithographic mask to expose the first second pattern region 100B-1 and the first overlapping region 100AB-1. The second exposure process does not expose the first pattern region 100A, the second second pattern region 100B-2, or the second overlapping region 100AB-2. In other embodiments, the second second pattern region 100B-2 may be exposed by the second exposure process instead of the first second pattern region 100B-1. After the second exposure process, the first overlapping region 100AB-1 is double-exposed, while the second overlapping region 100AB-2 remains individually exposed only by the first exposure process.

[0058] exist Figure 26 In this process, a third exposure process is performed using a second photolithographic mask to expose the second patterned region 100B-2 and the second overlapping region 100AB-2. The third exposure process does not expose the first patterned region 100A, the first and second patterned regions 100B-1, or the first overlapping region 100AB-1. In this way, by using the same photolithographic mask to expose multiple regions, a larger redistributed interposer layer can be achieved, costs can be reduced, and denser conductive components can be formed in multiple regions.

[0059] In some embodiments, the photoresist layer 23 has a plurality of second patterned regions 100B, and the exposure portions of adjacent second patterned regions 100B overlap, forming a double-exposure portion between adjacent second patterned regions 100B. For example, Figures 27-29 The diagram illustrates an intermediate step in the exposure of a first pattern region 100A, a first second pattern region 100B-1, a first overlapping region 100AB-1, a second second pattern region 100B-2, a second overlapping region 100AB-2, an overlapping region 100B-12, and an overlapping region 100AB-12. The first overlapping region 100AB-1 is located between the first second pattern region 100B-1 and the first pattern region 100A, and the second overlapping region 100AB-2 is located between the second second pattern region 100B-2 and the first pattern region 100A. The overlapping region 100AB-12 is a double-exposure region between the first second pattern region 100B-1 and the second second pattern region 100B-2. The overlapping region 100AB-12 is a region that can be exposed three times and is adjacent to the first pattern region 100A, the first second pattern region 100B-1, and the second second pattern region 100B-2. Figures 27-29 An example with two second patterned regions 100B is shown, but in other embodiments, three or more second patterned regions 100B may exist. Adjacent second patterned regions 100B may be separated by overlapping regions similar to overlapping regions 100B-12. The second patterned regions 100B may have the same size, so they can be exposed using the same photomask. The second patterned regions 100B may have the same dimensions as... Figures 27-29 The different arrangements or configurations shown.

[0060] exist Figure 27 In this process, a first exposure process is performed using a first photolithographic mask to expose a first patterned region 100A, a first overlapping region 100AB-1, a second overlapping region 100AB-2, and an overlapping region 100AB-12. The first exposure process does not expose the first or second patterned regions 100B-1, the second or second patterned regions 100B-2, or the overlapping region 100B-12. Therefore, the first or second patterned regions 100B-1 and 100B-2 are unexposed areas surrounded by the first patterned region 100A.

[0061] exist Figure 28 In the process, a second photolithography mask is used for a second exposure process to expose the first second pattern region 100B-1, the first overlapping region 100AB-1, the overlapping region 100B-12, and the overlapping region 100AB-12. After the second exposure process, the first overlapping region 100AB-1 and the overlapping region 100AB-12 are double-exposed, while the second second pattern region 100B-12 is not exposed.

[0062] exist Figure 29 In the process, a third exposure process is performed using a second photolithographic mask to expose the second patterned region 100B-2, the second overlapping region 100AB-2, the overlapping region 100B-12, and the overlapping region 100AB-12. After the second exposure process, the second overlapping region 100AB-2 and the overlapping region 100B-12 are double-exposed, and the overlapping region 100AB-12 has been exposed three times. The exposure of the overlapping second patterned region 100B allows for a larger redistributed interposer and smaller conductive components with larger areas within the redistributed interposer.

[0063] Figures 20-29 The second pattern region 100B described herein is an example, and any suitable configuration of the second pattern region 100B may be used in other embodiments. Figure 30 and Figure 31 An additional example arrangement of the second patterned area 100B according to some embodiments is shown. Figure 30 The arrangement of the second pattern region 100B is shown, wherein the edges of the second pattern region 100B are not aligned. Figure 30 An embodiment of the second patterned region 100B is shown, wherein some exposure overlaps of the second patterned region 100B are similar to... Figure 29 Other arrangements, arrangements, overlaps, or numbers of the second pattern areas 100B are possible. Various second pattern areas 100B have corresponding overlapping areas and are surrounded individually or collectively by the first pattern areas 100A.

[0064] Figures 32 to 47 The intermediate steps for forming an encapsulation assembly 200 including a redistributed intermediary layer 240 according to some embodiments are shown. Figures 32 to 44 Intermediate steps for forming a redistribution intermediary layer 240 according to some embodiments are illustrated. The redistribution intermediary layer 240 can be used as previously defined for... Figures 1-32The steps, materials, configurations, or techniques described herein will not be repeated in detail below. For example, as described below, a redistribution interposer 240 can be formed by forming multiple redistribution layers 230-235 in a first patterned region 100A, a second patterned region 100B, and an overlapping region 100AB, wherein each redistribution layer 230-235 is formed using multiple exposure processes. The redistribution interposer 240 is shown as having six redistribution layers 230-235, but more or fewer redistribution layers may be formed in other embodiments. The redistribution interposer 240 shown is an example, and other configurations are possible. In some cases, using a redistribution interposer instead of another type of interposer can increase the density or flexibility of electrical wiring, reduce package size, or lower manufacturing costs. In some cases, using multiple patterned regions as described herein can form a larger redistribution interposer. In some cases, the package assembly 200 itself can be considered a package.

[0065] Figure 32 A dielectric layer 220 formed on a carrier substrate 10 and a first photoresist layer 211 formed on the dielectric layer 220 are shown according to some embodiments. The carrier substrate 10 may be similar to the carrier substrate 10 previously described. The dielectric layer 220 may be similar to the dielectric layer 20 previously described and may be formed using similar techniques. For example, in some embodiments, the dielectric layer 220 may include polymers, etc. The first photoresist layer 211 may be similar to the first photoresist layer 21 previously described and may be formed using similar techniques. In the following description, it is assumed that the first photoresist layer 211 is a positive photoresist, but in other embodiments, the first photoresist layer 211 may be a negative photoresist. In some embodiments, a release layer (not shown) may be formed on the carrier substrate 10 prior to the formation of the dielectric layer 220. In some embodiments, a metallization pattern (not shown) may be formed on the carrier substrate 10 prior to the formation of the dielectric layer 220. The metallization pattern may include, for example, conductive pads, conductive wiring, etc., and may be formed using techniques similar to those used for forming redistribution layers 230-235.

[0066] like Figure 32 As shown, the carrier 10 and the overlying layer have a first patterned region 100A, a second patterned region 100B, and an overlapping region 100AB. The first patterned region 100A surrounds the second patterned region 100B and may be larger than the second patterned region 100B. The overlapping region 100AB borders the second patterned region 100B and separates the second patterned region 100B from the first patterned region 100A. In other embodiments, multiple second patterned regions 100B may exist.

[0067] exist Figure 33In some embodiments, a first photoresist layer 211 is exposed in a first exposure process to form an exposed portion 211A' of the first photoresist layer 211. The first exposure process may also expose a portion of the first photoresist layer 211 in the overlapping region 100AB. The first exposure process may be similar to that previously performed for... Figure 3 The process described above. For example, the first exposure process may use a first photomask (not shown) to expose the pattern of the first patterned region 100A and / or the overlapping region 100AB. Figure 33 The image shows an example exposure portion 211A' of the first photoresist layer 211 in the first patterned region 100A.

[0068] exist Figure 34 In some embodiments, the first photoresist layer 211 is exposed in a second exposure process to form an exposed portion 211B' of the first photoresist layer 211. The second exposure process may also expose portions of the first photoresist layer 211 in the overlapping region 100AB, which can double-exposure some portions of the overlapping region 1000AB. The second exposure process may be similar to that previously described for... Figure 4 The process described above. For example, the second exposure process may use a second photomask (not shown) to expose the pattern in the second patterned region 100B and / or the overlapping region 100AB. Figure 34 An example exposure portion 211B' of the first photoresist layer 211 in the second patterned region 100B is shown. In other embodiments, the second patterned region 100B is exposed in a first exposure process, and the first patterned region 100A is exposed in a second exposure process. In other embodiments where there are multiple second patterned regions 100B, an additional exposure process can be performed using a second photomask. In some embodiments, the second photomask may be smaller than the first photomask.

[0069] exist Figure 35 In some embodiments, the exposed portions 211A' and 211B' of the first photoresist layer 211 are removed during the development process. The development process can be performed concurrently with previous processes. Figure 5 The process described is similar. Developing the first photoresist layer 211 forms an opening 213, which exposes the underlying dielectric layer 220. In this way, patterning the first photoresist layer 211 can include multiple exposure process steps, but only one development process step. For example, patterning the first photoresist layer 211 can include exposing the first patterned region 100A and the second patterned region 100B separately, but simultaneously developing the first patterned region 110A and the second patterned region 100B. The development process can also remove any double-exposed portions of the first photoresist layer 211 that may exist in the overlapping region 100AB.

[0070] exist Figure 36In some embodiments, an etching process is performed to extend opening 213 into dielectric layer 220. The etching process can be performed in conjunction with previous... Figure 6 The process described herein is similar. For example, in some embodiments, the etching process may be an anisotropic dry etching process. After the etching process, the opening 213 may extend completely through the dielectric layer 220. In embodiments where a metallization pattern has been previously formed, the opening 213 may expose the metallization pattern. After etching the dielectric layer 220, a process similar to that previously described... Figure 7 The process described above removes the first photoresist layer 211, for example, by using an ashing process. In this way, the dielectric layer 220 can be patterned.

[0071] exist Figure 37 In some embodiments, a seed layer 215 and a second photoresist layer 217 are formed on a patterned dielectric layer 220. The seed layer 215 is as follows: Figure 37 As shown, but for clarity, the seed layer is omitted thereafter. Seed layer 215 can be similar to that previously used for... Figure 8 The seed layer 24 is described and can be formed using similar techniques. For example, in some embodiments, the seed layer 215 includes a titanium layer and a copper layer on the titanium layer. A second photoresist layer 217 is formed on the seed layer 215 and can be formed similarly to the previously described seed layer 217. Figure 9 The second photoresist layer 23 is described. In the following description, it is assumed that the second photoresist layer 217 is a positive photoresist, but in other embodiments, the second photoresist layer 217 may be a negative photoresist.

[0072] exist Figure 38 In some embodiments, a second photoresist layer 217 is exposed in a first exposure process to form an exposed portion 217A' of the first photoresist layer 211. The first exposure process may also expose portions of the second photoresist layer 217 in the overlapping region 100AB. The first exposure process can be similar to that previously performed on... Figure 10 The process described above. For example, the first exposure process may use a first photomask (not shown) to expose a pattern in a first patterned region 100A and / or an overlapping region 100AB. Figure 38 An example exposure portion 217A' of the second photoresist layer 217 in the first patterned region 100A and the overlapping region 100AB is shown. Figure 38 As shown, some exposed portions 217A' can extend from the first pattern area 100A to the overlapping area 100AB.

[0073] exist Figure 39In some embodiments, a second photoresist layer 217 is exposed in a second exposure process to form an exposed portion 217B' of the first photoresist layer 211. The second exposure process may also expose portions of the second photoresist layer 217 in the overlapping region 100AB. Exposing portions of the second photoresist layer 217 in the overlapping region 100AB may expose previously exposed portions 217A', forming a double-exposed portion 217AB' of the second photoresist layer 217 in the overlapping region 100AB. The second exposure process may be similar to the previous process for… Figure 11 The process described above. For example, the second exposure process may use a second photomask (not shown) to expose the pattern in the second patterned region 100B and / or the overlapping region 100AB. Figure 39 The diagram illustrates an example exposed portion 217B' of the second photoresist layer 217 in the second patterned region 100B and a double-exposed portion 217AB' in the overlapping region 100AB. In other embodiments, the second patterned region 100B is exposed in a first exposure process, and the first patterned region 100A is exposed in a second exposure process. In other embodiments where multiple second patterned regions 100B exist, additional exposure processes can be performed using a second photomask. In some embodiments, the second photomask may be smaller than the first photomask.

[0074] exist Figure 40 In some embodiments, the exposed portions 217A', 217B', and double-exposed portions 217AB' of the second photoresist layer 217 are removed during the development process. The development process may be different from the previous one. Figure 12 The process is similar. The second photoresist layer 217 is developed to form an opening 218, which exposes the underlying seed layer 215. Figure 40 (Not shown in the image). In this way, patterning the second photoresist layer 217 may include multiple exposure process steps, but only one development process step. For example, patterning the second photoresist layer 217 may include exposing the first patterned region 100A and the second patterned region 100B respectively, but simultaneously developing the first patterned region 110A and the second patterned region 100B.

[0075] exist Figure 41 In this process, conductive material 229 is formed on the exposed portion of the seed layer 215 within the opening 218 of the second photoresist layer 217. The conductive material 229 can be similar to that previously used for... Figure 13 The conductive material 28 is described. For example, the conductive material 229 can be formed by CVD, PVD, plating, etc., and can include metals such as copper, titanium, tungsten, aluminum, ruthenium, cobalt, etc., or combinations thereof. Other materials are also possible. In some embodiments, the thickness of the conductive material 229 can be less than the thickness of the second photoresist layer 217.

[0076] exist Figure 42 In some embodiments, portions of the second photoresist layer 217 and the underlying seed layer 215 are removed to form a redistribution layer 230. The second photoresist layer 217 can be removed using an acceptable ashing or stripping process (e.g., using oxygen plasma). Once the second photoresist layer 217 is removed, the exposed portions of the seed layer 215 are removed using, for example, an acceptable wet or dry etching process. The remaining portions of the seed layer 215 and the conductive material 229 form the redistribution layer 230. In some embodiments, the redistribution layer 230 includes conductive via portions extending through the dielectric layer 220 and conductive wire portions extending along the top surface of the dielectric layer 200. In some cases, the redistribution layer 30 can be considered as redistribution lines, metallization patterns, wiring layers, etc.

[0077] exist Figure 43 In some embodiments, additional dielectric layers 221 and 231 are formed on the redistribution layer 230. The dielectric layer 221 and redistribution layer 231 can be formed using techniques similar to those described above for forming the dielectric layer 220 and / or redistribution layer 230. For example, dielectric layer 221 can be deposited on dielectric layer 220 and redistribution layer 230. The dielectric layer 221 can be patterned using multiple exposure processes and photoresist layer development processes for patterned regions 100A and 100B, followed by an etching process. A seed layer and photoresist layer can be deposited on the patterned dielectric layer 221. The photoresist layer can be patterned using multiple exposure processes and development processes for patterned regions 100A and 100B. A conductive material can be deposited on the exposed portion of the seed layer, and then the photoresist and the portion below the seed layer can be removed. The remaining portion of the seed layer and conductive material forms the redistribution layer 231.

[0078] exist Figure 44 In some embodiments, additional dielectric layers 222-226 and additional redistribution layers 232-235 are formed to form a redistribution interposer 240. The additional dielectric layers 222-226 and redistribution layers 232-235 can be formed using steps and processes similar to those described for forming dielectric layers 220-221 and redistribution layers 230-231. These steps and processes can be performed more or fewer times to form more or fewer additional dielectric layers and redistribution layers. Figure 44In the illustrated embodiment, the topmost redistribution layer 235 is covered by the topmost dielectric layer 226, but in other embodiments, the topmost redistribution layer is not covered by the topmost dielectric layer. Due to the multiple exposure processes used for the first patterned region 100A and the second patterned region 100B, the dimensions (e.g., linewidth, pitch, etc.) of the portion of the redistribution layer in the second patterned region 100B of the redistribution interposer 240 can be smaller than the portion of the redistribution layer in the first patterned region 100A of the redistribution interposer 240.

[0079] exist Figure 45 In some embodiments, a UBM 242 is formed for external connection with the redistribution interposer 240. The UBM 242 has bump portions on the main surface of the topmost dielectric layer 226 of the redistribution interposer 240 and via portions extending through the dielectric layer 26 to physically and electrically couple the topmost redistribution layer 235. As a result, the UBM 242 is electrically coupled to the redistribution interposer 240. The UBM 242 may be formed of the same material as or a different material from the redistribution layers 230-235. In some embodiments, the UBM 242 has different dimensions than the redistribution layers 230-235. In other embodiments, the UBM 242 is not formed.

[0080] Still referencing Figure 45 In some embodiments, a conductive connector 244 is formed on the UBM 242. The conductive connector 244 may be a ball grid array (BGA) connector, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using electroless nickel-palladium immersion gold (ENEPIG) technology, etc. The conductive connector 244 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the conductive connector 244 is formed by initially forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is structurally formed, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 244 includes metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on top of the metal pillars. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof, and may be formed by a plating process. In other embodiments, the conductive connector 244 is not formed.

[0081] In some embodiments, an integrated passive device (not shown) is attached to the redistribution interposer 240. For example, the integrated passive device may be attached to a UBM 242 or a conductive connector 244. The integrated passive device may be a semiconductor die, chip, chiplet, surface mount device, etc. The integrated passive device may include passive components such as resistors, capacitors, inductors, etc. These are examples; other integrated passive devices are also possible.

[0082] exist Figure 46 In this process, carrier substrate debonding is performed to separate (or “debond”) the carrier substrate 10 from the redistribution interposer 240. According to some embodiments, debonding includes projecting light, such as laser or ultraviolet light, onto the release layer, causing the release layer to decompose under the heat of the light, and the carrier substrate 10 can be removed. The carrier substrate 10 can be removed using other techniques, such as chemical mechanical polishing (CMP), grinding, etching, or combinations thereof. According to some embodiments, the redistribution interposer 240 is then flipped and placed on a different carrier substrate 11. The carrier substrate 11 can be similar to the carrier substrate 10, or it can be tape, die-attach film (DAF), etc.

[0083] Still referencing Figure 46 According to some embodiments, a metallization pattern 246 and conductive pads 248 may be formed on the redistribution interposer 240. In some embodiments, the metallization pattern 246 may be formed on the dielectric layer 220 and the redistribution layer 230, with a portion extending along the surface of the dielectric layer 200. In this way, the metallization pattern 246 is physically connected and electrically connected to the redistribution interposer 240. The metallization pattern 246 may be formed using techniques similar to those used to form the redistribution layers 230-235. For example, a seed layer may be formed, a patterned photoresist may be formed on the seed layer, and a conductive material may be formed on the exposed portions of the seed layer. Other techniques are also possible. In other embodiments, the conductive pads 248 may be formed directly on the redistribution interposer 240 without the need for the metallization pattern 246. In other embodiments, as previously described, the metallization pattern is pre-formed on the carrier substrate 10, and therefore the metallization pattern 246 is not formed.

[0084] Still refer to Figure 46An insulating layer 245 may be deposited on the redistribution interposer 240 and the metallization pattern 245. The insulating layer 245 may be a passivation layer, a dielectric layer, etc., and may resemble dielectric layers 220-226. For example, the insulating layer 245 may be any suitable insulating material, such as PBO, polyimide, BCB, etc., and in some embodiments, may be a material that can be patterned using a photomask. In other embodiments, the insulating layer 245 may be formed from materials such as nitrides, such as silicon nitride; oxides, such as silicon oxide, PSG, BSG, BPSG, etc.; or similar materials. The insulating layer 245 may be formed by spin coating, lamination, CVD, etc., or combinations thereof. The insulating layer 245 is then patterned using a suitable photolithography technique to form openings that expose portions of the metallization pattern 246.

[0085] In some embodiments, conductive pads 248 are then formed on the exposed portions of the metallization pattern 246. The conductive pads 248 may be metal pads, conductive pillars, or allow semiconductor devices (e.g., Figure 47 Semiconductor devices 250A, 250B are connected to other conductive structures of the redistribution interposer 240. Conductive pads 248 may be made of a material similar to redistribution layers 230-235, UBM 242, or another material. In some embodiments, conductive pads 248 may be UBM, etc. In embodiments where the metallization pattern 246 is not formed, conductive pads 248 may be formed on the redistribution interposer 240. In some embodiments, multiple redistribution interposers 240 may be formed as a single structure and then monolithically processed into separate structures. Monolithization may be performed before or after the formation of conductive pads 248.

[0086] exist Figure 47In some embodiments, semiconductor devices 250A and 250B are connected to a redistribution interposer 240 to form a package assembly 200. Semiconductor devices 250A and 250B can be integrated circuit devices, semiconductor dies, chips, chiplets, packages, etc. For example, semiconductor devices 250A and 250B can include logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-chip (SoC), application processor (AP), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, microelectromechanical systems (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), or combinations thereof. In some embodiments, semiconductor devices 250A and 250B include stacked devices comprising a plurality of semiconductor substrates 52. For example, semiconductor devices 250A and 250B can be memory devices comprising multiple memory dies, such as hybrid memory cube (HMC) modules, high-bandwidth memory (HBM) modules, etc. Other types of semiconductor devices are also possible. Semiconductor devices 250A and 250B can be similar or different types of devices, and the size, arrangement, or number of semiconductor devices may differ from those shown.

[0087] Semiconductor devices 250A and 250B can be bonded to the redistribution interposer 240 via conductive connector 251. Conductive connector 251 can be similar to the conductive connector 244 described previously. For example, conductive connector 251 can be formed on semiconductor devices 250A and 250B. Conductive connector 251 can be placed on conductive pads 248, and a reflow process can be performed to bond semiconductor devices 250A and 250B to conductive pads 248A. In this way, semiconductor devices 250A and 250B are physically and electrically connected to the redistribution interposer 240.

[0088] After semiconductor devices 250A and 250B are bonded to conductive pads 248, an optional underfill 252 may be deposited beneath semiconductor devices 250A and 250B, between semiconductor devices 250A and 250B and the redistribution interposer 240, and around conductive connector 251. In some embodiments, the underfill 252 may extend upward between semiconductor devices 250A and 250B, or even to the upper surfaces of semiconductor devices 250A and 250B. The underfill 252 can reduce stress and protect the connector from backflow caused by conductive connector 251. The underfill 252 may be formed by a capillary flow process after semiconductor devices 250A and 250B are attached, or it may be formed by a suitable deposition method before semiconductor devices 250A and 250B are attached.

[0089] After depositing an optional underfill 252, a sealant 254 can be deposited on the redistribution interposer 240 and the semiconductor devices 250A, 250B. The sealant 254 can be a molding compound, epoxy resin, etc. The sealant 254 can be applied using suitable techniques, such as compression molding, transfer molding, etc. The sealant 254 can be applied in liquid or semi-liquid form and then cured. In some embodiments, the sealant 254 can be deposited to a thickness sufficient to completely cover the semiconductor devices 250A, 250B. A planarization process, such as CMP, can be used to flush the upper surface of the sealant 254 with the upper surfaces of the semiconductor devices 250A, 250B. In some embodiments, the semiconductor devices 250A, 250B can be thinned using a planarization process. In some embodiments, the underfill 252 can be omitted, and the sealant 254 can be used simultaneously as both the underfill 252 and the sealant 254. According to some embodiments, in this manner, an encapsulation assembly 200 including the redistribution interposer 240 can be formed. In some embodiments, the encapsulation component 200 may be formed as a single structure, which is monolithically divided into a single encapsulation component 200.

[0090] According to some embodiments, each individual package component 200 can then be mounted onto the package substrate 301 using a conductive connector 244 to form a package 300. The package substrate 301 includes a substrate core 302 and bonding pads 304 on the substrate core 302. The substrate core 302 can be made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide, gallium indium phosphide, and combinations thereof can also be used. Furthermore, the substrate core 302 can be an SOI substrate. Typically, an SOI substrate includes a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the substrate core 302 is based on an insulating core, such as a glass fiber reinforced resin core. An example core material is glass fiber resin, such as FR4. Alternatives to the core material include bismaleimide triazine BT resin, or other PCB materials or films. Deposited films such as ABF or other laminates can be used for the substrate core 302.

[0091] The substrate core 302 may include active and passive devices (not shown). A wide variety of devices, such as transistors, capacitors, resistors, and combinations thereof, can be used to generate the structural and functional requirements of the package 300 design. These devices can be formed using any suitable method.

[0092] The substrate core 302 may further include a metallization layer and vias (not shown), wherein bonding pads 304 are physically coupled and / or electrically coupled to the metallization layer and vias. The metallization layer may be formed over active and passive devices and is designed to connect various devices to form functional circuitry. The metallization layer may be formed of alternating layers of dielectric material (e.g., a low-k dielectric material) and conductive material (e.g., copper), and the vias interconnect the conductive material layers and can be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). In some embodiments, the substrate core 302 is substantially devoid of active and passive devices.

[0093] In some embodiments, the conductive connector 244 is reflowed to attach the package assembly 200 to the pad 304. The conductive connector 244 electrically couples and / or physically couples the package substrate 301 (including the metallization layer in the substrate core 302) to the package assembly 200. In some embodiments, an underfill 308 may be formed between the package assembly 200 and the package substrate 301, surrounding the conductive connector 244. The underfill 308 may be formed by a capillary flow process after attaching the package assembly 200, or by a suitable deposition method before attaching it to the package assembly 200. In some embodiments, passive devices (e.g., surface mount devices (SMDs), not shown) may also be attached to the package substrate 301 (e.g., to the bonding pad 304). In some embodiments, a ring structure 310 may be attached to the package substrate 301 by an adhesive or the like. The ring structure 310 may provide structural support and increase the rigidity of the package 300. In other embodiments, a cover, heat sink, or the like may be attached to the package substrate 301 and / or the package assembly 200.

[0094] Other features and processes may also be included. For example, test structures may be included to aid in the verification testing of 3D packaged or 3DIC devices. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which allow testing of the 3D package or 3DIC using probes and / or probe cards, etc. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to improve yield and reduce costs.

[0095] The embodiments can achieve advantages. The techniques described herein allow for the formation of larger redistributed interposers for packages or package assemblies. Furthermore, the techniques described herein allow for the formation of larger redistributed interposers with relatively fine conductive components. For example, the techniques described herein allow for the formation of larger redistributed interposers with dimensions of approximately 55 mm x 68 mm or larger, or an area of ​​approximately 3500 mm². 2 A redistributed interposer with conductive components having a linewidth of 2 μm can be formed in an area larger than the original size. Other sizes are also possible. The technique presented in this paper forms patterned and stitched regions (e.g., overlapping regions) in the redistributed layer, which allow for higher wireability and conductive wiring, meeting complex device integration requirements. Patterned and stitched regions can overcome tooling limitations by using multiple exposure processes. Furthermore, the technique presented in this paper can form the interposer without using local silicon interconnects (LSI), etc. In this way, the technique presented in this paper can form redistributed interposers with denser wiring, lower cost, larger size, and greater layout flexibility.

[0096] In some embodiments of this disclosure, a method of forming a package includes: forming a first photoresist layer on a dielectric layer; performing a first exposure process on the first photoresist layer using a first photomask, wherein during the first exposure process, a first region of the first photoresist layer is blocked from being exposed, a second region of the first photoresist layer is exposed, and a third region of the first photoresist layer is exposed, wherein the second region surrounds the first region, and the third region surrounds the second region; performing a second exposure process on the first photoresist layer using a second photomask, wherein in the second exposure process, the first region of the first photoresist layer is exposed, the second region of the first photoresist layer is exposed, and the third region of the first photoresist layer is blocked from being exposed; and developing the first photoresist layer. In one embodiment, the pattern of the first photomask has a larger linewidth than the pattern of the second photomask. In one embodiment, the second region is adjacent to the first region and the third region. In one embodiment, the method includes: using the developed first photoresist layer as an etching mask to perform an etching process to pattern the first dielectric layer; and depositing a conductive material on the patterned first dielectric layer. In one embodiment, the method includes: performing a third exposure process on a first photoresist layer using a second photomask, wherein during the third photoexposure process, a third region of the first photoresist layer is exposed, a fourth region of the first photoresist layer is exposed, and a fifth region of the first photoresist layer is exposed, wherein the fifth region surrounds the fourth region, and the third region surrounds the fifth region. In one embodiment, a second exposure process is performed prior to the first exposure process. In one embodiment, the width of the second region is in the range of 1 μm to 50 μm. In one embodiment, the first photoresist layer is developed to expose an underlying seed layer.

[0097] In some embodiments of this disclosure, a method of forming a package includes: exposing a first pattern in a first patterned region of a first photoresist layer, wherein the first pattern has a first linewidth; exposing a second pattern in a second patterned region of the first photoresist layer, wherein the second pattern has a second linewidth smaller than the first linewidth, wherein the first patterned region laterally surrounds the second patterned region; performing a first developing process on the first and second patterned regions of the first photoresist layer to form a pattern in the first photoresist layer; and depositing a conductive material in the pattern of the first photoresist layer. In one embodiment, performing the first developing process exposes an underlying seed layer, wherein the conductive material is deposited on the exposed seed layer. In one embodiment, the first pattern overlaps with the second pattern. In one embodiment, the overlapping portion of the first and second patterns laterally surrounds the second patterned region. In one embodiment, the method includes: removing the first photoresist layer; and depositing a dielectric layer over the conductive material. In one embodiment, the method includes exposing the second pattern in a third patterned region of the first photoresist layer. In one embodiment, the third patterned region overlaps with the second patterned region. In one embodiment, the first patterned region laterally surrounds the third patterned region.

[0098] In some embodiments of this disclosure, the package includes: a redistribution interposer comprising a plurality of redistribution layers among a plurality of dielectric layers, wherein each of the plurality of redistribution layers has a first region surrounding a second region, the first region having a first pitch, and a second region having a second pitch, wherein the second pitch is smaller than the first pitch, wherein the first region is adjacent to each sidewall of the redistribution interposer; a semiconductor die bonded to a first side of the redistribution interposer; and a package substrate bonded to a second side of the redistribution interposer. In one embodiment, the first regions of each of the plurality of redistribution layers have the same size. In one embodiment, the second region has at least 3500 mm. 2 The area. In one embodiment, the redistribution intermediary layer comprises at least six redistribution layers.

[0099] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A method of forming a package, comprising: A first photoresist layer is formed on the dielectric layer; A first exposure process is performed on the first photoresist layer using a first photomask, wherein during the first exposure process, a first region of the first photoresist layer is blocked from being exposed, a second region of the first photoresist layer is exposed, and a third region of the first photoresist layer is exposed, wherein the second region surrounds the first region, and the third region surrounds the second region. A second exposure process is performed on the first photoresist layer using a second photomask, wherein, in the second exposure process, the first region of the first photoresist layer is exposed, the second region of the first photoresist layer is exposed, and the third region of the first photoresist layer is blocked from being exposed; and The first photoresist layer is developed.

2. The method according to claim 1, wherein, The pattern of the first photolithographic mask has a larger linewidth than the pattern of the second photolithographic mask.

3. The method according to claim 1, wherein, The second region is adjacent to the first region and the third region.

4. The method according to claim 1, further comprising: The developed first photoresist layer is used as an etching mask to perform an etching process to pattern the first dielectric layer. as well as A conductive material is deposited on the patterned first dielectric layer.

5. The method according to claim 1, further comprising: A third exposure process is performed on the first photoresist layer using the second photomask, wherein during the third photoexposure process, the third region of the first photoresist layer is blocked from being exposed, a fourth region of the first photoresist layer is exposed, and a fifth region of the first photoresist layer is exposed, wherein the fifth region surrounds the fourth region, and the third region surrounds the fifth region.

6. A method of forming a package, comprising: A first pattern is exposed in a first patterned region of a first photoresist layer, wherein the first pattern has a first linewidth; Expose a second pattern in a second pattern region of the first photoresist layer, wherein the second pattern has a second linewidth smaller than the first linewidth, and wherein the first pattern region laterally surrounds the second pattern region; A first development process is performed on the first patterned region and the second patterned region of the first photoresist layer to form a pattern in the first photoresist layer; and Conductive material is deposited in the pattern of the first photoresist layer.

7. The method according to claim 6, wherein, The first developing process is performed to expose the underlying seed layer, wherein the conductive material is deposited on the exposed seed layer.

8. The method according to claim 7, wherein, The first pattern overlaps with the second pattern.

9. The method according to claim 6, wherein, The overlapping portion of the first pattern and the second pattern laterally surrounds the area of ​​the second pattern.

10. A package comprising: A redistribution interposer includes multiple redistribution layers among multiple dielectric layers, wherein each of the multiple redistribution layers has a first region surrounding a second region, the first region having a first pitch, the second region having a second pitch, wherein the second pitch is smaller than the first pitch, and wherein the first region is adjacent to each sidewall of the redistribution interposer. Semiconductor die, bonded to a first side of the redistributed interposer; and The encapsulation substrate is bonded to the second side of the redistribution interposer.

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