Package, semiconductor structure and forming method thereof

Abstract

The structure includes: a first core substrate; an adhesive layer on the first core substrate; a second core substrate on the adhesive layer, in which the second core substrate includes a first cavity; a first semiconductor device in the first cavity; a first insulating film extending over the second core substrate, over a top surface of the first semiconductor device, and within the first cavity; a via extending through the first insulating film, the first core substrate, and the second core substrate; a first wiring structure on the first core substrate and electrically connected to the through hole; and a second wiring structure on the first insulating film and electrically connected to the through hole and the first semiconductor device. The embodiment of the invention also relates to a package, a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of this application relate to packages, semiconductor structures, and methods of forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, these improvements in integration density stem from iterative reductions in the smallest component size, allowing more components to be integrated into a given area. As the demand for miniaturized electronics grows, the need arises for smaller and more innovative packaging technologies for semiconductor dies. Summary of the Invention

[0003] Some embodiments of this application provide a semiconductor structure including: a first core substrate; an adhesive layer located on the first core substrate; a second core substrate located on the adhesive layer, wherein the second core substrate includes a first cavity; a first semiconductor device located within the first cavity; a first insulating film extending above the second core substrate, above the top surface of the first semiconductor device, and within the first cavity; a via extending through the first insulating film, the first core substrate, and the second core substrate; a first wiring structure located on the first core substrate and electrically connected to the via; and a second wiring structure located on the first insulating film and electrically connected to the via and the first semiconductor device.

[0004] Other embodiments of this application provide a package comprising: a multi-stacked core substrate including a first core substrate bonded to a second core substrate via an adhesive layer; a first insulating film layer located within and laterally surrounded by the first core substrate; a first component located within and laterally surrounded by the first insulating film layer; and a via extending through the multi-stacked core substrate.

[0005] Further embodiments of this application provide a method for forming a semiconductor structure, comprising: forming a cavity extending through a first core substrate; placing a die within the cavity, wherein the die is separated from the first core substrate; forming an insulating film over the first core substrate and the die, wherein the insulating film fills the cavity; forming a first adhesive material on the first core substrate and the die; bonding a second core substrate to the first adhesive material; forming a through-hole extending through the insulating film, the first core substrate, the first adhesive material, and the second core substrate; forming a first wiring layer on the insulating film and the die; and forming a second wiring layer on the second core substrate. Attached Figure Description

[0006] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figures 1 to 13 A cross-sectional view is shown of an intermediate step during a process for forming a package substrate structure including a multi-stacked core substrate, according to some embodiments.

[0008] Figure 14 A cross-sectional view of a package including a packaging substrate structure according to some embodiments is shown.

[0009] Figure 15 A cross-sectional view of a package including a packaging substrate structure according to some embodiments is shown.

[0010] Figures 16 to 23 A cross-sectional view is shown of an intermediate step during a process for forming a package substrate structure including a multi-stacked core substrate, according to some embodiments.

[0011] Figures 24 to 35 A cross-sectional view is shown of an intermediate step during a process for forming a package substrate structure including a multi-stacked core substrate, according to some embodiments.

[0012] Figures 36 to 41 A cross-sectional view is shown of an intermediate step during a process for forming a package substrate structure including a multi-stacked core substrate, according to some embodiments.

[0013] Figures 42 to 51 A cross-sectional view is shown of an intermediate step during a process for forming a package substrate structure including a multi-stacked core substrate, according to some embodiments.

[0014] Figures 52 to 59 A cross-sectional view is shown of an intermediate step during a process for forming a package substrate structure including a multi-stacked core substrate, according to some embodiments.

[0015] Figures 60 to 67 A cross-sectional view is shown of an intermediate step during a process for forming a package substrate structure including a multi-stacked core substrate, according to some embodiments. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0018] According to some embodiments, a package substrate structure formed by a stacked structure of core substrates is described. For example, core substrates may be bonded together to form a single multi-stacked core substrate. In some embodiments, components (e.g., passive devices, dies, etc.) are embedded within the multi-stacked core substrate, which can allow for improved packaging functionality, flexibility, and performance. The multi-stacked core substrate is thicker than a single core substrate, which can improve rigidity and package stability.

[0019] Figures 1 to 13 A packaging substrate structure 70 including a multi-stacked core substrate is shown according to some embodiments (see Figure 13 The intermediate steps in the formation of ). Figure 1A cross-sectional view of a first core substrate 50A attached to a first carrier 10 according to some embodiments is shown. In some embodiments, the first core substrate 50A may include materials such as Ajinomoto polymer film (ABF), prepreg composite fiber (prepreg) material, resin film, epoxy resin, molding compound, epoxy molding compound, glass fiber reinforced resin material, printed circuit board (PCB) material, silica filler, polymer material, polyimide material, paper, glass fiber, nonwoven glass fiber, glass, ceramic, other polymer materials, other laminated materials, etc., or combinations thereof. Other materials are also possible. In some embodiments, the first core substrate 50A may have a thickness T1 in the range of about 50 μm to about 650 μm, but other thicknesses are also possible. In some cases, the thickness T1 is determined to correspond to the thickness T2 of component 20, as described below. Figure 4 More detailed description.

[0020] In some embodiments, a conductive prelayer 52' ​​is formed on the top surface of the first core substrate 50A. The conductive prelayer 52' ​​may comprise one or more layers of copper, nickel, aluminum, other conductive materials, or combinations thereof, laminated, deposited, or otherwise formed on the side of the first core substrate 50A. In some cases, the conductive prelayer 52' ​​may comprise a metal foil, such as copper foil. In this way, in some cases, the first core substrate 50A may be a copper-clad laminate (CCL) substrate, etc. Other materials or types of conductive layers are also possible.

[0021] The first carrier 10 may be a glass carrier substrate, a ceramic carrier substrate, a strip, etc. The first carrier 10 may be a wafer, etc., allowing multiple structures to be formed simultaneously on the first carrier 10. In some cases, the first core substrate 50A is attached to the first carrier 10 using a release layer 11. The release layer 11 may be an adhesive material, etc., which can be removed along with the first carrier 10 from the above structure to be formed in subsequent steps. For example, the release layer 11 may be formed of a polymer-based material. In some embodiments, the release layer 11 is a thermally release material based on epoxy resin that loses its tackiness upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, the release layer 11 may be a UV adhesive that loses its tackiness upon exposure to UV light. The release layer 11 may be dispensed and cured as a liquid, may be a laminated film laminated on the first carrier 10, or similar. In some cases, the top surface of the release layer 11 may be flush and may have a high degree of planarity.

[0022] exist Figure 2In some embodiments, a conductive wiring layer 52 is formed from a conductive prelayer 52'. The conductive wiring layer 52 may include conductive wiring, conductive traces, metal lines, etc. The conductive wiring layer 52 may be referred to herein as "wiring 52". In other embodiments, the wiring 52 may be formed before the first core substrate 50A is attached to the first carrier 10.

[0023] In some embodiments, a surface preparation process may be performed on the conductive prelayer 52' ​​before the wiring 52 is formed from the conductive prelayer 52'. The surface preparation process may include cleaning the exposed surfaces of the conductive prelayer 52' ​​with one or more cleaning solutions (e.g., sulfuric acid, chromic acid, neutralizing alkaline solutions, water rinsing, etc.) to remove or reduce dirt, oil, and / or native oxide films. After cleaning, a treatment with chemical modifiers, etc., may be used to promote the adsorption of activators used during subsequent electroless plating processes. In some embodiments, the moderating step may be followed by micro-etching of the conductive prelayer 52' ​​to micro-roughen the conductive prelayer 52' ​​for better bonding between the conductive prelayer 52' ​​and the conductive material subsequently deposited.

[0024] In some embodiments, a patterned mask (not shown) may then be formed over the conductive prelayer 52'. The patterned mask may be formed, for example, by: coating a surface with a photoresist layer; exposing the photoresist layer to an optical pattern; and developing the exposed photoresist layer to form openings defining the pattern within the photoresist layer. The openings of the pattern in the patterned mask expose portions of the conductive prelayer 52' ​​on which conductive material is subsequently deposited. The conductive material may then be deposited on the exposed areas of the conductive prelayer 52' ​​using, for example, a plating process, a chemical plating process, or another process. The deposition process may selectively deposit conductive material on the exposed areas of the conductive prelayer 52'. The conductive material may include, for example, copper, titanium, tungsten, aluminum, other metals, other alloys, etc.

[0025] After the conductive material is formed, the patterned mask (e.g., photoresist) can be removed using, for example, wet chemical processes, dry plasma processes, ashing processes, stripping processes, etc. The portion of the conductive prelayer 52' ​​covered by the patterned mask can be removed together with the patterned mask, or removed using a separate etching process. In this way, wiring 52 comprising the conductive material and the remaining portion of the conductive prelayer 52' ​​is formed on the side of the first core substrate 50A. In some embodiments, a cavity 53 (see [link to cavity 53]) is subsequently formed on the first core substrate 50A. Figure 3 Wiring 52 is not formed in the area of ​​). This is an example, and in other embodiments, wiring 52 may be formed using other materials or techniques.

[0026] exist Figure 3In some embodiments, a cavity 53 is formed in a first core substrate 50A. The cavity 53 can be formed, for example, using a laser drilling process. In other embodiments, other processes may also be used, such as mechanical drilling, etching, etc. Figure 3 As shown, cavity 53 can extend completely through the first core substrate 50A, thereby exposing the underlying release layer 11 or first carrier 10. In some embodiments, cavity 53 has a length L1 ranging from about 2 mm to about 11 mm, but other lengths are also possible. In some embodiments, a decontamination process can be performed to clean areas that may have been contaminated by the material of the first core substrate 50A during the formation of cavity 53. Decontamination can include mechanical processes (e.g., sandblasting with fine abrasives in a wet slurry), chemical processes (e.g., rinsing with a combination of organic solvents, permanganates, etc.), or combinations thereof.

[0027] exist Figure 4 In some embodiments, a component 20 is placed inside cavity 53. The component 20 can be placed inside cavity 53 using, for example, a pick-and-place (PnP) tool. In some embodiments, component 20 can be a passive device, such as a multilayer ceramic chip (MLCC) capacitor; an integrated passive device (IPD); an integrated voltage regulator (IVR), or a combination thereof. In some embodiments, component 20 can be an active device, such as a semiconductor die, an integrated circuit die, an electronic device, a memory die (e.g., a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, a high bandwidth memory (HBM) die, etc.), a logic chip, an analog chip, a microelectromechanical system (MEMS) chip, a radio frequency (RF) chip, or a combination thereof. Other types of component 20 are possible, and any suitable component can be contemplated within the scope of embodiments of this disclosure.

[0028] Although Figure 4A component 20 placed in cavity 53 is shown, but it should be understood that in other embodiments, multiple components (e.g., multiple dies or devices) may be placed in cavity 53. For example, in some embodiments, multiple components may be placed laterally adjacent to each other and / or stacked on top of each other, wherein the multiple components may have the same size or different sizes. Before being placed into cavity 53, component 20 may be processed according to applicable manufacturing processes to form a corresponding device structure. Component 20 may include connection terminals 21 formed as external connections. Connection terminals 21 may include, for example, conductive pads, conductive posts, conductive wiring, etc. In some embodiments, component 20 has a thickness T2 in the range of about 50 μm to about 650 μm, but other thicknesses are also possible. In some embodiments, the thickness T2 of component 20 is about the same as the thickness T1 of the first core substrate 50A. In other embodiments, the thickness T2 of component 20 is greater than or less than the thickness T2 of the first core substrate 50A. In some cases, the thickness T1 of the first core substrate 50A may be selected to match or appropriately correspond to the thickness T3 of the subsequently attached component 20.

[0029] In some embodiments, component 20 has a length L2 ranging from about 2 mm to about 10 mm, but other lengths are also possible. In some embodiments, the length L1 of cavity 53 is greater than the length L2 of component 20. In this way, component 20 can be laterally surrounded by a gap 22 between component 20 and the first core substrate 50A. Therefore, component 20 may not physically contact the first core substrate 50A. In some embodiments, the lateral distance D1 of the gap 22 between the sidewall of cavity 53 (e.g., the sidewall of the first core substrate 50A) and the sidewall of component 20 is in the range of about 10 μm to about 50 μm. In some cases, the lateral distance D1 of the gap 22 at one sidewall surface of component 20 is different from the lateral distance D1 of the gap 22 at different sidewall surfaces of the same component 20. The dimensions of cavity 53 (e.g., length, width, or area) may be larger than the dimensions of component 20. For example, in some embodiments, component 20 may have dimensions ranging from about 2 mm × 2 mm to about 10 mm × 10 mm, and cavity 53 may have dimensions ranging from about 2 mm × 2 mm to about 11 mm × 11 mm. Other dimensions or regions are also possible.

[0030] Component 20 can be placed on the surface of the release layer 11 exposed by cavity 53. In some embodiments, component 20 is bonded to the release layer 11 by an adhesive (not shown). The adhesive can be attached to the back side of component 20 and can also attach component 20 to the release layer 11. The adhesive can include any suitable adhesive, epoxy resin, die attachment film (DAF), etc. In some embodiments, the adhesive can be attached to the surface of the release layer 11 before component 20 is placed in cavity 53. In other embodiments, component 20 is placed on the surface of the first carrier 10 exposed by cavity 53, and an adhesive can be used.

[0031] exist Figure 5 In some embodiments, an insulating film 54 is formed over the first core substrate 50A, the component 20, and within the gap 22. The insulating film 54 extends continuously over and covers the top surfaces of the first core substrate 50A and the component 20. The insulating film 54 may partially or completely fill the gap 22. In some embodiments, the insulating film 54 covers the sidewalls of the first core substrate 50 and the component 20 within the gap 22. The insulating film 54 may physically contact the release layer 11, and the surfaces of the first core substrate 50A, the insulating film 54, and / or the component 20 may be substantially flush or coplanar. In some embodiments, the insulating film 54 may be an ABF film, a polymer material, a prepreg material, a laminate material, another material similar to those described above for the first core substrate 50A, or a combination thereof. The insulating film 54 may be formed by a lamination process, a coating process, or another suitable process. In some cases, after the insulating film 54 is formed, a thermal process, a pre-curing process, etc., may be performed on the insulating film 54. In some cases, thermal processes can facilitate the flow of insulating film 54 material into the gap 22. In some embodiments, the insulating film 54 may have a thickness ranging from about 5 μm to about 50 μm over the first core substrate 50A, but other thicknesses are also possible. In some cases, Figure 5 The structure shown can be considered a "core structure".

[0032] Figure 6 Similar to some embodiments are shown. Figure 5 The cross-sectional view shows a plan view of the structure. For example, Figure 6 The plan can be along a similar path as shown below. Figure 5 "in Figure 6 The section indicated. (e.g.) Figure 6 As shown, component 20 can be laterally surrounded by insulating film 54. In this way, insulating film 54 separates component 20 from the first core substrate 50A. The surrounding area of ​​component 20 and insulating film 54 is... Figure 6The figure is shown as a square shape in a plan view, but rectangles, curves, circles, ovals, other shapes or irregular shapes are also possible. Figure 6 The structures shown are illustrative examples, and the individual components may have different relative or absolute sizes or dimensions as shown.

[0033] exist Figure 7 In some embodiments, the first carrier 10 is removed (“stripped”) from the structure, and then the structure is flipped and attached to the second carrier 12. In some embodiments, stripping involves projecting light, such as laser or UV light, onto the release layer 11, causing the release layer 11 to decompose under the heat of the light, and the first carrier 10 can be removed. The structure is then flipped and placed on the second carrier 12, which may be similar to the first carrier 10. For example, the second carrier 12 may be a wafer, a strip, or another type of carrier. The structure may be attached to the second carrier 12 using a release layer 13, which may be similar to the release layer 11 previously described. For example, the insulating film 54 of the structure may be attached to the second carrier 12 via the release layer 13. In other embodiments, the release layer 13 is not present.

[0034] According to some embodiments, after the structure is attached to the second carrier 12, an adhesive layer 55 is deposited over the structure. The adhesive layer 55 may include any suitable adhesive, epoxy resin, die attachment film (DAF), prepreg layer, etc. Figure 7 As shown, the adhesive layer 55 covers the surfaces of the first core substrate 50A, the insulating film 54, and the component 20. In some embodiments, the adhesive layer 55 has a thickness in the range of about 20 μm to about 40 μm, but other thicknesses are also possible.

[0035] exist Figure 8In some embodiments, a second core substrate 50B is attached (e.g., "bonded") to a structure using an adhesive layer 55. The second core substrate 50B can be similar to the first core substrate 50A. For example, the second core substrate 50B may include ABF, a polymeric material, a laminated material, a glass fiber reinforced resin material, etc. The second core substrate 50B can be placed on the adhesive layer 55 to bond the second core substrate 50B to the first core substrate 50A. The structure including the first core substrate 50A bonded to the second core substrate 50B may be referred to herein as a "multi-stacked core substrate 51" and may also be considered as a "bonded core substrate," etc. In some cases, the first core substrate 50A may be considered as the "upper core," and the second core substrate 50B may be considered as the "lower core." In some embodiments, there is no metal (e.g., conductive layer, wiring, etc.) between the first core substrate 50A and the second core substrate 50B of the multi-stacked core substrate 51. In some embodiments, a conductive layer or wiring may be formed on the non-attached side of the second core substrate 50B before or after attachment.

[0036] In some embodiments, the second core substrate 50B may have a thickness T3 that is approximately the same as or greater than the thickness T1 of the first core substrate 50A. In some embodiments, the total thickness T4 of the multi-stacked core substrate 51 (e.g., the total thickness of the first core substrate 50A, the adhesive layer 55, and the second core substrate 50B) is approximately 1200 μm or greater, but other thicknesses are also possible. Forming a multi-stacked core substrate 51 at least 1200 μm thick can provide a package substrate structure 70 for subsequent formation (see...). Figure 13 This results in improved rigidity and reduced warpage. In some cases, the thickness T3 of the second core substrate 50B can be selected to appropriately correspond to the thickness T1 of the first core substrate 50A to provide a suitable thickness T4 for the multi-stack core substrate 51. In some embodiments, the second core substrate 50B may have a thickness T3 in the range of about 500 μm to about 1200 μm, but other thicknesses are also possible.

[0037] exist Figure 9 In some embodiments, the second carrier 12 is removed from the structure, and a through-hole 56 is formed. The second carrier 12 can be removed, for example, by removing the release layer 13 using techniques similar to those described for the release layer 11. Figure 9 In the middle, the structure has already changed from Figure 8 The orientation is reversed. According to some embodiments, after the second carrier 12 is removed, a through-hole 56 extending through the structure is formed. The through-hole 56 allows electrical connection between opposite sides of the structure. In some cases, the through-hole 56 can be physically and electrically connected to portions of the wiring 52. In some cases, the through-hole 56 can be considered a plated through-hole (PTH), a conductive conduit, etc.

[0038] The via 56 can be formed, for example, by forming an opening (not shown separately) extending through the structure. The opening can extend completely through the insulating film 54 and the multi-stack core substrate 51. In some embodiments, the opening is formed by laser drilling. Other processes, such as mechanical drilling, etching, etc., can also be used. The opening can have a rectangular, circular, or other shape in the top view. After forming the opening, a decontamination process can be performed, which can be similar to the decontamination processes previously described. In some cases, surface preparation processes, such as cleaning processes, can be performed on the structure and within the opening, which can be similar to the surface preparation processes previously described. In some cases, conditioning steps and / or micro-etching steps can be performed on the structure and within the opening, which can be similar to those previously described.

[0039] After the openings are formed, a patterned mask (not shown separately) can be formed over the structure. In some embodiments, a conductive pre-layer (e.g., a copper layer, metal foil, seed layer, etc.) can be deposited on the structure and within the openings before forming the patterned mask. The patterned mask can be formed, for example, by: coating a surface with a photoresist layer; exposing the photoresist layer to an optical pattern; and then developing the exposed photoresist layer to form an opening in the photoresist layer, defining a pattern that defines an area where conductive material can be deposited. For example, the openings in the patterned photoresist layer can correspond to the openings in the structure. Conductive material is then deposited on the sidewalls of the openings in the structure using, for example, a plating process, a chemical plating process, or another process. The conductive material can also be deposited on the portion of wiring 52 exposed by the openings. In embodiments where the conductive pre-layer is formed in the openings, the conductive material is deposited on the conductive pre-layer on the sidewalls of the openings. The conductive material can include, for example, copper, other metals, metal alloys, etc., or combinations thereof. After depositing the conductive material, the patterned mask (e.g., photoresist) can be removed using a wet chemical process or a dry process (e.g., an ashing process). The portion of the conductive prelayer covered by the patterned mask (if present) can be removed using the patterned mask or a separate etching process.

[0040] In some embodiments, after a conductive material is formed along the sidewalls of the opening, the opening can then be filled with a dielectric material, such as... Figure 9As shown in the diagram. The dielectric material can provide structural support, insulation, and protection for the conductive material. In some embodiments, the dielectric material can be an insulating material, such as a molding material, epoxy resin, epoxy molding compound, resin, or a combination thereof. The dielectric material can be formed using, for example, spin coating, lamination, deposition, sealing, or another process. In some embodiments, the conductive material can completely fill the via 56, omitting the dielectric material. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), grinding, etc., can be implemented to remove excess material from the surfaces of the insulating film 54 and / or the second core substrate 50B. In some embodiments, the surfaces of the via 56 and the insulating film 54 can be substantially flush or coplanar, and the surfaces of the via 56 and the second core substrate 50B can be substantially flush or coplanar.

[0041] exist Figure 10 In some embodiments, through-hole openings 59 for exposing the connection terminals 21 and / or wiring 52 of the exposed assembly 20 are formed in the insulating film 54. Through-hole portions of the subsequently formed wiring 60A are formed in the through-hole openings 59 (see...). Figure 11 This is done to create an electrical connection to component 20 and / or wiring 52. In some embodiments, the through-hole opening 59 is formed using, for example, laser drilling. In other embodiments, other processes may be used, such as mechanical drilling, etching, etc. In some embodiments, a decontamination process or other cleaning process may be performed after the through-hole opening 59 is formed.

[0042] exist Figure 11 In some embodiments, conductive wiring layers 60A (e.g., "wiring 60A") and 61A (e.g., "wiring 61A") are formed on opposite sides of the structure. Wiring 60A is formed over an insulating film 54 and a via 56 on one side (e.g., the "top side") of the structure, and wiring 61A is formed over a second core substrate 50B and a via 56 on the opposite side (e.g., the "bottom side") of the structure. In some embodiments, a conductive prelayer (not shown) may be formed over each side of the structure, which may serve as a seed layer for forming a conductive material (described below). The conductive prelayer may be similar to those previously described for... Figure 9 The conductive prelayer is described. For example, the conductive prelayer can be a metal foil such as copper foil or another type of material such as those described above for wiring 52. In other embodiments, the conductive prelayer may be formed on the structure before the via opening 59 is formed. In other embodiments, no conductive prelayer is formed.

[0043] In some embodiments, wiring 60A is formed by first forming a patterned mask over the top side of the structure. The patterned mask may be, for example, a patterned photoresist layer. Openings in the patterned mask may expose portions of a conductive prelayer on which conductive material will subsequently be formed. The conductive material is then deposited on the exposed areas of the conductive prelayer and in the via openings 59 using, for example, electroplating, electroless plating, or other processes. The conductive material may be similar to the conductive material previously described for wiring 52. After the conductive material is formed, the patterned mask and portions of the conductive prelayer on which the conductive material is not formed are then removed. After the conductive material is deposited, the underlying portions of the patterned mask (e.g., photoresist) and the conductive prelayer may be removed using one or more suitable wet chemical processes or dry processes. The remaining portions of the conductive prelayer and conductive material form wiring 60A. However, any suitable processes and materials may be used in the formation of wiring 60A.

[0044] In this manner, wiring 60A can be formed above and electrically connected to wiring 52 on the top side of via 56, component 20, and / or structure. Wiring 60A includes conductive trace portions extending along the surfaces of insulating film 54 and via 56, and conductive via portions extending through via opening 59 in insulating film 54. The via portions of wiring 60A physically and electrically connect the conductive trace portions of wiring 60A to underlying conductive components, such as connection terminals 21 or wiring 52.

[0045] Wiring 61A can be formed on the bottom side of the structure using techniques similar to those used to form wiring 60A on the top side of the structure. For example, a patterned mask can be formed above the bottom side of the structure, having openings that expose a conductive prelayer on which conductive material will subsequently be formed. Conductive material can then be deposited on the exposed portion of the conductive prelayer using, for example, plating techniques. The patterned mask and the lower portion of the conductive prelayer can then be removed, with the remaining portion of the conductive material and conductive prelayer forming wiring 61A. In other embodiments, no conductive prelayer is formed. In this way, wiring 61A can be formed above and electrically connected to via 56 on the bottom side of the structure. Wiring 61A includes conductive trace portions extending along the surfaces of the second core substrate 50B and via 56.

[0046] In some embodiments, some process steps for forming wiring 61A can be performed at the same time as the process steps for forming wiring 60A. For example, in some embodiments, conductive material can be deposited to simultaneously form wiring 60A and wiring 61A. In some cases, the same process steps can be used to simultaneously remove the patterned mask or underlying conductive prelayer from the top and bottom sides of the structure. In other embodiments, the conductive material of via 56 is deposited simultaneously with the conductive material of wiring 60A and / or wiring 61A. These are examples, and other shared process steps are also possible.

[0047] exist Figure 12 In some embodiments, an additional layer of wiring 60B is formed over wiring 60A on the top side of the structure, and an additional layer of wiring 61B is formed over wiring 61A on the bottom side of the structure. Wiring 60B and wiring 61B can be formed using similar process steps, and some process steps for forming wiring 60B and wiring 61B can be simultaneous. In some embodiments, a build-up layer 62A is formed on the top side of the structure, and a build-up layer 63A is formed on the bottom side of the structure. For example, build-up layer 62A is formed over insulating film 54 and wiring 60A, and build-up layer 63A is formed over second core substrate 50B and wiring 61A. Build-up layers 62A and 63A (e.g., "build-up layers 62A / 63A") can be similar types of build-up layers, or they can be different types of build-up layers. Build-up layers 62A / 63A can include materials similar to those previously described for insulating film 54 or first core substrate 50A, but other materials are also possible. In some embodiments, within the same structure, the materials of the accumulation layers 62A and / or 63A may differ from the material of the insulating film 54. The accumulation layers 62A / 63A may be formed by a lamination process, a coating process, or another suitable process. In some embodiments, the accumulation layers 62A and / or 63A may have a thickness ranging from about 5 μm to about 40 μm, but other thicknesses are also possible. In some embodiments, a conductive prelayer (not shown) may be formed over the accumulation layers 62A / 63A, which may serve as a seed layer for forming a conductive material (described below). The conductive prelayer may be similar to those previously described and may be, for example, a metal foil, such as copper foil. In other embodiments, no conductive prelayer is formed.

[0048] In some embodiments, an opening (not shown) is formed in the accumulation layer 62A to expose a portion of the wiring 60A, and an opening (not shown) is formed in the accumulation layer 63A to expose a portion of the wiring 61A. In some embodiments, the opening is formed by, for example, laser drilling. In other embodiments, other processes may be used, such as mechanical drilling, etching, etc. In some embodiments, after the opening is formed, optional surface preparation processes (e.g., decontamination processes, etc.) may be performed.

[0049] A conductive material is then deposited on the top side of the structure to form wiring 60B on the accumulation layer 62A and within openings in the accumulation layer 62A, and a conductive material is deposited on the bottom side of the structure to form wiring 61B on the accumulation layer 63A and within openings in the accumulation layer 63A. In some embodiments, wiring 60B is formed by first forming a patterned mask over the accumulation layer 62A. The patterned mask may be, for example, a patterned photoresist layer. Openings in the patterned mask may expose portions of the accumulation layer 62A (or, if present, a conductive prelayer on the accumulation layer 62A) on which the conductive material will subsequently be formed. Openings in the patterned mask may also expose openings in the accumulation layer 62A. The conductive material is then deposited on the exposed areas of the accumulation layer 62A and within the openings in the accumulation layer 62A using, for example, an electroplating process, a chemical plating process, or another process. After the conductive material is deposited, the patterned mask (e.g., photoresist) and the underlying portion of the conductive prelayer may be removed using one or more suitable wet chemical processes or dry processes. The conductive prelayer and the remaining portion of the conductive material form wiring 60B. In this way, additional wiring 60B is formed above wiring 60A and electrically connected to wiring 60A. Wiring 61B can be formed on the bottom side of the structure using techniques similar to those used to form wiring 60B on the top side of the structure, and some process steps for forming wiring 60B and wiring 61B can be shared. However, any suitable processes and materials can be used in the formation of wiring 60B or wiring 61B.

[0050] exist Figure 13 In some embodiments, additional wiring 60C is formed on wiring 60A to form a first wiring structure 64, and additional wiring 61C is formed on wiring 61B to form a second wiring structure 66. In this way, according to some embodiments, a package substrate structure 70 including a multi-stacked core substrate 51, component 20, first wiring structure 64, and second wiring structure 66 can be formed. Wiring 60C and wiring 61C can be similar to wiring 60A-60B or wiring 61A-61B, and can be formed using similar techniques. For example, a stacked layer 62B can be formed over stacked layer 62A and wiring 60B, openings can be formed in stacked layer 62B, and then a patterned mask can be used to deposit conductive material to form wiring 60C on and in stacked layer 62B. Similarly, a stacked layer 63B can be formed over the stacked layer 63A and the wiring 61B, an opening can be formed in the stacked layer 63B, and a conductive material can then be deposited using a patterned mask to form wiring 61C on and in the stacked layer 63B.

[0051] In some embodiments, the first wiring structure 64 includes conductive pads 67 formed on wiring 60C, and the second wiring structure 66 includes conductive pads 68 formed on wiring 66. Conductive pads 67 / 68 facilitate external electrical connections to the package substrate structure 70. For example, conductive pad 67 may allow electrical connections to the top side of the package substrate structure 70 (e.g., to the first wiring structure 64), and conductive pad 68 may allow electrical connections to the bottom side of the package substrate structure 70 (e.g., to the second wiring structure 66). In some embodiments, conductive pads 67 / 68 may be under-bump metallization (UBM) structures, etc. In some embodiments, conductive pads 67 / 68 may be formed using techniques similar to those previously described for wirings 60A-60C and wirings 61A-61C. In some cases, conductive pads 67 / 68 may be considered as another layer of wiring, such as the “outermost” layer of wiring. As an example, a build-up layer 62C can be formed over the build-up layer 62B and the wiring 60C. An opening can be formed in the build-up layer 62C, and a patterned mask can then be used to deposit conductive material to form conductive pads 67 on and in the build-up layer 62C. Similarly, a build-up layer 63C can be formed over the build-up layer 63B and the wiring 61C. An opening can be formed in the build-up layer 63C, and a patterned mask can then be used to deposit conductive material to form conductive pads 68 on and in the build-up layer 63C. In some embodiments, the conductive pads 67 may have a different size or spacing than the conductive pads 68. In some embodiments, a passivation layer, solder mask, etc. (not shown separately) can be formed over the outermost build-up layer (e.g., build-up layer 62C or 63C).

[0052] In this manner, according to some embodiments, a first wiring structure 64 is formed on the top side of the multi-stacked core substrate 51, and a second wiring structure 66 is formed on the bottom side of the multi-stacked core substrate 51. Thus, the multi-stacked core substrate 51 is sandwiched between the first wiring structure 64 and the second wiring structure 66. Through-holes 56 electrically connect the first wiring structure 64 to the second wiring structure 66. The first wiring structure 64 is shown as three layers with wirings 60A-60C, and the second wiring structure 66 is shown as three layers with wirings 61A-61C, but the wiring structures 64 / 66 can have any suitable number of wiring layers. The stacked layers of the wiring structures 64 / 66 can all be formed of the same material, or the stacked layers of the wiring structures 64 / 66 can be formed of different materials. In some cases, the wiring structures 64 / 66 can be considered as interconnect structures, redistribution structures, etc. Figure 13 As shown, the first wiring structure 64 is physically and electrically connected to component 20 (e.g., via wiring 60A), but the second wiring structure 66 is not physically connected to component 20 and is separated from component 20 by the second core substrate 50B. In some embodiments, the package substrate structure 70 may be pressed or subjected to heat treatment. Figure 13 The packaging substrate structure 70 shown is an example, and other configurations are also possible.

[0053] The packaging substrate structure 70 can be incorporated into other packages or structures. The packaging substrate structure 70 can be incorporated into, for example, integrated fan-out (InFO) packages, chip-on-wafer-on-substrate (CoWoS) packages, or another type of package. As a non-limiting example, Figure 14 A package 90 with a combined package substrate structure 70 according to some embodiments is shown. Figure 14 In some embodiments, the packaging component 80 is attached (e.g., bonded) to the packaging substrate structure 70.

[0054] The packaging component 80 may include, for example, a die, a chip, a semiconductor device, a stacked die, an electronic die, a chip-on-wafer (CoW) structure, a component, or any other suitable structure. Figure 14 In this example, package assembly 80 includes a plurality of dies 84 attached to an interposer 82. The dies 84 may be devices similar to those previously described with respect to assembly 20. For example, in some embodiments, the dies 84 may include logic dies and memory dies, but other combinations of dies 84 are also possible. The interposer 82 may include conductive wiring (not shown separately) formed in or on a wafer (e.g., a silicon wafer), a core substrate, etc. In some cases, the interposer 83 may be another type of interposer, such as a redistributed interposer, etc. The interposer 82 may have vias, etc. (not shown separately). In some cases, the interposer 82 may have no active and / or passive devices. The dies 84 may be attached to the interposer by conductive connections (e.g., solder bumps, etc.) or using direct bonding (such as fusion bonding or metal-to-metal bonding). Package assembly 80 is an illustrative example, and other package assemblies are also possible.

[0055] According to some embodiments, the package assembly 80 can be attached to the package substrate structure 70 via conductive connectors 86. For example, the conductive connectors 86 can physically and electrically connect the conductive pads 67 of the package substrate structure 70 to the package assembly 80. The conductive connectors 86 can be ball grid array (BGA) connectors, solder balls, metal pillars, solder bumps, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium-ion immersion gold (ENEPIG) technology, etc. The conductive connectors 86 can include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the conductive connectors 86 are formed by initially forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connectors 86 include metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal overlay is formed on the top of the metal pillars. The metal overlay may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof, and may be formed by a plating process. In some embodiments, the package assembly 80 may be disposed on the package substrate structure 70 such that the conductive connections 86 of the package assembly 80 are positioned in contact with the conductive pads 67 of the package substrate structure 70. Once disposed, a reflow process may be performed to bond the package assembly 80 to the package substrate structure 70. In other embodiments, the package assembly 80 may be bonded to the package substrate structure 70 using direct bonding (such as fusion bonding or metal-to-metal bonding).

[0056] In some embodiments, an underfill 87 may be optionally formed between the package assembly 80 and the package substrate structure 70. The underfill 87 may surround the conductive connector 86. The underfill 87 may be formed after the package assembly 80 has been attached using, for example, a capillary underfill process. Other deposition techniques are also possible. In some embodiments, the conductive connector 88 may be formed on the conductive pad 68. The conductive connector 88 may be similar to the conductive connector 86 previously described. In some embodiments, integrated passive devices (IPDs) such as (not shown separately) may be attached to the conductive pad 68. Figure 14 The package 90 shown is an example, and other packages 90 are also possible.

[0057] The use of the multi-stacked core substrate 51 as described herein allows one or more components 20 to be incorporated into the package substrate structure 70 of the package 90, while allowing the package substrate structure 70 to maintain appropriate stiffness. In this way, yield, design flexibility, and device functionality can be improved. Figure 14The component 20 is shown to be electrically connected to the package assembly 80 via a first wiring structure 64. Placing the component 20 within a cavity 53 of the multi-stacked core substrate 51 allows for a reduced distance between the component 20 and the package assembly 80. Reducing this distance can decrease the voltage drop between the component 20 and the package assembly 80, which can improve the power integrity, efficiency, and performance of the package 90. In some embodiments, the distance T5 between the component 20 and the package assembly 80 can range from about 130 μm to about 490 μm, but other distances are also possible. The distance T5 can depend on the number of wiring layers and / or the number of stacked layers in the first wiring structure 64. As described herein, forming the component 20 within the multi-stacked core substrate 51 can also reduce the amount of wiring in the package and reduce the overall size of the package.

[0058] Figure 14 A package assembly 80 is shown attached to a first wiring structure 64 of a package substrate structure 70, but in other embodiments, the package assembly 80 may be attached to a second wiring structure 66 of the package substrate structure 70. Therefore, Figure 15 An example of package 91 is shown. Package 91 is similar to Figure 14 The package 90 differs in that the package assembly 80 is attached to the "bottom side" of the package substrate structure 70 instead of the "top side" of the package substrate structure 70. In this way, the component 20 can be electrically connected to the package assembly 80 through the first wiring structure 64, the through-hole 56, and the second wiring structure 66. Figure 15 Package 91 is an illustrative example, and other configurations are possible. Similar to packages 90 / 91, other embodiments of the package substrate structure described herein may have a package assembly 80 attached to either side.

[0059] Figures 16 to 23 A cross-sectional view is shown of an intermediate step in the formation of a package substrate structure 100 according to some embodiments. The package substrate structure 100 is similar to... Figure 13 The encapsulation substrate structure 70 differs in that the first component 20A is placed within the first core substrate 50A, and the second component 20B is placed within the second core substrate 50B. Some materials, techniques, and / or process steps used to form the encapsulation substrate structure 100 may be similar to those used to form the encapsulation substrate structure 70, and therefore some details will not be repeated below.

[0060] Figure 16 A first core structure 101 according to some embodiments is shown. The first core structure 101 may be similar to those previously described. Figure 5The described core structure can be formed using similar techniques. For example, the first core structure 101 can be formed by forming a cavity in a first core substrate 50A and placing a first component 20A in the cavity. The first component 20A can be attached using an adhesive or the like (not shown separately). In some cases, wiring 52A can be formed over the first core substrate 50A. An insulating film 54A can then be formed over the first core substrate 50A, over the first component 20A, and inside the cavity. The insulating film 54A can be similar to that previously described for... Figure 5 The insulating film 54 is described. For example, in some embodiments, the insulating film 54 comprises ABF, but other materials are also possible.

[0061] exist Figure 17 In this configuration, the first core structure 101 is flipped vertically, and an adhesive layer 55 is formed over the first core substrate 50A and the first component 20A. The adhesive layer 55 can be similar to that previously used for... Figure 7 The adhesive layer is described. Figure 18 and Figure 19 In some embodiments, the second core structure 102 is attached to the first core structure 101 using an adhesive layer 55. Figure 18 The second core structure 102 prior to attachment is shown, and Figure 19 A second core structure 102 is shown after attachment to the first core structure 101. The second core structure 102 can be similar to the first core structure 101 and can be formed using similar techniques. For example, the second core structure 102 can be formed by forming a cavity in the second core substrate 50B and placing the second component 20B in the cavity. The second component 20B can be attached using an adhesive or the like (not shown separately). In some cases, wiring 52B can be formed over the second core substrate 50B. An insulating film 54B can then be formed over the second core substrate 50B, over the second component 20B, and inside the cavity. In some cases, the insulating film 54B can be similar to the insulating film 54A.

[0062] The first component 20A and the second component 20B can be similar or different components. The dimensions of the cavity and / or components of each core structure 101 / 102 can be similar or different. In other embodiments, one or both of the core structures 101 / 102 may include two or more components. The core substrates 50A / 50B can have similar or different thicknesses. (See reference...) Figure 19 According to some embodiments, a first core substrate 50A bonded to a second core substrate 50B forms a multi-stack core substrate 151. In some embodiments, the thickness T4 of the multi-stack core substrate 151 can be about 1200 μm or greater to maintain suitable stiffness and structural support. Other thicknesses are also possible. The first component 20A and the second component 20B can be laterally offset (e.g., Figure 19As shown in the image), or they can be aligned laterally (e.g., overlap). Figure 19 As shown, the first component 20A and the second component 20B are placed "back to back" and separated by an adhesive layer 55.

[0063] exist Figure 20 In some embodiments, one or more through holes 56 are formed extending through the structure. Figure 20 A single through-hole 56 is shown, but multiple through-holes 56 may be formed in other embodiments. The through-hole 56 may be similar to those previously shown. Figure 9 The aforementioned techniques can be used to form vias. For example, an opening extending through the structure can be formed, and a conductive material can then be deposited within the opening to form a via 56. The opening can then be filled with a dielectric material. In some cases, the via 56 can be physically and electrically connected to wirings 52A and / or 52B.

[0064] exist Figure 21 In some embodiments, an opening 59A can be formed in the insulating film 54A, and an opening 59B can be formed in the insulating film 54B. The openings 59A-59B can be similar to those previously used for... Figure 10 The described opening 59 can be formed using similar techniques, such as laser drilling. For example, opening 59A may expose the connection terminals of wiring 52A and / or the first component 20A, and opening 59B may expose the connection terminals of wiring 52B and / or the second component 20B.

[0065] exist Figure 22 In the middle, a layer of wiring 60A is formed on and in the insulating film 54B, and a layer of wiring 61A is formed on and in the insulating film 54A. Wiring 60A / 61A can be used similarly to those previously used for... Figure 11 The materials and techniques described are used to form the wiring. For example, a patterned mask may be formed over the insulating films 54A / 54B, and a conductive material may then be deposited over the insulating films 54A / 54B and within the openings 59A-59B. In some embodiments, forming wiring 60A / 61A may include forming a conductive prelayer over the insulating films 54A / 54B. Wiring 60A may be electrically connected to the second component 20B and / or the via 56, and wiring 61A may be electrically connected to the first component 20A and / or the via 56.

[0066] exist Figure 23 In some embodiments, additional wirings 60B-60C are formed above wiring 60A to form a first wiring structure 64, and additional wirings 61B-61C are formed above wiring 61A to form a second wiring structure 66. The additional wirings 60B-60C of the first wiring structure 64 and the additional wirings 61B-61C of the second wiring structure 66 can be used with previously designed wiring structures. Figures 12 to 13 Similar materials and techniques described herein can be used to form the wiring 60B. For example, to form wiring 60B, a stacked layer 62A can be formed over insulating film 54B and wiring 60A, openings can be formed in stacked layer 62A, and conductive material can then be deposited using a patterned mask to form wiring 60B on and in stacked layer 62A. Wiring 61B can be similarly formed on and in stacked layer 63A over wiring 61A and insulating film 54A. Additional layers of wiring (e.g., wirings 60C and 61C) can be formed by repeating similar processes with additional stacked layers (e.g., stacked layers 62B and 63B). The first wiring structure 64 may include conductive pads 67, and the second wiring structure 66 may include conductive pads 68. Conductive pads 67 / 68 can be used with previously designed materials. Figure 13 The described materials or techniques are used to form the wiring structure. The wiring structure 64 / 66 may include an additional number of stacked layers and / or wiring in addition to those shown.

[0067] In this way, according to some embodiments, a package substrate structure 100 can be formed. Additional process steps can be implemented, such as packaging the components (e.g., Figures 14 to 15 The package component 80) is attached to a conductive pad or a conductive connection is formed on the conductive pad. The techniques described herein allow for the formation of package substrate structures comprising multiple components, which can reduce package size, improve design flexibility, improve package functionality, improve package efficiency, and improve package performance.

[0068] Figures 24 to 35 A cross-sectional view is shown of an intermediate step in the formation of a package substrate structure 200 according to some embodiments. The package substrate structure 200 is similar to... Figure 13 The encapsulation substrate structure 70 differs in that component 20 is thicker than the first core substrate 50A and forms multiple insulating films with wiring. Furthermore, the second core substrate 50B may be thicker than the first core substrate 50A, forming an "asymmetric" multi-stacked core substrate 251. Some materials, techniques, and / or process steps used to form the encapsulation substrate structure 200 can be similar to those used to form the encapsulation substrate structure 70, and therefore some details will not be repeated below.

[0069] Figure 24 A first core substrate 50A is shown attached to a first carrier 10 according to some embodiments. The first core substrate 50A can be attached using a release layer 11 or the like. The first core substrate 50A, the first carrier 10, and the release layer 11 can be similar to those previously described for... Figure 1 Those described. In some embodiments, the first core substrate 50A may have a thickness T1 in the range of about 50 μm to about 650 μm, but other thicknesses are also possible. In other embodiments, a conductive prelayer 52' ​​or wiring 52 may be formed on the top side of the first core substrate 50A.

[0070] exist Figure 25 In some embodiments, a cavity 203 is formed in the first core substrate 50A. The cavity 203 can be formed using methods similar to those used for... Figure 3 Cavity 53 is formed using the techniques described above. For example, cavity 203 can be formed using laser drilling processes, etc. In some embodiments, after forming cavity 203, a decontamination process or other cleaning process may be performed. Cavity 203 may extend completely through the first core substrate 50A, such as... Figure 25 As shown in the diagram. In other embodiments, in a later step, a cavity is formed through the first core substrate 50A, and below for... Figures 36 to 41 An exemplary embodiment of this invention is described.

[0071] exist Figure 26 In some embodiments, a first core substrate 50A is peeled off from a first carrier 10, and a second core substrate 50B is attached to the first core substrate 50A. The second core substrate 50B may be attached to the first core substrate 50A using an adhesive layer 55 or the like. The second core substrate 50B may be similar to the first core substrate 50A, except that the second core substrate 50B has a thickness T3 greater than the thickness T1 of the first core substrate 50B. In some embodiments, the first core substrate 50A attached to the second core substrate 50B forms a multi-stack core substrate 251. In some embodiments, the thickness T4 of the multi-stack core substrate 251 may be about 1200 μm or greater to maintain suitable rigidity and structural support. Therefore, the thickness T3 of the second core substrate 50B can be selected to appropriately correspond to the thickness T1 of the first core substrate 50A to provide a suitable thickness T4 for the multi-stack core substrate 251. In some embodiments, the second core substrate 50B may have a thickness T3 in the range of about 500 μm to about 1200 μm. Other thicknesses are also possible. In some embodiments, after the first core substrate 50A is bonded to the second core substrate 50B, the surface of the adhesive layer 55 may be exposed within the cavity 203.

[0072] exist Figure 27 In some embodiments, one or more vias 56 are formed extending through the multi-stack core substrate 251. The vias 56 may be similar to those previously used for... Figure 9 The aforementioned techniques can be used to form such vias. For example, openings extending through the multi-stacked core substrate 251 can be formed, and conductive material can then be deposited within the openings to form vias 56. The openings can then be filled with a dielectric material.

[0073] exist Figure 28In some embodiments, wirings 252A and 61A are formed on a multi-stack core substrate 251. Wiring 252A is formed on a first core substrate 50A (e.g., on the top side of the multi-stack core substrate 251), and wiring 61A is formed on a second core substrate 50B (e.g., on the bottom side of the multi-stack core substrate 251). Wirings 252A and 61A (e.g., wirings 252A / 61A) can be formed using methods similar to those used for forming such components. Figure 11 The techniques described for forming wiring 61A are employed. For example, a patterned mask may be formed over the core substrate 50A / 50B, and a conductive material may then be deposited over the core substrate 50A / 50B using the patterned mask. In some embodiments, forming wiring 252A / 61A may include forming a conductive pre-layer over the core substrate 50A / 50B. Wiring 252A and / or wiring 61A may be electrically connected to via 56.

[0074] exist Figure 29 In some embodiments, an insulating film 254A is formed over the first core substrate 50A and within the cavity 203. Furthermore, in some embodiments, a layer for wiring 252B is formed on and within the insulating film 254A. The insulating film 254A can be similar to that previously used for… Figure 5 The insulating film 54 is described. For example, in some embodiments, the insulating film 254A comprises ABF, but other materials are also possible. In some embodiments, the insulating film 254A fills the cavity 203 and may cover the surface of the adhesive layer 55. The wiring 252B can use materials similar to those used for forming such a wiring. Figure 11 The described wiring 60A is formed using those techniques. Wiring 252B extends on and within insulating film 254A and is physically and electrically connected to wiring 252A.

[0075] exist Figure 30 In some embodiments, an insulating film 254B and wiring 252C are formed over the insulating film 254A and wiring 252B. The insulating film 254B can be similar to that previously used for... Figure 5 The insulating film 54 is described and may be similar to insulating film 254A. Wiring 252C can be formed using techniques similar to those used to form wiring 252B. In some embodiments, additional layers of insulating film and wiring can be formed by repeating these process steps.

[0076] exist Figure 31 In some embodiments, a cavity 205 is formed in insulating films 254A-254B. The cavity 205 can extend completely through insulating films 254A-254B. The cavity 205 is formed above the location of a previously formed cavity 203 (see...). Figure 25Therefore, cavity 205 can extend through the first core substrate 50A to expose the surfaces of adhesive layer 55 and / or the second core substrate 50B. In some embodiments, the width of cavity 205 is smaller than the width of cavity 203, such that the sidewalls of the first core substrate 50A remain covered by insulating film 254A. Furthermore, some portions of adhesive layer 55 may remain covered by insulating film 254A. In some embodiments, the width of cavity 205 may be between approximately 2 mm and approximately 6 mm smaller than the width of the previously formed cavity 203. Other widths are also possible. Cavity 205 can be formed using laser drilling or another suitable technique. In some cases, a cleaning process, such as a decontamination process, can be performed after cavity 205 is formed. In other embodiments, an additional layer of insulating film and / or an additional layer of wiring can be formed over insulating film 254B before cavity 205 is formed. In other embodiments, multiple cavities 203 and cavities 205 can be formed.

[0077] exist Figure 32 In some embodiments, component 20 is placed within cavity 205. Component 20 may be similar to those previously described and may be attached to the bottom surface of cavity 205 (e.g., the surface of adhesive layer 55). In some embodiments, component 20 is attached using an adhesive (not shown separately). In some embodiments, the width of component 20 is less than the width of cavity 205, such that a gap surrounds component 20, and the sidewalls of component 20 are separated from insulating films 254A-254B. In some embodiments, the lateral distance of the gap between the sidewalls of cavity 205 (e.g., the sidewalls of insulating films 254A-254B) and the sidewalls of component 20 is in the range of about 10 μm to about 50 μm. Other distances are also possible. In some embodiments, component 20 has a thickness T2 greater than the thickness T1 of the first core substrate 50A. Therefore, the top surface of component 20 protrudes above the top surface of the first core substrate 50A. In some embodiments, the thickness T2 of component 20 is approximately the same as the depth of cavity 205, but in some cases, the thickness T2 may be greater than or less than the depth of cavity 205. In some embodiments, the number and / or thickness of the insulating film (e.g., insulating films 254A-254B) above the first core substrate 50A are selected to correspond to the thickness T2 of component 20. For example, in some embodiments, the top surface of component 20 may be approximately flush with the top surface of the topmost insulating film (e.g., insulating film 254B) and / or the topmost wiring (e.g., wiring 252C). In some embodiments, component 20 has a thickness T2 in the range of about 50 μm to about 650 μm, but other thicknesses are also possible. In other embodiments, multiple components 20 may be placed in one or more cavities 205.

[0078] exist Figure 33An insulating film 254C is formed over the insulating film 254B, over the wiring 252C, over the assembly 20, and within the cavity 205. The insulating film 254C can be similar to insulating films 254A-254B. For example, in some embodiments, the insulating film 254C comprises ABF, but other materials are also possible. The insulating film 254C fills the cavity 205 and covers the assembly 20. Therefore, in some embodiments, the insulating film 254C can cover the surface of the adhesive layer 55 and the sidewalls of the assembly 20. The thickness of the insulating film 254C on the sidewalls of the assembly 20 can be approximately the same as that described above for... Figure 32 The lateral distances of the described gaps are the same. In some cases, insulating films 254A-254C and wiring 252A-252C can be considered as wiring structure 256. In other embodiments, wiring structure 256 includes another number of layers of insulating film and / or wiring.

[0079] exist Figure 34 In some embodiments, a layer for forming wiring 60A is formed on and within the insulating film 254C. Wiring 60A can be formed using methods similar to those previously used for forming... Figure 11 The wiring 60A is formed using the materials and techniques described herein. For example, openings exposing portions of wiring 252C and connection terminals of component 20 may be formed in insulating film 254C. A patterned mask may be formed over insulating film 254C, and conductive material may then be deposited over insulating film 254C and within the openings. In some embodiments, forming wiring 60A may include forming a conductive prelayer over insulating film 254C. Wiring 60A may be electrically connected to component 20 and / or wiring 252C.

[0080] exist Figure 35 In some embodiments, additional wirings 60B-60C are formed above wiring 60A to form a first wiring structure 64, and additional wirings 61B-61C are formed above wiring 61A to form a second wiring structure 66. The additional wirings 60B-60C of the first wiring structure 64 and the additional wirings 61B-61C of the second wiring structure 66 can be used with previously designed wiring structures. Figures 12 to 13 Similar materials and techniques described herein may be used to form the wiring structure. For example, the first wiring structure 64 may include multiple stacked layers 62A-62C, and the second wiring structure 66 may include multiple stacked layers 63A-63C. The stacked layers 62A-62C / 63A-63C may include materials similar to or different from insulating films 254A-254C. The first wiring structure 64 may include conductive pads 67, and the second wiring structure 66 may include conductive pads 68. The conductive pads 67 / 68 may use materials previously used for... Figure 13 The described materials or techniques are used to form the wiring structure. The wiring structure 64 / 66 may include an additional number of stacked layers and / or wiring in addition to those shown.

[0081] In this way, according to some embodiments, a package substrate structure 200 can be formed. Additional process steps can be implemented, such as packaging the components (e.g., Figures 14 to 15 The package component 80 is attached to conductive pads or conductive connections are formed on the conductive pads. The techniques described herein allow for a smaller distance between component 20 and the package component 80 (not shown separately) attached thereto. Reducing this distance can reduce the voltage drop between component 20 and package component 80, which can improve the power integrity, efficiency, and performance of the package. As described herein, forming component 20 within a multi-stacked core substrate 251 can also reduce package size, improve design flexibility, improve package functionality, improve package efficiency, and improve package performance.

[0082] Figures 36 to 41 A cross-sectional view is shown of an intermediate step in the formation of a package substrate structure 201 according to some embodiments. The package substrate structure 201 is similar to... Figure 35 The packaging substrate structure 200 differs in that it does not form a cavity 203. Instead, a cavity 215 is formed in a single process through insulating layers 254A-254B and a first core substrate 50A. Some of the materials, techniques, and / or process steps used to form the packaging substrate structure 201 can be similar to those used to form the packaging substrate structure 200, and therefore some details will not be repeated below.

[0083] Figure 36 A multi-stacked core substrate 251' according to some embodiments is shown. The multi-stacked core substrate 251' is similar to... Figure 28 The multi-stacked core substrate 251 differs in that no cavity 203 is formed in the first core substrate 50A. Similar to... Figure 28 The multi-stacked core substrate 251 has wiring 252A, wiring 61A and via 56 formed on and in the multi-stacked core substrate 251'.

[0084] exist Figure 37 In some embodiments, a layer of wirings 252A-252B is formed above a first core substrate 50A. Wirings 252A-252B can be used for... Figures 29 to 30 The wirings 252A-252B described herein can be formed using similar techniques. For example, wirings 252A-252B can be formed in and on layers of insulating films 254A-254B, which can be similar to... Figures 29 to 30 The insulating films 254A-254B are used. In other embodiments, another number of insulating films and / or wiring layers may be formed.

[0085] exist Figure 38In some embodiments, a cavity 215 is formed in the insulating films 254A-254B and the first core substrate 50A. The cavity 215 can extend completely through the insulating films 254A-254B and the first core substrate 50A. The cavity 215 can expose the adhesive layer 55 and / or the surface of the second core substrate 50B. In some embodiments, the sidewalls of the first core substrate 50A can be exposed by the cavity 215. The cavity 215 can be formed using a laser drilling process or another suitable technique. In some cases, a cleaning process, such as a decontamination process, can be performed after the cavity 215 is formed.

[0086] exist Figure 39 In some embodiments, component 20 is placed within cavity 215. Component 20 can be similar to that previously designed for... Figure 32 The described component 20 can be attached to the bottom surface of cavity 215 (e.g., the surface of adhesive layer 55). In some embodiments, component 20 is attached using an adhesive (not shown separately). In some embodiments, the width of component 20 is smaller than the width of cavity 215, such that a gap surrounds component 20, and the sidewalls of component 20 are separated from insulating films 254A-254B and the first core substrate 50A. In some embodiments, the lateral distance of the gap between the sidewalls of cavity 205 (e.g., the sidewalls of insulating films 254A-254B or the first core substrate 50A) and the sidewalls of component 20 is in the range of about 10 μm to about 50 μm. Other distances are also possible.

[0087] exist Figure 40 An insulating film 254C is formed above the insulating film 254B, above the wiring 252C, above the assembly 20, and within the cavity 215. The insulating film 254C can be similar to that previously used for... Figure 33 The insulating film 254C is described. The insulating film 254C fills cavity 215 and covers assembly 20. Therefore, in some embodiments, the insulating film 254C may cover the surface of adhesive layer 55 and the sidewalls of assembly 20, the sidewalls of insulating films 254A-254B, and the sidewalls of the first core substrate 50A. The thickness of the insulating film 254C on the sidewalls of assembly 20 may be approximately the same as described above. Figure 39 The lateral distances of the described gaps are the same. In some cases, insulating films 254A-254C and wiring 252A-252C can be considered as wiring structure 256. In other embodiments, wiring structure 256 includes another number of layers of insulating film and / or wiring.

[0088] exist Figure 41 In some embodiments, wiring structures 64 and 66 are formed. Wiring structures 64 / 66 can use methods similar to those previously used for... Figures 34 to 35The techniques described are used to form the package substrate structure. In other embodiments, the wiring structure 64 / 66 may include another number of accumulation layers and / or wiring layers. In this way, the package substrate structure 201 can be formed. The package substrate structure 201 has similar benefits to those previously described for the package substrate structure 200.

[0089] Figures 42 to 51 A cross-sectional view is shown of an intermediate step in the formation of a package substrate structure 300 according to some embodiments. The package substrate structure 300 is similar to... Figure 13 The packaging substrate structure 70 differs in that the thickness of component 20 is less than the thickness of the first core substrate 50A. Some of the materials, techniques, and / or process steps used to form the packaging substrate structure 300 can be similar to those used to form the packaging substrate structure 70, and therefore some details will not be repeated below.

[0090] Figure 42 A first core substrate 50A is shown attached to a first carrier 10 according to some embodiments. The first core substrate 50A may be similar to those previously shown for... Figure 1 The first core substrate 50A is described and can be attached to the first carrier 10 via a release layer 11, etc. In some embodiments, a layer of wiring 52A can be formed on the bottom side of the first core substrate 50A (such as the side attached to the release layer 11). In other embodiments, wiring 52A can be formed in subsequent process steps. Wiring 52A can be similar to that previously described for... Figure 2 The wiring 52 is described and can be formed using similar techniques. In some embodiments, the first core substrate 50A may have a thickness T1 ranging from about 50 μm to about 1200 μm, but other thicknesses are also possible.

[0091] exist Figure 43 In some embodiments, a cavity 305 is formed in a first core substrate 50A. The cavity 305 can be formed using methods similar to those used for... Figure 3 Cavity 53 is formed using the techniques described herein. For example, cavity 305 can be formed using laser drilling processes, etc. In some embodiments, after cavity 305 is formed, a decontamination process or other cleaning process may be performed. Cavity 305 may extend completely through the first core substrate 50A, such as... Figure 43 As shown in the image.

[0092] exist Figure 44In some embodiments, component 20 is placed within cavity 305. Component 20 may be attached to the bottom surface of cavity 305 (e.g., the surface of release layer 11). In some embodiments, component 20 is attached using an adhesive (not shown separately). In some embodiments, the width of component 20 is less than the width of cavity 305, such that a gap surrounds component 20, and the sidewalls of component 20 are separated from the first core substrate 50A. In some embodiments, component 20 has a thickness T2 in the range of about 40 μm to about 600 μm, but other thicknesses are also possible. In some embodiments, the thickness T2 of component 20 is less than the thickness T1 of the first core substrate 50A, such that the top surface of the first core substrate 50A is located a distance D2 above the top surface of component 20. Distance D2 may be in the range of about 10 μm to about 1200 μm, but other distances are also possible.

[0093] exist Figure 45 In some embodiments, an insulating film 354 is formed above component 20 and in cavity 305. The insulating film 354 can be similar to that previously used for... Figure 5 The insulating film 54 is described. For example, in some embodiments, the insulating film 354 comprises ABF, but other materials are also possible. In some embodiments, the insulating film 354 fills the cavity 305 and may cover the surface of the release layer 11. In some embodiments, excess insulating film 354 may be removed from the top surface of the first core substrate 50A using a chemical mechanical polishing (CMP) process, a grinding process, or the like. In some embodiments, the top surfaces of the first core substrate 50A and the insulating film 354 may be approximately flush or coplanar. Therefore, the thickness of the insulating film 354 above the assembly 20 may be approximately equal to the distance D2.

[0094] exist Figure 46 In some embodiments, a second core substrate 50B is attached to a first core substrate 50A. The second core substrate 50B can be attached to the first core substrate 50A and the insulating film 354 using an adhesive layer 55, etc. The second core substrate 50B can be similar to the first core substrate 50A, except that the second core substrate 50B has a thickness T3 greater than the thickness T1 of the first core substrate 50A. In some embodiments, the first core substrate 50A attached to the second core substrate 50B forms a multi-stack core substrate 351. In some embodiments, the thickness T4 of the multi-stack core substrate 351 can be about 1200 μm or greater to maintain suitable rigidity and structural support. Therefore, the thickness T3 of the second core substrate 50B can be selected to appropriately correspond to the thickness T1 of the first core substrate 50A to provide a suitable thickness T4 for the multi-stack core substrate 351. In some embodiments, the second core substrate 50B can have a thickness T3 in the range of about 50 μm to about 1200 μm. Other thicknesses are also possible. Figure 46As shown, component 20 is surrounded by an insulating film 354 and is separated from the first core substrate 50A, the adhesive layer 55, and the second core substrate 50B by the insulating film 354. In other words, component 20 does not physically contact the multi-stack core substrate 351.

[0095] In some embodiments, after the first core substrate 50A is bonded to the second core substrate 50B, wiring 52B may be formed on the second core substrate 50B. Wiring 52B may be formed on the side of the second core substrate 50B opposite to the first core substrate 50A. In other embodiments, wiring 52B may be formed before attaching the second core substrate 50B, or may be formed in a subsequent process step. Wiring 52B may be similar to that previously used for... Figure 2 The described wiring 52 can be formed using similar techniques.

[0096] Figure 47 The structure after peeling and flipping from the first carrier 10 according to some embodiments is shown. In some embodiments, the adhesive used to attach the component 20 can be removed after peeling, which can expose the connection terminals of the component 20. In some embodiments, the surface of the insulating film 354 can protrude above the surface of the first core substrate 50A, such as... Figure 47 As shown in the diagram. In other embodiments, the surfaces of the insulating film 354 and the first core substrate 50A may be approximately flush or coplanar. In some embodiments, wirings 52A-52B may be formed after being peeled from the first carrier 10, rather than in an earlier process step as shown.

[0097] exist Figure 48 In some embodiments, an insulating film 54A is formed over a first core substrate 50A, and an insulating film 54B is formed over a second core substrate 50B. In some embodiments, insulating films 54A-54B may resemble insulating film 354. In some embodiments, after the insulating film 54A is formed, component 20 is completely surrounded and isolated by insulating films 354 and 54A. In some cases, the first core substrate 50A, component 20, insulating film 354, insulating film 54A, and wiring 52A can be considered as a first core structure 301, and the second core substrate 50B, insulating film 54B, and wiring 52B can be considered as a second core structure 302. Therefore, Figure 48 The structure includes a first core structure 301 bonded to the second core structure 302 via an adhesive layer 55.

[0098] exist Figure 49 In some embodiments, one or more through holes 56 are formed extending through the structure. The through holes 56 may be similar to those previously used for... Figure 9The aforementioned techniques can be used to form vias. For example, an opening extending through the structure can be formed, and a conductive material can then be deposited within the opening to form a via 56. The opening can then be filled with a dielectric material. In some cases, the via 56 can be physically and electrically connected to wirings 52A and / or 52B.

[0099] exist Figure 50 In some embodiments, wiring 60A is formed on and in the insulating film 54A, and wiring 61A is formed on the insulating film 54B. Wiring 60A and wiring 61A can be used similarly to those for... Figure 11 The wiring 60A describes those techniques used to form the wiring. Wiring 60A can be electrically connected to component 20 and electrically connected to via 56, and wiring 61A can be electrically connected to via 56.

[0100] exist Figure 51 In some embodiments, additional wirings 60B-60C are formed above wiring 60A to form a first wiring structure 64, and additional wirings 61B-61C are formed above wiring 61A to form a second wiring structure 66. The additional wirings 60B-60C of the first wiring structure 64 and the additional wirings 61B-61C of the second wiring structure 66 can be used with previously designed wiring structures. Figures 12 to 13 Similar materials and techniques described herein may be used to form the wiring structure. For example, the first wiring structure 64 may include multiple stacked layers 62A-62C, and the second wiring structure 66 may include multiple stacked layers 63A-63C. The stacked layers 62A-62C / 63A-63C may include materials similar to or different from insulating films 54A-54B. The first wiring structure 64 may include conductive pads 67, and the second wiring structure 66 may include conductive pads 68. The conductive pads 67 / 68 may use materials previously used for... Figure 13 The described materials or techniques are used to form the wiring structure. The wiring structure 64 / 66 may include an additional number of stacked layers and / or wiring in addition to those shown.

[0101] In this way, according to some embodiments, a package substrate structure 300 can be formed. Additional process steps can be implemented, such as packaging the components (e.g., Figures 14 to 15The package component 80 is attached to conductive pads or conductive connections are formed on the conductive pads. The techniques described herein allow for a smaller distance between component 20 and the package component 80 (not shown separately) attached thereto. Reducing this distance can reduce the voltage drop between component 20 and package component 80, which can improve the power integrity, efficiency, and performance of the package. As described herein, forming component 20 within a multi-stack core substrate 351 can also reduce package size, improve design flexibility, improve package functionality, improve package efficiency, and improve package performance. Furthermore, the multi-stack core substrate 351 described herein can be adapted to incorporate relatively thin components 20, such as components 20 having a thickness of about 50 μm or less (e.g., thickness T2). Other thicknesses are also possible.

[0102] Figures 52 to 59 A cross-sectional view is shown of an intermediate step in the formation of a package substrate structure 400 according to some embodiments. The package substrate structure 400 is similar to... Figure 51 The packaging substrate structure 300 differs in that it forms a cavity that extends completely through the multi-stacked core substrate. Some of the materials, techniques, and / or process steps used to form the packaging substrate structure 500 can be similar to those used to form the packaging substrate structure 300 and / or the packaging substrate structure 70, and therefore some details will not be repeated below.

[0103] Figure 52 A multi-stacked core substrate 451, including a first core substrate 50A attached to a second core substrate 50B, is shown according to some embodiments. The second core substrate 50B may be attached to the first core substrate 50A using an adhesive layer 55 or the like. In some embodiments, the first core substrate 50A may have a thickness T1 ranging from about 50 μm to about 650 μm, and the second core substrate 50B may have a thickness T3 ranging from about 50 μm to about 650 μm. Other thicknesses are also possible. In some embodiments, the thickness T4 of the multi-stacked core substrate 451 may be about 1200 μm or greater to maintain suitable rigidity and structural support. Thus, in some embodiments, the thicknesses T1 and T3 of the core substrates 50A-50B may be selected such that the thickness T4 is greater than about 1200 μm. Other thicknesses are also possible. In some embodiments, wirings 52A-52B may be formed on the core substrates 50A-50B. Wiring 52A may be formed on the first core substrate 50A, and wiring 52B may be formed on the second core substrate 50B. In other embodiments, wirings 52A-52B may be formed prior to the attachment core substrates 50A-50B. Wirings 52A-52B may be similar to those previously used for... Figure 2 The described wiring 52 can be formed using similar techniques. Figure 52A multi-stacked core substrate 451 is shown attached to a first carrier 10 via a release layer 11, such that a second core substrate 50B is adjacent to the first carrier 10.

[0104] exist Figure 53 In some embodiments, a cavity 405 is formed in a multi-stacked core substrate 451. The cavity 405 can be formed using methods similar to those used for... Figure 3 Cavity 53 is formed using the techniques described herein. For example, cavity 405 can be formed using laser drilling, mechanical drilling, etc. In some embodiments, a decontamination process or other cleaning process may be performed after cavity 405 is formed. Cavity 405 may extend completely through the multi-stacked core substrate 451, such as... Figure 53 As shown in the image.

[0105] exist Figure 54 In some embodiments, component 20 is placed within cavity 405. Component 20 may be attached to the bottom surface of cavity 405 (e.g., the surface of release layer 11). In some embodiments, component 20 is attached using an adhesive (not shown separately). In some embodiments, the width of component 20 is less than the width of cavity 405, such that a gap surrounds component 20, and the sidewalls of component 20 are separated from the multi-stacked core substrate 451. In some embodiments, component 20 has a thickness T2 in the range of about 50 μm to about 1200 μm, but other thicknesses are also possible. For example, in some embodiments, component 20 may be a relatively thick stacked device, system on integrated circuit (SoIC), etc., comprising two or more dies bonded together (e.g., using direct bonding, hybrid bonding, fusion bonding, conductive interconnects, etc.). In some embodiments, the thickness T2 of component 20 may be greater than, less than, or approximately equal to the thickness T3 of the second core substrate 50B. Therefore, the distance D3 between the top surface of the first core substrate 50A and the top surface of the component 20 can be greater than, less than, or approximately equal to the thickness T1 of the first core substrate 50A. The distance D3 can be in the range of approximately 10 μm to approximately 1200 μm, but other distances are also possible.

[0106] exist Figure 55 An insulating film 454A is formed above the multi-stacked core substrate 451, above the assembly 20, and within the cavity 405. The insulating film 454A can be similar to that previously used for… Figure 5 The insulating film 54 is described. For example, in some embodiments, the insulating film 454A comprises ABF, but other materials are also possible. The insulating film 454A fills the cavity 405 and covers the assembly 20. In some embodiments, the insulating film 454A may cover the surface of the first core substrate 50A, the release layer 11, the sidewalls of the assembly 20, and the sidewalls of the multi-stack core substrate 451. In this way, the assembly 20 can be separated from the multi-stack core substrate 451 by the insulating film 454A.

[0107] exist Figure 56 In some embodiments, the multi-stacked core substrate 451 is peeled and flipped from the first carrier 10, and an insulating film 454B is formed over the second core substrate 50B. In some embodiments, the insulating film 454B may be similar to the insulating film 454A. In some embodiments, after the insulating film 454B is formed, the assembly 20 is completely surrounded and isolated by the insulating films 454A-54B. In some embodiments, the surface of the insulating film 454A may protrude above the surface of the second core substrate 50B, such as... Figure 56 As shown in the diagram. In other embodiments, the surfaces of the insulating film 454A and the second core substrate 50B may be approximately flush or coplanar.

[0108] exist Figure 57 In some embodiments, one or more through holes 56 are formed extending through the structure. The through holes 56 may be similar to those previously used for... Figure 9 The aforementioned techniques can be used to form vias. For example, an opening extending through the structure can be formed, and a conductive material can then be deposited within the opening to form a via 56. The opening can then be filled with a dielectric material. In some cases, the via 56 can be physically and electrically connected to wirings 52A and / or 52B.

[0109] exist Figure 58 In some embodiments, wiring 60A is formed on insulating film 454A, and wiring 61A is formed on insulating film 454B. Wiring 60A and wiring 61A can be used similarly to those for... Figure 11 The wiring 60A describes those techniques used to form the wiring. Wiring 61A can be electrically connected to component 20 and electrically connected to via 56, and wiring 60A can be electrically connected to via 56.

[0110] exist Figure 59 In some embodiments, additional wirings 60B-60C are formed above wiring 60A to form a first wiring structure 64, and additional wirings 61B-61C are formed above wiring 61A to form a second wiring structure 66. The additional wirings 60B-60C of the first wiring structure 64 and the additional wirings 61B-61C of the second wiring structure 66 can be used with previously designed wiring structures. Figures 12 to 13 Similar materials and techniques described herein may be used to form the wiring structure. For example, the first wiring structure 64 may include multiple stacked layers 62A-62C, and the second wiring structure 66 may include multiple stacked layers 63A-63C. The stacked layers 62A-62C / 63A-63C may include materials similar to or different from insulating films 454A-54B. The first wiring structure 64 may include conductive pads 67, and the second wiring structure 66 may include conductive pads 68. The conductive pads 67 / 68 may use materials previously used for... Figure 13 The described materials or techniques are used to form the wiring structure. The wiring structure 64 / 66 may include an additional number of stacked layers and / or wiring in addition to those shown.

[0111] In this way, according to some embodiments, a package substrate structure 400 can be formed. Additional process steps can be implemented, such as packaging the components (e.g., ... Figures 14 to 15 The package component 80 is attached to conductive pads or conductive connections are formed on the conductive pads. The techniques described herein allow for a smaller distance between component 20 and the package component 80 (not shown separately) attached thereto. Reducing this distance can reduce the voltage drop between component 20 and package component 80, which can improve the power integrity, efficiency, and performance of the package. As described herein, forming component 20 within a multi-stack core substrate 451 can also reduce package size, improve design flexibility, improve package functionality, improve package efficiency, and improve package performance. Furthermore, the multi-stack core substrate 451 as described herein can be adapted to incorporate relatively thin or relatively thick components 20, such as components 20 having a thickness of less than about 50 μm or greater than about 600 μm (e.g., thickness T2). Other thicknesses are also possible.

[0112] Figures 60 to 67 A cross-sectional view is shown of an intermediate step in the formation of a package substrate structure 500 according to some embodiments. The package substrate structure 500 is similar to the previously described package substrate structures, except that the package substrate structure 500 is formed by separately forming wiring structures and then bonding them to a core structure. In some embodiments, the wiring structures and the core structure may each include one or more components (e.g., active or passive devices). Some of the materials, techniques, and / or process steps used to form the package substrate structure 500 may be similar to those used to form other package substrate structures described herein, and therefore some details will not be repeated below.

[0113] Figures 60 to 64 Intermediate steps in the formation of a first wiring structure 510 according to some embodiments are shown. Figure 60 In some embodiments, multiple layers of wirings 512A-512D are formed over a first carrier 10. In some embodiments, a release layer 11 is also present on the first carrier 10. Wirings 512A-512D can be formed using techniques similar to those described for forming wiring structure 256, such as those for... Figures 28 to 30The described methods are as follows. For example, wiring 512A can be formed over release layer 11 using techniques similar to those used to form wiring 252A. An insulating film 514A, which may be similar to insulating film 254A, can be formed over wiring 512A and release layer 11. In some embodiments, insulating film 514A comprises ABF, but other materials, such as a build-up layer, are also possible. Openings can be formed in insulating film 514A using laser drilling processes, and then a conductive material can be deposited on and in insulating film 514A using a patterned mask. Similar steps can be repeated to form multiple layers of wiring 512A-512D on and in multiple layers of insulating films 514A-514C. In other embodiments, another number of insulating film and / or wiring layers can be formed. In other embodiments, wiring layers can be formed on and in a build-up layer, similar to... Figure 13 The formation of the wiring structure 66.

[0114] exist Figure 61 In some embodiments, cavities 515 are formed in insulating films 514A-514C. Cavities 515 may extend completely through insulating films 514A-514C. Cavities 515 may expose the surface of release layer 11. Cavities 515 may be formed using laser drilling or another suitable technique. In some cases, cleaning processes such as decontamination processes may be performed after the formation of cavities 515.

[0115] exist Figure 62 In some embodiments, component 20A is placed within cavity 515. Component 20A may be similar to component 20 previously described and may be attached to the bottom surface of cavity 515 (e.g., the surface of release layer 11). In some embodiments, component 20A is attached using an adhesive (not shown separately). In some embodiments, the width of component 20A is less than the width of cavity 515, such that a gap surrounds component 20A. In some embodiments, the thickness of component 20A is approximately the same as the depth of cavity 515, but other thicknesses are also possible. In other embodiments, multiple components 20A may be used.

[0116] exist Figure 63 An insulating film 514D is formed over the insulating film 514C, over the component 20A, and within the cavity 515. The material of the insulating film 514D can be similar to or different from the insulating films 514A-514C. For example, in some embodiments, the insulating film 514D comprises ABF, but other materials are also possible. The insulating film 514D fills the cavity 515 and covers the component 20A. Therefore, the insulating film 514D can cover the surface of the release layer 11 and the sidewalls of the component 20A. Furthermore, in... Figure 63In some embodiments, a layer for forming wiring 518 is formed on and within the insulating film 514D. Wiring 518 can be formed using methods similar to those previously used for forming... Figure 34 The wiring 60A is formed using the materials and techniques described herein. Wiring 518 may be electrically connected to component 20A and / or wiring 512D.

[0117] exist Figure 64 In some embodiments, conductive pads 519 are formed over an insulating film 514D to form a first wiring structure 510. The conductive pads 519 can be used similarly to those used for forming... Figure 13 The conductive pad 67 is formed using techniques described above. For example, a build-up layer 517 can be formed over the insulating film 514D and the wiring 518. Openings can be formed in the build-up layer 517 using processes such as laser drilling, and conductive material can then be deposited on and in the build-up layer 517 using a patterned mask. In other embodiments, additional layers of the build-up layer and / or wiring can be formed. In other embodiments, conductive pads 519 can be formed on and in the insulating film, similar to... Figure 13 The wiring structure 66 is formed. Although the first wiring structure 510 is shown as four layers with insulating films 514A-514D and an accumulation layer 517, all these layers may be made of the same material (e.g., ABF, accumulation material, etc.) or may be arranged differently of the individual layers with different materials.

[0118] Figure 65 A core structure 520 according to some embodiments is shown. The core structure 520 is similar to... Figure 12 The structure shown can be formed using similar techniques. For example, core structure 520 may include a multi-stacked core substrate 51 formed from a first core substrate 50A bonded to a second core substrate 50B. It should be noted that... Figure 65 The core structure 520 shown is an example, and the core structure 520 may be similar to other core structures, other multi-stacked core substrates, or other packaging substrate structures described herein. In some embodiments, the multi-stacked core substrate 51 has a thickness of about 1200 μm or greater, but other thicknesses are also possible. For reference, the side of the core structure 520 above the first core substrate 50A (e.g., Figure 65 The side facing upwards (the middle side) can be referred to as the "top side", and the side of the core structure 520 above the second core substrate 50B (e.g., Figure 65The side facing downwards can be referred to as the "bottom side". A cavity can be formed in the first core substrate 50A, and the component 20B is disposed within the cavity. An insulating film 54 covers the first core substrate 50A and the component 20A, and also fills the cavity. Wiring 60A-60B is formed above the first core substrate 50A, wherein a build-up layer 62A is located between wiring 60A and wiring 60B. Wiring 61A-61B is formed above the second core substrate 50B, wherein a build-up layer 63A is located between wiring 61A and wiring 61B. In other embodiments, additional build-up layers and wiring layers can be structurally formed. In some cases, wiring 60A-60B with build-up layer 62A can be considered as a wiring structure, and wiring 61A-61B with build-up layer 63A can be considered as a wiring structure.

[0119] exist Figure 66 In some embodiments, a first bonding film 502A is formed above the top side of the core structure 520, and a second bonding film 502B is formed above the bottom side of the core structure 520. In embodiments, bonding films 502A-502B can be pre-impregnated composite fiber (prepreg) material, polymer resin film, epoxy resin film, adhesive film, dielectric material, etc. In some embodiments, bonding films 502A-502B can be applied to the core structure 520 using processes such as spin coating, dip coating, air knife coating, curtain coating, wire rod coating, gravure coating, lamination, extrusion coating, and combinations thereof. In embodiments, bonding films 502A-502B can be applied in liquid or semi-liquid form and then subsequently cured or partially cured. However, any suitable material and forming method can be used.

[0120] In some embodiments, a via region 504A extending through a first bonding film 502A is formed, and a via region 504B extending through a second bonding film 502B is formed. The via region 504A is a conductive region physically and electrically connected to wiring 60B, and the via region 504B is a conductive region physically and electrically connected to wiring 61B. The via region 504A may be formed, for example, by forming an opening in the first bonding film 502A and then depositing a conductive material in the opening. The via region 504B may be formed, for example, by forming an opening in the second bonding film 502B and then depositing a conductive material in the opening. In some cases, the conductive materials for the via regions 504A and 504B may be deposited simultaneously. In other embodiments, the via regions 504A-504B may be formed on the core structure 520 prior to the formation of the bonding films 502A-502B. In some embodiments, the top surfaces of the through-hole region 504A and the first bonding film 502A are substantially coplanar or flush, and the top surfaces of the through-hole region 504B and the second bonding film 502B are substantially coplanar or flush.

[0121] exist Figure 67 In some embodiments, a first wiring structure 510 is attached to a core structure 520 via a first bonding film 502A, and a second wiring structure 530 is attached to the core structure 520 via a second bonding film 502B. In this way, according to some embodiments, a package substrate structure 500 can be formed. The second wiring structure 530 can be similar to the first wiring structure 510 and can be formed using similar materials or techniques. For example, the second wiring structure 530 may include components 20C within various wiring layers. In some cases, the first wiring structure 510 and the second wiring structure 530 may have different numbers of wiring layers. The first wiring structure 510 is electrically connected to the core structure 520 via a via region 504A, and the second wiring structure 530 is electrically connected to the core structure 520 via a via region 504B.

[0122] A first wiring structure 510 may be placed on a first bonding film 502A, wherein wiring 512A contacts via region 504A. In some embodiments, an adhesive layer (not shown separately) may be formed between the first bonding film 502A and the first wiring structure 510 to facilitate attachment. Similarly, a second wiring structure 530 may be placed on a second bonding film 502B. An adhesive layer (not shown) may be present between the second bonding film 502B and the second wiring structure 530. The bonding films 502A-502B may then be cured to harden the material of the bonding films 502A-502B. In some embodiments, the structure may also be pressed to facilitate attachment of wiring structures 510 / 530 to the core structure 520. This is an example; other attachment techniques are also possible. In other embodiments, additional core structures and / or wiring structures may be attached using bonding films. In other embodiments, only one of the first wiring structure 510 or the second wiring structure 530 is present.

[0123] In this way, according to some embodiments, a package substrate structure 500 can be formed. Additional process steps can be implemented, such as packaging the components (e.g., Figures 14 to 15 The package component 80 is attached to conductive pads or conductive connections are formed on the conductive pads. The techniques described herein allow for smaller distances between components and external structures such as package component 80. Furthermore, the techniques described herein allow for the formation of package substrate structures comprising multiple components, which can reduce package size, improve design flexibility, improve package functionality, improve package efficiency, and improve package performance.

[0124] Other components and processes may also be included. For example, test structures may be included to aid in the verification testing of 3D packaged or 3DIC devices. Test structures may include, for example, test pads formed in the redistribution layer or on the substrate, which allow testing of the 3D package or 3DIC using probes and / or probe cards, etc. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0125] The embodiments can achieve advantages. The techniques described herein allow for the formation of a package substrate incorporating one or more components (e.g., active or passive devices) while also allowing the package substrate to have sufficient rigidity and thickness. Some of the package substrates described herein include core substrates attached together to form a single multi-stacked core substrate. In some embodiments, there are no metal components, conductive wiring, ground planes, power planes, etc., between the attached core substrates. In this way, the multi-stacked core substrates described herein can embed thin components and efficiently form electrical connections to the components. The multi-stacked core substrates described herein can reduce package warpage. The package substrate structures described herein can be incorporated into a variety of packages, such as integrated fan-out (InFO) packages, chip-on-wafer (CoWoS) packages, or other suitable packages. In some cases, the techniques described herein can allow for reduced cost, reduced package size, improved design flexibility, improved package stability, and improved power integrity.

[0126] In some embodiments, the structure includes: a first core substrate; an adhesive layer located on the first core substrate; a second core substrate located on the adhesive layer, wherein the second core substrate includes a first cavity; a first semiconductor device located within the first cavity; a first insulating film extending over the second core substrate, over the top surface of the first semiconductor device, and within the first cavity; a via extending through the first insulating film, the first core substrate, and the second core substrate; a first wiring structure located on the first core substrate and electrically connected to the via; and a second wiring structure located on the first insulating film and electrically connected to the via and the first semiconductor device. In another embodiment, the structure includes: a second cavity located within the first core substrate; a second semiconductor device located within the second cavity; and a second insulating film extending over the first core substrate, over the second semiconductor device, and within the second cavity. In another embodiment, the thickness of the first semiconductor device is greater than the thickness of the second core substrate. In another embodiment, the thickness of the first core substrate is different from the thickness of the second core substrate. In another embodiment, the first insulating film covers the bottom surface of the first semiconductor device. In another embodiment, the structure includes a packaging assembly bonded to the second wiring structure. In another embodiment, the first insulating film physically contacts the adhesive layer. In one embodiment, the first semiconductor device is separated from the second core substrate by a first insulating film.

[0127] In some embodiments, the package includes: a multi-stacked core substrate, including a first core substrate bonded to a second core substrate via an adhesive layer; a first insulating layer located within and laterally surrounded by the first core substrate; a first component located within and laterally surrounded by the first insulating layer; and a via extending through the multi-stacked core substrate. In an embodiment, the first component is completely separated from the multi-stacked core substrate by the first insulating layer. In an embodiment, the top surface of the first core substrate does not have the first insulating layer. In an embodiment, the first insulating layer is located within and laterally surrounded by the second core substrate. In an embodiment, the total thickness of the multi-stacked core substrate is at least 1200 μm. In an embodiment, the package includes a second insulating layer located above the top surface of the first core substrate, the first insulating layer, and the first component. In an embodiment, the insulating layer includes an Ajinomoto polymer film (ABF). In an embodiment, the thickness of the first component is less than the thickness of the first core substrate.

[0128] In some embodiments, the method includes: forming a cavity extending through a first core substrate; placing a die within the cavity, wherein the die is separated from the first core substrate; forming an insulating film over the first core substrate and the die, wherein the insulating film fills the cavity; forming a first adhesive material on the first core substrate and the die; bonding a second core substrate to the first adhesive material; forming a through-hole extending through the insulating film, the first core substrate, the first adhesive material, and the second core substrate; forming a first wiring layer on the insulating film and the die; and forming a second wiring layer on the second core substrate. In an embodiment, the method includes: forming a second adhesive material on the first wiring layer; and bonding a first wiring structure to the second adhesive material. In an embodiment, the second adhesive material comprises a pre-impregnated composite fiber (prepreg) material layer. In an embodiment, the method includes: forming a third adhesive material on the second wiring layer; and bonding a second wiring structure to the third adhesive material.

[0129] Some embodiments of this application provide a semiconductor structure including: a first core substrate; an adhesive layer located on the first core substrate; a second core substrate located on the adhesive layer, wherein the second core substrate includes a first cavity; a first semiconductor device located within the first cavity; a first insulating film extending above the second core substrate, above the top surface of the first semiconductor device, and within the first cavity; a via extending through the first insulating film, the first core substrate, and the second core substrate; a first wiring structure located on the first core substrate and electrically connected to the via; and a second wiring structure located on the first insulating film and electrically connected to the via and the first semiconductor device.

[0130] In some embodiments, the semiconductor structure further includes: a second cavity located within the first core substrate; a second semiconductor device located within the second cavity; and a second insulating film extending over the first core substrate, over the second semiconductor device, and within the second cavity. In some embodiments, the thickness of the first semiconductor device is greater than the thickness of the second core substrate. In some embodiments, the thickness of the first core substrate is different from the thickness of the second core substrate. In some embodiments, the first insulating film covers the bottom surface of the first semiconductor device. In some embodiments, the semiconductor structure further includes a packaging assembly bonded to the second wiring structure. In some embodiments, the first insulating film physically contacts the adhesive layer. In some embodiments, the first semiconductor device is separated from the second core substrate by the first insulating film.

[0131] Other embodiments of this application provide a package comprising: a multi-stacked core substrate including a first core substrate bonded to a second core substrate via an adhesive layer; a first insulating film layer located within and laterally surrounded by the first core substrate; a first component located within and laterally surrounded by the first insulating film layer; and a via extending through the multi-stacked core substrate.

[0132] In some embodiments, the first component is completely separated from the multi-stacked core substrate by the first insulating film layer. In some embodiments, the top surface of the first core substrate does not have the first insulating film layer. In some embodiments, the first insulating film layer is located within and laterally surrounded by the second core substrate. In some embodiments, the total thickness of the multi-stacked core substrate is at least 1200 μm. In some embodiments, the package further includes a second insulating film layer located above the first core substrate, the first insulating film layer, and the top surface of the first component. In some embodiments, the insulating film comprises an Ajinomoto polymer film (ABF). In some embodiments, the thickness of the first component is less than the thickness of the first core substrate.

[0133] Further embodiments of this application provide a method for forming a semiconductor structure, comprising: forming a cavity extending through a first core substrate; placing a die within the cavity, wherein the die is separated from the first core substrate; forming an insulating film over the first core substrate and the die, wherein the insulating film fills the cavity; forming a first adhesive material on the first core substrate and the die; bonding a second core substrate to the first adhesive material; forming a through-hole extending through the insulating film, the first core substrate, the first adhesive material, and the second core substrate; forming a first wiring layer on the insulating film and the die; and forming a second wiring layer on the second core substrate.

[0134] In some embodiments, the method further includes: forming a second adhesive material on the first wiring layer; and bonding a first wiring structure to the second adhesive material. In some embodiments, the second adhesive material comprises a pre-impregnated composite fiber (prepreg) material layer. In some embodiments, the method further includes: forming a third adhesive material on the second wiring layer; and bonding a second wiring structure to the third adhesive material.

[0135] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A semiconductor structure, comprising: First core substrate; An adhesive layer is located on the first core substrate; A second core substrate is located on the adhesive layer, wherein the second core substrate includes a first cavity; A first semiconductor device is located within the first cavity; A first insulating film extends above the second core substrate, above the top surface of the first semiconductor device, and within the first cavity; A through-hole extends through the first insulating film, the first core substrate, and the second core substrate; A first wiring structure is located on the first core substrate and electrically connected to the via; and The second wiring structure is located on the first insulating film and is electrically connected to the through hole and the first semiconductor device.

2. The semiconductor structure according to claim 1, further comprising: The second cavity is located within the first core substrate; A second semiconductor device is located within the second cavity; as well as The second insulating film extends above the first core substrate, above the second semiconductor device, and within the second cavity.

3. The semiconductor structure according to claim 1, wherein, The thickness of the first semiconductor device is greater than the thickness of the second core substrate.

4. The semiconductor structure according to claim 1, wherein, The thickness of the first core substrate is different from the thickness of the second core substrate.

5. The semiconductor structure according to claim 1, wherein, The first insulating film covers the bottom surface of the first semiconductor device.

6. The semiconductor structure of claim 1, further comprising a packaging component bonded to the second wiring structure.

7. The semiconductor structure according to claim 1, wherein, The first insulating film is in physical contact with the adhesive layer.

8. The semiconductor structure according to claim 1, wherein, The first semiconductor device is separated from the second core substrate by the first insulating film.

9. A package comprising: A multi-stacked core substrate, including a first core substrate bonded to a second core substrate via an adhesive layer; A first insulating film layer is located within the first core substrate and is laterally surrounded by the first core substrate; A first component is located within the first insulating film layer and is laterally surrounded by the first insulating film layer; as well as Through-holes extend through the multi-stacked core substrate.

10. A method for forming a semiconductor structure, comprising: Forming a cavity that extends through the first core substrate; The die is placed inside the cavity, wherein the die is separated from the first core substrate; An insulating film is formed above the first core substrate and the die, wherein the insulating film fills the cavity; A first adhesive material is formed on the first core substrate and the die; The second core substrate is bonded to the first adhesive material; Forming through-holes extending through the insulating film, the first core substrate, the first adhesive material, and the second core substrate; A first wiring layer is formed on the insulating film and the die; and A second wiring layer is formed on the second core substrate.

Images