Control method and device of switching power supply system and switching power supply system

Abstract

The invention discloses a control method and device of a switching power supply system and the switching power supply system, and belongs to the field of switching power supplies. The control method of the switching power supply system comprises the following steps: acquiring a drain terminal voltage of a synchronous rectifier tube and an output voltage corresponding to the switching power supply system; controlling the secondary side synchronous rectification chip to enter a sleep mode under the condition that the drain terminal voltage is determined not to send waves based on the magnitude relationship between the drain terminal voltage and the output voltage and the duration of the non-sending of the waves of the drain terminal voltage is greater than a first duration threshold value; in the sleep mode, under the condition that it is determined that wave transmission of the drain terminal voltage is carried out again based on the magnitude relation between the drain terminal voltage and the output voltage, the driving control circuit is controlled to be started, so that a synchronous rectification control signal corresponding to the driving control circuit is obtained; and under the condition that the pulse number corresponding to the synchronous rectification control signal is greater than or equal to a first number threshold value or the continuous wave sending time length of the synchronous rectification control signal is greater than a second time length threshold value, controlling the secondary side synchronous rectification chip to exit the sleep mode.

Description

Technical Field

[0001] This application belongs to the field of switching power supply technology, and in particular relates to a control method, device and switching power supply system for a switching power supply system. Background Technology

[0002] For switching converters, conversion efficiency is a crucial performance indicator, related to input voltage, output voltage, load conditions, and the parameters of the power transistor itself. Synchronous rectification technology improves power efficiency by replacing traditional diodes with low on-resistance MOSFETs, reducing conduction losses. However, under light loads, the power savings from synchronous rectification are minimal, sometimes even lower than the power consumed by the chip itself. Therefore, to optimize power conversion efficiency in such cases, some technologies compare the drive voltage DRV of the synchronous rectifier (SR) with reference voltage 1 to determine whether to enter sleep mode, and compare the drain-source voltage VDS of the SR with reference voltage 2 to determine whether to exit sleep mode. However, this method can lead to the chip incorrectly entering sleep mode, forcing the SR to rely on its body diode for freewheeling, increasing its conduction losses and reducing the overall power system efficiency. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the related art. To this end, this application proposes a control method, apparatus, and switching power supply system for a switching power supply system, which reduces the conduction loss of the synchronous rectifier, improves the conversion efficiency of the switching power supply system under light load, and enhances the stability and reliability of chip operation.

[0004] In a first aspect, this application provides a control method for a switching power supply system, the switching power supply system including a secondary-side synchronous rectifier chip and a synchronous rectifier diode connected in series; the method includes:

[0005] Obtain the drain voltage of the synchronous rectifier and the corresponding output voltage of the switching power supply system;

[0006] Based on the relationship between the drain voltage and the output voltage, if it is determined that the drain voltage does not ripple and the duration of the drain voltage not ripple is greater than a first duration threshold, the secondary-side synchronous rectifier chip is controlled to enter a sleep mode; in the sleep mode, the drive control circuit in the secondary-side synchronous rectifier chip is in a closed state, and the drive control circuit is used to drive the synchronous rectifier tube;

[0007] In the sleep mode, if it is determined that the drain voltage will be re-transmitted based on the relationship between the drain voltage and the output voltage, the drive control circuit is turned on to obtain the synchronous rectification control signal corresponding to the drive control circuit.

[0008] If the number of pulses corresponding to the synchronous rectification control signal is greater than or equal to a first quantity threshold, or if the continuous transmission duration of the synchronous rectification control signal is greater than a second duration threshold, the secondary synchronous rectification chip is controlled to exit the sleep mode.

[0009] According to the control method of the switching power supply system provided in the embodiments of this application, by monitoring the ripple of the drain voltage, it is determined whether the primary-side control circuit has entered a light load state. Then, based on the state of the primary-side control circuit, it is determined whether the secondary-side synchronous rectifier chip enters or exits the sleep mode. When it is determined that the primary-side control circuit has entered a light load state, the secondary-side synchronous rectifier chip is controlled to enter the sleep mode, which reduces the conduction loss of the synchronous rectifier tube, improves the conversion efficiency of the switching power supply system under light load, and enhances the stability and reliability of the chip operation.

[0010] A control method for a switching power supply system according to an embodiment of this application, wherein when the number of pulses corresponding to the synchronous rectification control signal is greater than or equal to a first quantity threshold, or the continuous emission duration of the synchronous rectification control signal is greater than a second duration threshold, the method controls the secondary-side synchronous rectification chip to exit the sleep mode, including:

[0011] When the drain voltage is greater than or less than the output voltage, the start time of the first pulse of the synchronous rectification control signal is obtained;

[0012] If, at the start time of the first pulse of the synchronous rectification control signal, the continuous transmission duration of the synchronous rectification control signal is detected to be greater than the second duration threshold, or the number of pulses of the synchronous rectification control signal is detected to be greater than or equal to the first quantity threshold, the secondary-side synchronous rectification chip is controlled to exit the sleep mode.

[0013] A control method for a switching power supply system according to an embodiment of this application, wherein determining that the drain voltage does not ripple based on the magnitude relationship between the drain voltage and the output voltage includes:

[0014] Obtain the margin voltage, and derive the first voltage based on the margin voltage and the output voltage;

[0015] If the drain voltage is greater than or less than the first voltage, it is determined that the drain voltage does not generate a wave.

[0016] One embodiment of the control method for a switching power supply system of this application includes a secondary-side synchronous rectifier chip comprising a ZVS module; the method further includes:

[0017] When the secondary-side synchronous rectifier chip is controlled to enter sleep mode, the minimum turn-on time corresponding to the synchronous rectifier tube is reduced, and the ZVS module is controlled to turn off; the ZVS module is used to control the synchronous rectifier tube to turn on and off in a zero-voltage conduction mode, and the minimum turn-on time is used to characterize the shortest duration for which the synchronous rectifier tube is turned on in one conduction cycle under synchronous rectification conduction mode;

[0018] When the secondary-side synchronous rectifier chip exits the sleep mode, the minimum turn-on time corresponding to the synchronous rectifier tube is increased, and the ZVS module is turned on.

[0019] Secondly, this application provides a switching power supply system based on the control method of the switching power supply system as described in the first aspect, comprising:

[0020] Synchronous rectifier tube;

[0021] A secondary-side synchronous rectifier chip includes: a sleep mode control circuit and a drive control circuit, wherein the drive control circuit includes: a drive function module and a drive circuit;

[0022] The input terminal of the sleep mode control circuit is connected to the drain terminal of the synchronous rectifier and the output terminal of the drive function module, respectively. The output terminal of the sleep mode control circuit is connected to the drive function module and the drive circuit, respectively. The input terminal of the drive circuit is connected to the output terminal of the drive function module. The sleep mode control circuit is used to output a first sleep control signal and a second sleep control signal. The drive function module is used to output a synchronous rectification control signal. When the first sleep control signal is high, the drive control circuit is in a closed state. When the first sleep control signal is low, the drive control circuit is in a closed state. When the second sleep control signal changes from low to high, the secondary-side synchronous rectifier chip enters sleep mode. When the second sleep control signal changes from high to low, the secondary-side synchronous rectifier chip exits sleep mode.

[0023] According to the switching power supply system provided in the embodiments of this application, by monitoring the ripple of the drain voltage, it is determined whether the primary-side control circuit has entered a light load state. Then, based on the state of the primary-side control circuit, it is determined whether the secondary-side synchronous rectifier chip enters or exits the sleep mode. When it is determined that the primary-side control circuit has entered a light load state, the secondary-side synchronous rectifier chip is controlled to enter the sleep mode, which reduces the conduction loss of the synchronous rectifier tube, improves the conversion efficiency of the switching power supply system under light load, and enhances the stability and reliability of the chip operation.

[0024] One embodiment of the switching power supply system of this application includes a sleep mode control circuit comprising:

[0025] A ringing detection circuit, wherein the input terminal of the ringing detection circuit is connected to the drain terminal of the synchronous rectifier tube;

[0026] A sleep mode trigger circuit, wherein the input terminal of the sleep mode trigger circuit is connected to the output terminal of the ringing detection circuit;

[0027] A sleep mode wake-up circuit, wherein the input terminal of the sleep mode wake-up circuit is connected to the output terminal of the ringing detection circuit;

[0028] A control logic circuit, wherein the input terminals of the control logic circuit are respectively connected to the output terminals of the sleep mode trigger circuit and the sleep mode wake-up circuit.

[0029] One embodiment of the switching power supply system of this application includes a sleep mode triggering circuit comprising:

[0030] An edge detection circuit, wherein the input terminal of the edge detection circuit is connected to the output terminal of the ringing detection circuit;

[0031] A first switch is connected to the output terminal of the edge detection circuit.

[0032] A first current source is connected to the first switch;

[0033] The first capacitor is connected in parallel with the first switch and in series with the first current source, and the end of the first capacitor away from the first current source is grounded.

[0034] The second comparator has one input connected between the first current source and the first capacitor to receive the capacitor voltage corresponding to the first capacitor. The other input of the second comparator is used to receive a reference voltage. The output of the second comparator is connected to the input of the control logic circuit.

[0035] One embodiment of the switching power supply system of this application includes a sleep mode wake-up circuit comprising:

[0036] A counting circuit, wherein one input terminal of the counting circuit is used to receive a synchronous rectification control signal, and the other input terminal of the counting circuit is used to receive the first sleep control signal;

[0037] The AND circuit has its input terminal connected to the output terminal of the counting circuit, and its output terminal connected to the input terminal of the control logic circuit.

[0038] One embodiment of the switching power supply system of this application includes a control logic circuit comprising:

[0039] The first trigger has its set terminal connected to the output terminal of the sleep mode trigger circuit, its reset terminal connected to the sleep mode trigger circuit, and its output terminal used to output the first sleep control signal.

[0040] The second trigger has its set terminal connected to the output terminal of the sleep mode trigger circuit, and its reset terminal connected to the output terminal of the sleep mode wake-up circuit. The output terminal of the second trigger is used to output a second sleep control signal.

[0041] Thirdly, this application provides a control device for a switching power supply system, the switching power supply system including a secondary-side synchronous rectifier chip and a synchronous rectifier diode connected in series; the device includes:

[0042] The first processing module is used to obtain the drain voltage of the synchronous rectifier and the corresponding output voltage of the switching power supply system;

[0043] The second processing module is used to control the secondary-side synchronous rectifier chip to enter a sleep mode when, based on the relationship between the drain voltage and the output voltage, it is determined that the drain voltage does not ripple and the duration of the drain voltage not ripple is greater than a first duration threshold. In the sleep mode, the drive control circuit in the secondary-side synchronous rectifier chip is in a closed state, and the drive control circuit is used to drive the synchronous rectifier tube.

[0044] The third processing module is used to control the drive control circuit to turn on in the sleep mode, based on the magnitude relationship between the drain voltage and the output voltage, when it is determined that the drain voltage is re-transmitted, so as to obtain the synchronous rectification control signal corresponding to the drive control circuit.

[0045] The fourth processing module is used to control the secondary-side synchronous rectification chip to exit the sleep mode when the number of pulses corresponding to the synchronous rectification control signal is greater than or equal to a first quantity threshold, or when the continuous transmission duration of the synchronous rectification control signal is greater than a second duration threshold.

[0046] According to the control device of the switching power supply system provided in the embodiments of this application, by monitoring the ripple of the drain voltage, it determines whether the primary-side control circuit has entered a light load state, and then determines whether the secondary-side synchronous rectifier chip enters or exits the sleep mode based on the state of the primary-side control circuit. When it is determined that the primary-side control circuit has entered a light load state, the secondary-side synchronous rectifier chip is controlled to enter the sleep mode, which reduces the conduction loss of the synchronous rectifier tube, improves the conversion efficiency of the switching power supply system under light load, and enhances the stability and reliability of the chip operation.

[0047] Fourthly, this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the control method of the switching power supply system as described in the first aspect above.

[0048] Fifthly, this application provides a chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the control method of the switching power supply system as described in the first aspect.

[0049] The above-described one or more technical solutions in the embodiments of this application have at least one of the following technical effects:

[0050] By monitoring the voltage fluctuations at the drain terminal, it is determined whether the primary-side control circuit has entered a light-load state. Based on this, the secondary-side synchronous rectifier chip is then controlled to enter or exit sleep mode. When a light-load state is confirmed for the primary-side control circuit, the secondary-side synchronous rectifier chip is controlled to enter sleep mode. This reduces the conduction losses of the synchronous rectifier diodes, improves the conversion efficiency of the switching power supply system under light load, and enhances the stability and reliability of the chip operation. Furthermore,

[0051] Furthermore, by controlling the secondary side to exit sleep mode based on the continuous ripple duration or number of pulses of the synchronous rectification control signal when the drain voltage is determined to be re-rippled, it can be ensured that the system wakes up stably according to the preset cycle, avoiding delays caused by missing or excessive pulses.

[0052] Furthermore, by simultaneously reducing the minimum turn-on time of the synchronous rectifier when entering sleep mode, the conduction loss of the synchronous rectifier is reduced; by simultaneously increasing the minimum turn-on time of the synchronous rectifier when exiting sleep mode, sufficient conduction capability can be quickly provided to the synchronous rectifier, thereby improving the overall efficiency and dynamic response stability of the switching power supply.

[0053] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0054] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0055] Figure 1 This is one of the structural schematic diagrams of the switching power supply system provided in the embodiments of this application;

[0056] Figure 2 This is a second schematic diagram of the switching power supply system provided in the embodiments of this application;

[0057] Figure 3 This is the third schematic diagram of the switching power supply system provided in the embodiments of this application;

[0058] Figure 4 This is the fourth schematic diagram of the switching power supply system provided in the embodiments of this application;

[0059] Figure 5 This is the fifth schematic diagram of the switching power supply system provided in the embodiments of this application;

[0060] Figure 6 This is the sixth schematic diagram of the switching power supply system provided in the embodiments of this application;

[0061] Figure 7 This is a waveform diagram of the control method for the switching power supply system provided in the embodiments of this application;

[0062] Figure 8 This is one of the flowcharts illustrating the control method of the switching power supply system provided in the embodiments of this application;

[0063] Figure 9 This is the seventh schematic diagram of the switching power supply system provided in the embodiments of this application;

[0064] Figure 10 This is a second schematic flowchart of the control method for the switching power supply system provided in the embodiments of this application;

[0065] Figure 11 This is the third flowchart illustrating the control method of the switching power supply system provided in the embodiments of this application;

[0066] Figure 12 This is a schematic diagram of the structure of the control device of the switching power supply system provided in the embodiments of this application;

[0067] Figure 13 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application.

[0068] Figure label:

[0069] Secondary-side synchronous rectifier chip 110; Sleep mode control circuit 120; Ringing detection circuit 130;

[0070] Sleep mode trigger circuit 140; Sleep mode wake-up circuit 150; Control logic circuit 160;

[0071] Output voltage sampling circuit 170; Drain voltage sampling circuit 180; Adder / subtractor 190; Edge detection circuit 200;

[0072] Counting circuit 210; driving function module 220; driving circuit 230; minimum turn-on time circuit 240;

[0073] ZVS module 250; VD detection circuit 260; ZVS control logic circuit 270; slope detection circuit 280;

[0074] Main DRV control logic circuit 290; power supply circuit 300; synchronous rectifier diode SR; first comparator comp1;

[0075] First switch S1; First current source I1; First capacitor C1; Second comparator comp2; AND circuit AND1;

[0076] First flip-flop RS1; second flip-flop RS2. Detailed Implementation

[0077] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0078] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0079] The control method, control device, electronic device, and readable storage medium of the switching power supply system provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0080] The control method of the switching power supply system can be applied to the terminal, and can be executed by the hardware or software in the terminal.

[0081] The terminal includes, but is not limited to, portable communication devices such as mobile phones or tablets with touch-sensitive surfaces (e.g., touchscreen displays and / or touchpads). It should also be understood that, in some embodiments, the terminal may not be a portable communication device, but rather a desktop computer with touch-sensitive surfaces (e.g., touchscreen displays and / or touchpads).

[0082] The following embodiments describe a terminal including a display and a touch-sensitive surface. However, it should be understood that the terminal may include one or more other physical user interface devices such as a physical keyboard, mouse, and joystick.

[0083] The control method for a switching power supply system provided in this application embodiment can be executed by an electronic device or a functional module or entity in an electronic device that can implement the control method for the switching power supply system. The electronic devices mentioned in this application embodiment include, but are not limited to, mobile phones, tablets, computers, cameras, and wearable devices. The control method for a switching power supply system provided in this application embodiment will be described below using an electronic device as the execution subject as an example.

[0084] like Figure 11 As shown, the control method of the switching power supply system includes steps S1, S2, S3 and S4.

[0085] It should be noted that a switching power supply system may include a primary-side control circuit and a secondary-side control circuit.

[0086] The secondary-side control circuit may include a secondary-side synchronous rectifier chip and a synchronous rectifier diode.

[0087] Synchronous rectifiers can be used to replace traditional diodes for rectification. They can be turned on during the freewheeling phase and reduce losses and improve efficiency by utilizing the low on-resistance of MOSFETs (rather than the forward voltage drop of diodes).

[0088] The control method of this switching power supply system can be applied to ZVS (Zero Voltage Switching) synchronous rectification control chips, or it can be applied to synchronous rectification control chips without ZVS. This application does not limit it.

[0089] Step S1: Obtain the drain voltage of the synchronous rectifier and the corresponding output voltage of the switching power supply system;

[0090] In this step, the drain voltage of the synchronous rectifier can be monitored using a voltage divider circuit or a comparator.

[0091] The system output voltage can be obtained through a feedback network, drain voltage, or a dedicated pin.

[0092] The waveform of the drain voltage of the synchronous rectifier can be used to reflect the waveform of the primary control circuit.

[0093] Step S2: Based on the relationship between the drain voltage and the output voltage, if the duration of the drain voltage not emitting a waveform is greater than the first duration threshold, control the secondary side synchronous rectifier chip to enter sleep mode.

[0094] In this step, when the primary-side control circuit enters light-load mode and stops generating waves, the drain voltage may decay to be equal to the output voltage. A comparator can be set so that its two inputs receive the drain voltage and the output voltage respectively, or the two inputs of the comparator can be set to receive the drain voltage and the output voltage after safety margin processing respectively. By detecting the output signal of the comparator, it can be determined whether the drain voltage is not generating waves.

[0095] For example, the two input terminals of the comparator can be configured to receive the drain voltage and the output voltage after safety margin processing, respectively. If the drain voltage is continuously greater than or continuously less than the output voltage after safety margin processing, the output signal of the comparator may remain at a low level or a high level. It can be determined that the primary-side control circuit no longer generates a waveform, that is, the drain voltage does not generate a waveform.

[0096] Once it is determined that the drain voltage does not ripple, the duration of this non-ripple period can be monitored.

[0097] If the duration of the non-wavering drain voltage exceeds a first duration threshold, the secondary synchronous rectifier chip can be controlled to enter sleep mode. The value of the first duration threshold can be user-defined and is not limited in this application.

[0098] In sleep mode, the drive control circuit can be turned off, the internal oscillator or clock can be disabled, and only the power supply circuit can be kept for power supply. The chip power supply pin can be pulled low or the chip can be put into a low power state through the enable pin.

[0099] In this application, when the duration of the detected drain voltage not emitting a waveform exceeds a first duration threshold, the secondary-side synchronous rectifier chip is controlled to enter sleep mode, which solves the problem of frequent entry into sleep mode and improves the anti-interference capability of mode switching.

[0100] Step S3: In sleep mode, based on the relationship between the drain voltage and the output voltage, and when the drain voltage is determined to re-wave, the drive control circuit is turned on to obtain the synchronous rectification control signal corresponding to the drive control circuit.

[0101] In this step, when the primary-side control circuit re-waves, the drain voltage will be greater than or less than the output voltage. The comparator's output signal may be a pulse signal. For example, if a narrow pulse signal (which can be a rising edge, a falling edge, or a rising edge + a falling edge) is detected at the edge of the comparator's output signal, it can be determined that the drain is re-waved.

[0102] The drive control circuit is in the off state in sleep mode. The drive control circuit can be connected to the gate of the synchronous rectifier to drive the synchronous rectifier.

[0103] For example, when controlling the secondary-side synchronous rectifier chip to enter sleep mode, the drive control circuit in the secondary-side synchronous rectifier chip can be turned off simultaneously.

[0104] If the drain voltage is detected to be greater than or less than the output voltage, the drive control circuit can be turned on first to obtain the synchronous rectification control signal main_drv.

[0105] Step S4: When the number of pulses corresponding to the synchronous rectification control signal is greater than or equal to the first quantity threshold, or the continuous transmission duration of the synchronous rectification control signal is greater than the second duration threshold, control the secondary synchronous rectification chip to exit the sleep mode.

[0106] In this step, the synchronous rectification control signal is a pulse signal. When the drive control signal is detected to be turned on and the synchronous rectification control signal is started to be output, the number of pulses of the synchronous rectification control signal can be counted to determine whether the control conditions for exiting sleep mode are met based on the number of pulses of the synchronous rectification control signal.

[0107] For example, if the number of pulses of the synchronous rectification control signal is detected to be greater than or equal to a first quantity threshold, the secondary synchronous rectification chip can be controlled to exit sleep mode.

[0108] like Figure 5 As shown, the synchronous rectification control signal main_drv can be used as the CLK (clock input) terminal of the counting circuit, and the sleep1 signal can be used as the Reset (reset) terminal of the counting circuit. The Reset terminal is active high.

[0109] The output signal of the counting circuit is fed into AND circuit AND1 to generate the sleep mode wake-up signal slp_rst.

[0110] When the sleep1 signal is high, the counting circuit is reset, and all outputs are low, so the slp_rst signal is also low. In sleep mode, the counting circuit starts working when the drain voltage is detected to be greater than or less than the output voltage, causing the sleep1 signal to change from high to low. Figure 7 As shown, if the number of pulses corresponding to the detected synchronous rectification control signal is greater than or equal to the first quantity threshold, the secondary synchronous rectification chip can be controlled to exit the sleep mode.

[0111] The first quantity threshold can be 2. n -1, for example, when the number of pulses of the synchronous rectification control signal detected is 2.n When the value is -1, the sleep mode wake-up signal slp_rst changes from low to high, controlling the secondary-side synchronous rectifier chip to exit sleep mode.

[0112] In the case of determining that the drain voltage is re-emitted, the duration of continuous emission of the synchronous rectification control signal can also be timed. If the duration of continuous emission is detected to be greater than the second duration threshold, the secondary synchronous rectification chip can be controlled to exit sleep mode.

[0113] The value of the second duration threshold can be user-defined, and this application does not impose any restrictions.

[0114] By controlling the secondary-side synchronous rectifier chip to exit sleep mode, the drive circuit and clock can be reactivated, and the timer and comparator states can be reset to enter normal operating mode.

[0115] In this application, when the drain voltage is greater than or less than the output voltage, the drive control circuit in the secondary synchronous rectifier chip is turned on to obtain the synchronous rectification control signal corresponding to the drive control circuit. Then, based on the number of pulses of the synchronous rectification control signal, it is determined whether the secondary synchronous rectifier chip needs to exit the sleep mode. This can filter out brief false pulses or glitches and avoid premature wake-up caused by accidental interference.

[0116] When the continuous transmission duration of the synchronous rectification control signal is detected to be greater than the second duration threshold, or when the number of pulses corresponding to the synchronous rectification control chip is detected to be greater than or equal to the first quantity threshold, the secondary synchronous rectification chip is controlled to exit the sleep mode, which solves the problem of frequent exit from the sleep mode and improves the anti-interference of mode switching.

[0117] According to the control method of the switching power supply system provided in the embodiments of this application, by monitoring the ripple of the drain voltage, it is determined whether the primary-side control circuit has entered a light load state. Then, based on the state of the primary-side control circuit, it is determined whether the secondary-side synchronous rectifier chip enters or exits the sleep mode. When it is determined that the primary-side control circuit has entered a light load state, the secondary-side synchronous rectifier chip is controlled to enter the sleep mode, which reduces the conduction loss of the synchronous rectifier tube, improves the conversion efficiency of the switching power supply system under light load, and enhances the stability and reliability of the chip operation.

[0118] In some embodiments, step S4 may include:

[0119] When the drain voltage is greater than or less than the output voltage, obtain the start time of the first pulse of the synchronous rectification control signal;

[0120] When the starting time of the first pulse of the synchronous rectification control signal is detected, and the continuous wave generation duration of the synchronous rectification control signal is greater than the second duration threshold, or when the number of pulses of the synchronous rectification control signal is greater than or equal to the first quantity threshold, control the secondary side synchronous rectification chip to exit the sleep mode.

[0121] In this embodiment, as Figure 3 shown, when the drain voltage is greater than or less than the output voltage, the pulse signal vd_ring is a pulse signal. When the edge signal of the vd_ring signal is detected, the reset signal vd_rst obtains a narrow pulse signal. When vd_rst is at a high level, the switch s1 closes, clearing the capacitance on the capacitor C1, Vc1 = 0 < Vref, and the sleep trigger signal slp_set is at a low level, indicating not entering the sleep mode.

[0122] As Figure 6 shown, the set terminal (S terminal) of the RS flip - flop 1 can be used to receive the slp_set signal, and the reset terminal (R terminal) of the RS flip - flop 1 can be used to receive the vd_rst signal. When the slp_set signal is at a high level and the vd_rst signal is at a low level, the signal sleep1 output by the RS flip - flop 1 is at a high level.

[0123] When the slp_set signal is at a low level and the vd_rst signal is at a high level, the signal sleep1 output by the RS flip - flop 1 is at a low level.

[0124] When the sleep1 signal changes from a high level to a low level, the synchronous rectification control signal starts to generate waves. The moment when the sleep1 signal changes from a high level to a low level can be determined as the starting time of the first pulse of the synchronous rectification control signal.

[0125] As Figure 6 shown, the sleep mode trigger signal slp_set can be used as the set (S) terminal of the RS flip - flop 2, and the sleep mode wake - up signal slp_rst can be used as the reset (R) terminal of the RS flip - flop 2. The RS flip - flop 2 outputs the sleep control signal sleep2.

[0126] It is possible to start timing from when the sleep1 signal changes from a high level to a low level. When the timing duration (i.e., the continuous wave generation duration of the synchronous rectification control signal) is greater than the second duration threshold, the sleep mode wake - up signal slp_rst outputs a high level, the sleep2 signal output by the RS flip - flop 2 changes from a high level to a low level, and the secondary side synchronous rectification chip exits the sleep mode.

[0127] According to the control method of the switching power supply system provided in the embodiments of this application, by controlling the secondary side to exit the sleep mode based on the continuous wave duration or number of pulses of the synchronous rectification control signal when the drain voltage is determined to re-wave, it can ensure that the system wakes up stably according to the preset cycle and avoids the situation of delay caused by missing or excessive pulses.

[0128] In some embodiments, determining that the drain voltage does not ripple based on the relationship between the drain voltage and the output voltage includes:

[0129] Obtain the margin voltage, and derive the first voltage based on the margin voltage and the output voltage;

[0130] If the drain voltage is greater than or less than the first voltage, it is determined that the drain voltage does not generate a wave.

[0131] In this embodiment, the margin voltage is the "fault tolerance boundary" for determining whether the drain voltage is rippled. By setting an offset, the system only confirms that it is stable (not rippled) when the drain voltage deviates significantly from the output voltage. This avoids misjudgment caused by noise or small signal interference and adds one-sided hysteresis to the comparator, thereby improving the anti-interference capability.

[0132] The first voltage can be obtained based on the sum of the output voltage and the margin voltage; or it can be obtained based on the difference between the output voltage and the margin voltage.

[0133] like Figure 3 As shown, the output voltage sampling signal vo_sen can be obtained through the Vo sampling circuit, and then the output voltage sampling signal vo_sen can be input to an adder or a subtractor to obtain the first voltage vo_sen1.

[0134] Where vo_sen1=vo_sen±ΔV, ΔV is the margin voltage.

[0135] like Figure 7 As shown, vo_sen1 = vo_sen + ΔV can be set, and by comparing the magnitude of the drain voltage and the first voltage, it can be determined whether the drain voltage is rippled.

[0136] When the primary-side control circuit enters light-load mode and stops generating waveforms, the drain voltage decays to be equal to the output voltage (i.e., the drain voltage is greater than or less than the first voltage). Figure 3 The comparator comp1 outputs a fixed signal vd_ring (low or high level) instead of a pulse signal.

[0137] When the drain voltage is detected to be greater than or less than the first voltage, vd_ring is a fixed value, which means that the drain voltage will not generate a waveform.

[0138] In some embodiments, step S2 may include:

[0139] Given that the drain voltage is not emitting waves, obtain the moment when the drain voltage stops emitting waves;

[0140] If the duration of the drain voltage cessation exceeds a first duration threshold when the drain voltage cessation occurs, the secondary-side synchronous rectifier chip is controlled to enter sleep mode.

[0141] In this embodiment, such as Figure 7 As shown, when the drain voltage does not emit waves, vd_ring is a fixed value, and neither the rising nor falling edge of the vd_ring signal will be detected. The moment when the edge signal of the vd_ring signal disappears can be determined as the moment when the drain voltage stops emitting waves. By detecting the duration for which the edge signal of the vd_ring signal is not detected, it can be determined as the duration for which the drain voltage stops emitting waves.

[0142] For example, if no edge signal of the vd_ring signal is detected within the first time threshold, the sleep trigger signal slp_set can be controlled to go high, thereby controlling the secondary synchronous rectifier chip to enter sleep mode.

[0143] like Figure 4 A timing circuit is provided, in which the vd_ring signal can be sent to an edge detection circuit to obtain a narrow pulse signal vd_rst of the vd_ring signal edge, which is used to control switch s1, i.e., the reset signal of the timing circuit. Switch s1 is connected to capacitor C1, current source I1 and the positive input terminal of comparator comp2. The reference voltage vref is connected to the inverting input terminal of comp2. Comp2 generates a sleep mode trigger signal slp_set by comparing the voltage Vc1 on capacitor C1 and the reference voltage vref. The first time threshold can be set as: Tslp = Vref * C1 / I1. Tslp can be set according to system requirements. If no edge signal of vd_ring is detected within the set time threshold Tslp, the secondary side synchronous rectifier chip can be controlled to enter sleep mode.

[0144] In some embodiments, the method may further include:

[0145] When the secondary-side synchronous rectifier chip enters sleep mode, the minimum turn-on time corresponding to the synchronous rectifier tube is reduced, and the ZVS module is turned off.

[0146] When the secondary-side synchronous rectifier chip exits sleep mode, the minimum turn-on time corresponding to the synchronous rectifier tube is increased, and the ZVS module is turned on.

[0147] In this embodiment, the minimum turn-on time is used to characterize the shortest duration for which the synchronous rectifier tube is turned on within one conduction cycle under synchronous rectification conduction mode.

[0148] When the secondary-side synchronous rectifier chip is controlled to enter sleep mode, the minimum start time can be reduced simultaneously.

[0149] When controlling the secondary-side synchronous rectifier chip to exit sleep mode, the minimum on-time can be increased simultaneously.

[0150] In actual implementation, such as Figure 6 As shown, the sleep mode trigger signal slp_set can be used as the set (S) terminal of RS flip-flop 2, and the sleep mode wake-up signal slp_rst can be used as the reset (R) terminal of RS flip-flop 2. RS flip-flop 2 outputs the sleep control signal sleep2. The sleep2 signal can be used to control and adjust the minimum on time. After main_drv resumes normal operation and continuously emits waves to reach the set number of times or the set time threshold, the minimum on time can be switched (increased).

[0151] In this application, by simultaneously reducing the minimum turn-on time of the synchronous rectifier when entering sleep mode, the conduction loss of the synchronous rectifier is reduced; by simultaneously increasing the minimum turn-on time of the synchronous rectifier when exiting sleep mode, sufficient conduction capability can be quickly provided to the synchronous rectifier, thereby improving the overall efficiency and dynamic response stability of the switching power supply.

[0152] The ZVS module is used to control the synchronous rectifier tubes to turn on and off in a zero-voltage conduction mode.

[0153] When entering sleep mode, the ZVS module is simultaneously turned off, and when exiting sleep mode, the ZVS module is simultaneously turned on.

[0154] When the re-emission of the drain voltage is detected, the drive control circuit can be turned on to obtain the corresponding synchronous rectification control signal. When the synchronous rectification control signal is high, and the emission of the synchronous rectification control signal is detected to determine that the continuous emission of the synchronous rectification control signal has reached a set number of times or a set time threshold, the slp_rst signal can be triggered to change from low to high, thereby triggering the sleep2 signal to change from high to low.

[0155] When the sleep2 signal changes from low to high, the ZVS module can be turned off; when the sleep2 signal changes from high to low, the ZVS module can be turned on.

[0156] During the research and development process, the inventors discovered that in related technologies, synchronous rectification chips are usually equipped with slope detection to prevent the SR tube from turning on accidentally during ringing. If the VDS drop slope is too slow and does not meet the slope setting threshold, the primary side will generate a normal waveform while the secondary side does not, which will cause the chip to enter sleep mode incorrectly.

[0157] In this application, the sleep mode control method ensures the accurate startup of the ZVS module, avoiding the situation where the chip incorrectly enters sleep mode due to the primary side transmitting a wave normally while the secondary side does not, thereby further improving power efficiency and enhancing the stability and reliability of chip operation.

[0158] The following is combined with Figure 1 , Figure 8 , Figure 9 and Figure 10 The control method of the switching power supply system provided in the embodiments of this application will be described in detail below:

[0159] like Figure 9 As shown, a switching power supply system may include a power supply circuit, a sleep mode control circuit, a DRV function module, and a drive circuit.

[0160] like Figure 1 As shown, the switching power supply system may also include a ZVS module.

[0161] The DRV functional module may include a slope detection circuit, a main DRV control logic circuit, and a minimum turn-on time circuit.

[0162] The slope detection circuit is connected to the chip pin RSET, and the slope detection circuit and the minimum turn-on time circuit are connected to the control logic circuit.

[0163] The DRV function module can control the external SR tube to turn on and off in a synchronous rectification conduction mode.

[0164] The ZVS module can include a VD detection circuit and a ZVS control logic circuit. The VD detection circuit is connected to the ZVS logic control circuit. The ZVS module can control the external SR transistor to turn on and off in a zero-voltage conduction mode.

[0165] The sleep mode control circuit is connected to the external SR tube drain voltage VD, ZVS module, DRV function module and drive circuit. The sleep mode control circuit is used to control the system to enter and exit sleep mode, as well as control the working status or function of DRV function module, ZVS module and drive circuit. In sleep mode, the chip power loss is reduced, the overall power supply efficiency is improved, and the stability and reliability of chip operation are improved.

[0166] The external pin VCC is connected to the external pin HV through a power supply circuit to supply power to the internal circuitry of the chip.

[0167] The drive circuit can be connected to the DRV function module and the ZVS module to enhance the driving capability of the synchronous rectification control signal main_drv and the zero voltage switching control signal zvs_drv, so as to drive the external SR transistor.

[0168] like Figure 8 As shown, the chip starts up and begins normal operation; then it checks whether the drain voltage VD of the SR transistor remains undisturbed within a set time threshold. If so, it enters sleep mode, shutting down the DRV function and the drive circuit. In the case of a switching power supply system including a ZVS module, the ZVS module can also be shut down, while reducing the minimum on-time; otherwise, the chip operates normally.

[0169] After entering sleep mode, it is determined whether the drain voltage VD of the SR transistor is retransmitted. If so, the DRV function and the drive module are restored, and the VD platform voltage sampling is refreshed. Otherwise, the current sleep mode is maintained.

[0170] After restoring the DRV function and the normal operation of the drive module, determine whether the synchronous rectifier gate drive control signal main_drv has been continuously emitted to the set number of times or the set time threshold. If so, exit the sleep mode and increase the minimum turn-on time. If the switching power supply system includes the ZVS module, restore the operation of the ZVS module. If not, return to the step of determining whether the drain voltage VD of the SR tube is re-emitted.

[0171] In this application, after entering sleep mode, if the drain voltage is detected to be greater than or less than the output voltage, the function of the drive control module is restored and the VD platform voltage sampling is refreshed, which can ensure the accuracy of subsequent chip operation and avoid logic and functional errors.

[0172] The control device for the switching power supply system provided in this application is described below. The control device for the switching power supply system described below can be referred to in correspondence with the control method for the switching power supply system described above.

[0173] The control method for a switching power supply system provided in this application can be executed by a control device for the switching power supply system. This application uses the example of a control device executing the control method for a switching power supply system to illustrate the control device for the switching power supply system provided in this application.

[0174] This application also provides a control device for a switching power supply system.

[0175] like Figure 12As shown, the control device of the switching power supply system includes a secondary-side synchronous rectifier chip and a synchronous rectifier tube connected to each other; the device includes: a first processing module 1210, a second processing module 1220, a third processing module 1230 and a fourth processing module 1240.

[0176] The first processing module 1210 is used to obtain the drain voltage of the synchronous rectifier and the corresponding output voltage of the switching power supply system.

[0177] The second processing module 1220 is used to control the secondary-side synchronous rectifier chip to enter sleep mode when it is determined, based on the relationship between the drain voltage and the output voltage, that the drain voltage does not ripple and the duration of the drain voltage not ripple is greater than a first duration threshold. In sleep mode, the drive control circuit in the secondary-side synchronous rectifier chip is in the off state, and the drive control circuit is used to drive the synchronous rectifier tube.

[0178] The third processing module 1230 is used to control the drive control circuit to turn on in sleep mode, based on the relationship between the drain voltage and the output voltage, to obtain the synchronous rectification control signal corresponding to the drive control circuit.

[0179] The fourth processing module 1240 is used to control the secondary synchronous rectification chip to exit the sleep mode when the number of pulses corresponding to the synchronous rectification control signal is greater than or equal to the first quantity threshold, or the continuous transmission duration of the synchronous rectification control signal is greater than the second duration threshold.

[0180] According to the control device of the switching power supply system provided in the embodiments of this application, by monitoring the ripple of the drain voltage, it determines whether the primary-side control circuit has entered a light load state, and then determines whether the secondary-side synchronous rectifier chip enters or exits the sleep mode based on the state of the primary-side control circuit. When it is determined that the primary-side control circuit has entered a light load state, the secondary-side synchronous rectifier chip is controlled to enter the sleep mode, which reduces the conduction loss of the synchronous rectifier tube, improves the conversion efficiency of the switching power supply system under light load, and enhances the stability and reliability of the chip operation.

[0181] In some embodiments, the fourth processing module 1240 can also be used for:

[0182] When the drain voltage is greater than or less than the output voltage, obtain the start time of the first pulse of the synchronous rectification control signal;

[0183] At the start of the first pulse of the synchronous rectification control signal, if the continuous transmission duration of the synchronous rectification control signal is detected to be greater than the second duration threshold, or if the number of pulses of the synchronous rectification control signal is detected to be greater than or equal to the first quantity threshold, the secondary synchronous rectification chip is controlled to exit the sleep mode.

[0184] In some embodiments, the second processing module 1220 may also be used for:

[0185] Obtain the margin voltage, and derive the first voltage based on the margin voltage and the output voltage;

[0186] If the drain voltage is greater than or less than the first voltage, it is determined that the drain voltage does not generate a wave.

[0187] In some embodiments, the secondary-side synchronous rectifier chip includes a ZVS module; the control device of the switching power supply system may further include a fourth processing module, used for:

[0188] When the secondary-side synchronous rectifier chip enters sleep mode, the minimum turn-on time of the synchronous rectifier tube is reduced, and the ZVS module is turned off. The ZVS module is used to control the synchronous rectifier tube to turn on and off in a zero-voltage conduction mode. The minimum turn-on time is used to characterize the shortest duration for which the synchronous rectifier tube is turned on in one conduction cycle under synchronous rectification conduction mode.

[0189] When the secondary-side synchronous rectifier chip exits sleep mode, the minimum turn-on time corresponding to the synchronous rectifier tube is increased, and the ZVS module is turned on.

[0190] The control device of the switching power supply system in this application embodiment can be an electronic device or a component in an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, handheld computer, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM or self-service machine, etc. The embodiments of this application do not specifically limit it.

[0191] The control device of the switching power supply system in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system used.

[0192] The control device for the switching power supply system provided in this application embodiment can achieve... Figures 1 to 11 The various processes implemented in the method implementation examples will not be described again here to avoid repetition.

[0193] In some embodiments, such as Figure 13 As shown, this application embodiment also provides an electronic device 1300, including a processor 1301, a memory 1302, and a computer program stored in the memory 1302 and executable on the processor 1301. When the program is executed by the processor 1301, it implements the various processes of the control method embodiment of the switching power supply system described above and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0194] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0195] This application also provides a switching power supply system, including: a synchronous rectifier diode SR and a secondary-side synchronous rectifier chip 110.

[0196] In this embodiment, such as Figure 1 and Figure 9 As shown, the secondary-side synchronous rectifier chip 110 includes a sleep mode control circuit 120 and a drive control circuit.

[0197] The input terminal of the sleep mode control circuit 120 is connected to the drain terminal of the synchronous rectifier SR and the output terminal of the drive control circuit, respectively, and the output terminal of the sleep mode control circuit 120 is connected to the drive control circuit.

[0198] The sleep mode control circuit 120 is used to output a first sleep control signal and a second sleep control signal.

[0199] When the first sleep control signal is high, the drive control circuit is in the off state; when the first sleep control signal is low, the drive control circuit is in the on state.

[0200] When the second sleep control signal changes from low to high, the secondary-side synchronous rectifier chip enters sleep mode; when the second sleep control signal changes from high to low, the secondary-side synchronous rectifier chip exits sleep mode.

[0201] The drive control circuit may include a drive function module 220 and a drive circuit 230.

[0202] The driver module 220 is used to output the synchronous rectification control signal main_drv.

[0203] The input terminal of the drive circuit 230 is connected to the output terminal of the drive function module 220. The output terminal of the sleep mode control circuit 120 is connected to both the drive function module 220 and the drive circuit 230. The drive circuit 230 can be connected to the gate of the synchronous rectifier diode SR.

[0204] The first sleep control signal output by the sleep mode control circuit 120 is used to control the working state of the drive circuit 230 and the drive function module 220. When the first sleep control signal changes from low level to high level, the drive circuit 230 and the drive function module 220 are turned off. In sleep mode, chip power consumption can be reduced, thereby improving the overall power efficiency. When the first sleep control signal changes from high level to low level, the drive circuit 230 and the drive function module 220 are turned on.

[0205] According to the control system of the switching power supply system provided in the embodiments of this application, by monitoring the ripple of the drain voltage, it is determined whether the primary-side control circuit has entered a light load state. Then, based on the state of the primary-side control circuit, it is determined whether the secondary-side synchronous rectifier chip 110 enters or exits the sleep mode. When it is determined that the primary-side control circuit has entered a light load state, the secondary-side synchronous rectifier chip 110 is controlled to enter the sleep mode, which reduces the conduction loss of the synchronous rectifier tube SR, improves the conversion efficiency of the switching power supply system under light load, and enhances the stability and reliability of the chip operation.

[0206] like Figure 2 As shown, in some embodiments, the sleep mode control circuit 120 may include: a ring detection circuit 130, a sleep mode trigger circuit 140, a sleep mode wake-up circuit 150, and a control logic circuit 160.

[0207] In this embodiment, the input terminal of the ring detection circuit 130 is connected to the drain terminal of the synchronous rectifier SR to sample the drain voltage, and the ring detection circuit 130 outputs the vd_ring signal.

[0208] The input terminal of the sleep mode trigger circuit 140 is connected to the output terminal of the ringing detection circuit 130. The sleep mode trigger circuit 140 outputs a sleep trigger signal slp_set and a reset signal vd_rst.

[0209] The input terminal of the sleep mode wake-up circuit 150 is connected to the output terminal of the ringing detection circuit 130. The input terminal of the sleep mode wake-up circuit 150 is also used to receive the synchronous rectification control signal main_drv and the first sleep control signal sleep1. The sleep mode wake-up circuit 150 outputs the sleep mode wake-up signal slp_rst.

[0210] The input terminals of the control logic circuit 160 are connected to the output terminals of the sleep mode trigger circuit 140 and the sleep mode wake-up circuit 150, respectively. The control logic circuit 160 outputs the first sleep control signal sleep1 and the second sleep control signal sleep2.

[0211] like Figure 3 As shown, in some embodiments, the ringing detection circuit 130 may include: an output voltage sampling circuit 170, a drain voltage sampling circuit 180, an adder / subtractor 190, and a first comparator comp1.

[0212] In this embodiment, the input terminal of the output voltage sampling circuit 170 is connected to the drain terminal of the synchronous rectifier diode SR, and VD can obtain the output voltage sampling signal vo_sen through the output voltage sampling circuit 170. In some embodiments, if the chip includes a pin connected to the output voltage Vo, the output voltage information can also be obtained directly through this pin, which is not limited in this application.

[0213] The input terminal of the drain voltage sampling circuit 180 is connected to the drain terminal of the synchronous rectifier diode SR, and is used to output the drain voltage sampling signal vd_sen.

[0214] The input terminal of the adder / subtractor 190 is connected to the output terminal of the output voltage sampling circuit 170. The adder / subtractor 190 can perform addition or subtraction operations on the output voltage. The selection can be based on user needs and is not limited in this application.

[0215] The output voltage sampling signal vo_sen can be sent to adder / subtractor 190 to obtain the first voltage vo_sen1.

[0216] One input of the first comparator comp1 is connected to the output of the adder / subtractor 190, the other input of the first comparator comp1 is connected to the output of the drain voltage sampling circuit 180, and the output of the first comparator comp1 is connected to the inputs of the sleep mode trigger circuit 140 and the sleep mode wake-up circuit 150, respectively.

[0217] By feeding the first voltage and the drain voltage into the inverting input and non-inverting input of the first comparator comp1, respectively, the output signal vd_ring of the first comparator comp1 can be obtained.

[0218] If the primary side enters light load mode and stops emitting waves, when the ringing voltage of vd_sen decays to be equal to that of vo_sen, the output signal vd_ring of comp1 will be a fixed value (low level or high level) instead of a pulse signal. This is used to determine whether the primary side is still emitting waves, which facilitates subsequent determination of whether the secondary side should enter sleep mode.

[0219] As Figure 4 shown, in some embodiments, the sleep mode trigger circuit 140 may include: an edge detection circuit 200, a first switch S1, a first current source I1, a first capacitor C1, and a second comparator comp2.

[0220] In this embodiment, the input end of the edge detection circuit 200 is connected to the output end of the ringing detection circuit 130. The VD sampling signal vd_sen and the Vo sampling signal vo_sen are compared to obtain a pulse signal vd_ring, and this signal is sent to the edge detection circuit 200 to obtain an edge narrow pulse signal vd_rst of vd_ring.

[0221] The first switch S1 is connected to the output end of the edge detection circuit 200. The edge narrow pulse signal vd_rst can be used to control the first switch S1, that is, the reset signal of the timing circuit.

[0222] The first current source I1 is connected to the first switch S1.

[0223] The first capacitor C1 is connected in parallel with the first switch S1 and in series with the first current source I1. One end of the first capacitor C1 far from the first current source I1 is grounded.

[0224] One input end of the second comparator comp2 is connected between the first current source I1 and the first capacitor C1 for receiving the capacitor voltage corresponding to the first capacitor C1. The other input end of the second comparator comp2 is used to receive a reference voltage. The output end of the second comparator comp2 is connected to the input end of the control logic circuit 160. For example, the reference voltage can be connected to the inverting input end of the second comparator comp2. The second comparator comp2 can generate a sleep mode trigger signal slp_set by comparing the magnitudes of the capacitor voltage on the first capacitor C1 and the reference voltage.

[0225] When the edge signal of vd_ring is detected, the reset signal vd_rst obtains a narrow pulse signal. When rst is at a high level, the first switch S1 closes, clearing the capacitance on the first capacitor C1, that is, Vc1 = 0 < Vref, and the sleep trigger signal slp_set is at a low level, indicating that the sleep mode is not entered; when the rising edge or falling edge of vd_ring is not detected, the reset signal vd_rst is at a low level, the first switch S1 is disconnected, and the first current source I1 starts to charge the first capacitor C1. When Vc1 > Vref, the sleep trigger signal slp_set becomes at a high level, indicating that the system should enter the sleep mode.

[0226] As Figure 5 shown, in some embodiments, the sleep mode wake-up circuit 150 may include: a counting circuit 210 and an AND circuit AND1.

[0227] In this embodiment, one input terminal (CLK, clock input terminal) of the counting circuit 210 is used to receive the synchronous rectification control signal main drv, and the other input terminal (Reset, reset terminal) of the counting circuit 210 is used to receive the first sleep control signal sleep1, wherein the Reset terminal is active high.

[0228] The input terminal of AND1 is connected to the output terminal of the counting circuit 210, and the output terminal of AND1 is connected to the input terminal of the control logic circuit 160. The output signal of the counting circuit 210 is sent into AND1, which can generate a sleep mode wake-up signal slp_rst.

[0229] When sleep1 is high, the counting circuit 210 is reset and its output is low, so slp_rst is also low. When sleep1 changes from high to low, the counting circuit 210 starts working. When the main_drv pulse count reaches 2n-1, slp_rst changes from low to high. The counting circuit 210 can be replaced by a timing circuit, that is, timing starts when sleep1 changes from high to low, and slp_rst outputs high after the set time threshold is reached.

[0230] like Figure 6 As shown, in some embodiments, the control logic circuit 160 may include: a first flip-flop RS1 and a second flip-flop RS2.

[0231] In this embodiment, the set (S) terminal of the first flip-flop RS1 is connected to the output terminal of the sleep mode trigger circuit 140 to receive the sleep mode trigger signal slp_set, the reset (R) terminal of the first flip-flop RS1 is connected to the sleep mode trigger circuit 140 to receive the ringing reset signal vd_rst, and the output terminal of the first flip-flop RS1 is used to output the first sleep control signal sleep1.

[0232] The set (S) terminal of the second flip-flop RS2 is connected to the output terminal of the sleep mode trigger circuit 140 and is used to receive the sleep mode trigger signal slp_set. The reset (R) terminal of the second flip-flop RS2 is connected to the output terminal of the sleep mode wake-up circuit 150 and is used to receive the sleep mode wake-up signal slp_rst. The output terminal of the second flip-flop RS2 is used to output the second sleep control signal sleep2.

[0233] In some embodiments, the drive function module 220 may include a minimum turn-on time circuit 240.

[0234] In this embodiment, the minimum turn-on time circuit 240 is used to output the minimum turn-on time corresponding to the synchronous rectifier tube.

[0235] The second sleep control signal sleep2 can be used to adjust the minimum on time. When the second sleep control signal changes from low level to high level, the minimum on time output by the minimum on time circuit decreases, and when the second sleep control signal changes from high level to low level, the minimum on time output by the minimum on time circuit increases.

[0236] In some embodiments, the drive function module 220 may include a slope detection circuit 280 and a main DRV control logic circuit 290.

[0237] In this embodiment, the slope detection circuit 280 is connected to the chip pin RSET, and the signal Tslew output by the slope detection circuit 280 is input to the main DRV control logic circuit 290. The main DRV control logic circuit 290 outputs the synchronous rectification control signal main_drv.

[0238] The main DRV control logic circuit 290 can also be connected to the minimum turn-on time circuit 240.

[0239] like Figure 1 As shown, in some embodiments, the secondary-side synchronous rectifier chip 110 may include a ZVS module 250.

[0240] In this embodiment, the ZVS module 250 may include a VD detection circuit 260 and a ZVS control logic circuit 270.

[0241] One end of the VD detection circuit 260 can be connected to the drain of the synchronous rectifier diode SR, and the other end of the VD detection circuit 260 can be connected to the slope detection circuit 280. The output of the VD detection circuit 260 is connected to the input of the ZVS control logic circuit 270.

[0242] The ZVS module 250 is connected to the output of the sleep mode control circuit 120. The input of the ZVS control logic circuit 270 can also be used to receive the second sleep control signal sleep2. The second sleep control signal sleep2 can be used to control whether the ZVS module 250 works. When the second sleep control signal changes from low level to high level, the ZVS module 250 is turned off. When the second sleep control signal changes from high level to low level, the ZVS module 250 is turned on, ensuring the stability and reliability of the ZVS synchronous rectification operation.

[0243] ZVS control logic circuit 270 is used to output zero-voltage switching control signal, which can be sent to drive circuit 230.

[0244] The driver circuit 230 can enhance the driving capability of the synchronous rectification control signal main_drv and the zero-voltage switching control signal zvs_drv to drive the external synchronous rectifier tube SR.

[0245] In this application, the sleep mode control method ensures the accurate startup of the ZVS module 250, further improving power efficiency and enhancing the stability and reliability of chip operation.

[0246] like Figure 1 As shown, in some embodiments, the secondary-side synchronous rectifier chip 110 may include a power supply circuit 300.

[0247] In this embodiment, the external pin VCC is connected to the external pin HV through the power supply circuit 300 to supply power to the internal circuitry of the chip.

[0248] On the other hand, this application also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the various processes of the control method embodiment of the above-described switching power supply system and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0249] In another aspect, this application also provides a non-transitory computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it implements the various processes of the control method embodiment of the above-described switching power supply system and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0250] In another aspect, this application embodiment provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the control method embodiment of the above-described switching power supply system, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0251] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0252] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0253] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of software products. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0254] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A control method for a switching power supply system, characterized in that, The switching power supply system includes a secondary-side synchronous rectifier chip and a synchronous rectifier diode connected together; the method includes: Obtain the drain voltage of the synchronous rectifier and the corresponding output voltage of the switching power supply system; Based on the relationship between the drain voltage and the output voltage, if it is determined that the drain voltage does not ripple and the duration of the drain voltage not ripple is greater than a first duration threshold, the secondary-side synchronous rectifier chip is controlled to enter a sleep mode; in the sleep mode, the drive control circuit in the secondary-side synchronous rectifier chip is in a closed state, and the drive control circuit is used to drive the synchronous rectifier tube; In the sleep mode, if it is determined that the drain voltage will be re-transmitted based on the relationship between the drain voltage and the output voltage, the drive control circuit is turned on to obtain the synchronous rectification control signal corresponding to the drive control circuit. If the number of pulses corresponding to the synchronous rectification control signal is greater than or equal to a first quantity threshold, or if the continuous transmission duration of the synchronous rectification control signal is greater than a second duration threshold, the secondary synchronous rectification chip is controlled to exit the sleep mode.

2. The control method for a switching power supply system according to claim 1, characterized in that, When the number of pulses corresponding to the synchronous rectification control signal is greater than or equal to a first quantity threshold, or the continuous transmission duration of the synchronous rectification control signal is greater than a second duration threshold, controlling the secondary-side synchronous rectification chip to exit the sleep mode includes: When the drain voltage is greater than or less than the output voltage, the start time of the first pulse of the synchronous rectification control signal is obtained; If, at the start time of the first pulse of the synchronous rectification control signal, the continuous transmission duration of the synchronous rectification control signal is detected to be greater than the second duration threshold, or the number of pulses of the synchronous rectification control signal is detected to be greater than or equal to the first quantity threshold, the secondary-side synchronous rectification chip is controlled to exit the sleep mode.

3. The control method for the switching power supply system according to claim 1 or 2, characterized in that, The step of determining that the drain voltage does not emit waves based on the magnitude relationship between the drain voltage and the output voltage includes: Obtain the margin voltage, and derive the first voltage based on the margin voltage and the output voltage; If the drain voltage is greater than or less than the first voltage, it is determined that the drain voltage does not generate a wave.

4. The control method for the switching power supply system according to claim 1 or 2, characterized in that, The secondary-side synchronous rectifier chip includes a ZVS module; the method further includes: When the secondary-side synchronous rectifier chip is controlled to enter sleep mode, the minimum turn-on time corresponding to the synchronous rectifier tube is reduced, and the ZVS module is controlled to turn off; the ZVS module is used to control the synchronous rectifier tube to turn on and off in a zero-voltage conduction mode, and the minimum turn-on time is used to characterize the shortest duration for which the synchronous rectifier tube is turned on in one conduction cycle under synchronous rectification conduction mode; When the secondary-side synchronous rectifier chip exits the sleep mode, the minimum turn-on time corresponding to the synchronous rectifier tube is increased, and the ZVS module is turned on.

5. A switching power supply system based on the control method of the switching power supply system as described in any one of claims 1-4, characterized in that, include: Synchronous rectifier tube; A secondary-side synchronous rectifier chip includes: a sleep mode control circuit and a drive control circuit, wherein the drive control circuit includes: a drive function module and a drive circuit; The input terminal of the sleep mode control circuit is connected to the drain terminal of the synchronous rectifier and the output terminal of the drive function module, respectively. The output terminal of the sleep mode control circuit is connected to the drive function module and the drive circuit, respectively. The input terminal of the drive circuit is connected to the output terminal of the drive function module. The sleep mode control circuit is used to output a first sleep control signal and a second sleep control signal. The drive function module is used to output a synchronous rectification control signal. When the first sleep control signal is high, the drive control circuit is in a closed state. When the first sleep control signal is low, the drive control circuit is in a closed state. When the second sleep control signal changes from low to high, the secondary-side synchronous rectifier chip enters sleep mode. When the second sleep control signal changes from high to low, the secondary-side synchronous rectifier chip exits sleep mode.

6. The switching power supply system according to claim 5, characterized in that, The sleep mode control circuit includes: A ringing detection circuit, wherein the input terminal of the ringing detection circuit is connected to the drain terminal of the synchronous rectifier tube; A sleep mode trigger circuit, wherein the input terminal of the sleep mode trigger circuit is connected to the output terminal of the ringing detection circuit; A sleep mode wake-up circuit, wherein the input terminal of the sleep mode wake-up circuit is connected to the output terminal of the ringing detection circuit; A control logic circuit, wherein the input terminals of the control logic circuit are respectively connected to the output terminals of the sleep mode trigger circuit and the sleep mode wake-up circuit.

7. The switching power supply system according to claim 6, characterized in that, The sleep mode triggering circuit includes: An edge detection circuit, wherein the input terminal of the edge detection circuit is connected to the output terminal of the ringing detection circuit; A first switch is connected to the output terminal of the edge detection circuit. A first current source is connected to the first switch; The first capacitor is connected in parallel with the first switch and in series with the first current source, and the end of the first capacitor away from the first current source is grounded. The second comparator has one input connected between the first current source and the first capacitor to receive the capacitor voltage corresponding to the first capacitor. The other input of the second comparator is used to receive a reference voltage. The output of the second comparator is connected to the input of the control logic circuit.

8. The switching power supply system according to claim 6, characterized in that, The sleep mode wake-up circuit includes: A counting circuit, wherein one input terminal of the counting circuit is used to receive a synchronous rectification control signal, and the other input terminal of the counting circuit is used to receive the first sleep control signal; The AND circuit has its input terminal connected to the output terminal of the counting circuit, and its output terminal connected to the input terminal of the control logic circuit.

9. The switching power supply system according to claim 6, characterized in that, The control logic circuit includes: The first trigger has its set terminal connected to the output terminal of the sleep mode trigger circuit, its reset terminal connected to the sleep mode trigger circuit, and its output terminal used to output the first sleep control signal. The second trigger has its set terminal connected to the output terminal of the sleep mode trigger circuit, and its reset terminal connected to the output terminal of the sleep mode wake-up circuit. The output terminal of the second trigger is used to output a second sleep control signal.

10. A control device for a switching power supply system, characterized in that, The switching power supply system includes a secondary-side synchronous rectifier chip and a synchronous rectifier diode connected together; the device includes: The first processing module is used to obtain the drain voltage of the synchronous rectifier and the corresponding output voltage of the switching power supply system; The second processing module is used to control the secondary-side synchronous rectifier chip to enter a sleep mode when, based on the relationship between the drain voltage and the output voltage, it is determined that the drain voltage does not ripple and the duration of the drain voltage not ripple is greater than a first duration threshold. In the sleep mode, the drive control circuit in the secondary-side synchronous rectifier chip is in a closed state, and the drive control circuit is used to drive the synchronous rectifier tube. The third processing module is used to control the drive control circuit to turn on in the sleep mode, based on the magnitude relationship between the drain voltage and the output voltage, when it is determined that the drain voltage is re-transmitted, so as to obtain the synchronous rectification control signal corresponding to the drive control circuit. The fourth processing module is used to control the secondary-side synchronous rectification chip to exit the sleep mode when the number of pulses corresponding to the synchronous rectification control signal is greater than or equal to a first quantity threshold, or when the continuous transmission duration of the synchronous rectification control signal is greater than a second duration threshold.

11. A chip, the chip comprising a processor and a communication interface, the communication interface being coupled to the processor, characterized in that, The processor is used to run programs or instructions, and when the processor executes the programs or instructions, it implements the control method of the switching power supply system as described in any one of claims 1-4.

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