Digital tuned filter, digital tuned filtering method and electronic equipment

Abstract

The invention discloses a digital tuned filter, a digital tuned filtering method and electronic equipment. The digital tuned filter comprises a data interface, a tuning module and a power supply module windowing structure. The data interface is used for receiving information data and a trigger signal; the tuning module is respectively connected with the communication interface and the trigger signal interface, and is used for calculating an address code according to the received information data and preparing a new parameter in a table look-up mode, and is used for responding to the trigger signal and switching to the new parameter and establishing a new filtering state; the power supply module is connected with the tuning module and is used for providing working voltage for the tuning module; and the windowing structure is arranged at the bottom of the digital tuned filter. The tuning performance and reliability of the digital tuned filter can be improved.

Description

Technical Field

[0001] This invention relates to the field of tuning filters, and more particularly to a digital tuning filter, a digital tuning filtering method, and an electronic device. Background Technology

[0002] As a core component of signal processing systems, filters are widely used in fields such as communications, radar, and electronic warfare. Their core function is to extract target frequency band signals from complex electromagnetic environments and suppress out-of-band interference. Traditional filter technologies mainly include fixed-frequency filters and analog tuned filters. However, existing tuned filters rely on voltage-controlled varactor diodes or mechanical adjustments and complex state machine logic, making it difficult to achieve rapid real-time frequency switching.

[0003] It is evident that existing technologies still need improvement and development. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide a digital tuning filter, a digital tuning filtering method and an electronic device, in order to solve the problem that the tuning filter in the prior art is difficult to achieve fast real-time frequency switching.

[0005] The technical solution of the present invention is as follows:

[0006] A digital tuned filter includes: a data interface, a tuning module, a power supply module, and a window structure. The data interface is used to receive information data and trigger signals; the tuning module is connected to the communication interface and the trigger signal interface respectively, and is used to calculate an address code based on the received information data and prepare new parameters by looking up a table, and to switch to the new parameters and establish a new filtering state in response to the trigger signal; the power supply module is connected to the tuning module and is used to provide the operating voltage to the tuning module; the window structure is disposed at the bottom of the digital tuned filter.

[0007] The advantages of the above solution are as follows: This digital tuned filter can complete parameter switching within microseconds through address code calculation and table lookup mechanism of the tuning module. Actual measurements show that the digital tuned filter has the characteristics of low insertion loss, strong out-of-band rejection, and short tuning time. Furthermore, the bottom window structure prevents solder paste from spreading to the device edges, which helps to ensure uniform distribution of molten solder, reduces the risk of edge overflow, and simultaneously improves heat dissipation and electromagnetic shielding effects, reduces vibration interference and electromagnetic radiation during high-frequency operation, and enhances the tuning performance and reliability of the device.

[0008] In a further preferred embodiment, the digital tuning filter includes a data interface comprising: a chip select signal interface, a clock signal interface, a tuning data interface, and a trigger interface; the chip select signal interface is connected to the tuning module and is used to receive a chip select signal; the clock signal interface is connected to the tuning module and is used to receive a clock signal; the tuning data interface is connected to the tuning module and is used to receive tuning data; and the trigger interface is connected to the tuning module and is used to receive a trigger signal, wherein the trigger signal interface integrates a pull-up resistor.

[0009] The advantages of the above solution are as follows: the chip select signal interface connects to the tuning module and can accurately receive the chip select signal; the clock signal interface receives the clock signal, providing a stable timing reference for the entire tuning process and ensuring the synchronization of data transmission and processing; the tuning data interface is used to receive tuning data, making the configuration of filter parameters more targeted and efficient; the trigger interface receives the trigger signal and integrates a pull-up resistor internally. On the one hand, the timing of the tuning operation can be started or controlled by the trigger signal; on the other hand, the integrated design of the pull-up resistor can effectively improve the interface's anti-interference capability, avoid malfunctions of the trigger signal due to external interference, and ensure the reliability and stability of the trigger signal transmission, thereby improving the overall accuracy, stability, and adaptability of the digital tuning filter.

[0010] In a further preferred embodiment, the digital tuning filter includes a chip select signal comprising a falling edge and a rising edge, and a clock signal comprising multiple rising edges and multiple falling edges; wherein the falling edge of the chip select signal occurs earlier than the first rising edge of the clock signal, and the interval between the falling edge of the chip select signal and the first rising edge of the clock signal is greater than or equal to 0.25 μs; the last falling edge of the clock signal occurs earlier than the rising edge of the chip select signal, and the interval between the last falling edge of the clock signal and the rising edge of the chip select signal is greater than or equal to 0.25 μs; in the trigger signal, the time corresponding to the falling edge of the trigger signal is the time to trigger the switching, and the low-level pulse width is greater than or equal to 3 μs; the rising edge of the chip select signal occurs earlier than the falling edge of the trigger signal, and the interval between the rising edge of the chip select signal and the falling edge of the trigger signal is greater than or equal to 3 μs.

[0011] The above scheme achieves the following effects: The design of the chip select signal's falling edge preceding the first rising edge of the clock signal with an interval ≥0.25μs improves the timing consistency between module selection and clock synchronization, reducing clock signal misreception caused by selection delay; the last falling edge of the clock signal preceding the rising edge of the chip select signal with an interval ≥0.25μs helps ensure chip select is deselected only after data transmission is complete, reducing parameter configuration errors caused by chip select failure during data transmission. The trigger signal uses the falling edge as the switching trigger point with a low-level pulse width ≥3μs, reducing false triggering due to glitches through sufficient pulse width; and the timing setting of the chip select signal's rising edge preceding the falling edge of the trigger signal with an interval ≥3μs, by setting a time margin between chip select deselection and trigger switching, reduces the triggering of switching operations when the chip select state is not fully released. Thus, through the timing coordination and time threshold limitation of each signal, the anti-interference capability and operational accuracy of the digital tuning filter during parameter configuration and state switching are effectively improved.

[0012] In a further preferred embodiment, the digital tuning filter includes a tuning module that acquires the tuning center frequency, lowest frequency, highest frequency, and total number of steps within the frequency band based on the information data; calculates an address code based on the tuning center frequency, lowest frequency, highest frequency, and total number of steps within the frequency band; if the calculated address code has decimal places, it is rounded to an integer to obtain an integer address code; and the integer address code is converted into a binary address code.

[0013] The formula for calculating the address code is:

[0014] D = [(f x -f low ) / (f high -f low )]×N;

[0015] f x f is the tuning center frequency within the frequency band. low f is the lowest frequency within the frequency band. high is the highest frequency in the frequency band, and N is the total number of steps in the frequency band.

[0016] The above scheme achieves the following results: It extracts the tuning center frequency, lowest frequency, highest frequency, and total number of steps within the frequency band from the information data. The formula for calculating the address code performs a linear mapping transformation of the frequency parameters, enabling rapid frequency conversion. Rounding is applied to the decimal places of the calculation results, ensuring address code accuracy while converting floating-point operation results into integer form. This adapts to the integer addressing mechanism of digital systems, reducing addressing failures caused by decimal errors. Converting the integer address code to binary form further conforms to the signal transmission format of digital circuits, facilitating rapid execution of subsequent table lookup operations.

[0017] In a further preferred embodiment, the digital tuning filter wherein the binary address code is an 8-bit binary address code, wherein the 8th bit of the 8-bit binary address code is used for frequency band selection, and the frequency band is 1300-1700MHz when D8=0, and the frequency band is 1700-1950MHz when D8=1.

[0018] The advantages of the above scheme are as follows: This digital tuning filter, by defining the 8th bit of the 8-bit binary address code as the frequency band selection bit, can achieve efficient switching and precise control of dual-band filtering. When D8=0, the address code corresponds to the 1300-1700MHz frequency band. The remaining 7 bits of the 8-bit address code can be used for fine-grained addressing of frequency steps within the band. Integrating frequency band selection and frequency addressing into the same address code structure allows the tuning module to simultaneously determine the target frequency band and the specific frequency point within the band by parsing the binary bits of the address code. This reduces the number of external control signals, improves system integration, and the logical judgment of the binary bits can be executed quickly through digital circuits, ensuring the real-time performance of frequency band switching and frequency tuning.

[0019] In a further preferred embodiment, the digital tuning filter includes a power supply module comprising a power supply voltage circuit, a tuning voltage circuit, and a common ground circuit; the power supply circuit provides a voltage of 3.3V, and the tuning circuit provides a voltage of 28V.

[0020] The advantages of the above solution are as follows: This invention employs a dual-voltage domain power supply scheme. The power supply circuit provides 3.3V to match the operating voltage requirements of the tuning module, ensuring stable operation of digital processing processes such as address code calculation and parameter lookup. The tuning voltage circuit provides 28V to provide sufficient driving capability for the tuning components in the filter network, ensuring the component response speed and state stability during filter parameter switching in the high-frequency band (1300–1950MHz). This invention's circuit can eliminate potential difference interference between different voltage domains, effectively reducing the impact of ground loop noise on filter characteristics. It improves the power supply reliability of the digital tuning filter during parameter calculation, frequency band switching, and filter state establishment, enhancing the stability and anti-interference capability of the equipment when operating over a wide frequency band.

[0021] In a further preferred embodiment, the digital tuning filter wherein the window structure is rectangular, the window structure is located in the bottom center region of the digital tuning filter, the length of the window structure is 5mm, the width of the window structure is 5mm, the digital tuning filter is a rectangular digital tuning filter, the length of the digital tuning filter is 25mm, and the width of the digital tuning filter is 24mm.

[0022] The advantages of the above solution are as follows: the window structure can absorb excess solder paste during reflow soldering, preventing it from spreading to the device edges or non-soldered areas and ensuring soldering reliability; placing the window at the bottom center (the device is 25mm long and 24mm wide, and the geometric position of the central area can be achieved through symmetrical layout) utilizes the synergistic effect of gravity and surface tension to evenly distribute molten solder across the pad area, reducing the risk of edge overflow; the 5mm×5mm rectangular window is proportionally reasonable to the overall device size (25mm×24mm), providing sufficient solder absorption area without excessively occupying wiring space. Furthermore, the grounding pad enhances the mechanical connection strength between the device and the circuit board, reduces vibration interference during high-frequency operation, and improves the device's heat dissipation and electromagnetic shielding through a large-area grounding plane. Therefore, while solving soldering process problems, it also improves the overall reliability and electrical performance of the digital tuned filter.

[0023] In a further preferred embodiment, the digital tuning filter has DC blocking capacitors connected to both its input and output terminals; the bottom region of the digital tuning filter is a non-trace region.

[0024] The above solution achieves the following effects: Connecting DC blocking capacitors at the input and output terminals blocks the influence of DC components on the filter network, ensuring the tuning module accurately switches filter parameters based on AC signal characteristics (e.g., the 1300–1950 MHz band), while simultaneously isolating DC bias voltage from the preceding or following circuits. By designating the bottom area as a non-trace area, the digital tuned filter avoids electrical interference between traces and components, ensuring the integrity of the grounding pad and a low-impedance grounding path, thus improving ground potential stability during high-frequency signal filtering. Connecting DC blocking capacitors at the input and output terminals blocks the influence of DC components on the filter network, ensuring the tuning module accurately switches filter parameters based on AC signal characteristics and preventing damage to power devices due to DC overload.

[0025] In a further preferred embodiment, the digital tuning filter, wherein the tuning module includes: a tuning chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor. The tuning chip has a first pin, a second pin, a third pin, a fourth pin, and a fifth pin. The first end of the first resistor is connected to the first pin, and the second end of the first resistor is connected to a trigger interface. The first end of the second resistor is connected to the second pin, and the second end of the second resistor is connected to a clock signal interface. The first end of the third resistor is connected to the third pin, and the second end of the third resistor is connected to a tuning data interface. The first end of the fourth resistor is connected to the fourth pin, and the second end of the fourth resistor is connected to a chip select signal interface. The first end of the fifth resistor is connected to the fifth pin, and the second end of the fifth resistor is connected to a power supply module. The first end of the first capacitor is connected to the second end of the first resistor, and the second end of the first capacitor is grounded. The first end of the second capacitor is connected to the second end of the second resistor, and the second end of the second capacitor is grounded. The first end of the third capacitor is connected to the second end of the third resistor, and the second end of the third capacitor is grounded. The first end of the fourth capacitor is connected to the second end of the fourth resistor, and the second end of the fourth capacitor is grounded. The first end of the fifth capacitor is connected to the second end of the fifth resistor, and the second end of the fifth capacitor is grounded. The first end of the sixth capacitor is connected to the second end of the fifth resistor, and the second end of the sixth capacitor is grounded.

[0026] The above scheme achieves the following effects: The first to fourth resistors are connected in series between the trigger interface, clock signal interface, tuning data interface, and chip select signal interface and the tuning chip pins, respectively, providing impedance matching and reducing reflections and distortion during signal transmission. The first to fourth capacitors are connected in parallel between each signal interface and ground, forming a filter network that effectively filters out high-frequency noise, ensuring the purity of the input signal. The fifth resistor is connected in series between the tuning chip's power supply pin and the power supply module, limiting current and working in conjunction with the decoupling network formed by the fifth and sixth capacitors. The fifth capacitor filters out low-frequency ripple, while the sixth capacitor handles high-frequency transient current demands, jointly ensuring the stability of the power supply voltage. This combination of resistors and capacitors with the tuning chip achieves signal buffering and protection through resistors, and high-frequency noise suppression and power supply decoupling through capacitors. This allows the tuning module to more reliably receive control signals and stably execute parameter switching when operating at high frequencies of 1300–1950MHz, improving the overall stability and anti-interference capability of the digital tuning filter.

[0027] A digital tuning filter method includes: acquiring information data and a trigger signal; calculating an address code based on the received information data and preparing new parameters by looking up a table; and switching to the new parameters and establishing a new filtering state in response to the trigger signal.

[0028] The above scheme has the following advantages: through the address code calculation and table lookup mechanism of the tuning module, parameter switching can be completed in microseconds. Actual tests show that the digital tuning filter has the characteristics of low insertion loss, strong out-of-band rejection, and short tuning time.

[0029] An electronic device includes a digital tuning filter as described above and an MCU connected to the digital tuning filter.

[0030] The above solution achieves the following results: the MCU sends information data to the digital tuning filter and accurately transmits the address code under clock signal synchronization. After receiving the data, the filter pre-stores new parameters through a lookup table mechanism. This asynchronous mode of "data transmission - lookup table preparation" can shorten the parameter call delay, improve the response speed, and enable electronic devices to dynamically adjust the filtering characteristics according to real-time requirements. It is suitable for wireless communication that requires frequent switching of frequency bands or filtering parameters, simplifies the system control logic, and improves the overall integration and working stability.

[0031] Compared with existing technologies, the digital tuned filter of this invention can complete parameter switching within microseconds through address code calculation and table lookup mechanism of the tuning module. Experimental results show that the digital tuned filter has the characteristics of low insertion loss, strong out-of-band rejection, and short tuning time. Furthermore, the bottom window structure prevents solder paste from spreading to the device edges, ensuring soldering reliability, promoting uniform distribution of molten solder, reducing the risk of edge overflow, and simultaneously improving heat dissipation and electromagnetic shielding effects. This reduces vibration interference and electromagnetic radiation during high-frequency operation, enhancing the electrical performance of the device. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the connection relationship of the tuning module in one embodiment of the present invention.

[0033] Figure 2 This is a schematic diagram of the appearance of a digital tuning filter according to one embodiment of the present invention.

[0034] Figure 3 This is a schematic diagram of the working timing of the tuning module in one embodiment of the present invention.

[0035] Figure 4 This is a partial circuit diagram of the tuning module in one embodiment of the present invention. Detailed Implementation

[0036] This embodiment provides a digital tuning filter, a digital tuning filtering method, and an electronic device. To make the objectives, technical solutions, and effects of this embodiment clearer and more explicit, the following detailed description is provided with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this embodiment.

[0037] Please see Figure 1 , Figure 1 This example describes a digitally tuned filter. The digitally tuned filter includes: a data interface 10, a tuning module 20, and a power supply module 30. The data interface 10 receives information data and trigger signals; the tuning module 20 is connected to the communication interface and the trigger signal interface, respectively, and is used to calculate the address code based on the received information data and prepare new parameters using a lookup table, and to switch to the new parameters and establish a new filtering state in response to the trigger signal; the power supply module 30 is connected to the tuning module 20 and provides operating voltage to the tuning module 20; a window structure is located at the bottom of the digitally tuned filter.

[0038] Data interface 10 serves as the signal input channel, transmitting data to the tuning module 20 via the communication interface. The trigger signal interface receives low-level pulses (TRIG signals) from the MCU, providing the instruction source for parameter calculation and state switching, respectively. The tuning module 20 is the filter's processing center, interacting with data interface 10 via circuit connection. After receiving data, it calculates the address code based on a formula and pre-stores new parameters using a lookup table. When the trigger signal arrives, it immediately switches to the new parameters and establishes the filtering state. Power supply module 30 provides power to the tuning module 20. The bottom window structure is a key design feature of the physical layout, absorbing excess solder paste to prevent solder spread and short circuits, and also improving heat dissipation and electromagnetic shielding.

[0039] The information received by data interface 10 drives tuning module 20 to calculate address code and prepare parameters. A trigger signal controls the timing of parameter switching, and power supply module 30 provides stable power for this process. The bottom window structure ensures the reliability of component soldering from a process perspective and improves electrical performance through grounding design. In wireless communication equipment, the MCU sends frequency band parameters through data interface 10. Tuning module 20 calculates and prepares new filter parameters, and the frequency band is switched after the trigger signal is issued. Power supply module 30 ensures stable operation of all components, and the bottom window structure ensures the reliability of components during high-frequency soldering and operation.

[0040] Please see Figure 2 , Figure 2 This is a schematic diagram of the appearance of a digitally tuned filter according to one embodiment of the present invention. This digitally tuned filter, through the address code calculation and lookup table mechanism of the tuning module 20, can complete parameter switching within microseconds. Actual measurements show that the digitally tuned filter has the characteristics of low insertion loss, strong out-of-band rejection, and short tuning time. Furthermore, the bottom window structure prevents solder paste from spreading to the device edges, ensuring soldering reliability, facilitating uniform distribution of molten solder, reducing the risk of edge overflow, and simultaneously improving heat dissipation performance and electromagnetic shielding effect, reducing vibration interference and electromagnetic radiation during high-frequency operation, and enhancing the tuning performance and reliability of the device.

[0041] In a further preferred embodiment, the digital tuning filter includes a data interface 10 comprising: a chip select signal interface, a clock signal interface, a tuning data interface 10, and a trigger interface; the chip select signal interface is connected to the tuning module 20 and is used to receive a chip select signal; the clock signal interface is connected to the tuning module 20 and is used to receive a clock signal; the tuning data interface 10 is connected to the tuning module 20 and is used to receive tuning data; and the trigger interface is connected to the tuning module 20 and is used to receive a trigger signal, wherein the trigger signal interface integrates a pull-up resistor.

[0042] The chip select signal interface, clock signal interface, and tuning data interface 10 are all serial peripheral interfaces. The chip select signal interface receives the chip select signal from the MCU. When the chip select signal is valid, the tuning module 20 is activated and ready to receive subsequent data. The clock signal interface receives the clock signal from the MCU, providing a timing reference for the synchronous transmission of tuning data. The tuning module 20 samples data based on the rising or falling edge of the clock signal to ensure correct data reception. The tuning data interface 10 is a parameter configuration information channel that receives tuning data from the MCU. These interfaces are connected to the tuning module 20 and are used to receive information data, which includes three-wire data: the chip select signal, the clock signal, and the tuning data.

[0043] The trigger interface is used to receive trigger signals from the MCU. The trigger signal is a low-level signal. An internally integrated pull-up resistor ensures that the interface remains high when there is no signal input, preventing false triggering; when the falling edge of the trigger signal arrives, the tuning module 20 immediately switches to the pre-stored new parameters.

[0044] This invention employs a three-wire connection mechanism (three wires: CS, CLK, MOSI), with a trigger mechanism of a low-level TRIG signal. Specifically, the MCU first selects the filter using a chip select signal, then synchronously sends tuning data via a clock signal. The tuning module 20 calculates the address code and prepares new parameters. Subsequently, the MCU sends a low-level trigger signal, and the filter immediately switches to the new frequency band, completing the dynamic adjustment of the communication frequency.

[0045] The chip select signal interface connects to the tuning module 20 and can accurately receive the chip select signal; the clock signal interface receives the clock signal, providing a stable timing reference for the entire tuning process and ensuring the synchronization of data transmission and processing; the tuning data interface 10 is used to receive tuning data, making the configuration of filter parameters more targeted and efficient; the trigger interface receives the trigger signal and integrates a pull-up resistor internally. On the one hand, the timing of the tuning operation can be started or controlled by the trigger signal; on the other hand, the integrated design of the pull-up resistor can effectively improve the interface's anti-interference capability, avoid the trigger signal from malfunctioning due to external interference, and ensure the reliability and stability of the trigger signal transmission, thereby improving the overall accuracy, stability, and adaptability of the digital tuning filter.

[0046] In a further preferred embodiment, the digital tuning filter includes a chip select signal comprising a falling edge and a rising edge, and a clock signal comprising multiple rising edges and multiple falling edges; wherein the falling edge of the chip select signal occurs earlier than the first rising edge of the clock signal, and the interval between the falling edge of the chip select signal and the first rising edge of the clock signal is greater than or equal to 0.25 μs; the last falling edge of the clock signal occurs earlier than the rising edge of the chip select signal, and the interval between the last falling edge of the clock signal and the rising edge of the chip select signal is greater than or equal to 0.25 μs; in the trigger signal, the time corresponding to the falling edge of the trigger signal is the time to trigger the switching, and the low-level pulse width is greater than or equal to 3 μs; the rising edge of the chip select signal occurs earlier than the falling edge of the trigger signal, and the interval between the rising edge of the chip select signal and the falling edge of the trigger signal is greater than or equal to 3 μs.

[0047] The ChipSelect (CS) signal selects the tuning module 20 when it is active low, putting it into data reception mode. The timing characteristics of the ChipSelect signal are as follows: it includes a falling edge and a rising edge, and must meet the following conditions: the falling edge is ≥0.25μs earlier than the first rising edge of the clock, meaning the MCU pulls CS low before sending the clock signal to ensure the module has sufficient time to respond to the activation command; the rising edge is ≥0.25μs later than the last falling edge of the clock, so CS is pulled high only after data transmission is complete to avoid data loss due to deselection during transmission.

[0048] The clock signal (Clock, CLK) serves as the timing reference for data transmission, synchronizing data sampling through rising and falling edges. Clock signal timing characteristics: It consists of multiple pulses (e.g., 8 clock cycles per byte in SPI communication), and the falling edge of the last pulse must be at least 0.25 μs apart from the rising edge of the chip select to ensure stable data latching.

[0049] The trigger signal (TRIG) serves as the execution command for parameter switching. It is triggered by a falling edge, with a low-level pulse width ≥3μs to prevent accidental triggering by interference pulses. Timing characteristics of the trigger signal: the falling edge must be ≥3μs later than the chip select rising edge to prevent the module from performing switching before data reception is complete.

[0050] The MCU first pulls the chip select signal low (falling edge), activating the tuning module 20 and waiting to receive data. At least 0.25μs later, the MCU sends the first rising edge of the clock signal to begin synchronously transmitting tuning data. The clock signal drives the tuning data interface 10 according to the agreed timing. The tuning module 20 samples data based on the clock edge to complete address code reception. After data transmission is complete, the clock signal generates its last falling edge, at which point the module has completed address code parsing and lookup preparation. At least 0.25μs after the last falling edge of the clock, the MCU pulls the chip select signal high (rising edge), canceling the module's selection state. At least 3μs later, the MCU sends the falling edge of the trigger signal (low-level pulse width ≥ 3μs), triggering the module and switching to the new parameters.

[0051] Optionally, the communication interface is a serial peripheral interface, a three-wire system (CS, CLK, MOSI). Signal transmission parameters include: MSB priority in transmission direction, maximum speed of 8Mb / s, transmission mode MODE0 (phase 0, rising edge), and data length of 16 bits.

[0052] Please see Figure 3 The diagram includes four signal lines: CS (chip select), CLK (clock), MOSI (data output), and TRIG (trigger). The CS signal is used for communication selection, CLK provides a synchronization clock, MOSI transmits 16-bit data, and TRIG is the signal that triggers the switching of filter parameters. Specifically, t3 requires a ≥3μs interval between the rising edge of CS and the falling edge of TRIG to ensure stable execution of the trigger action after chip select release; t4 specifies a ≥3μs duration for the low-level pulse of TRIG to ensure the trigger signal is valid; t5 requires the falling edge of CS to precede the first rising edge of CLK by ≥0.25μs to prepare for data transmission; and t6 requires a ≥0.25μs interval between the sixteenth falling edge of CLK and the rising edge of CS to ensure complete data transmission before chip select is released. These timing constraints ensure the stability and data accuracy of communication between the digital tuned filter and the MCU, allowing the filter to accurately switch filter parameters according to MCU instructions.

[0053] The design of the chip select signal's falling edge preceding the first rising edge of the clock signal with an interval of ≥0.25μs improves the timing consistency between module selection and clock synchronization, reducing clock signal misreception caused by selection delay. Similarly, the clock signal's last falling edge preceding the chip select signal's rising edge with an interval of ≥0.25μs ensures chip select is deselected only after data transmission is complete, reducing parameter configuration errors caused by chip select failure during data transmission. The trigger signal uses the falling edge as the switching trigger point with a low-level pulse width of ≥3μs, reducing false triggering due to glitches. The timing setting of the chip select signal's rising edge preceding the trigger signal's falling edge with an interval of ≥3μs provides a time margin between chip select deselection and trigger switching, reducing the risk of triggering switching operations before the chip select state is fully released. Thus, through the timing coordination and time threshold limitation of each signal, the anti-interference capability and operational accuracy of the digital tuning filter during parameter configuration and state switching are effectively improved.

[0054] In a further preferred embodiment, the digital tuning filter includes a digitally adjustable time interval between the falling edge of the chip select signal and the first rising edge of the clock signal. The time interval between the last falling edge of the clock signal and the rising edge of the chip select signal is also dynamically adjustable. The time intervals cannot be too large, otherwise it will affect the efficiency of the digital tuning filter. The specific steps are as follows:

[0055] Step 10: When the system starts up, configure the initial timing parameters according to the recommended values ​​in the device manual.

[0056] Step 11: Automatically initiate parameter optimization once every k data transmissions (e.g., k=1000); trigger optimization immediately when signal quality degradation (e.g., bit error rate exceeds threshold) or power consumption anomalies are detected.

[0057] Step 12: Fine-tune the parameter Δt for each time interval (e.g., Δt = 0.05 μs); after each fine-tuning, collect the filter's operating status (e.g., signal strength, out-of-band rejection, power consumption, and time consumption) through the feedback monitoring circuit, and calculate the efficiency score. The efficiency score is positively correlated with signal strength and out-of-band rejection, and negatively correlated with power consumption and time consumption.

[0058] Alternatively, the present invention may calculate the fine-tuning value using the following method.

[0059] Δt=λ(Δp i / Δp i-1 )×Δt i-1 / [(tt max (tt) min )]

[0060] Where Δt is the current fine-tuning value, and the next time interval parameter is t + Δt. i is the number of parameter optimization attempts, and Δp... i and Δp i-1 Δt represents the difference between the efficiency score of the i-th iteration and the efficiency score of the (i-1)-th iteration, and the difference between the efficiency score of the (i-1)-th iteration and the efficiency score of the (i-2)-th iteration, respectively. i-1 This is the (i-1)th fine-tuning value, i.e., the previous fine-tuning value of Δt. t is the current time interval parameter. max Let t be the maximum value of t. min λ is the minimum value of t. λ is an adjustment coefficient, adjusted according to the actual situation. t in the formula cannot be the maximum or minimum value.

[0061] Step 13: Select the parameter combination that gives the highest efficiency score and update the timer configuration.

[0062] The present invention also sets lower limits for timing parameters (e.g., t5≥0.2μs, t6≥0.2μs, t3≥2.5μs) to prevent signal transmission errors due to excessively small parameters; and sets upper limits for timing parameters (e.g., t5≤0.5μs, t6≤0.5μs, t3≤5μs) to avoid reduced working efficiency due to excessively large parameters.

[0063] In a further preferred embodiment, the digital tuning filter includes a tuning module 20 that acquires the tuning center frequency, lowest frequency, highest frequency, and total number of steps within the frequency band based on the information data; calculates an address code based on the tuning center frequency, lowest frequency, highest frequency, and total number of steps within the frequency band; if the calculated address code has decimal places, it is rounded to an integer to obtain an integer address code; and the integer address code is converted into a binary address code.

[0064] The formula for calculating the address code is:

[0065] D = [(f x -f low ) / (f high -f low )]×N;

[0066] f x f is the tuning center frequency within the frequency band. low f is the lowest frequency within the frequency band. high is the highest frequency in the frequency band, and N is the total number of steps in the frequency band.

[0067] The tuning center frequency (f) within the frequency band x The center frequency of the target filtering band (e.g., 1500MHz) represents the desired signal processing frequency; the lowest frequency within the band (f) lowThe lower limit of the frequency band (e.g., 1300MHz) defines the starting boundary of the frequency range; the highest frequency within the band (f) high The upper limit of the frequency band (e.g., 1700MHz) defines the termination boundary of the frequency range; the total number of steps (N) within the frequency band is the number of discrete frequency points that can be divided within the frequency band (e.g., N = 256), which determines the frequency resolution.

[0068] Specifically, the trigger parameter is the TRIG pin, which is internally pulled up and triggered on the falling edge. Operating principle: 1. The customer MCU sends data to the module via SPI. After receiving the data, the module looks up a table to prepare new parameters. 2. The customer MCU sends a low-level pulse to the TRIG pin, and the module immediately establishes a new state using the new parameters. 3. Address code calculation: Address code = [(f x -f low ) / (f high -f low )]×250;f x f is the tuning center frequency within the frequency band. low f is the lowest frequency within the segment. high The highest frequency within the segment is 250, and the total number of steps within the segment is 250. If the calculated result has decimal places, it should be rounded to an integer. For example: center frequency f x =1400MHz, address code = [(1400-1300) / (1700-1300)]×250 = 62.5, rounded to approximately 63, converted to binary code 00111111. 4. D8 = 0, 1300~1700MHz, D8 = 1, 1700~1950MHz. Rounding reduces the accumulation of decimal errors and enhances system stability; binary encoding facilitates digital circuit processing and reduces noise interference during transmission.

[0069] The tuning center frequency, lowest frequency, highest frequency, and total number of steps within the frequency band are extracted from the information data. A linear mapping relationship is then established for the frequency parameters in the address code calculation formula, enabling rapid frequency conversion. Rounding is applied to the decimal places of the calculation results to ensure address code accuracy while converting floating-point arithmetic results into integer form, adapting to the integer addressing mechanism of digital systems and reducing addressing failures caused by decimal errors. Converting the integer address code to binary form further conforms to the signal transmission format of digital circuits, facilitating rapid execution of subsequent table lookup operations.

[0070] In a further preferred embodiment, the digital tuning filter wherein the binary address code is an 8-bit binary address code, wherein the 8th bit of the 8-bit binary address code is used for frequency band selection, and the frequency band is 1300-1700MHz when D8=0, and the frequency band is 1700-1950MHz when D8=1.

[0071] In the binary address code (D1~D8), the highest bit D8 is used as the frequency band selection bit, and the remaining 7 bits (D1~D7) are used for frequency step addressing within the frequency band. When the tuning module 20 receives the 8-bit address code: if D8=0, the module automatically switches to the parameter table for the 1300~1700MHz frequency band; if D8=1, it switches to the parameter table for the 1700~1950MHz frequency band. The lower 7 bits are converted to decimal values, multiplied by the frequency resolution of the corresponding frequency band, and added to the starting frequency of the frequency band to obtain the actual tuning frequency.

[0072] The digital tuning filter defines the 8th bit of the 8-bit binary address code as the band selection bit, enabling efficient switching and precise control of dual-band filtering. When D8 = 0, the address code corresponds to the 1300–1700 MHz band. The remaining 7 bits of the 8-bit address code can be used for fine-grained addressing of frequency steps within the band. Integrating band selection and frequency addressing into the same address code structure allows the tuning module 20 to simultaneously determine the target band and specific frequency points within the band by parsing the binary bits of the address code. This reduces the number of external control signals, improves system integration, and ensures real-time performance of band switching and frequency tuning through rapid execution of the binary bit logic judgments via digital circuits.

[0073] In a further preferred embodiment, the digital tuning filter includes a power supply module 30 comprising a power supply voltage circuit, a tuning voltage circuit, and a common ground circuit; the power supply circuit provides a voltage of 3.3V, and the tuning circuit provides a voltage of 28V.

[0074] The 3.3V power supply circuit is the Vcc power supply circuit, which powers the digital chips (such as logic controllers and arithmetic units) within the tuning module 20, meeting their low-power operating requirements and ensuring stable operation of digital processing processes such as address code calculation and parameter lookup. The 28V voltage circuit is the Vbb tuning voltage circuit, which mainly powers the analog components in the filter network, ensuring the component response speed when switching filter parameters in the 1300-1950MHz high-frequency band. The common ground circuit (GND) ensures that the 3.3V digital ground and the 28V power ground form a unified potential reference, eliminating potential difference interference between different voltage domains and avoiding signal distortion caused by ground loop noise.

[0075] This invention employs a dual-voltage-domain power supply scheme. The power supply circuit provides 3.3V to meet the operating voltage requirements of the tuning module 20, ensuring stable operation of digital processing processes such as address code calculation and parameter lookup. The tuning voltage circuit provides 28V to provide sufficient driving capability for the tuning components in the filter network, ensuring the component response speed and state stability during filter parameter switching in the high-frequency band (1300–1950MHz). This circuit eliminates potential difference interference between different voltage domains, effectively reducing the impact of ground loop noise on filter characteristics. It enhances the power supply reliability of the digital tuning filter during parameter calculation, frequency band switching, and filter state establishment, improving the stability and anti-interference capability of the equipment during wide-band operation.

[0076] In a further preferred embodiment, the digital tuning filter wherein the window structure is rectangular, the window structure is located in the bottom center region of the digital tuning filter, the length of the window structure is 5mm, the width of the window structure is 5mm, the digital tuning filter is a rectangular digital tuning filter, the length of the digital tuning filter is 25mm, and the width of the digital tuning filter is 24mm.

[0077] The 5mm×5mm rectangular window structure at the bottom of the digital tuned filter, located in the center of the 25mm×24mm rectangular device, can absorb excess solder paste during reflow soldering, enhancing the ground potential stability during high-frequency signal filtering. Simultaneously, the large grounding plane improves the device's heat dissipation and electromagnetic shielding performance. The rectangular window structure can also serve as a grounding pad.

[0078] The window structure absorbs excess solder paste during reflow soldering, preventing it from spreading to device edges or non-soldered areas and ensuring soldering reliability. Positioning the window at the bottom center (device length 25mm, width 24mm; the central area's geometry can be achieved through symmetrical layout) utilizes the synergistic effect of gravity and surface tension to evenly distribute molten solder across the pad area, reducing the risk of edge overflow. The 5mm × 5mm rectangular window's proportion to the overall device size (25mm × 24mm) is reasonable, providing sufficient solder absorption area without excessively occupying wiring space. Furthermore, this grounding pad enhances the mechanical connection between the device and the circuit board, reduces vibration interference during high-frequency operation, and improves heat dissipation and electromagnetic shielding through a large grounding plane. Thus, while addressing soldering process issues, it also improves the overall reliability and electrical performance of the digital tuned filter.

[0079] In a further preferred embodiment, the digital tuning filter has DC blocking capacitors connected to both its input and output terminals; the bottom region of the digital tuning filter is a non-trace region.

[0080] The bottom region of a digitally tuned filter may overlap with the windowed structure. The bottom region of a digitally tuned filter includes the windowed structure, or in other words, the windowed structure is part of the first portion of the bottom region of the digitally tuned filter.

[0081] Digital tuned filters require DC blocking capacitors at both the input and output. No traces are allowed on the bottom layer of the digital tuned filter. The DC blocking capacitors at the input and output utilize the "DC blocking, AC passing" characteristic to block DC components from entering the filter network. This prevents DC bias from the preceding circuitry from interfering with the bias state of the varactor diodes, ensuring that high-frequency signals in the 1300–1950MHz range pass through without attenuation. Simultaneously, it isolates the DC potential difference between the preceding and following circuits, preventing power devices from being damaged by overload. The non-trace area at the bottom reduces interference caused by bottom-layer traces, improving the stability of the high-frequency signal ground potential.

[0082] Connecting DC blocking capacitors at the input and output terminals blocks the influence of DC components on the filter network, ensuring that the tuning module 20 accurately switches filter parameters based on AC signal characteristics, while also isolating DC bias voltage from the preceding or following circuits. By designating the bottom area as a non-trace area, the digital tuning filter avoids interference between traces and components, ensuring the integrity of the grounding pad and a low-impedance grounding path, thus improving ground potential stability during high-frequency signal filtering. Connecting DC blocking capacitors at the input and output terminals blocks the influence of DC components on the filter network, ensuring that the tuning module 20 accurately switches filter parameters based on AC signal characteristics (e.g., the 1300–1950MHz frequency band), and preventing power devices from being damaged by DC overload.

[0083] For further optimization, please refer to Figure 4The tuning module 20 includes: a tuning chip U3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6. The tuning chip U3 has a first pin, a second pin, a third pin, a fourth pin, and a fifth pin. The first end of the first resistor R1 is connected to the first pin, and the second end of the first resistor R1 is connected to a trigger interface. The first end of the second resistor R2 is connected to the second pin, and the second end of the second resistor R2 is connected to a clock signal interface. The first end of the third resistor R3 is connected to the third pin, and the second end of the third resistor R3 is connected to a tuning data interface 10. The first end of the fourth resistor R4 is connected to the fourth pin, and the second end of the fourth resistor R4 is connected to a chip select signal interface. The first end of the fifth resistor R5 is connected to the fifth pin, and the second end of the fifth resistor R5 is connected to a power supply module 3. 0 connection; the first terminal of the first capacitor C1 is connected to the second terminal of the first resistor R1, and the second terminal of the first capacitor C1 is grounded; the first terminal of the second capacitor C2 is connected to the second terminal of the second resistor R2, and the second terminal of the second capacitor C2 is grounded; the first terminal of the third capacitor C3 is connected to the second terminal of the third resistor R3, and the second terminal of the third capacitor C3 is grounded; the first terminal of the fourth capacitor C4 is connected to the second terminal of the fourth resistor R4, and the second terminal of the fourth capacitor C4 is grounded; the first terminal of the fifth capacitor C5 is connected to the second terminal of the fifth resistor R5, and the second terminal of the fifth capacitor C5 is grounded; the first terminal of the sixth capacitor C6 is connected to the second terminal of the fifth resistor R5, and the second terminal of the sixth capacitor C6 is grounded.

[0084] Four resistors (R1-R4) are connected in series in the trigger, clock, tuning data, and chip select signal paths, forming an impedance matching network. This reduces signal reflections and limits the current flowing into the chip pins, protecting the tuning chip U3 from transient high-voltage surges. Capacitors (C1-C4) connected in parallel to ground at each signal input form an RC low-pass filter, filtering out high-frequency noise (such as RF interference) and improving signal quality. Resistor R5 contributes to circuit stability. The two sets of parallel capacitors (C5, C6) at the power supply end use different capacitance combinations (e.g., C5 = 10μF to filter low-frequency ripple, C6 = 0.1μF to compensate for high-frequency transient current), forming a multi-stage decoupling network to ensure the stability of the 3.3V power supply voltage and reduce the impact of power supply noise on chip operation. This circuit structure enables the tuning module 20 to have stronger anti-interference capabilities in high-frequency environments. For example, when operating in the 1950MHz band, C1-C4 can effectively attenuate noise above the cutoff frequency, while C5-C6 suppresses power fluctuations, which helps ensure that the tuning chip U3 accurately calculates the address code and stably switches the filter parameters.

[0085] The first to fourth resistors R4 are connected in series between the trigger interface, clock signal interface, tuning data interface 10, and chip select signal interface and the pins of the tuning chip U3, respectively. This provides impedance matching, reducing reflections and distortion during signal transmission. The first to fourth capacitors C4 are connected in parallel between each signal interface and ground, forming a filter network that effectively filters out high-frequency noise, ensuring the purity of the input signal. The fifth resistor R5 is connected in series between the power supply pin of the tuning chip U3 and the power supply module 30. This limits the current and, together with the decoupling network formed by the fifth and sixth capacitors C6, filters out low-frequency ripple, while the sixth capacitor C6 handles high-frequency transient current demands, jointly ensuring the stability of the power supply voltage. This combination of resistors and capacitors with the tuning chip U3 achieves signal buffering and protection through resistors, and high-frequency noise suppression and power supply decoupling through capacitors. This allows the tuning module 20 to more reliably receive control signals and stably execute parameter switching when operating at high frequencies of 1300–1950MHz, improving the overall stability and anti-interference capability of the digital tuning filter.

[0086] A digital tuning filter method includes: acquiring information data and a trigger signal; calculating an address code based on the received information data and preparing new parameters by looking up a table; and switching to the new parameters and establishing a new filtering state in response to the trigger signal.

[0087] The principle of the digital tuning filter method of this invention can be found in the above description of the relevant modules in the digital tuning filter, so it will not be repeated here.

[0088] Through the address code calculation and table lookup mechanism of the tuning module, parameter switching can be completed in microseconds. Experimental results show that the digital tuned filter has the characteristics of low insertion loss, strong out-of-band rejection, and short tuning time.

[0089] An electronic device includes a digital tuning filter as described above and an MCU connected to the digital tuning filter.

[0090] The chip select, clock, data, and trigger interfaces of the MCU (Microcontroller Unit) are connected to the filter's data interface 10. The falling edge of the chip select signal precedes the first rising edge of the clock by ≥0.25μs, the interval between the last falling edge of the clock and the rising edge of the chip select signal is ≥0.25μs, and the falling edge of the trigger signal follows the rising edge of the chip select signal by ≥3μs. This strict timing ensures data transmission errors are avoided. As the control core, the MCU sends an address code to the filter through the interface. The most significant bit (D8) of the 8-bit binary address code is used for frequency band selection (D8=0 corresponds to 1300–1700MHz, D8=1 corresponds to 1700–1950MHz), and the remaining 7 bits determine the specific frequency point within the band. After sending data, the MCU outputs a low-level pulse (width ≥3μs) through the TRIG pin to trigger the filter switching parameters, ensuring real-time updates of the filter status within the 1300–1950MHz band.

[0091] The MCU sends information data to the digital tuning filter and accurately transmits address codes under clock signal synchronization. After receiving the data, the filter pre-stores new parameters through a lookup table mechanism, improving the response speed and enabling electronic devices to dynamically adjust the filtering characteristics according to real-time requirements, thereby improving the overall integration and operational stability.

[0092] The technical specifications of the digital tuned filter in this embodiment are shown in the table below.

[0093]

[0094]

[0095] Compared with existing technologies, the digital tuned filter of this invention can complete parameter switching within microseconds through the address code calculation and lookup table mechanism of the tuning module 20. Experimental results show that the digital tuned filter has the characteristics of low insertion loss, strong out-of-band rejection, and short tuning time. Furthermore, the bottom window structure prevents solder paste from spreading to the device edges, which is beneficial for uniform distribution of molten solder, reduces the risk of edge overflow, and simultaneously improves heat dissipation and electromagnetic shielding effects, reduces vibration interference and electromagnetic radiation during high-frequency operation, and enhances the tuning performance and reliability of the device.

[0096] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A digital tuning filter, characterized in that, include: The data interface is used to receive information data and trigger signals. The tuning module is connected to the communication interface and the trigger signal interface respectively. It is used to calculate the address code according to the received information data and prepare new parameters by looking up a table, and to switch to the new parameters and establish a new filtering state in response to the trigger signal. A power supply module, connected to the tuning module, is used to provide operating voltage to the tuning module; A window structure is provided at the bottom of the digital tuning filter.

2. The digital tuning filter according to claim 1, characterized in that, The data interface includes: A chip select signal interface, connected to the tuning module, is used to receive chip select signals; A clock signal interface, connected to the tuning module, is used to receive clock signals; A tuning data interface, connected to the tuning module, is used to receive tuning data; A trigger interface, connected to the tuning module, is used to receive trigger signals. The trigger signal interface integrates a pull-up resistor.

3. The digital tuning filter according to claim 2, characterized in that, The chip select signal includes a falling edge and a rising edge, and the clock signal includes multiple rising edges and multiple falling edges; wherein, the falling edge of the chip select signal occurs earlier than the first rising edge of the clock signal, and the interval between the falling edge of the chip select signal and the first rising edge of the clock signal is greater than or equal to 0.25μs; the last falling edge of the clock signal occurs earlier than the rising edge of the chip select signal, and the interval between the last falling edge of the clock signal and the rising edge of the chip select signal is greater than or equal to 0.25μs. In the trigger signal, the time corresponding to the falling edge of the trigger signal is the time to trigger the switching, and the low-level pulse width is greater than or equal to 3μs; The rising edge of the chip select signal occurs earlier than the falling edge of the trigger signal, and the time interval between the rising edge of the chip select signal and the falling edge of the trigger signal is greater than or equal to 3μs.

4. The digital tuning filter according to claim 1, characterized in that, The tuning module is used to obtain the tuning center frequency, lowest frequency, highest frequency, and total number of steps within the frequency band based on the information data; calculate the address code based on the tuning center frequency, lowest frequency, highest frequency, and total number of steps within the frequency band; if the calculated address code has decimal places, it is rounded to an integer to obtain an integer address code; and convert the integer address code into a binary address code. The formula for calculating the address code is: D=[(f x -f low ) / (f high -f low )]×N; f x f is the tuning center frequency within the frequency band. low f is the lowest frequency within the frequency band. high is the highest frequency in the frequency band, and N is the total number of steps in the frequency band.

5. The digital tuning filter according to claim 4, characterized in that, The binary address code is an 8-bit binary address code, where the 8th bit of the 8-bit binary address code is used for frequency band selection. If D8 = 0, the frequency band is 1300-1700MHz; if D8 = 1, the frequency band is 1700-1950MHz.

6. The digital tuning filter according to claim 1, characterized in that, The power supply module includes: a power supply voltage circuit, a tuning voltage circuit, and a common ground circuit; the power supply circuit provides a voltage of 3.3V, and the tuning circuit provides a voltage of 28V.

7. The digital tuning filter according to claim 1, characterized in that, The window structure is rectangular and located in the bottom center area of ​​the digital tuning filter. The window structure has a length of 5mm and a width of 5mm. The digital tuning filter is a rectangular digital tuning filter with a length of 25mm and a width of 24mm. The digital tuning filter has DC blocking capacitors connected to both its input and output terminals; the bottom region of the digital tuning filter is a non-trace region.

8. The digital tuning filter according to claim 2, characterized in that, The tuning module includes: A tuning chip, wherein the tuning chip is provided with a first pin, a second pin, a third pin, a fourth pin, and a fifth pin; A first resistor, the first end of which is connected to the first pin, and the second end of which is connected to the trigger interface; The second resistor has its first end connected to the second pin and its second end connected to the clock signal interface. The third resistor has its first end connected to the third pin and its second end connected to the tuning data interface. The fourth resistor has its first end connected to the fourth pin and its second end connected to the chip select signal interface. The fifth resistor has its first end connected to the fifth pin and its second end connected to the power supply module. A first capacitor, the first terminal of which is connected to the second terminal of a first resistor, and the second terminal of the first capacitor is grounded; The second capacitor has its first terminal connected to the second terminal of the second resistor, and its second terminal is grounded. The third capacitor has its first terminal connected to the second terminal of the third resistor, and its second terminal is grounded. The fourth capacitor has its first terminal connected to the second terminal of the fourth resistor, and its second terminal is grounded. The fifth capacitor has its first terminal connected to the second terminal of the fifth resistor, and its second terminal is grounded. The sixth capacitor has its first terminal connected to the second terminal of the fifth resistor, and its second terminal is grounded.

9. A digital tuning filtering method, characterized in that, include: Acquire information data and trigger signals; The address code is calculated based on the received information data, and new parameters are prepared by looking up a table, in response to the trigger signal to switch to the new parameters and establish a new filtering state.

10. An electronic device, characterized in that, Includes a digital tuning filter as described in any one of claims 1 to 8 and an MCU connected to the digital tuning filter.

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