Dac array chip and method of digital-to-analog conversion

Abstract

The application relates to the technical field of integrated circuits and provides a digital-to-analog converter array chip and a digital-to-analog conversion method. The digital-to-analog converter array chip comprises a digital module and a digital-to-analog converter array. The digital module comprises an encoder, and the digital-to-analog converter array comprises a decoder and a plurality of digital-to-analog converter units. The encoder is used for parsing one-beat data based on a serial port protocol to determine a read-write bit, an address segment and a data segment corresponding to the one-beat data, and converting the read-write bit into a synchronization control signal, the address segment into an addressing signal, and the data segment into digital-to-analog conversion data. The decoder is used for determining a corresponding digital-to-analog converter unit in the plurality of digital-to-analog converter units based on the addressing signal. The digital-to-analog converter array determines whether to latch the digital-to-analog conversion data in the corresponding digital-to-analog converter unit based on the synchronization control signal. In this way, the complexity is simplified and the number of wirings is reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a digital-to-analog converter array chip and a digital-to-analog conversion method. Background Technology

[0002] A digital-to-analog converter (DAC) converts digital signals into analog electrical signals and controls the strength of the final output analog electrical signal, such as controlling the voltage magnitude of a voltage signal and the current magnitude of a current signal. With increasing demands for DAC speed and scale, a large number of DAC units capable of precisely controlling the output voltage are integrated into a DAC array within a limited space. Each DAC unit in the array can be controlled individually, thus forming a high-density, controllable array. Generally, a host computer can connect to multiple DAC array chips via a communication bus. Each DAC array chip integrates a communication module to receive the digital signal to be converted from the host computer and has its own DAC array. This allows the host computer to control a large number of DAC units via the communication bus. The DAC array chip has a dedicated module responsible for processing the communication protocol and storing the digital signal to be converted. In existing technology, this dedicated module receives configuration from the host computer and transmits the input to the corresponding DAC unit via a metal wire. For an M x N DAC array, assuming a data bit width of L bits, current digital-to-analog converter array (DAC) chip solutions require each bit of data to be sent to the DAC unit in the DAC array via a separate metal line, totaling L x M x N metal lines. For example, a 10-bit DAC unit has 10 input lines. If the DAC array is an 8 x 256 10-bit DAC, each DAC requires at least 10 control lines, so the routing from the digital module to the DAC array will be 258 x 8 x 10 = 20480 lines. If the array is larger, the number of lines will increase further. This order of magnitude of lines will bring a series of engineering difficulties. For example, more metal layers are needed to achieve layout and routing within a limited area. The core circuit originally only needed 3 metal layers, but because of so many lines, more than 6 metal layers are needed, increasing costs. Furthermore, so many connections will affect the power line layout, making it difficult to design the chip's power integrity, and also reducing the flexibility of circuit design due to routing limitations, preventing performance improvements from being achieved through more advanced design solutions. For example, the parasitic capacitance of the DAC's core circuitry and its traces can be quite large, ultimately affecting circuit performance. Finally, in terms of engineering implementation, tens of thousands of traces significantly increase the workload for layout engineers and greatly enhance the complexity of the project.

[0003] To address this, this application provides a digital-to-analog converter array chip and a digital-to-analog conversion method. By utilizing timing control technology and dynamic adjustment, the number of control lines required is significantly reduced, optimizing engineering complexity and design costs. This facilitates high-density layout and wiring within a limited area, helps optimize power line layout and improve chip power integrity, reduces parasitic capacitance, and enhances circuit performance. Summary of the Invention

[0004] In a first aspect, this application provides a digital-to-analog converter (DAC) array chip. The DAC array chip includes a digital module and a DAC array. The digital module includes an encoder, and the DAC array includes a decoder and multiple DAC units. The encoder is used to parse a single-pass data packet based on a serial port protocol to determine the read / write bit, address segment, and data segment corresponding to the single-pass data packet. Furthermore, it converts the read / write bit into a synchronization control signal, the address segment into an addressing signal, and the data segment into DAC-converted data. The decoder is used to determine the corresponding DAC unit among the multiple DAC units based on the addressing signal. The DAC array determines whether to latch the DAC data in the corresponding DAC unit based on the synchronization control signal.

[0005] Through the first aspect of this application, timing control technology and dynamic adjustment methods are used to simplify control complexity, reduce the trouble of layout and wiring caused by direct metal wire connection, and simplify the difficulty of upper computer control, resulting in improvements in cost and system efficiency; at the same time, the clock resources inherent in serial port protocol communication can be utilized, combined with resource pooling technology, to flexibly adapt to the digital-to-analog conversion requirements of various serial port protocols, as well as to the configuration of various digital-to-analog conversion hardware.

[0006] In one possible implementation of the first aspect of this application, the plurality of digital-to-analog converter units are configured as a virtual resource pool for digital-to-analog conversion functions through resource pooling. The plurality of digital-to-analog converter units are respectively assigned virtual addresses in the virtual resource pool, and the addressing signal is used to indicate the virtual address in the virtual resource pool to which the corresponding digital-to-analog converter unit is assigned.

[0007] In one possible implementation of the first aspect of this application, the maximum bit width of the digital signal supported by the digital-to-analog conversion operation of each of the plurality of digital-to-analog converter units is consistent or inconsistent.

[0008] In one possible implementation of the first aspect of this application, the plurality of digital-to-analog converter units include a first type of digital-to-analog converter unit and a second type of digital-to-analog converter unit, wherein the maximum bit width of the digital signal supported by the digital-to-analog conversion operation of the first type of digital-to-analog converter unit is different from the maximum bit width of the digital signal supported by the digital-to-analog conversion operation of the second type of digital-to-analog converter unit, and the virtual address in the virtual resource pool to which the first type of digital-to-analog converter unit is allocated is located in a first virtual address range, and the virtual address in the virtual resource pool to which the second type of digital-to-analog converter unit is allocated is located in a second virtual address range, wherein the first virtual address range and the second virtual address range do not overlap.

[0009] In one possible implementation of the first aspect of this application, the mapping relationship between the virtual addresses in the virtual resource pool and the plurality of digital-to-analog converter units can be configured to support changes in the number of the plurality of digital-to-analog converter units, and changes in the spatial distribution relationship of the plurality of digital-to-analog converter units in the digital-to-analog converter array. Furthermore, the digital-to-analog converter array chip also includes a built-in self-test system for detecting faulty digital-to-analog converter units and removing the faulty digital-to-analog converter units from the plurality of digital-to-analog converter units.

[0010] In one possible implementation of the first aspect of this application, the digital module is connected to the digital-to-analog converter array via a synchronization control line, an address line, and a digital-to-analog conversion data line. The synchronization control line is used to transmit the synchronization control signal, the address line is used to transmit the addressing signal, and the digital-to-analog conversion data line is used to transmit the digital-to-analog conversion data. The digital-to-analog conversion operations of the plurality of digital-to-analog converter units share the synchronization control line, the address line, and the digital-to-analog conversion data line.

[0011] In one possible implementation of the first aspect of this application, when the address signal is a one-dimensional array, the address lines are a single set of metal lines; when the address signal is a two-dimensional array, the address lines are two sets of metal lines used to transmit the two dimensions of the two-dimensional array respectively.

[0012] In one possible implementation of the first aspect of this application, the plurality of digital-to-analog converter units form an N-row, M-column matrix, the addressing signals are a two-dimensional array including row address signals and column address signals, the address lines are two sets of metal lines including N row address lines for transmitting the row address signals and M column address lines for transmitting the column address signals, where N and M are both positive integers greater than 1.

[0013] In one possible implementation of the first aspect of this application, the read / write bit is used to indicate whether the data segment needs to be used to update the corresponding digital-to-analog converter unit. When the read / write bit indicates writing, the synchronization control signal indicates that the digital-to-analog conversion data is latched in the corresponding digital-to-analog converter unit. When the read / write bit indicates reading, the synchronization control signal indicates that the digital-to-analog conversion data is not latched in the corresponding digital-to-analog converter unit.

[0014] In one possible implementation of the first aspect of this application, the synchronization control signal is independent of each other among the multi-phase data based on the serial port protocol, the read and write bits of each of the multi-phase data are respectively used to generate the synchronization control signal corresponding to each of the multi-phase data, and the address segment and data segment of each of the multi-phase data are used to define the effective range of the synchronization control signal corresponding to each of the multi-phase data.

[0015] In one possible implementation of the first aspect of this application, the digital-to-analog converter array further includes a timing controller for timing control between the multi-phase data, the multi-phase data including the first-phase data and the next-phase data relative to the first-phase data, the timing controller being configured to: update the synchronization control signal, the addressing signal, and the digital-to-analog converter data using the last rising edge of the first-phase data, and reset the synchronization control signal using a clock other than the last clock after the address segment of the next-phase data.

[0016] In one possible implementation of the first aspect of this application, the digital-to-analog converter array further includes control logic and latches, the control logic and latches including the timing controller, and the control logic and latches are connected to the decoder, the control logic and latches being configured to generate timing control signals for timing control between the multi-shot data.

[0017] In one possible implementation of the first aspect of this application, the control logic and latch are used to convert the parallel transmission of digital signal bit information into serial port transmission based on the timing control signal, wherein the timing control signal is generated by the control logic and latch based on the clock of the serial port protocol.

[0018] In one possible implementation of the first aspect of this application, the serial port protocol defines the data format of the one-time data, and the serial port protocol is a serial peripheral device interface protocol, an integrated circuit bus protocol, a serializer deserializer protocol, or a quick peripheral component interconnection protocol.

[0019] Secondly, this application provides a digital-to-analog (D / A) conversion method. The D / A conversion method is applied to a digital-to-analog converter (DAC) array chip, which includes a digital module and a DAC array. The digital module includes an encoder, and the DAC array includes a decoder and multiple DAC units. The D / A conversion method includes: parsing a single-pass data sequence based on a serial port protocol using the encoder to determine the read / write bit, address segment, and data segment corresponding to the single-pass data sequence; converting the read / write bit into a synchronization control signal, converting the address segment into an addressing signal, and converting the data segment into D / A converted data; and using the decoder to determine the corresponding DAC unit among the multiple DAC units based on the addressing signal, wherein the DAC array determines whether to latch the D / A converted data in the corresponding DAC unit based on the synchronization control signal.

[0020] Through the second aspect of this application, timing control technology and dynamic adjustment methods are used to simplify control complexity, reduce the layout and wiring trouble caused by direct metal wire connection, and simplify the difficulty of upper computer control, resulting in cost and system efficiency improvements; at the same time, the clock resources inherent in serial port protocol communication can be utilized, combined with resource pooling technology, to flexibly adapt to the digital-to-analog conversion requirements of various serial port protocols, as well as to the configuration of various digital-to-analog conversion hardware. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic diagram of a digital-to-analog converter array chip according to a first embodiment of this application;

[0023] Figure 2 A schematic diagram of a digital-to-analog converter array chip according to a second embodiment of this application;

[0024] Figure 3 A flowchart illustrating the control logic and the method for generating timing control signals for the latch provided in the embodiments of this application;

[0025] Figure 4 This is a flowchart illustrating a digital-to-analog conversion method provided in an embodiment of this application. Detailed Implementation

[0026] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0027] It should be understood that in the description of this application, "at least one" means one or more, and "multiple" means two or more. In addition, the words "first," "second," etc., unless otherwise stated, are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance or order.

[0028] Figure 1 This is a schematic diagram of a digital-to-analog converter array chip according to a first embodiment of this application. Figure 1 As shown, the digital-to-analog converter array chip A101 includes a digital module A103 and a digital-to-analog converter array A105. The digital module A103 includes an encoder A110. The digital-to-analog converter array A105 includes a decoder A120 and multiple digital-to-analog converter units A130. The encoder A110 is used to parse a single-pass data packet based on a serial port protocol to determine the read / write bits, address segment, and data segment corresponding to the single-pass data packet. It converts the read / write bits into synchronization control signals, the address segment into addressing signals, and the data segment into digital-to-analog converted data. The decoder A120 is used to determine the corresponding digital-to-analog converter unit among the multiple digital-to-analog converter units A130 based on the addressing signals. The digital-to-analog converter array A105 determines whether to latch the digital-to-analog converted data in the corresponding digital-to-analog converter unit based on the synchronization control signals.

[0029] Figure 1 The illustrated digital-to-analog converter (DAC) array chip A101 converts digital signals into analog electrical signals and controls the strength of the final output analog electrical signal. DAC array chip A101 includes DAC array A105, which comprises multiple DAC units A130, integrating a large number of precisely controllable DAC units within a limited space. Each DAC unit in A130 can be controlled individually, thus forming a high-density controllable array. Taking DAC array chip A101 as an example, a host computer can connect to multiple DAC array chips (each with the structure of DAC array chip A101) via a communication bus. Each DAC array chip (e.g., DAC array chip A101) integrates a communication module to receive the digital signal to be converted from digital to analog signals from the host computer and has its own DAC array. Thus, the host computer can control a large number of DAC units via the communication bus. Figure 1Not shown, the digital-to-analog converter array chip A101 may include a communication module for receiving digital signals to be converted from digital to analog signals from a host computer and handling communication protocols. Common communication protocols may include, for example, Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I2C), Serializer / Deserializer (SERDES), or Peripheral Component Interconnect Express (PCIe). Assuming the digital-to-analog converter array A105 is an M-row N-column DAC array, and further assuming that the data bit width of all DAC units in this array is L bits, there is a total control requirement of L times M times N bits. For example, the input of a 10-bit DAC unit requires 10 bits to be controlled. If the DAC array is an 8-row 256-column 10-bit DAC, this means that the control requirement for the entire DAC array is at least 258 times 8 times 10 equals 20480 bits. Therefore, if different bits of information are controlled via individual metal wires, the number of traces increases dramatically with the size of the DAC array and the data bit width. Multiple arrays further increase the overall trace count, leading to a series of problems such as increased cost, impact on power line routing, excessive parasitic capacitance, and excessive engineering complexity. However, to meet the requirements for digital-to-analog conversion speed and scale, while ensuring individual and precise control of each digital-to-analog converter unit, it is also necessary to consider how to achieve high digital-to-analog conversion speed and large conversion scale. Figure 1 The A101 digital-to-analog converter array chip shown simplifies control complexity and reduces the layout and wiring trouble caused by direct metal wire connection by utilizing timing control technology and dynamic adjustment method. It also simplifies the difficulty of upper computer control, resulting in improvements in cost and system efficiency. At the same time, it can also utilize the clock resources of the serial port protocol communication itself, combined with resource pooling technology, to flexibly adapt to the digital-to-analog conversion requirements of various serial port protocols, as well as to the configuration of various digital-to-analog conversion hardware. Further details are provided below.

[0030] See Figure 1The digital-to-analog converter array chip A101 includes a digital module A103 and a digital-to-analog converter array A105. Here, the digital module A103 is responsible for communication with the host computer, including processing the communication protocol, receiving control commands from the host computer, and receiving the digital signals to be converted from digital to analog. The digital module A103 and the digital-to-analog converter array A105 are relatively independent; typically, on a mixed-signal chip, these two are completely separate, thus requiring metal interconnects for signal transmission. The digital module A103 also includes a register for temporary data storage, used to temporarily store configurations issued from the host computer for input to the corresponding digital-to-analog converter unit. Figure 1Not shown, the digital module A103 in the digital-to-analog converter array chip A101 may include a communication module for receiving digital signals to be converted from digital to analog signals from the host computer and for handling communication protocols. This communication module may be a serial protocol processor, or a serial protocol processor, for handling serial protocols such as SPI and I2C. On the digital module A103 side, the digital module A103 includes an encoder A110. The encoder A110 is used to parse a single frame of data based on the serial protocol to determine the read / write bits, address segments, and data segments corresponding to the single frame of data. It then converts the read / write bits into synchronization control signals, the address segments into addressing signals, and the data segments into digital-to-analog conversion data. Therefore, after the host computer sends the control data for digital-to-analog conversion to the digital-to-analog converter array chip A101, it is first processed by the protocol processor in the digital-to-analog converter array chip A101, and then converted into a series of signals by the encoder A110, namely, synchronization control signals, addressing signals, and digital-to-analog conversion data. Conversely, on the digital-to-analog converter (DAC) array A105 side, DAC array A105 includes a decoder A120 and a plurality of DAC units A130. The decoder A120 is used to determine the corresponding DAC unit among the plurality of DAC units A130 based on the addressing signal. Furthermore, DAC array A105 determines whether to latch the DAC data in the corresponding DAC unit based on the synchronization control signal. Thus, the synchronization control signal, addressing signal, and DAC data converted by encoder A110 are transmitted to DAC array A105 via a trace between digital module A103 and DAC array A105. Then, decoder A120 determines the corresponding DAC unit among the plurality of DAC units A130 based on the addressing signal, and DAC array A105 determines whether to latch the DAC data in the corresponding DAC unit based on the synchronization control signal. In this way, addressing signals can be used to achieve individual and precise control of each digital-to-analog converter (DAC) unit. DAC data can be sent to the corresponding DAC unit, and a synchronization control signal determines whether to latch it, that is, selectively hold the DAC data in the corresponding DAC unit until the next modification. Finally, the DAC array A105 as a whole controls the strength of the final output analog electrical signal, thereby realizing the DAC function.

[0031] Continue reading Figure 1Because encoder A110 is used to convert the read / write bits, address segments, and data segments corresponding to a single data step, obtaining synchronization control signals, addressing signals, and digital-to-analog conversion data respectively, encoder A110 can be used to convert each data step in a multi-step data set. This means that encoder A110 can be shared to meet the data transmission needs of the digital-to-analog converter units corresponding to different data steps. Therefore, multiple sets of traces can be shared to transmit the synchronization control signals, addressing signals, and digital-to-analog conversion data to be sent to different digital-to-analog converter units. This avoids the inconvenience of direct metal wire connections to the digital-to-analog converter units. By sharing multiple sets of traces between digital module A103 and digital-to-analog converter array A105, the data transmission needs from encoder A110 to digital-to-analog converter array A105 can be met. This can be used to send configurations from the host computer to each digital-to-analog converter unit, achieving individual and precise control of each digital-to-analog converter unit. Thus, through system architecture optimization and the use of encoded and then decoded wiring optimization schemes, the number of required metal wires is significantly reduced. Furthermore, based on the data format of each data cycle specified by the serial port protocol, multiple fields of the data cycle can be determined by parsing the data, including read / write bits, address fields, and data fields. The specific distribution of these fields in the data cycle can be adjusted according to the serial port protocol specifications; for example, the data field can be set before the address field, or vice versa. Thus, the read / write bits, which indicate the content of a read or write operation, can be used to determine whether the data in the corresponding digital-to-analog converter unit needs to be updated. Furthermore, the synchronization control signal can be used to determine whether to latch, or selectively keep the digital-to-analog converter data in the corresponding digital-to-analog converter unit until the next modification. Furthermore, by avoiding the direct metal wire connection from the digital module A103 to the digital-to-analog converter (DAC) units in the DAC array A105, and instead using an optimized wiring system scheme of encoding followed by decoding, the configuration received by the host computer from the digital module A103 is decoupled from the micro-manipulation of individual DAC units in the DAC array A105. In other words, the host computer does not directly control the individual DAC units in the DAC array A105, but achieves fine-grained control through the optimized wiring system scheme of encoding followed by decoding provided by the encoder A110 in the digital module A103 and the decoder A120 in the DAC array A105. Therefore, the host computer indirectly controls the individual DAC units in the DAC array A105 through the encoder A110 in the digital module A103 and the decoder A120 in the DAC array A105. In this way, by combining resource pooling technology, it is equivalent to building virtual addresses in the chip that correspond one-to-one with the digital-to-analog converter units. For example, 8 x 256 DACs correspond to 8 x 256 virtual addresses.Furthermore, it is compatible with serial port protocol row and column encoders and controllers, and can translate address information into row and column information.

[0032] Continue reading Figure 1 Serial communication protocols have their own clock resources and transmit multiple data packets according to the serial protocol's clock. Therefore, a single data packet based on the serial protocol utilizes the protocol's own clock. This means that the serial protocol's own clock can naturally distinguish between preceding and following data packets, such as the current data packet and the next data packet relative to it. Figure 1The digital-to-analog converter array chip A101 shown, based on the optimized interconnection scheme of encoding and decoding provided by the encoder A110 in the digital module A103 and the decoder A120 in the digital-to-analog converter array A105, can utilize the serial port protocol clock to generate control timing. Furthermore, the timing control technology can flexibly adapt to the digital-to-analog conversion requirements of various serial port protocols and the configuration of various digital-to-analog conversion hardware, realizing dynamic adjustment of specific digital-to-analog converter units. As mentioned above, multiple sets of traces are shared to transmit synchronization control signals, addressing signals, and digital-to-analog conversion data to be sent to different digital-to-analog converter units. Addressing signals can be sequence numbers, such as those from 0 to 1000, transmitted via a single set of address lines. Addressing signals can also be row and column control signals transmitted via two sets of address lines. In the A105 digital-to-analog converter (DAC) array, any one of the multiple DAC units A130, regardless of its data width (6-bit, 8-bit, or 10-bit), is pooled as a DAC resource, forming a unified virtual resource pool for DAC functionality. The addressing signal then transmits a virtual address from this virtual resource pool. Thus, the host computer does not need to know how to directly connect to a specific DAC unit (e.g., via an actual physical address); it only needs to select a DAC unit from the virtual resource pool using the virtual address, simplifying control complexity. Furthermore, as the number of DAC units changes, and the bit width of the digital signals that each DAC unit can process changes, the configuration of the virtual resource pool can be adjusted accordingly. For example, 1000 DAC units can be set for 6-bit DAC functionality, or 500 DAC units can be set for 6-bit DAC functionality while another 200 DAC units are set for 8-bit DAC functionality. Various combinations of DAC units can also be configured, such as 8x256, 16x16, etc. By combining resource pooling technology and an optimized wiring system scheme that uses encoding followed by decoding (avoiding direct metal wire connections), multiple sets of traces can be shared between the digital module A103 and the digital-to-analog converter array A105, facilitating the positioning and reading / writing of the digital-to-analog converter units. It can flexibly adapt to the digital-to-analog conversion requirements of various serial port protocols, as well as the configuration of various digital-to-analog conversion hardware. This reduces the layout and wiring complexities caused by direct metal wire connections and simplifies the difficulty of upper-computer control, resulting in improvements in cost and system efficiency. It should be understood that... Figure 1 The digital-to-analog converter array chip A101 shown can represent multiple array chips with similar structures and operating principles. These array chips constitute a high-density and configurable multi-array, enabling the host computer to control a large number of digital-to-analog converter units through a communication bus.

[0033] Continue reading Figure 1The following example illustrates how to generate control timing using the serial port protocol clock, taking row and column control signals, where addressing signals are transmitted via two sets of address lines, as an example. Here, the two sets of address lines are row address lines (also called row control lines) and column address lines (also called column control lines). Therefore, the connection between digital module A103 and digital-to-analog converter array A105 includes four types of metal lines: row address lines, adapted to the number of digital-to-analog converter units in the row dimension, for example, an 8-row, 256-column DAC array corresponds to 8 row address lines; column address lines, adapted to the number of digital-to-analog converter units in the column dimension, for example, an 8-row, 256-column DAC array corresponds to 256 column address lines; synchronization control lines, used to transmit synchronization control signals to determine whether to latch the digital-to-analog conversion data in the corresponding digital-to-analog converter unit; and digital-to-analog conversion data lines, adapted to the data bit width, for example, a 10-bit data bit width corresponds to 10 digital-to-analog conversion data lines. Conversely, in digital module A103, encoder A110 includes row and column encoders, and also provides control logic for synchronization control and latches, thus providing corresponding inputs for the four types of metal wires mentioned above. Therefore, by adding row and column encoding and control logic to digital module A103, and adding corresponding row and column decoders (decoder A120 includes row and column decoders), control logic, and latch circuits at the interface of digital-to-analog converter array A105, the one-to-one mapping relationship between metal wires and digital-to-analog converter units in the direct metal wire connection scheme is transformed into a one-to-many mapping relationship between shared multiple sets of traces and digital-to-analog converter units, thereby significantly reducing the number of connections. Furthermore, using timing control technology, the parallel transmission of digital signal bit information can be converted into serial port transmission based on the timing control signals. An exemplary control timing generation can be executed sequentially: determining whether the address segment is the virtual address corresponding to the DAC; if so, then outputting the corresponding row control signal and column control signal; then, determining whether the read / write bit indicates write; if so, outputting the timing control signal. Here, the host computer triggers control logic when it needs to write data. Additionally, utilizing the inherent clock of the serial protocol as the control timing for generating the DAC, address information is translated into row and column information, and data is compiled from serial data into the data required by the specific digital-to-analog converter unit, i.e., digital-to-analog conversion data. Then, the digital-to-analog conversion data is latched into the corresponding local latch before the next data arrives via timing control signals. Specifically, the row and column information / data, along with the synchronization control signal, is updated using the last rising edge of a data cycle; the synchronization control signal is reset using any non-last clock cycle after the address bits of the next data cycle; these row / column information and synchronization control signals work together to store the data in the corresponding location in a timely manner.Thus, the built-in clock of the serial port protocol is used to distinguish data from different data packets, and control timing is generated to support timing control technology. This is combined with dynamic adjustment and resource pooling techniques to ensure that the synchronization control signal is independent between different data packets. The read / write bits of the current data packet are used to determine the corresponding synchronization control signal information, and the address and data bits of the current data packet are used to limit the effective range of the corresponding synchronization control signal. Furthermore, through resource pooling, a built-in self-test system can be implemented to detect digital-to-analog converter (DAC) units, excluding faulty DAC units from the virtual resource pool, or shutting down or bypassing faulty DAC units. The entire DAC array A105 is used to control the strength of the final output analog electrical signal (voltage or current). From a system application perspective, when the proportion of faulty DAC units exceeds a certain percentage, such as 10%, the entire DAC array chip A101 can be terminated, improving system stability and security. Additionally, the synchronization control signal is used to instruct specific DAC units to perform data latching operations. For example, in the first operation cycle, the digital-to-analog converter (DAC) unit in row 3, column 5 is selected. A synchronization control signal is used to perform a latching operation based on whether a read or write operation is performed; if a write operation is performed, the corresponding DAC unit in row 3, column 5 is latched. In the second operation cycle, the DAC unit in row 3, column 7 is selected. A synchronization control signal is used to perform a latching operation based on whether a read or write operation is performed; if a write operation is performed, the corresponding DAC unit in row 3, column 7 is not latched. Thus, the encoder A110 converts the high-speed serially received read / write indication into a synchronization control signal. If a read operation is performed, the DAC unit retains its previous value; if a write operation is performed, the DAC unit replaces its previously retained value with the current digital-to-analog conversion data. This allows for the low-cost and high-efficiency design of large-scale DAC array chips, providing an extremely effective design method for various specific needs.

[0034] In short, Figure 1 The A101 digital-to-analog converter array chip shown simplifies control complexity and reduces the layout and wiring trouble caused by direct metal wire connection by utilizing timing control technology and dynamic adjustment method. It also simplifies the difficulty of upper computer control, resulting in improvements in cost and system efficiency. At the same time, it can also utilize the clock resources of the serial port protocol communication itself, combined with resource pooling technology, to flexibly adapt to the digital-to-analog conversion requirements of various serial port protocols, as well as to the configuration of various digital-to-analog conversion hardware.

[0035] Figure 2 This is a schematic diagram of a digital-to-analog converter array chip according to a second embodiment of this application. Figure 2As shown, the digital-to-analog converter array chip B201 includes a digital module B203 and a digital-to-analog converter array B205. The digital module B203 includes an encoder B210. The digital-to-analog converter array B205 includes a decoder B220 and multiple digital-to-analog converter units B230. The encoder B210 is used to parse a single data cycle based on a serial port protocol to determine the read / write bits, address segment, and data segment corresponding to the single data cycle, and converts the read / write bits into synchronization control signals, the address segment into addressing signals, and the data segment into digital-to-analog converted data. The decoder B220 is used to determine the corresponding digital-to-analog converter unit among the multiple digital-to-analog converter units B230 based on the addressing signals, wherein the digital-to-analog converter array B205 determines whether to latch the digital-to-analog converted data in the corresponding digital-to-analog converter unit based on the synchronization control signals. Furthermore, the digital module B203 and the digital-to-analog converter array B205 are connected via a synchronization control line 252, an address line 250, and a digital-to-analog conversion data line 254. The synchronization control line 252 transmits the synchronization control signal, the address line 250 transmits the addressing signal, and the digital-to-analog conversion data line 254 transmits the digital-to-analog conversion data. The digital-to-analog conversion operations of the plurality of digital-to-analog converter units B230 share the synchronization control line 252, the address line 250, and the digital-to-analog conversion data line 254. The digital-to-analog converter array B205 also includes a timing controller for timing control between the multi-phase data, which includes the current phase data and the next phase data relative to the current phase data. The timing controller is used to: update the synchronization control signal, the addressing signal, and the digital-to-analog conversion data using the last rising edge of the current phase data; and to reset the synchronization control signal using a clock signal following the address segment of the next phase data, excluding the last clock cycle. Furthermore, the digital-to-analog converter array B205 also includes control logic and latch 260, which includes the timing controller and is connected to the decoder B220. The control logic and latch 260 is configured to generate timing control signals for timing control between the multi-shot data.

[0036] Figure 2The digital-to-analog converter (DAC) array chip B201 shown shares multiple sets of traces to transmit synchronization control signals, addressing signals, and DAC data to be sent to different DAC units. This avoids the inconvenience of direct metal wire connections between DAC units. By sharing multiple sets of traces between the digital module B203 and the DAC array B205, the data transmission requirements from the encoder B210 to the DAC array B205 can be met. This allows configurations from the host computer to be sent to each DAC unit, achieving individual and precise control of each DAC unit. Thus, through system architecture optimization and using an encoding-and-decoding connection optimization scheme, the number of required metal wires is significantly reduced. Any one of the multiple DAC units B230 in the DAC array B205, regardless of its data bit width (6 bits, 8 bits, or 10 bits), is pooled as a DAC resource, forming a unified virtual resource pool for DAC functionality. The addressing signals then transmit a virtual address from this virtual resource pool. In this way, the host computer does not need to know how to directly connect to a specific digital-to-analog converter (DAC) unit (e.g., via an actual physical address). It only needs to select a DAC unit from a virtual resource pool via a virtual address, simplifying control complexity. Furthermore, as the number of DAC units changes, and the bit width of the digital signals that each DAC unit can process changes, the configuration of the virtual resource pool can be adjusted accordingly. The one-to-one mapping relationship between metal wires and DAC units in the direct metal wire connection scheme is transformed into a one-to-many mapping relationship between shared multiple sets of traces and DAC units, thereby significantly reducing the number of connections. Further, using timing control technology, the parallel transmission of digital signal bit information can be converted into serial port transmission based on the timing control signal. The serial port protocol's built-in clock is used to distinguish data from different phases, and control timing is generated to support timing control technology. This, combined with dynamic adjustment and resource pooling technology, ensures that the synchronization control signal is independent between different phases of data. The read / write bits of the current phase's data are used to determine the corresponding synchronization control signal information, and the address and data bits of the current phase's data are used to limit the effective range of the corresponding synchronization control signal.

[0037] In short, Figure 2 The B201 digital-to-analog converter array chip shown simplifies control complexity and reduces the layout and wiring trouble caused by direct metal wire connection by utilizing timing control technology and dynamic adjustment method. It also simplifies the difficulty of upper computer control, resulting in improvements in cost and system efficiency. At the same time, it can also utilize the clock resources of the serial port protocol communication itself, combined with resource pooling technology, to flexibly adapt to the digital-to-analog conversion requirements of various serial port protocols, as well as to the configuration of various digital-to-analog conversion hardware.

[0038] Figure 3 This is a flowchart illustrating the control logic and the method for generating timing control signals for the latch provided in the embodiments of this application. Figure 3 As shown, the method for generating timing control signals for control logic and latches includes the following steps.

[0039] Step S300: Begin.

[0040] Step S301: Determine whether the address segment is the virtual address corresponding to the digital-to-analog converter unit. If yes, proceed to step S303; otherwise, proceed to step S350.

[0041] Step S303: Output the corresponding row control signal and column control signal.

[0042] Step S305: Determine whether the read / write bit indicates a write operation. If yes, proceed to step S307; otherwise, proceed to step S350.

[0043] Step S307: Output timing control signal.

[0044] Step S350: End.

[0045] Figure 3 The control logic and latch generation method shown utilize the built-in clock of the serial port protocol to distinguish data from different phases and generate control timing to support timing control technology. Furthermore, it combines dynamic adjustment and resource pooling technology to ensure that the synchronization control signal is independent between data from different phases. The read / write bits of the current phase data are used to determine the information of the corresponding synchronization control signal, and the address bits and data bits of the current phase data are used to limit the effective range of the corresponding synchronization control signal.

[0046] See Figure 1 , Figure 2 and Figure 3In one possible implementation, the plurality of digital-to-analog converter (DAC) units are pooled to form a virtual resource pool for DAC functionality. Each DAC unit is assigned a virtual address within this virtual resource pool, and the addressing signal indicates the assigned virtual address within the virtual resource pool for that specific DAC unit. Thus, any DAC unit in the DAC array, regardless of its data width (6 bits, 8 bits, or 10 bits), is pooled as a DAC resource, forming a unified virtual resource pool for DAC functionality. The addressing signal then transmits a virtual address from this virtual resource pool. Consequently, the host computer does not need to know how to directly connect to a specific DAC unit (e.g., via an actual physical address); it only needs to select a DAC unit from the virtual resource pool using its virtual address, simplifying control complexity. Furthermore, as the number of digital-to-analog converter (DAC) units changes, and the bit width of the digital signals that each DAC unit can process changes, the configuration of the virtual resource pool can be adjusted accordingly. For example, 1000 DAC units can be set up for 6-bit DAC functions, or 500 DAC units can be set up for 6-bit DAC functions while another 200 DAC units are set up for 8-bit DAC functions. Various combinations of DAC units can also be configured, such as 8x256, 16x16, etc. Combining resource pooling technology with an optimized wiring system scheme that uses encoding followed by decoding (avoiding direct metal wire connections), multiple sets of traces can be shared between digital modules and the DAC array, facilitating the positioning and reading / writing of DAC units. It can flexibly adapt to the DAC conversion requirements of various serial port protocols, as well as the configuration of various DAC hardware, reducing the layout and wiring troubles caused by direct metal wire connections, simplifying the difficulty of host computer control, and bringing improvements in cost and system efficiency.

[0047] In one possible implementation, the maximum bit width of the digital signal supported by the digital-to-analog conversion operations of the plurality of digital-to-analog converter units may be consistent or inconsistent. This facilitates adaptation to the digital-to-analog conversion requirements of various serial port protocols and the configuration of various digital-to-analog conversion hardware.

[0048] In one possible implementation, the plurality of digital-to-analog converter (DAC) units include a first type of DAC unit and a second type of DAC unit. The maximum bit width of the digital signal supported by the DAC operation of the first type of DAC unit differs from the maximum bit width of the digital signal supported by the DAC operation of the second type of DAC unit. Furthermore, the virtual addresses allocated to the first type of DAC unit in the virtual resource pool are located within a first virtual address range, and the virtual addresses allocated to the second type of DAC unit in the virtual resource pool are located within a second virtual address range. The first and second virtual address ranges do not overlap. This allows for flexible adaptation to the DAC requirements of various serial port protocols, as well as the configuration of various DAC hardware. It reduces the layout and wiring difficulties caused by direct metal wire connections and simplifies the control complexity of the host computer, resulting in improvements in cost and system efficiency. Moreover, by utilizing the corresponding configurations in the virtual resource pool and ensuring the non-overlapping of virtual address ranges, the control complexity is simplified, which is beneficial for adapting to the DAC requirements of various serial port protocols and the configuration of various DAC hardware.

[0049] In one possible implementation, the mapping relationship between virtual addresses in the virtual resource pool and the plurality of digital-to-analog converter (DAC) units can be configured to support changes in the number of DAC units and changes in the spatial distribution of the DAC units in the DAC array. Furthermore, the DAC array chip includes a built-in self-test system for detecting and removing faulty DAC units from the plurality of DAC units. Thus, by configuring the mapping relationship between virtual addresses in the virtual resource pool and the plurality of DAC units, changes in the number of DAC units and changes in their spatial distribution in the DAC array can be reflected in real time, which is beneficial for achieving dense and configurable multi-array configurations. Moreover, through resource pooling, a built-in self-test system can detect DAC units, exclude faulty DAC units from the virtual resource pool, and shut down or bypass faulty DAC units. The strength of the final output analog electrical signal (voltage or current) is controlled using the entire DAC array. Furthermore, from a system application perspective, when the proportion of faulty digital-to-analog converter units exceeds a certain percentage, such as 10%, the entire digital-to-analog converter array chip can be terminated, thereby improving system stability and security.

[0050] In one possible implementation, the digital module and the digital-to-analog converter array are connected via synchronization control lines, address lines, and digital-to-analog conversion data lines. The synchronization control lines transmit synchronization control signals, the address lines transmit addressing signals, and the digital-to-analog conversion data lines transmit digital-to-analog conversion data. The digital-to-analog conversion operations of the multiple digital-to-analog converter units share the synchronization control lines, the address lines, and the digital-to-analog conversion data lines. In this way, the one-to-one mapping relationship between metal wires and digital-to-analog converter units in the direct metal wire connection scheme is transformed into a one-to-many mapping relationship between multiple shared sets of traces and digital-to-analog converter units, thereby significantly reducing the number of connections.

[0051] In some embodiments, when the addressing signal is a one-dimensional array, the address lines are a single set of metal lines; when the addressing signal is a two-dimensional array, the address lines are two sets of metal lines used to transmit the two dimensions of the two-dimensional array respectively. Thus, combined with resource pooling technology and an optimized wiring system using encoding followed by decoding (avoiding direct metal line connections), multiple sets of traces can be shared between the digital module and the digital-to-analog converter array, facilitating the positioning and reading / writing of the digital-to-analog converter unit. It can flexibly adapt to the digital-to-analog conversion requirements of various serial port protocols, as well as the configuration of various digital-to-analog conversion hardware, reducing the layout and wiring difficulties caused by direct metal line connections and simplifying the difficulty of upper-computer control, resulting in improvements in cost and system efficiency.

[0052] In some embodiments, the plurality of digital-to-analog converter (DAC) units form an N x M matrix. The addressing signals are a two-dimensional array including row address signals and column address signals. The address lines are two sets of metal lines, including N row address lines for transmitting the row address signals and M column address lines for transmitting the column address signals, where N and M are both positive integers greater than 1. Thus, by adding row and column encoding and control logic to the digital module, and adding corresponding row and column decoders (decoders include row and column decoders), control logic, and latching circuits at the interface of the DAC array, the one-to-one mapping relationship between metal lines and DAC units in the direct metal line connection scheme is transformed into a one-to-many mapping relationship between shared multiple sets of traces and DAC units, thereby significantly reducing the number of connections. Furthermore, it can be compatible with serial port protocols for row and column encoders and controllers, which can translate address bit information into row and column information.

[0053] In one possible implementation, the read / write bit indicates whether the data segment needs to be used to update the corresponding digital-to-analog converter (DAC) unit. When the read / write bit indicates a write operation, the synchronization control signal instructs the DAC unit to latch the DAC data; when the read / write bit indicates a read operation, the synchronization control signal instructs the DAC unit not to latch the DAC data. Thus, the encoder converts the high-speed serially received read / write indications into synchronization control signals. If a read operation is performed without latching, the DAC unit retains the previous value; if a write operation is performed with latching, the DAC unit replaces the previously retained value with the current DAC data. This enables the low-cost and high-efficiency design of large-scale DAC array chips, providing an extremely effective design method for various specific needs.

[0054] In one possible implementation, the synchronization control signals are independent of each other among the multi-phase data based on the serial port protocol. The read / write bits of each multi-phase data are used to generate their respective corresponding synchronization control signals, and the address and data segments of each multi-phase data are used to define the effective range of their respective synchronization control signals. Thus, by introducing an optimized system scheme that combines encoding and decoding provided by the encoder in the digital module and the decoder in the digital-to-analog converter array, the control timing can be generated using the clock of the serial port protocol. Furthermore, the timing control technology can flexibly adapt to the digital-to-analog conversion requirements of various serial port protocols and the configuration of various digital-to-analog converter hardware, enabling dynamic adjustment of specific digital-to-analog converter units.

[0055] In some embodiments, the digital-to-analog converter array further includes a timing controller for timing control between the multi-phase data, which includes the current phase data and the next phase data relative to the current phase data. The timing controller is used to: update the synchronization control signal, the addressing signal, and the digital-to-analog conversion data using the last rising edge of the current phase data; and to reset the synchronization control signal using a clock signal following the address segment of the next phase data, excluding the last clock cycle. Thus, by utilizing the built-in clock of the serial port protocol to distinguish data from different phases and generating control timing to support timing control technology, and combining dynamic adjustment and resource pooling techniques, the synchronization control signal is ensured to be independent between different phases of data. The read / write bits of the current phase data are used to determine the information of the corresponding synchronization control signal, and the address and data bits of the current phase data are used to define the effective range of the corresponding synchronization control signal. By utilizing the inherent clock resources of the serial port protocol communication, combined with resource pooling technology, the digital-to-analog conversion requirements of various serial port protocols and the configuration of various digital-to-analog conversion hardware can be flexibly adapted.

[0056] In some embodiments, the digital-to-analog converter array further includes control logic and latches, which include the timing controller and are connected to the decoder. The control logic and latches are configured to generate timing control signals for timing control between the multi-data sessions. Thus, by utilizing the built-in clock of the serial port protocol to distinguish data from different sessions and generating control timing to support timing control technology, and combining dynamic adjustment and resource pooling techniques, the synchronization control signals are ensured to be independent between data sessions. The read / write bits of the current session's data are used to determine the information of the corresponding synchronization control signal, and the address and data bits of the current session's data are used to define the effective range of the corresponding synchronization control signal.

[0057] In some embodiments, the control logic and latch are used to convert the parallel transmission of digital signal bit information into serial port transmission based on the timing control signal, wherein the timing control signal is generated by the control logic and latch based on the clock of the serial port protocol. Thus, by utilizing the clock provided by the serial port protocol to distinguish data from different data packets and generating control timing to support timing control technology, and combining dynamic adjustment and resource pooling techniques, it is ensured that the synchronization control signal is independent between data packets of different data packets. The read / write bits of the current data packet are used to determine the information of the corresponding synchronization control signal, and the address bits and data bits of the current data packet are used to define the effective range of the corresponding synchronization control signal.

[0058] In one possible implementation, the serial port protocol defines the data format of the data in one pulse. The serial port protocol can be a serial peripheral device interface protocol, an integrated circuit bus protocol, a serializer / deserializer protocol, or a quick peripheral component interconnection protocol. Thus, by utilizing timing control technology and dynamic adjustment methods, the control complexity is simplified, the layout and wiring troubles caused by direct metal wire connections are reduced, and the difficulty of upper-computer control is also simplified, resulting in improvements in cost and system efficiency. Simultaneously, the inherent clock resources of the serial port protocol communication, combined with resource pooling technology, can flexibly adapt to the digital-to-analog conversion requirements of various serial port protocols, as well as the configuration of various digital-to-analog conversion hardware.

[0059] Figure 4 This is a flowchart illustrating a digital-to-analog conversion method provided in an embodiment of this application. The digital-to-analog conversion method is applied to a digital-to-analog converter array chip, which includes a digital module and a digital-to-analog converter array. The digital module includes an encoder, and the digital-to-analog converter array includes a decoder and multiple digital-to-analog converter units. Figure 4 As shown, the digital-to-analog conversion method includes the following steps.

[0060] Step S401: Using the encoder, the read / write bit, address segment, and data segment corresponding to the one-time data are determined by parsing the serial port protocol-based one-time data. The read / write bit is converted into a synchronization control signal, the address segment is converted into an addressing signal, and the data segment is converted into digital-to-analog conversion data.

[0061] Step S403: The decoder determines the corresponding digital-to-analog converter unit among the plurality of digital-to-analog converter units based on the addressing signal, wherein the digital-to-analog converter array determines whether to latch the digital-to-analog conversion data in the corresponding digital-to-analog converter unit based on the synchronization control signal.

[0062] Figure 4 The analog-to-digital conversion method shown simplifies control complexity and reduces the layout and wiring trouble caused by direct metal wire connection by utilizing timing control technology and dynamic adjustment. It also simplifies the difficulty of upper computer control, resulting in improvements in cost and system efficiency. At the same time, it can also utilize the clock resources inherent in serial port communication, combined with resource pooling technology, to flexibly adapt to the analog-to-digital conversion requirements of various serial port protocols, as well as to the configuration of various analog-to-digital conversion hardware.

[0063] The methods and devices provided in this application are based on the same inventive concept. Since the principles by which the methods and devices solve problems are similar, the embodiments, implementation methods, examples, or methods of implementation of the methods and devices can be referred to each other, and repeated details will not be repeated. This application also provides a system comprising multiple computing devices, the structure of each computing device of which can refer to the structure of the computing devices described above. The functions or operations achievable by this system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0064] This application also provides a computer-readable storage medium storing computer instructions. When these computer instructions are executed on a computer device (such as one or more processors), they can implement the method steps described in the above method embodiments. The specific implementation of the above method steps by the processor of the computer-readable storage medium can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0065] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. This application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Embodiments of this application can be implemented wholly or partially by software, hardware, firmware, or any other combination. When implemented in software, the above embodiments can be implemented wholly or partially as a computer program product. This application can take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that a computer can access, or a data storage device such as a server or data center that contains one or more sets of available media. Available media can be magnetic media (such as floppy disks, hard disks, and magnetic tapes), optical media, or semiconductor media. Semiconductor media can be solid-state drives, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other suitable form of storage medium.

[0066] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. Each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0067] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. The steps in the methods of the embodiments of this application can be adjusted in order, combined, or deleted according to actual needs; the modules in the systems of the embodiments of this application can be divided, combined, or deleted according to actual needs. If these modifications and variations of the embodiments of this application fall within the scope of the claims of this application and their equivalents, then this application also intends to include these modifications and variations.

Claims

1. A digital-to-analog converter array chip, characterized in that, The digital-to-analog converter array chip includes a digital module and a digital-to-analog converter array. The digital module includes an encoder, and the digital-to-analog converter array includes a decoder and multiple digital-to-analog converter units. The encoder is used to parse a single frame of data based on a serial port protocol to determine the read / write bit, address segment, and data segment corresponding to the single frame of data, and to convert the read / write bit into a synchronization control signal, the address segment into an addressing signal, and the data segment into digital-to-analog conversion data. The decoder is used to determine the corresponding digital-to-analog converter (DAC) unit among the plurality of DAC units based on the addressing signal, wherein the DAC array determines whether to latch the DAC data in the corresponding DAC unit based on the synchronization control signal. The digital module and the digital-to-analog converter array are connected via a synchronization control line, an address line, and a digital-to-analog conversion data line. The synchronization control line is used to transmit the synchronization control signal, the address line is used to transmit the addressing signal, and the digital-to-analog conversion data line is used to transmit the digital-to-analog conversion data. The digital-to-analog conversion operations of the multiple digital-to-analog converter units share the synchronization control line, the address line, and the digital-to-analog conversion data line.

2. The digital-to-analog converter array chip according to claim 1, characterized in that, The plurality of digital-to-analog converter units are configured into a virtual resource pool for digital-to-analog conversion functions through resource pooling. The plurality of digital-to-analog converter units are respectively assigned virtual addresses in the virtual resource pool, and the addressing signal is used to indicate the virtual address in the virtual resource pool assigned to the corresponding digital-to-analog converter unit.

3. The digital-to-analog converter array chip according to claim 1, characterized in that, The maximum bit width of the digital signal supported by the digital-to-analog conversion operations of the plurality of digital-to-analog converter units is either consistent or inconsistent.

4. The digital-to-analog converter array chip according to claim 2, characterized in that, The plurality of digital-to-analog converter (DAC) units include a first type of DAC unit and a second type of DAC unit. The maximum bit width of the digital signal supported by the DAC operation of the first type of DAC unit is different from the maximum bit width of the digital signal supported by the DAC operation of the second type of DAC unit. Furthermore, the virtual addresses in the virtual resource pool allocated to the first type of DAC unit are located in a first virtual address range, and the virtual addresses in the virtual resource pool allocated to the second type of DAC unit are located in a second virtual address range. The first virtual address range and the second virtual address range do not overlap.

5. The digital-to-analog converter array chip according to claim 2, characterized in that, The mapping relationship between the virtual addresses in the virtual resource pool and the plurality of digital-to-analog converter units can be configured to support changes in the number of the plurality of digital-to-analog converter units and changes in the spatial distribution of the plurality of digital-to-analog converter units in the digital-to-analog converter array. Furthermore, the digital-to-analog converter array chip also includes a built-in self-test system for detecting faulty digital-to-analog converter units and removing the faulty digital-to-analog converter units from the plurality of digital-to-analog converter units.

6. The digital-to-analog converter array chip according to claim 1, characterized in that, When the address signal is a one-dimensional array, the address line is a single set of metal lines; when the address signal is a two-dimensional array, the address line is two sets of metal lines used to transmit the two dimensions of the two-dimensional array respectively.

7. The digital-to-analog converter array chip according to claim 6, characterized in that, The plurality of digital-to-analog converter units form an N-row, M-column matrix. The addressing signal is a two-dimensional array that includes row address signals and column address signals. The address lines are two sets of metal lines that include N row address lines for transmitting the row address signals and M column address lines for transmitting the column address signals. N and M are both positive integers greater than 1.

8. The digital-to-analog converter array chip according to claim 1, characterized in that, The read / write bit is used to indicate whether the data segment needs to be used to update the corresponding digital-to-analog converter unit. When the read / write bit indicates writing, the synchronization control signal indicates that the digital-to-analog conversion data is latched in the corresponding digital-to-analog converter unit. When the read / write bit indicates reading, the synchronization control signal indicates that the digital-to-analog conversion data is not latched in the corresponding digital-to-analog converter unit.

9. The digital-to-analog converter array chip according to claim 1, characterized in that, The synchronization control signals are independent of each other among the multi-phase data based on the serial port protocol. The read and write bits of each multi-phase data are used to generate the corresponding synchronization control signals of each multi-phase data. The address segment and data segment of each multi-phase data are used to define the effective range of the corresponding synchronization control signals of each multi-phase data.

10. The digital-to-analog converter array chip according to claim 9, characterized in that, The digital-to-analog converter array further includes a timing controller for timing control between the multi-phase data, the multi-phase data including the first-phase data and the next-phase data relative to the first-phase data, the timing controller being used to: update the synchronization control signal, the addressing signal, and the digital-to-analog conversion data using the last rising edge of the first-phase data, and to reset the synchronization control signal using a clock other than the last clock after the address segment of the next-phase data.

11. The digital-to-analog converter array chip according to claim 10, characterized in that, The digital-to-analog converter array further includes control logic and latches, the control logic and latches include the timing controller, and the control logic and latches are connected to the decoder. The control logic and latches are configured to generate timing control signals for timing control between the multi-shot data.

12. The digital-to-analog converter array chip according to claim 11, characterized in that, The control logic and latch are used to convert the parallel transmission of digital signal bit information into serial port transmission based on the timing control signal, wherein the timing control signal is generated by the control logic and latch based on the clock of the serial port protocol.

13. The digital-to-analog converter array chip according to claim 1, characterized in that, The serial port protocol defines the data format of the one-time data. The serial port protocol is a serial peripheral device interface protocol, an integrated circuit bus protocol, a serializer / deserializer protocol, or a quick peripheral component interconnection protocol.

14. A digital-to-analog conversion method, characterized in that, The digital-to-analog conversion method is applied to a digital-to-analog converter array chip, which includes a digital module and a digital-to-analog converter array. The digital module includes an encoder, and the digital-to-analog converter array includes a decoder and multiple digital-to-analog converter units. The digital-to-analog conversion method includes: The encoder parses a single frame of data based on the serial port protocol to determine the read / write bit, address segment, and data segment corresponding to the single frame of data. The read / write bit is converted into a synchronization control signal, the address segment is converted into an addressing signal, and the data segment is converted into digital-to-analog conversion data. The decoder determines the corresponding digital-to-analog converter (DAC) unit among the plurality of DAC units based on the addressing signal. The DAC array determines whether to latch the DAC data in the corresponding DAC unit based on the synchronization control signal. The digital module and the digital-to-analog converter array are connected via a synchronization control line, an address line, and a digital-to-analog conversion data line. The synchronization control line is used to transmit the synchronization control signal, the address line is used to transmit the addressing signal, and the digital-to-analog conversion data line is used to transmit the digital-to-analog conversion data. The digital-to-analog conversion operations of the multiple digital-to-analog converter units share the synchronization control line, the address line, and the digital-to-analog conversion data line.

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